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generic: ar8216: mib_work_func: read all port mibs everytime
[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/of_device.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_net.h>
29 #include <linux/bitops.h>
30 #include <net/genetlink.h>
31 #include <linux/switch.h>
32 #include <linux/delay.h>
33 #include <linux/phy.h>
34 #include <linux/etherdevice.h>
35 #include <linux/lockdep.h>
36 #include <linux/ar8216_platform.h>
37 #include <linux/workqueue.h>
38 #include <linux/version.h>
39
40 #include "ar8216.h"
41
42 extern const struct ar8xxx_chip ar8327_chip;
43 extern const struct ar8xxx_chip ar8337_chip;
44
45 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
46
47 #define MIB_DESC(_s , _o, _n) \
48 { \
49 .size = (_s), \
50 .offset = (_o), \
51 .name = (_n), \
52 }
53
54 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
55 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
56 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
57 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
58 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
59 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
60 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
61 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
62 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
63 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
64 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
65 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
66 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
67 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
68 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
69 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
70 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
71 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
72 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
73 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
74 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
75 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
76 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
77 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
78 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
79 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
80 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
81 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
82 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
83 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
84 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
85 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
86 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
87 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
88 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
89 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
90 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
91 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
92 };
93
94 const struct ar8xxx_mib_desc ar8236_mibs[39] = {
95 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
96 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
97 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
98 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
99 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
100 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
101 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
102 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
103 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
104 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
105 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
106 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
107 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
108 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
109 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
110 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
111 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
112 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
113 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
114 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
115 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
116 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
117 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
118 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
119 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
120 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
121 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
122 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
123 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
124 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
125 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
126 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
127 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
128 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
129 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
130 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
131 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
132 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
133 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
134 };
135
136 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
137 static LIST_HEAD(ar8xxx_dev_list);
138
139 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
140 static int
141 ar8xxx_phy_poll_reset(struct mii_bus *bus)
142 {
143 unsigned int sleep_msecs = 20;
144 int ret, elapsed, i;
145
146 for (elapsed = sleep_msecs; elapsed <= 600;
147 elapsed += sleep_msecs) {
148 msleep(sleep_msecs);
149 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
150 ret = mdiobus_read(bus, i, MII_BMCR);
151 if (ret < 0)
152 return ret;
153 if (ret & BMCR_RESET)
154 break;
155 if (i == AR8XXX_NUM_PHYS - 1) {
156 usleep_range(1000, 2000);
157 return 0;
158 }
159 }
160 }
161 return -ETIMEDOUT;
162 }
163
164 static int
165 ar8xxx_phy_check_aneg(struct phy_device *phydev)
166 {
167 int ret;
168
169 if (phydev->autoneg != AUTONEG_ENABLE)
170 return 0;
171 /*
172 * BMCR_ANENABLE might have been cleared
173 * by phy_init_hw in certain kernel versions
174 * therefore check for it
175 */
176 ret = phy_read(phydev, MII_BMCR);
177 if (ret < 0)
178 return ret;
179 if (ret & BMCR_ANENABLE)
180 return 0;
181
182 dev_info(&phydev->mdio.dev, "ANEG disabled, re-enabling ...\n");
183 ret |= BMCR_ANENABLE | BMCR_ANRESTART;
184 return phy_write(phydev, MII_BMCR, ret);
185 }
186
187 void
188 ar8xxx_phy_init(struct ar8xxx_priv *priv)
189 {
190 int i;
191 struct mii_bus *bus;
192
193 bus = priv->sw_mii_bus ?: priv->mii_bus;
194 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
195 if (priv->chip->phy_fixup)
196 priv->chip->phy_fixup(priv, i);
197
198 /* initialize the port itself */
199 mdiobus_write(bus, i, MII_ADVERTISE,
200 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
201 if (ar8xxx_has_gige(priv))
202 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
203 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
204 }
205
206 ar8xxx_phy_poll_reset(bus);
207 }
208
209 u32
210 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
211 {
212 struct mii_bus *bus = priv->mii_bus;
213 u16 lo, hi;
214
215 lo = bus->read(bus, phy_id, regnum);
216 hi = bus->read(bus, phy_id, regnum + 1);
217
218 return (hi << 16) | lo;
219 }
220
221 void
222 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
223 {
224 struct mii_bus *bus = priv->mii_bus;
225 u16 lo, hi;
226
227 lo = val & 0xffff;
228 hi = (u16) (val >> 16);
229
230 if (priv->chip->mii_lo_first)
231 {
232 bus->write(bus, phy_id, regnum, lo);
233 bus->write(bus, phy_id, regnum + 1, hi);
234 } else {
235 bus->write(bus, phy_id, regnum + 1, hi);
236 bus->write(bus, phy_id, regnum, lo);
237 }
238 }
239
240 u32
241 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
242 {
243 struct mii_bus *bus = priv->mii_bus;
244 u16 r1, r2, page;
245 u32 val;
246
247 split_addr((u32) reg, &r1, &r2, &page);
248
249 mutex_lock(&bus->mdio_lock);
250
251 bus->write(bus, 0x18, 0, page);
252 wait_for_page_switch();
253 val = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
254
255 mutex_unlock(&bus->mdio_lock);
256
257 return val;
258 }
259
260 void
261 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
262 {
263 struct mii_bus *bus = priv->mii_bus;
264 u16 r1, r2, page;
265
266 split_addr((u32) reg, &r1, &r2, &page);
267
268 mutex_lock(&bus->mdio_lock);
269
270 bus->write(bus, 0x18, 0, page);
271 wait_for_page_switch();
272 ar8xxx_mii_write32(priv, 0x10 | r2, r1, val);
273
274 mutex_unlock(&bus->mdio_lock);
275 }
276
277 u32
278 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
279 {
280 struct mii_bus *bus = priv->mii_bus;
281 u16 r1, r2, page;
282 u32 ret;
283
284 split_addr((u32) reg, &r1, &r2, &page);
285
286 mutex_lock(&bus->mdio_lock);
287
288 bus->write(bus, 0x18, 0, page);
289 wait_for_page_switch();
290
291 ret = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
292 ret &= ~mask;
293 ret |= val;
294 ar8xxx_mii_write32(priv, 0x10 | r2, r1, ret);
295
296 mutex_unlock(&bus->mdio_lock);
297
298 return ret;
299 }
300 void
301 ar8xxx_phy_dbg_read(struct ar8xxx_priv *priv, int phy_addr,
302 u16 dbg_addr, u16 *dbg_data)
303 {
304 struct mii_bus *bus = priv->mii_bus;
305
306 mutex_lock(&bus->mdio_lock);
307 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
308 *dbg_data = bus->read(bus, phy_addr, MII_ATH_DBG_DATA);
309 mutex_unlock(&bus->mdio_lock);
310 }
311
312 void
313 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
314 u16 dbg_addr, u16 dbg_data)
315 {
316 struct mii_bus *bus = priv->mii_bus;
317
318 mutex_lock(&bus->mdio_lock);
319 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
320 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
321 mutex_unlock(&bus->mdio_lock);
322 }
323
324 static inline void
325 ar8xxx_phy_mmd_prep(struct mii_bus *bus, int phy_addr, u16 addr, u16 reg)
326 {
327 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
328 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, reg);
329 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr | 0x4000);
330 }
331
332 void
333 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data)
334 {
335 struct mii_bus *bus = priv->mii_bus;
336
337 mutex_lock(&bus->mdio_lock);
338 ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
339 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
340 mutex_unlock(&bus->mdio_lock);
341 }
342
343 u16
344 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg)
345 {
346 struct mii_bus *bus = priv->mii_bus;
347 u16 data;
348
349 mutex_lock(&bus->mdio_lock);
350 ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
351 data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA);
352 mutex_unlock(&bus->mdio_lock);
353
354 return data;
355 }
356
357 static int
358 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
359 unsigned timeout)
360 {
361 int i;
362
363 for (i = 0; i < timeout; i++) {
364 u32 t;
365
366 t = ar8xxx_read(priv, reg);
367 if ((t & mask) == val)
368 return 0;
369
370 usleep_range(1000, 2000);
371 cond_resched();
372 }
373
374 return -ETIMEDOUT;
375 }
376
377 static int
378 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
379 {
380 unsigned mib_func = priv->chip->mib_func;
381 int ret;
382
383 lockdep_assert_held(&priv->mib_lock);
384
385 /* Capture the hardware statistics for all ports */
386 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
387
388 /* Wait for the capturing to complete. */
389 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
390 if (ret)
391 goto out;
392
393 ret = 0;
394
395 out:
396 return ret;
397 }
398
399 static int
400 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
401 {
402 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
403 }
404
405 static int
406 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
407 {
408 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
409 }
410
411 static void
412 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
413 {
414 unsigned int base;
415 u64 *mib_stats;
416 int i;
417
418 WARN_ON(port >= priv->dev.ports);
419
420 lockdep_assert_held(&priv->mib_lock);
421
422 base = priv->chip->reg_port_stats_start +
423 priv->chip->reg_port_stats_length * port;
424
425 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
426 for (i = 0; i < priv->chip->num_mibs; i++) {
427 const struct ar8xxx_mib_desc *mib;
428 u64 t;
429
430 mib = &priv->chip->mib_decs[i];
431 t = ar8xxx_read(priv, base + mib->offset);
432 if (mib->size == 2) {
433 u64 hi;
434
435 hi = ar8xxx_read(priv, base + mib->offset + 4);
436 t |= hi << 32;
437 }
438
439 if (flush)
440 mib_stats[i] = 0;
441 else
442 mib_stats[i] += t;
443 cond_resched();
444 }
445 }
446
447 static void
448 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
449 struct switch_port_link *link)
450 {
451 u32 status;
452 u32 speed;
453
454 memset(link, '\0', sizeof(*link));
455
456 status = priv->chip->read_port_status(priv, port);
457
458 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
459 if (link->aneg) {
460 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
461 } else {
462 link->link = true;
463
464 if (priv->get_port_link) {
465 int err;
466
467 err = priv->get_port_link(port);
468 if (err >= 0)
469 link->link = !!err;
470 }
471 }
472
473 if (!link->link)
474 return;
475
476 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
477 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
478 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
479
480 if (link->aneg && link->duplex && priv->chip->read_port_eee_status)
481 link->eee = priv->chip->read_port_eee_status(priv, port);
482
483 speed = (status & AR8216_PORT_STATUS_SPEED) >>
484 AR8216_PORT_STATUS_SPEED_S;
485
486 switch (speed) {
487 case AR8216_PORT_SPEED_10M:
488 link->speed = SWITCH_PORT_SPEED_10;
489 break;
490 case AR8216_PORT_SPEED_100M:
491 link->speed = SWITCH_PORT_SPEED_100;
492 break;
493 case AR8216_PORT_SPEED_1000M:
494 link->speed = SWITCH_PORT_SPEED_1000;
495 break;
496 default:
497 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
498 break;
499 }
500 }
501
502 static struct sk_buff *
503 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
504 {
505 struct ar8xxx_priv *priv = dev->phy_ptr;
506 unsigned char *buf;
507
508 if (unlikely(!priv))
509 goto error;
510
511 if (!priv->vlan)
512 goto send;
513
514 if (unlikely(skb_headroom(skb) < 2)) {
515 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
516 goto error;
517 }
518
519 buf = skb_push(skb, 2);
520 buf[0] = 0x10;
521 buf[1] = 0x80;
522
523 send:
524 return skb;
525
526 error:
527 dev_kfree_skb_any(skb);
528 return NULL;
529 }
530
531 static void
532 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
533 {
534 struct ar8xxx_priv *priv;
535 unsigned char *buf;
536 int port, vlan;
537
538 priv = dev->phy_ptr;
539 if (!priv)
540 return;
541
542 /* don't strip the header if vlan mode is disabled */
543 if (!priv->vlan)
544 return;
545
546 /* strip header, get vlan id */
547 buf = skb->data;
548 skb_pull(skb, 2);
549
550 /* check for vlan header presence */
551 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
552 return;
553
554 port = buf[0] & 0x7;
555
556 /* no need to fix up packets coming from a tagged source */
557 if (priv->vlan_tagged & (1 << port))
558 return;
559
560 /* lookup port vid from local table, the switch passes an invalid vlan id */
561 vlan = priv->vlan_id[priv->pvid[port]];
562
563 buf[14 + 2] &= 0xf0;
564 buf[14 + 2] |= vlan >> 8;
565 buf[15 + 2] = vlan & 0xff;
566 }
567
568 int
569 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
570 {
571 int timeout = 20;
572 u32 t = 0;
573
574 while (1) {
575 t = ar8xxx_read(priv, reg);
576 if ((t & mask) == val)
577 return 0;
578
579 if (timeout-- <= 0)
580 break;
581
582 udelay(10);
583 cond_resched();
584 }
585
586 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
587 (unsigned int) reg, t, mask, val);
588 return -ETIMEDOUT;
589 }
590
591 static void
592 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
593 {
594 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
595 return;
596 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
597 val &= AR8216_VTUDATA_MEMBER;
598 val |= AR8216_VTUDATA_VALID;
599 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
600 }
601 op |= AR8216_VTU_ACTIVE;
602 ar8xxx_write(priv, AR8216_REG_VTU, op);
603 }
604
605 static void
606 ar8216_vtu_flush(struct ar8xxx_priv *priv)
607 {
608 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
609 }
610
611 static void
612 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
613 {
614 u32 op;
615
616 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
617 ar8216_vtu_op(priv, op, port_mask);
618 }
619
620 static int
621 ar8216_atu_flush(struct ar8xxx_priv *priv)
622 {
623 int ret;
624
625 ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
626 if (!ret)
627 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_OP_FLUSH |
628 AR8216_ATU_ACTIVE);
629
630 return ret;
631 }
632
633 static int
634 ar8216_atu_flush_port(struct ar8xxx_priv *priv, int port)
635 {
636 u32 t;
637 int ret;
638
639 ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
640 if (!ret) {
641 t = (port << AR8216_ATU_PORT_NUM_S) | AR8216_ATU_OP_FLUSH_PORT;
642 t |= AR8216_ATU_ACTIVE;
643 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, t);
644 }
645
646 return ret;
647 }
648
649 static u32
650 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
651 {
652 return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
653 }
654
655 static void
656 __ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members,
657 bool ath_hdr_en)
658 {
659 u32 header;
660 u32 egress, ingress;
661 u32 pvid;
662
663 if (priv->vlan) {
664 pvid = priv->vlan_id[priv->pvid[port]];
665 if (priv->vlan_tagged & (1 << port))
666 egress = AR8216_OUT_ADD_VLAN;
667 else
668 egress = AR8216_OUT_STRIP_VLAN;
669 ingress = AR8216_IN_SECURE;
670 } else {
671 pvid = port;
672 egress = AR8216_OUT_KEEP;
673 ingress = AR8216_IN_PORT_ONLY;
674 }
675
676 header = ath_hdr_en ? AR8216_PORT_CTRL_HEADER : 0;
677
678 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
679 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
680 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
681 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
682 AR8216_PORT_CTRL_LEARN | header |
683 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
684 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
685
686 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
687 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
688 AR8216_PORT_VLAN_DEFAULT_ID,
689 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
690 (ingress << AR8216_PORT_VLAN_MODE_S) |
691 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
692 }
693
694 static void
695 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
696 {
697 return __ar8216_setup_port(priv, port, members,
698 chip_is_ar8216(priv) && priv->vlan &&
699 port == AR8216_PORT_CPU);
700 }
701
702 static int
703 ar8216_hw_init(struct ar8xxx_priv *priv)
704 {
705 if (priv->initialized)
706 return 0;
707
708 ar8xxx_phy_init(priv);
709
710 priv->initialized = true;
711 return 0;
712 }
713
714 static void
715 ar8216_init_globals(struct ar8xxx_priv *priv)
716 {
717 /* standard atheros magic */
718 ar8xxx_write(priv, 0x38, 0xc000050e);
719
720 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
721 AR8216_GCTRL_MTU, 1518 + 8 + 2);
722 }
723
724 static void
725 __ar8216_init_port(struct ar8xxx_priv *priv, int port,
726 bool cpu_ge, bool flow_en)
727 {
728 /* Enable port learning and tx */
729 ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
730 AR8216_PORT_CTRL_LEARN |
731 (4 << AR8216_PORT_CTRL_STATE_S));
732
733 ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
734
735 if (port == AR8216_PORT_CPU) {
736 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
737 AR8216_PORT_STATUS_LINK_UP |
738 (cpu_ge ? AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
739 AR8216_PORT_STATUS_TXMAC |
740 AR8216_PORT_STATUS_RXMAC |
741 (flow_en ? AR8216_PORT_STATUS_RXFLOW : 0) |
742 (flow_en ? AR8216_PORT_STATUS_TXFLOW : 0) |
743 AR8216_PORT_STATUS_DUPLEX);
744 } else {
745 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
746 AR8216_PORT_STATUS_LINK_AUTO);
747 }
748 }
749
750 static void
751 ar8216_init_port(struct ar8xxx_priv *priv, int port)
752 {
753 __ar8216_init_port(priv, port, ar8xxx_has_gige(priv),
754 chip_is_ar8316(priv));
755 }
756
757 static void
758 ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
759 {
760 int timeout = 20;
761
762 while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout) {
763 udelay(10);
764 cond_resched();
765 }
766
767 if (!timeout)
768 pr_err("ar8216: timeout waiting for atu to become ready\n");
769 }
770
771 static void ar8216_get_arl_entry(struct ar8xxx_priv *priv,
772 struct arl_entry *a, u32 *status, enum arl_op op)
773 {
774 struct mii_bus *bus = priv->mii_bus;
775 u16 r2, page;
776 u16 r1_func0, r1_func1, r1_func2;
777 u32 t, val0, val1, val2;
778
779 split_addr(AR8216_REG_ATU_FUNC0, &r1_func0, &r2, &page);
780 r2 |= 0x10;
781
782 r1_func1 = (AR8216_REG_ATU_FUNC1 >> 1) & 0x1e;
783 r1_func2 = (AR8216_REG_ATU_FUNC2 >> 1) & 0x1e;
784
785 switch (op) {
786 case AR8XXX_ARL_INITIALIZE:
787 /* all ATU registers are on the same page
788 * therefore set page only once
789 */
790 bus->write(bus, 0x18, 0, page);
791 wait_for_page_switch();
792
793 ar8216_wait_atu_ready(priv, r2, r1_func0);
794
795 ar8xxx_mii_write32(priv, r2, r1_func0, AR8216_ATU_OP_GET_NEXT);
796 ar8xxx_mii_write32(priv, r2, r1_func1, 0);
797 ar8xxx_mii_write32(priv, r2, r1_func2, 0);
798 break;
799 case AR8XXX_ARL_GET_NEXT:
800 t = ar8xxx_mii_read32(priv, r2, r1_func0);
801 t |= AR8216_ATU_ACTIVE;
802 ar8xxx_mii_write32(priv, r2, r1_func0, t);
803 ar8216_wait_atu_ready(priv, r2, r1_func0);
804
805 val0 = ar8xxx_mii_read32(priv, r2, r1_func0);
806 val1 = ar8xxx_mii_read32(priv, r2, r1_func1);
807 val2 = ar8xxx_mii_read32(priv, r2, r1_func2);
808
809 *status = (val2 & AR8216_ATU_STATUS) >> AR8216_ATU_STATUS_S;
810 if (!*status)
811 break;
812
813 a->portmap = (val2 & AR8216_ATU_PORTS) >> AR8216_ATU_PORTS_S;
814 a->mac[0] = (val0 & AR8216_ATU_ADDR5) >> AR8216_ATU_ADDR5_S;
815 a->mac[1] = (val0 & AR8216_ATU_ADDR4) >> AR8216_ATU_ADDR4_S;
816 a->mac[2] = (val1 & AR8216_ATU_ADDR3) >> AR8216_ATU_ADDR3_S;
817 a->mac[3] = (val1 & AR8216_ATU_ADDR2) >> AR8216_ATU_ADDR2_S;
818 a->mac[4] = (val1 & AR8216_ATU_ADDR1) >> AR8216_ATU_ADDR1_S;
819 a->mac[5] = (val1 & AR8216_ATU_ADDR0) >> AR8216_ATU_ADDR0_S;
820 break;
821 }
822 }
823
824 static int
825 ar8216_phy_read(struct ar8xxx_priv *priv, int addr, int regnum)
826 {
827 u32 t, val = 0xffff;
828 int err;
829
830 if (addr >= AR8216_NUM_PORTS)
831 return 0xffff;
832 t = (regnum << AR8216_MDIO_CTRL_REG_ADDR_S) |
833 (addr << AR8216_MDIO_CTRL_PHY_ADDR_S) |
834 AR8216_MDIO_CTRL_MASTER_EN |
835 AR8216_MDIO_CTRL_BUSY |
836 AR8216_MDIO_CTRL_CMD_READ;
837
838 ar8xxx_write(priv, AR8216_REG_MDIO_CTRL, t);
839 err = ar8xxx_reg_wait(priv, AR8216_REG_MDIO_CTRL,
840 AR8216_MDIO_CTRL_BUSY, 0, 5);
841 if (!err)
842 val = ar8xxx_read(priv, AR8216_REG_MDIO_CTRL);
843
844 return val & AR8216_MDIO_CTRL_DATA_M;
845 }
846
847 static int
848 ar8216_phy_write(struct ar8xxx_priv *priv, int addr, int regnum, u16 val)
849 {
850 u32 t;
851 int ret;
852
853 if (addr >= AR8216_NUM_PORTS)
854 return -EINVAL;
855
856 t = (addr << AR8216_MDIO_CTRL_PHY_ADDR_S) |
857 (regnum << AR8216_MDIO_CTRL_REG_ADDR_S) |
858 AR8216_MDIO_CTRL_MASTER_EN |
859 AR8216_MDIO_CTRL_BUSY |
860 AR8216_MDIO_CTRL_CMD_WRITE |
861 val;
862
863 ar8xxx_write(priv, AR8216_REG_MDIO_CTRL, t);
864 ret = ar8xxx_reg_wait(priv, AR8216_REG_MDIO_CTRL,
865 AR8216_MDIO_CTRL_BUSY, 0, 5);
866
867 return ret;
868 }
869
870 static int
871 ar8229_hw_init(struct ar8xxx_priv *priv)
872 {
873 int phy_if_mode;
874
875 if (priv->initialized)
876 return 0;
877
878 ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
879 ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
880
881 phy_if_mode = of_get_phy_mode(priv->pdev->of_node);
882
883 if (phy_if_mode == PHY_INTERFACE_MODE_GMII) {
884 ar8xxx_write(priv, AR8229_REG_OPER_MODE0,
885 AR8229_OPER_MODE0_MAC_GMII_EN);
886 } else if (phy_if_mode == PHY_INTERFACE_MODE_MII) {
887 ar8xxx_write(priv, AR8229_REG_OPER_MODE0,
888 AR8229_OPER_MODE0_PHY_MII_EN);
889 } else {
890 pr_err("ar8229: unsupported mii mode\n");
891 return -EINVAL;
892 }
893
894 if (priv->port4_phy) {
895 ar8xxx_write(priv, AR8229_REG_OPER_MODE1,
896 AR8229_REG_OPER_MODE1_PHY4_MII_EN);
897 /* disable port5 to prevent mii conflict */
898 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(5), 0);
899 }
900
901 ar8xxx_phy_init(priv);
902
903 priv->initialized = true;
904 return 0;
905 }
906
907 static void
908 ar8229_init_globals(struct ar8xxx_priv *priv)
909 {
910
911 /* Enable CPU port, and disable mirror port */
912 ar8xxx_write(priv, AR8216_REG_GLOBAL_CPUPORT,
913 AR8216_GLOBAL_CPUPORT_EN |
914 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
915
916 /* Setup TAG priority mapping */
917 ar8xxx_write(priv, AR8216_REG_TAG_PRIORITY, 0xfa50);
918
919 /* Enable aging, MAC replacing */
920 ar8xxx_write(priv, AR8216_REG_ATU_CTRL,
921 0x2b /* 5 min age time */ |
922 AR8216_ATU_CTRL_AGE_EN |
923 AR8216_ATU_CTRL_LEARN_CHANGE);
924
925 /* Enable ARP frame acknowledge */
926 ar8xxx_reg_set(priv, AR8229_REG_QM_CTRL,
927 AR8229_QM_CTRL_ARP_EN);
928
929 /* Enable Broadcast/Multicast frames transmitted to the CPU */
930 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
931 AR8229_FLOOD_MASK_BC_DP(0) |
932 AR8229_FLOOD_MASK_MC_DP(0));
933
934 /* setup MTU */
935 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
936 AR8236_GCTRL_MTU, AR8236_GCTRL_MTU);
937
938 /* Enable MIB counters */
939 ar8xxx_reg_set(priv, AR8216_REG_MIB_FUNC,
940 AR8236_MIB_EN);
941
942 /* setup Service TAG */
943 ar8xxx_rmw(priv, AR8216_REG_SERVICE_TAG, AR8216_SERVICE_TAG_M, 0);
944 }
945
946 static void
947 ar8229_init_port(struct ar8xxx_priv *priv, int port)
948 {
949 __ar8216_init_port(priv, port, true, true);
950 }
951
952
953 static int
954 ar7240sw_hw_init(struct ar8xxx_priv *priv)
955 {
956 if (priv->initialized)
957 return 0;
958
959 ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
960 ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
961
962 priv->port4_phy = 1;
963 /* disable port5 to prevent mii conflict */
964 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(5), 0);
965
966 ar8xxx_phy_init(priv);
967
968 priv->initialized = true;
969 return 0;
970 }
971
972 static void
973 ar7240sw_init_globals(struct ar8xxx_priv *priv)
974 {
975
976 /* Enable CPU port, and disable mirror port */
977 ar8xxx_write(priv, AR8216_REG_GLOBAL_CPUPORT,
978 AR8216_GLOBAL_CPUPORT_EN |
979 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
980
981 /* Setup TAG priority mapping */
982 ar8xxx_write(priv, AR8216_REG_TAG_PRIORITY, 0xfa50);
983
984 /* Enable ARP frame acknowledge, aging, MAC replacing */
985 ar8xxx_write(priv, AR8216_REG_ATU_CTRL,
986 AR8216_ATU_CTRL_RESERVED |
987 0x2b /* 5 min age time */ |
988 AR8216_ATU_CTRL_AGE_EN |
989 AR8216_ATU_CTRL_ARP_EN |
990 AR8216_ATU_CTRL_LEARN_CHANGE);
991
992 /* Enable Broadcast frames transmitted to the CPU */
993 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
994 AR8236_FM_CPU_BROADCAST_EN);
995
996 /* setup MTU */
997 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
998 AR8216_GCTRL_MTU,
999 AR8216_GCTRL_MTU);
1000
1001 /* setup Service TAG */
1002 ar8xxx_rmw(priv, AR8216_REG_SERVICE_TAG, AR8216_SERVICE_TAG_M, 0);
1003 }
1004
1005 static void
1006 ar7240sw_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1007 {
1008 return __ar8216_setup_port(priv, port, members, false);
1009 }
1010
1011 static void
1012 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1013 {
1014 u32 egress, ingress;
1015 u32 pvid;
1016
1017 if (priv->vlan) {
1018 pvid = priv->vlan_id[priv->pvid[port]];
1019 if (priv->vlan_tagged & (1 << port))
1020 egress = AR8216_OUT_ADD_VLAN;
1021 else
1022 egress = AR8216_OUT_STRIP_VLAN;
1023 ingress = AR8216_IN_SECURE;
1024 } else {
1025 pvid = port;
1026 egress = AR8216_OUT_KEEP;
1027 ingress = AR8216_IN_PORT_ONLY;
1028 }
1029
1030 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
1031 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
1032 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
1033 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
1034 AR8216_PORT_CTRL_LEARN |
1035 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
1036 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
1037
1038 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
1039 AR8236_PORT_VLAN_DEFAULT_ID,
1040 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
1041
1042 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
1043 AR8236_PORT_VLAN2_VLAN_MODE |
1044 AR8236_PORT_VLAN2_MEMBER,
1045 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
1046 (members << AR8236_PORT_VLAN2_MEMBER_S));
1047 }
1048
1049 static void
1050 ar8236_init_globals(struct ar8xxx_priv *priv)
1051 {
1052 /* enable jumbo frames */
1053 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1054 AR8316_GCTRL_MTU, 9018 + 8 + 2);
1055
1056 /* enable cpu port to receive arp frames */
1057 ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
1058 AR8236_ATU_CTRL_RES);
1059
1060 /* enable cpu port to receive multicast and broadcast frames */
1061 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
1062 AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
1063
1064 /* Enable MIB counters */
1065 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1066 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1067 AR8236_MIB_EN);
1068 }
1069
1070 static int
1071 ar8316_hw_init(struct ar8xxx_priv *priv)
1072 {
1073 u32 val, newval;
1074
1075 val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
1076
1077 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
1078 if (priv->port4_phy) {
1079 /* value taken from Ubiquiti RouterStation Pro */
1080 newval = 0x81461bea;
1081 pr_info("ar8316: Using port 4 as PHY\n");
1082 } else {
1083 newval = 0x01261be2;
1084 pr_info("ar8316: Using port 4 as switch port\n");
1085 }
1086 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
1087 /* value taken from AVM Fritz!Box 7390 sources */
1088 newval = 0x010e5b71;
1089 } else {
1090 /* no known value for phy interface */
1091 pr_err("ar8316: unsupported mii mode: %d.\n",
1092 priv->phy->interface);
1093 return -EINVAL;
1094 }
1095
1096 if (val == newval)
1097 goto out;
1098
1099 ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
1100
1101 if (priv->port4_phy &&
1102 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
1103 /* work around for phy4 rgmii mode */
1104 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
1105 /* rx delay */
1106 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
1107 /* tx delay */
1108 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
1109 msleep(1000);
1110 }
1111
1112 ar8xxx_phy_init(priv);
1113
1114 out:
1115 priv->initialized = true;
1116 return 0;
1117 }
1118
1119 static void
1120 ar8316_init_globals(struct ar8xxx_priv *priv)
1121 {
1122 /* standard atheros magic */
1123 ar8xxx_write(priv, 0x38, 0xc000050e);
1124
1125 /* enable cpu port to receive multicast and broadcast frames */
1126 ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
1127
1128 /* enable jumbo frames */
1129 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1130 AR8316_GCTRL_MTU, 9018 + 8 + 2);
1131
1132 /* Enable MIB counters */
1133 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1134 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1135 AR8236_MIB_EN);
1136 }
1137
1138 int
1139 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1140 struct switch_val *val)
1141 {
1142 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1143 priv->vlan = !!val->value.i;
1144 return 0;
1145 }
1146
1147 int
1148 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1149 struct switch_val *val)
1150 {
1151 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1152 val->value.i = priv->vlan;
1153 return 0;
1154 }
1155
1156
1157 int
1158 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1159 {
1160 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1161
1162 /* make sure no invalid PVIDs get set */
1163
1164 if (vlan < 0 || vlan >= dev->vlans ||
1165 port < 0 || port >= AR8X16_MAX_PORTS)
1166 return -EINVAL;
1167
1168 priv->pvid[port] = vlan;
1169 return 0;
1170 }
1171
1172 int
1173 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1174 {
1175 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1176
1177 if (port < 0 || port >= AR8X16_MAX_PORTS)
1178 return -EINVAL;
1179
1180 *vlan = priv->pvid[port];
1181 return 0;
1182 }
1183
1184 static int
1185 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1186 struct switch_val *val)
1187 {
1188 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1189
1190 if (val->port_vlan >= AR8X16_MAX_VLANS)
1191 return -EINVAL;
1192
1193 priv->vlan_id[val->port_vlan] = val->value.i;
1194 return 0;
1195 }
1196
1197 static int
1198 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1199 struct switch_val *val)
1200 {
1201 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1202 val->value.i = priv->vlan_id[val->port_vlan];
1203 return 0;
1204 }
1205
1206 int
1207 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1208 struct switch_port_link *link)
1209 {
1210 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1211
1212 ar8216_read_port_link(priv, port, link);
1213 return 0;
1214 }
1215
1216 static int
1217 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1218 {
1219 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1220 u8 ports;
1221 int i;
1222
1223 if (val->port_vlan >= AR8X16_MAX_VLANS)
1224 return -EINVAL;
1225
1226 ports = priv->vlan_table[val->port_vlan];
1227 val->len = 0;
1228 for (i = 0; i < dev->ports; i++) {
1229 struct switch_port *p;
1230
1231 if (!(ports & (1 << i)))
1232 continue;
1233
1234 p = &val->value.ports[val->len++];
1235 p->id = i;
1236 if (priv->vlan_tagged & (1 << i))
1237 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1238 else
1239 p->flags = 0;
1240 }
1241 return 0;
1242 }
1243
1244 static int
1245 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1246 {
1247 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1248 u8 *vt = &priv->vlan_table[val->port_vlan];
1249 int i, j;
1250
1251 *vt = 0;
1252 for (i = 0; i < val->len; i++) {
1253 struct switch_port *p = &val->value.ports[i];
1254
1255 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1256 priv->vlan_tagged |= (1 << p->id);
1257 } else {
1258 priv->vlan_tagged &= ~(1 << p->id);
1259 priv->pvid[p->id] = val->port_vlan;
1260
1261 /* make sure that an untagged port does not
1262 * appear in other vlans */
1263 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1264 if (j == val->port_vlan)
1265 continue;
1266 priv->vlan_table[j] &= ~(1 << p->id);
1267 }
1268 }
1269
1270 *vt |= 1 << p->id;
1271 }
1272 return 0;
1273 }
1274
1275 static void
1276 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1277 {
1278 int port;
1279
1280 /* reset all mirror registers */
1281 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1282 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1283 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1284 for (port = 0; port < AR8216_NUM_PORTS; port++) {
1285 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1286 AR8216_PORT_CTRL_MIRROR_RX);
1287
1288 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1289 AR8216_PORT_CTRL_MIRROR_TX);
1290 }
1291
1292 /* now enable mirroring if necessary */
1293 if (priv->source_port >= AR8216_NUM_PORTS ||
1294 priv->monitor_port >= AR8216_NUM_PORTS ||
1295 priv->source_port == priv->monitor_port) {
1296 return;
1297 }
1298
1299 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1300 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1301 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1302
1303 if (priv->mirror_rx)
1304 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1305 AR8216_PORT_CTRL_MIRROR_RX);
1306
1307 if (priv->mirror_tx)
1308 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1309 AR8216_PORT_CTRL_MIRROR_TX);
1310 }
1311
1312 static inline u32
1313 ar8xxx_age_time_val(int age_time)
1314 {
1315 return (age_time + AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS / 2) /
1316 AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS;
1317 }
1318
1319 static inline void
1320 ar8xxx_set_age_time(struct ar8xxx_priv *priv, int reg)
1321 {
1322 u32 age_time = ar8xxx_age_time_val(priv->arl_age_time);
1323 ar8xxx_rmw(priv, reg, AR8216_ATU_CTRL_AGE_TIME, age_time << AR8216_ATU_CTRL_AGE_TIME_S);
1324 }
1325
1326 int
1327 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1328 {
1329 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1330 const struct ar8xxx_chip *chip = priv->chip;
1331 u8 portmask[AR8X16_MAX_PORTS];
1332 int i, j;
1333
1334 mutex_lock(&priv->reg_mutex);
1335 /* flush all vlan translation unit entries */
1336 priv->chip->vtu_flush(priv);
1337
1338 memset(portmask, 0, sizeof(portmask));
1339 if (!priv->init) {
1340 /* calculate the port destination masks and load vlans
1341 * into the vlan translation unit */
1342 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1343 u8 vp = priv->vlan_table[j];
1344
1345 if (!vp)
1346 continue;
1347
1348 for (i = 0; i < dev->ports; i++) {
1349 u8 mask = (1 << i);
1350 if (vp & mask)
1351 portmask[i] |= vp & ~mask;
1352 }
1353
1354 chip->vtu_load_vlan(priv, priv->vlan_id[j],
1355 priv->vlan_table[j]);
1356 }
1357 } else {
1358 /* vlan disabled:
1359 * isolate all ports, but connect them to the cpu port */
1360 for (i = 0; i < dev->ports; i++) {
1361 if (i == AR8216_PORT_CPU)
1362 continue;
1363
1364 portmask[i] = 1 << AR8216_PORT_CPU;
1365 portmask[AR8216_PORT_CPU] |= (1 << i);
1366 }
1367 }
1368
1369 /* update the port destination mask registers and tag settings */
1370 for (i = 0; i < dev->ports; i++) {
1371 chip->setup_port(priv, i, portmask[i]);
1372 }
1373
1374 chip->set_mirror_regs(priv);
1375
1376 /* set age time */
1377 if (chip->reg_arl_ctrl)
1378 ar8xxx_set_age_time(priv, chip->reg_arl_ctrl);
1379
1380 mutex_unlock(&priv->reg_mutex);
1381 return 0;
1382 }
1383
1384 int
1385 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1386 {
1387 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1388 const struct ar8xxx_chip *chip = priv->chip;
1389 int i;
1390
1391 mutex_lock(&priv->reg_mutex);
1392 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1393 offsetof(struct ar8xxx_priv, vlan));
1394
1395 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1396 priv->vlan_id[i] = i;
1397
1398 /* Configure all ports */
1399 for (i = 0; i < dev->ports; i++)
1400 chip->init_port(priv, i);
1401
1402 priv->mirror_rx = false;
1403 priv->mirror_tx = false;
1404 priv->source_port = 0;
1405 priv->monitor_port = 0;
1406 priv->arl_age_time = AR8XXX_DEFAULT_ARL_AGE_TIME;
1407
1408 chip->init_globals(priv);
1409 chip->atu_flush(priv);
1410
1411 mutex_unlock(&priv->reg_mutex);
1412
1413 return chip->sw_hw_apply(dev);
1414 }
1415
1416 int
1417 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1418 const struct switch_attr *attr,
1419 struct switch_val *val)
1420 {
1421 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1422 unsigned int len;
1423 int ret;
1424
1425 if (!ar8xxx_has_mib_counters(priv))
1426 return -EOPNOTSUPP;
1427
1428 mutex_lock(&priv->mib_lock);
1429
1430 len = priv->dev.ports * priv->chip->num_mibs *
1431 sizeof(*priv->mib_stats);
1432 memset(priv->mib_stats, '\0', len);
1433 ret = ar8xxx_mib_flush(priv);
1434 if (ret)
1435 goto unlock;
1436
1437 ret = 0;
1438
1439 unlock:
1440 mutex_unlock(&priv->mib_lock);
1441 return ret;
1442 }
1443
1444 int
1445 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1446 const struct switch_attr *attr,
1447 struct switch_val *val)
1448 {
1449 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1450
1451 mutex_lock(&priv->reg_mutex);
1452 priv->mirror_rx = !!val->value.i;
1453 priv->chip->set_mirror_regs(priv);
1454 mutex_unlock(&priv->reg_mutex);
1455
1456 return 0;
1457 }
1458
1459 int
1460 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1461 const struct switch_attr *attr,
1462 struct switch_val *val)
1463 {
1464 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1465 val->value.i = priv->mirror_rx;
1466 return 0;
1467 }
1468
1469 int
1470 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1471 const struct switch_attr *attr,
1472 struct switch_val *val)
1473 {
1474 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1475
1476 mutex_lock(&priv->reg_mutex);
1477 priv->mirror_tx = !!val->value.i;
1478 priv->chip->set_mirror_regs(priv);
1479 mutex_unlock(&priv->reg_mutex);
1480
1481 return 0;
1482 }
1483
1484 int
1485 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1486 const struct switch_attr *attr,
1487 struct switch_val *val)
1488 {
1489 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1490 val->value.i = priv->mirror_tx;
1491 return 0;
1492 }
1493
1494 int
1495 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1496 const struct switch_attr *attr,
1497 struct switch_val *val)
1498 {
1499 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1500
1501 mutex_lock(&priv->reg_mutex);
1502 priv->monitor_port = val->value.i;
1503 priv->chip->set_mirror_regs(priv);
1504 mutex_unlock(&priv->reg_mutex);
1505
1506 return 0;
1507 }
1508
1509 int
1510 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1511 const struct switch_attr *attr,
1512 struct switch_val *val)
1513 {
1514 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1515 val->value.i = priv->monitor_port;
1516 return 0;
1517 }
1518
1519 int
1520 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1521 const struct switch_attr *attr,
1522 struct switch_val *val)
1523 {
1524 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1525
1526 mutex_lock(&priv->reg_mutex);
1527 priv->source_port = val->value.i;
1528 priv->chip->set_mirror_regs(priv);
1529 mutex_unlock(&priv->reg_mutex);
1530
1531 return 0;
1532 }
1533
1534 int
1535 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1536 const struct switch_attr *attr,
1537 struct switch_val *val)
1538 {
1539 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1540 val->value.i = priv->source_port;
1541 return 0;
1542 }
1543
1544 int
1545 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1546 const struct switch_attr *attr,
1547 struct switch_val *val)
1548 {
1549 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1550 int port;
1551 int ret;
1552
1553 if (!ar8xxx_has_mib_counters(priv))
1554 return -EOPNOTSUPP;
1555
1556 port = val->port_vlan;
1557 if (port >= dev->ports)
1558 return -EINVAL;
1559
1560 mutex_lock(&priv->mib_lock);
1561 ret = ar8xxx_mib_capture(priv);
1562 if (ret)
1563 goto unlock;
1564
1565 ar8xxx_mib_fetch_port_stat(priv, port, true);
1566
1567 ret = 0;
1568
1569 unlock:
1570 mutex_unlock(&priv->mib_lock);
1571 return ret;
1572 }
1573
1574 static void
1575 ar8xxx_byte_to_str(char *buf, int len, u64 byte)
1576 {
1577 unsigned long b;
1578 const char *unit;
1579
1580 if (byte >= 0x40000000) { /* 1 GiB */
1581 b = byte * 10 / 0x40000000;
1582 unit = "GiB";
1583 } else if (byte >= 0x100000) { /* 1 MiB */
1584 b = byte * 10 / 0x100000;
1585 unit = "MiB";
1586 } else if (byte >= 0x400) { /* 1 KiB */
1587 b = byte * 10 / 0x400;
1588 unit = "KiB";
1589 } else {
1590 b = byte;
1591 unit = "Byte";
1592 }
1593 if (strcmp(unit, "Byte"))
1594 snprintf(buf, len, "%lu.%lu %s", b / 10, b % 10, unit);
1595 else
1596 snprintf(buf, len, "%lu %s", b, unit);
1597 }
1598
1599 int
1600 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1601 const struct switch_attr *attr,
1602 struct switch_val *val)
1603 {
1604 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1605 const struct ar8xxx_chip *chip = priv->chip;
1606 u64 *mib_stats, mib_data;
1607 unsigned int port;
1608 int ret;
1609 char *buf = priv->buf;
1610 char buf1[64];
1611 const char *mib_name;
1612 int i, len = 0;
1613 bool mib_stats_empty = true;
1614
1615 if (!ar8xxx_has_mib_counters(priv))
1616 return -EOPNOTSUPP;
1617
1618 port = val->port_vlan;
1619 if (port >= dev->ports)
1620 return -EINVAL;
1621
1622 mutex_lock(&priv->mib_lock);
1623 ret = ar8xxx_mib_capture(priv);
1624 if (ret)
1625 goto unlock;
1626
1627 ar8xxx_mib_fetch_port_stat(priv, port, false);
1628
1629 len += snprintf(buf + len, sizeof(priv->buf) - len,
1630 "MIB counters\n");
1631
1632 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1633 for (i = 0; i < chip->num_mibs; i++) {
1634 mib_name = chip->mib_decs[i].name;
1635 mib_data = mib_stats[i];
1636 len += snprintf(buf + len, sizeof(priv->buf) - len,
1637 "%-12s: %llu\n", mib_name, mib_data);
1638 if ((!strcmp(mib_name, "TxByte") ||
1639 !strcmp(mib_name, "RxGoodByte")) &&
1640 mib_data >= 1024) {
1641 ar8xxx_byte_to_str(buf1, sizeof(buf1), mib_data);
1642 --len; /* discard newline at the end of buf */
1643 len += snprintf(buf + len, sizeof(priv->buf) - len,
1644 " (%s)\n", buf1);
1645 }
1646 if (mib_stats_empty && mib_data)
1647 mib_stats_empty = false;
1648 }
1649
1650 if (mib_stats_empty)
1651 len = snprintf(buf, sizeof(priv->buf), "No MIB data");
1652
1653 val->value.s = buf;
1654 val->len = len;
1655
1656 ret = 0;
1657
1658 unlock:
1659 mutex_unlock(&priv->mib_lock);
1660 return ret;
1661 }
1662
1663 int
1664 ar8xxx_sw_set_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1665 struct switch_val *val)
1666 {
1667 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1668 int age_time = val->value.i;
1669 u32 age_time_val;
1670
1671 if (age_time < 0)
1672 return -EINVAL;
1673
1674 age_time_val = ar8xxx_age_time_val(age_time);
1675 if (age_time_val == 0 || age_time_val > 0xffff)
1676 return -EINVAL;
1677
1678 priv->arl_age_time = age_time;
1679 return 0;
1680 }
1681
1682 int
1683 ar8xxx_sw_get_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1684 struct switch_val *val)
1685 {
1686 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1687 val->value.i = priv->arl_age_time;
1688 return 0;
1689 }
1690
1691 int
1692 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
1693 const struct switch_attr *attr,
1694 struct switch_val *val)
1695 {
1696 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1697 struct mii_bus *bus = priv->mii_bus;
1698 const struct ar8xxx_chip *chip = priv->chip;
1699 char *buf = priv->arl_buf;
1700 int i, j, k, len = 0;
1701 struct arl_entry *a, *a1;
1702 u32 status;
1703
1704 if (!chip->get_arl_entry)
1705 return -EOPNOTSUPP;
1706
1707 mutex_lock(&priv->reg_mutex);
1708 mutex_lock(&bus->mdio_lock);
1709
1710 chip->get_arl_entry(priv, NULL, NULL, AR8XXX_ARL_INITIALIZE);
1711
1712 for(i = 0; i < AR8XXX_NUM_ARL_RECORDS; ++i) {
1713 a = &priv->arl_table[i];
1714 duplicate:
1715 chip->get_arl_entry(priv, a, &status, AR8XXX_ARL_GET_NEXT);
1716
1717 if (!status)
1718 break;
1719
1720 /* avoid duplicates
1721 * ARL table can include multiple valid entries
1722 * per MAC, just with differing status codes
1723 */
1724 for (j = 0; j < i; ++j) {
1725 a1 = &priv->arl_table[j];
1726 if (!memcmp(a->mac, a1->mac, sizeof(a->mac))) {
1727 /* ignore ports already seen in former entry */
1728 a->portmap &= ~a1->portmap;
1729 if (!a->portmap)
1730 goto duplicate;
1731 }
1732 }
1733 }
1734
1735 mutex_unlock(&bus->mdio_lock);
1736
1737 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1738 "address resolution table\n");
1739
1740 if (i == AR8XXX_NUM_ARL_RECORDS)
1741 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1742 "Too many entries found, displaying the first %d only!\n",
1743 AR8XXX_NUM_ARL_RECORDS);
1744
1745 for (j = 0; j < priv->dev.ports; ++j) {
1746 for (k = 0; k < i; ++k) {
1747 a = &priv->arl_table[k];
1748 if (!(a->portmap & BIT(j)))
1749 continue;
1750 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1751 "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1752 j,
1753 a->mac[5], a->mac[4], a->mac[3],
1754 a->mac[2], a->mac[1], a->mac[0]);
1755 }
1756 }
1757
1758 val->value.s = buf;
1759 val->len = len;
1760
1761 mutex_unlock(&priv->reg_mutex);
1762
1763 return 0;
1764 }
1765
1766 int
1767 ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,
1768 const struct switch_attr *attr,
1769 struct switch_val *val)
1770 {
1771 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1772 int ret;
1773
1774 mutex_lock(&priv->reg_mutex);
1775 ret = priv->chip->atu_flush(priv);
1776 mutex_unlock(&priv->reg_mutex);
1777
1778 return ret;
1779 }
1780
1781 int
1782 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
1783 const struct switch_attr *attr,
1784 struct switch_val *val)
1785 {
1786 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1787 int port, ret;
1788
1789 port = val->port_vlan;
1790 if (port >= dev->ports)
1791 return -EINVAL;
1792
1793 mutex_lock(&priv->reg_mutex);
1794 ret = priv->chip->atu_flush_port(priv, port);
1795 mutex_unlock(&priv->reg_mutex);
1796
1797 return ret;
1798 }
1799
1800 int
1801 ar8xxx_sw_get_port_stats(struct switch_dev *dev, int port,
1802 struct switch_port_stats *stats)
1803 {
1804 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1805 u64 *mib_stats;
1806
1807 if (!ar8xxx_has_mib_counters(priv))
1808 return -EOPNOTSUPP;
1809
1810 if (!(priv->chip->mib_rxb_id || priv->chip->mib_txb_id))
1811 return -EOPNOTSUPP;
1812
1813 if (port >= dev->ports)
1814 return -EINVAL;
1815
1816 mutex_lock(&priv->mib_lock);
1817
1818 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
1819
1820 stats->tx_bytes = mib_stats[priv->chip->mib_txb_id];
1821 stats->rx_bytes = mib_stats[priv->chip->mib_rxb_id];
1822
1823 mutex_unlock(&priv->mib_lock);
1824 return 0;
1825 }
1826
1827 static int
1828 ar8xxx_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr)
1829 {
1830 struct ar8xxx_priv *priv = bus->priv;
1831 return priv->chip->phy_read(priv, phy_addr, reg_addr);
1832 }
1833
1834 static int
1835 ar8xxx_phy_write(struct mii_bus *bus, int phy_addr, int reg_addr,
1836 u16 reg_val)
1837 {
1838 struct ar8xxx_priv *priv = bus->priv;
1839 return priv->chip->phy_write(priv, phy_addr, reg_addr, reg_val);
1840 }
1841
1842 static const struct switch_attr ar8xxx_sw_attr_globals[] = {
1843 {
1844 .type = SWITCH_TYPE_INT,
1845 .name = "enable_vlan",
1846 .description = "Enable VLAN mode",
1847 .set = ar8xxx_sw_set_vlan,
1848 .get = ar8xxx_sw_get_vlan,
1849 .max = 1
1850 },
1851 {
1852 .type = SWITCH_TYPE_NOVAL,
1853 .name = "reset_mibs",
1854 .description = "Reset all MIB counters",
1855 .set = ar8xxx_sw_set_reset_mibs,
1856 },
1857 {
1858 .type = SWITCH_TYPE_INT,
1859 .name = "enable_mirror_rx",
1860 .description = "Enable mirroring of RX packets",
1861 .set = ar8xxx_sw_set_mirror_rx_enable,
1862 .get = ar8xxx_sw_get_mirror_rx_enable,
1863 .max = 1
1864 },
1865 {
1866 .type = SWITCH_TYPE_INT,
1867 .name = "enable_mirror_tx",
1868 .description = "Enable mirroring of TX packets",
1869 .set = ar8xxx_sw_set_mirror_tx_enable,
1870 .get = ar8xxx_sw_get_mirror_tx_enable,
1871 .max = 1
1872 },
1873 {
1874 .type = SWITCH_TYPE_INT,
1875 .name = "mirror_monitor_port",
1876 .description = "Mirror monitor port",
1877 .set = ar8xxx_sw_set_mirror_monitor_port,
1878 .get = ar8xxx_sw_get_mirror_monitor_port,
1879 .max = AR8216_NUM_PORTS - 1
1880 },
1881 {
1882 .type = SWITCH_TYPE_INT,
1883 .name = "mirror_source_port",
1884 .description = "Mirror source port",
1885 .set = ar8xxx_sw_set_mirror_source_port,
1886 .get = ar8xxx_sw_get_mirror_source_port,
1887 .max = AR8216_NUM_PORTS - 1
1888 },
1889 {
1890 .type = SWITCH_TYPE_STRING,
1891 .name = "arl_table",
1892 .description = "Get ARL table",
1893 .set = NULL,
1894 .get = ar8xxx_sw_get_arl_table,
1895 },
1896 {
1897 .type = SWITCH_TYPE_NOVAL,
1898 .name = "flush_arl_table",
1899 .description = "Flush ARL table",
1900 .set = ar8xxx_sw_set_flush_arl_table,
1901 },
1902 };
1903
1904 const struct switch_attr ar8xxx_sw_attr_port[] = {
1905 {
1906 .type = SWITCH_TYPE_NOVAL,
1907 .name = "reset_mib",
1908 .description = "Reset single port MIB counters",
1909 .set = ar8xxx_sw_set_port_reset_mib,
1910 },
1911 {
1912 .type = SWITCH_TYPE_STRING,
1913 .name = "mib",
1914 .description = "Get port's MIB counters",
1915 .set = NULL,
1916 .get = ar8xxx_sw_get_port_mib,
1917 },
1918 {
1919 .type = SWITCH_TYPE_NOVAL,
1920 .name = "flush_arl_table",
1921 .description = "Flush port's ARL table entries",
1922 .set = ar8xxx_sw_set_flush_port_arl_table,
1923 },
1924 };
1925
1926 const struct switch_attr ar8xxx_sw_attr_vlan[1] = {
1927 {
1928 .type = SWITCH_TYPE_INT,
1929 .name = "vid",
1930 .description = "VLAN ID (0-4094)",
1931 .set = ar8xxx_sw_set_vid,
1932 .get = ar8xxx_sw_get_vid,
1933 .max = 4094,
1934 },
1935 };
1936
1937 static const struct switch_dev_ops ar8xxx_sw_ops = {
1938 .attr_global = {
1939 .attr = ar8xxx_sw_attr_globals,
1940 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1941 },
1942 .attr_port = {
1943 .attr = ar8xxx_sw_attr_port,
1944 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1945 },
1946 .attr_vlan = {
1947 .attr = ar8xxx_sw_attr_vlan,
1948 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1949 },
1950 .get_port_pvid = ar8xxx_sw_get_pvid,
1951 .set_port_pvid = ar8xxx_sw_set_pvid,
1952 .get_vlan_ports = ar8xxx_sw_get_ports,
1953 .set_vlan_ports = ar8xxx_sw_set_ports,
1954 .apply_config = ar8xxx_sw_hw_apply,
1955 .reset_switch = ar8xxx_sw_reset_switch,
1956 .get_port_link = ar8xxx_sw_get_port_link,
1957 .get_port_stats = ar8xxx_sw_get_port_stats,
1958 };
1959
1960 static const struct ar8xxx_chip ar7240sw_chip = {
1961 .caps = AR8XXX_CAP_MIB_COUNTERS,
1962
1963 .reg_port_stats_start = 0x20000,
1964 .reg_port_stats_length = 0x100,
1965 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1966
1967 .name = "Atheros AR724X/AR933X built-in",
1968 .ports = AR7240SW_NUM_PORTS,
1969 .vlans = AR8216_NUM_VLANS,
1970 .swops = &ar8xxx_sw_ops,
1971
1972 .hw_init = ar7240sw_hw_init,
1973 .init_globals = ar7240sw_init_globals,
1974 .init_port = ar8229_init_port,
1975 .phy_read = ar8216_phy_read,
1976 .phy_write = ar8216_phy_write,
1977 .setup_port = ar7240sw_setup_port,
1978 .read_port_status = ar8216_read_port_status,
1979 .atu_flush = ar8216_atu_flush,
1980 .atu_flush_port = ar8216_atu_flush_port,
1981 .vtu_flush = ar8216_vtu_flush,
1982 .vtu_load_vlan = ar8216_vtu_load_vlan,
1983 .set_mirror_regs = ar8216_set_mirror_regs,
1984 .get_arl_entry = ar8216_get_arl_entry,
1985 .sw_hw_apply = ar8xxx_sw_hw_apply,
1986
1987 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1988 .mib_decs = ar8236_mibs,
1989 .mib_func = AR8216_REG_MIB_FUNC,
1990 .mib_rxb_id = AR8236_MIB_RXB_ID,
1991 .mib_txb_id = AR8236_MIB_TXB_ID,
1992 };
1993
1994 static const struct ar8xxx_chip ar8216_chip = {
1995 .caps = AR8XXX_CAP_MIB_COUNTERS,
1996
1997 .reg_port_stats_start = 0x19000,
1998 .reg_port_stats_length = 0xa0,
1999 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2000
2001 .name = "Atheros AR8216",
2002 .ports = AR8216_NUM_PORTS,
2003 .vlans = AR8216_NUM_VLANS,
2004 .swops = &ar8xxx_sw_ops,
2005
2006 .hw_init = ar8216_hw_init,
2007 .init_globals = ar8216_init_globals,
2008 .init_port = ar8216_init_port,
2009 .setup_port = ar8216_setup_port,
2010 .read_port_status = ar8216_read_port_status,
2011 .atu_flush = ar8216_atu_flush,
2012 .atu_flush_port = ar8216_atu_flush_port,
2013 .vtu_flush = ar8216_vtu_flush,
2014 .vtu_load_vlan = ar8216_vtu_load_vlan,
2015 .set_mirror_regs = ar8216_set_mirror_regs,
2016 .get_arl_entry = ar8216_get_arl_entry,
2017 .sw_hw_apply = ar8xxx_sw_hw_apply,
2018
2019 .num_mibs = ARRAY_SIZE(ar8216_mibs),
2020 .mib_decs = ar8216_mibs,
2021 .mib_func = AR8216_REG_MIB_FUNC,
2022 .mib_rxb_id = AR8216_MIB_RXB_ID,
2023 .mib_txb_id = AR8216_MIB_TXB_ID,
2024 };
2025
2026 static const struct ar8xxx_chip ar8229_chip = {
2027 .caps = AR8XXX_CAP_MIB_COUNTERS,
2028
2029 .reg_port_stats_start = 0x20000,
2030 .reg_port_stats_length = 0x100,
2031 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2032
2033 .name = "Atheros AR8229",
2034 .ports = AR8216_NUM_PORTS,
2035 .vlans = AR8216_NUM_VLANS,
2036 .swops = &ar8xxx_sw_ops,
2037
2038 .hw_init = ar8229_hw_init,
2039 .init_globals = ar8229_init_globals,
2040 .init_port = ar8229_init_port,
2041 .phy_read = ar8216_phy_read,
2042 .phy_write = ar8216_phy_write,
2043 .setup_port = ar8236_setup_port,
2044 .read_port_status = ar8216_read_port_status,
2045 .atu_flush = ar8216_atu_flush,
2046 .atu_flush_port = ar8216_atu_flush_port,
2047 .vtu_flush = ar8216_vtu_flush,
2048 .vtu_load_vlan = ar8216_vtu_load_vlan,
2049 .set_mirror_regs = ar8216_set_mirror_regs,
2050 .get_arl_entry = ar8216_get_arl_entry,
2051 .sw_hw_apply = ar8xxx_sw_hw_apply,
2052
2053 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2054 .mib_decs = ar8236_mibs,
2055 .mib_func = AR8216_REG_MIB_FUNC,
2056 .mib_rxb_id = AR8236_MIB_RXB_ID,
2057 .mib_txb_id = AR8236_MIB_TXB_ID,
2058 };
2059
2060 static const struct ar8xxx_chip ar8236_chip = {
2061 .caps = AR8XXX_CAP_MIB_COUNTERS,
2062
2063 .reg_port_stats_start = 0x20000,
2064 .reg_port_stats_length = 0x100,
2065 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2066
2067 .name = "Atheros AR8236",
2068 .ports = AR8216_NUM_PORTS,
2069 .vlans = AR8216_NUM_VLANS,
2070 .swops = &ar8xxx_sw_ops,
2071
2072 .hw_init = ar8216_hw_init,
2073 .init_globals = ar8236_init_globals,
2074 .init_port = ar8216_init_port,
2075 .setup_port = ar8236_setup_port,
2076 .read_port_status = ar8216_read_port_status,
2077 .atu_flush = ar8216_atu_flush,
2078 .atu_flush_port = ar8216_atu_flush_port,
2079 .vtu_flush = ar8216_vtu_flush,
2080 .vtu_load_vlan = ar8216_vtu_load_vlan,
2081 .set_mirror_regs = ar8216_set_mirror_regs,
2082 .get_arl_entry = ar8216_get_arl_entry,
2083 .sw_hw_apply = ar8xxx_sw_hw_apply,
2084
2085 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2086 .mib_decs = ar8236_mibs,
2087 .mib_func = AR8216_REG_MIB_FUNC,
2088 .mib_rxb_id = AR8236_MIB_RXB_ID,
2089 .mib_txb_id = AR8236_MIB_TXB_ID,
2090 };
2091
2092 static const struct ar8xxx_chip ar8316_chip = {
2093 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
2094
2095 .reg_port_stats_start = 0x20000,
2096 .reg_port_stats_length = 0x100,
2097 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2098
2099 .name = "Atheros AR8316",
2100 .ports = AR8216_NUM_PORTS,
2101 .vlans = AR8X16_MAX_VLANS,
2102 .swops = &ar8xxx_sw_ops,
2103
2104 .hw_init = ar8316_hw_init,
2105 .init_globals = ar8316_init_globals,
2106 .init_port = ar8216_init_port,
2107 .setup_port = ar8216_setup_port,
2108 .read_port_status = ar8216_read_port_status,
2109 .atu_flush = ar8216_atu_flush,
2110 .atu_flush_port = ar8216_atu_flush_port,
2111 .vtu_flush = ar8216_vtu_flush,
2112 .vtu_load_vlan = ar8216_vtu_load_vlan,
2113 .set_mirror_regs = ar8216_set_mirror_regs,
2114 .get_arl_entry = ar8216_get_arl_entry,
2115 .sw_hw_apply = ar8xxx_sw_hw_apply,
2116
2117 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2118 .mib_decs = ar8236_mibs,
2119 .mib_func = AR8216_REG_MIB_FUNC,
2120 .mib_rxb_id = AR8236_MIB_RXB_ID,
2121 .mib_txb_id = AR8236_MIB_TXB_ID,
2122 };
2123
2124 static int
2125 ar8xxx_read_id(struct ar8xxx_priv *priv)
2126 {
2127 u32 val;
2128 u16 id;
2129 int i;
2130
2131 val = ar8xxx_read(priv, AR8216_REG_CTRL);
2132 if (val == ~0)
2133 return -ENODEV;
2134
2135 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2136 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2137 u16 t;
2138
2139 val = ar8xxx_read(priv, AR8216_REG_CTRL);
2140 if (val == ~0)
2141 return -ENODEV;
2142
2143 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2144 if (t != id)
2145 return -ENODEV;
2146 }
2147
2148 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2149 priv->chip_rev = (id & AR8216_CTRL_REVISION);
2150 return 0;
2151 }
2152
2153 static int
2154 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2155 {
2156 int ret;
2157
2158 ret = ar8xxx_read_id(priv);
2159 if(ret)
2160 return ret;
2161
2162 switch (priv->chip_ver) {
2163 case AR8XXX_VER_AR8216:
2164 priv->chip = &ar8216_chip;
2165 break;
2166 case AR8XXX_VER_AR8236:
2167 priv->chip = &ar8236_chip;
2168 break;
2169 case AR8XXX_VER_AR8316:
2170 priv->chip = &ar8316_chip;
2171 break;
2172 case AR8XXX_VER_AR8327:
2173 priv->chip = &ar8327_chip;
2174 break;
2175 case AR8XXX_VER_AR8337:
2176 priv->chip = &ar8337_chip;
2177 break;
2178 default:
2179 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2180 priv->chip_ver, priv->chip_rev);
2181
2182 return -ENODEV;
2183 }
2184
2185 return 0;
2186 }
2187
2188 static void
2189 ar8xxx_mib_work_func(struct work_struct *work)
2190 {
2191 struct ar8xxx_priv *priv;
2192 int err, i;
2193
2194 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2195
2196 mutex_lock(&priv->mib_lock);
2197
2198 err = ar8xxx_mib_capture(priv);
2199 if (err)
2200 goto next_attempt;
2201
2202 for (i = 0; i < priv->dev.ports; i++)
2203 ar8xxx_mib_fetch_port_stat(priv, i, false);
2204
2205 next_attempt:
2206 mutex_unlock(&priv->mib_lock);
2207 schedule_delayed_work(&priv->mib_work,
2208 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2209 }
2210
2211 static int
2212 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2213 {
2214 unsigned int len;
2215
2216 if (!ar8xxx_has_mib_counters(priv))
2217 return 0;
2218
2219 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2220
2221 len = priv->dev.ports * priv->chip->num_mibs *
2222 sizeof(*priv->mib_stats);
2223 priv->mib_stats = kzalloc(len, GFP_KERNEL);
2224
2225 if (!priv->mib_stats)
2226 return -ENOMEM;
2227
2228 return 0;
2229 }
2230
2231 static void
2232 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2233 {
2234 if (!ar8xxx_has_mib_counters(priv))
2235 return;
2236
2237 schedule_delayed_work(&priv->mib_work,
2238 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2239 }
2240
2241 static void
2242 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2243 {
2244 if (!ar8xxx_has_mib_counters(priv))
2245 return;
2246
2247 cancel_delayed_work_sync(&priv->mib_work);
2248 }
2249
2250 static struct ar8xxx_priv *
2251 ar8xxx_create(void)
2252 {
2253 struct ar8xxx_priv *priv;
2254
2255 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2256 if (priv == NULL)
2257 return NULL;
2258
2259 mutex_init(&priv->reg_mutex);
2260 mutex_init(&priv->mib_lock);
2261 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2262
2263 return priv;
2264 }
2265
2266 static void
2267 ar8xxx_free(struct ar8xxx_priv *priv)
2268 {
2269 if (priv->chip && priv->chip->cleanup)
2270 priv->chip->cleanup(priv);
2271
2272 kfree(priv->chip_data);
2273 kfree(priv->mib_stats);
2274 kfree(priv);
2275 }
2276
2277 static int
2278 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2279 {
2280 const struct ar8xxx_chip *chip;
2281 struct switch_dev *swdev;
2282 int ret;
2283
2284 chip = priv->chip;
2285
2286 swdev = &priv->dev;
2287 swdev->cpu_port = AR8216_PORT_CPU;
2288 swdev->name = chip->name;
2289 swdev->vlans = chip->vlans;
2290 swdev->ports = chip->ports;
2291 swdev->ops = chip->swops;
2292
2293 ret = ar8xxx_mib_init(priv);
2294 if (ret)
2295 return ret;
2296
2297 return 0;
2298 }
2299
2300 static int
2301 ar8xxx_start(struct ar8xxx_priv *priv)
2302 {
2303 int ret;
2304
2305 priv->init = true;
2306
2307 ret = priv->chip->hw_init(priv);
2308 if (ret)
2309 return ret;
2310
2311 ret = ar8xxx_sw_reset_switch(&priv->dev);
2312 if (ret)
2313 return ret;
2314
2315 priv->init = false;
2316
2317 ar8xxx_mib_start(priv);
2318
2319 return 0;
2320 }
2321
2322 static int
2323 ar8xxx_phy_config_init(struct phy_device *phydev)
2324 {
2325 struct ar8xxx_priv *priv = phydev->priv;
2326 struct net_device *dev = phydev->attached_dev;
2327 int ret;
2328
2329 if (WARN_ON(!priv))
2330 return -ENODEV;
2331
2332 if (priv->chip->config_at_probe)
2333 return ar8xxx_phy_check_aneg(phydev);
2334
2335 priv->phy = phydev;
2336
2337 if (phydev->mdio.addr != 0) {
2338 if (chip_is_ar8316(priv)) {
2339 /* switch device has been initialized, reinit */
2340 priv->dev.ports = (AR8216_NUM_PORTS - 1);
2341 priv->initialized = false;
2342 priv->port4_phy = true;
2343 ar8316_hw_init(priv);
2344 return 0;
2345 }
2346
2347 return 0;
2348 }
2349
2350 ret = ar8xxx_start(priv);
2351 if (ret)
2352 return ret;
2353
2354 /* VID fixup only needed on ar8216 */
2355 if (chip_is_ar8216(priv)) {
2356 dev->phy_ptr = priv;
2357 dev->priv_flags |= IFF_NO_IP_ALIGN;
2358 dev->eth_mangle_rx = ar8216_mangle_rx;
2359 dev->eth_mangle_tx = ar8216_mangle_tx;
2360 }
2361
2362 return 0;
2363 }
2364
2365 static bool
2366 ar8xxx_check_link_states(struct ar8xxx_priv *priv)
2367 {
2368 bool link_new, changed = false;
2369 u32 status;
2370 int i;
2371
2372 mutex_lock(&priv->reg_mutex);
2373
2374 for (i = 0; i < priv->dev.ports; i++) {
2375 status = priv->chip->read_port_status(priv, i);
2376 link_new = !!(status & AR8216_PORT_STATUS_LINK_UP);
2377 if (link_new == priv->link_up[i])
2378 continue;
2379
2380 priv->link_up[i] = link_new;
2381 changed = true;
2382 /* flush ARL entries for this port if it went down*/
2383 if (!link_new)
2384 priv->chip->atu_flush_port(priv, i);
2385 dev_info(&priv->phy->mdio.dev, "Port %d is %s\n",
2386 i, link_new ? "up" : "down");
2387 }
2388
2389 mutex_unlock(&priv->reg_mutex);
2390
2391 return changed;
2392 }
2393
2394 static int
2395 ar8xxx_phy_read_status(struct phy_device *phydev)
2396 {
2397 struct ar8xxx_priv *priv = phydev->priv;
2398 struct switch_port_link link;
2399
2400 /* check for switch port link changes */
2401 if (phydev->state == PHY_CHANGELINK)
2402 ar8xxx_check_link_states(priv);
2403
2404 if (phydev->mdio.addr != 0)
2405 return genphy_read_status(phydev);
2406
2407 ar8216_read_port_link(priv, phydev->mdio.addr, &link);
2408 phydev->link = !!link.link;
2409 if (!phydev->link)
2410 return 0;
2411
2412 switch (link.speed) {
2413 case SWITCH_PORT_SPEED_10:
2414 phydev->speed = SPEED_10;
2415 break;
2416 case SWITCH_PORT_SPEED_100:
2417 phydev->speed = SPEED_100;
2418 break;
2419 case SWITCH_PORT_SPEED_1000:
2420 phydev->speed = SPEED_1000;
2421 break;
2422 default:
2423 phydev->speed = 0;
2424 }
2425 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2426
2427 phydev->state = PHY_RUNNING;
2428 netif_carrier_on(phydev->attached_dev);
2429 if (phydev->adjust_link)
2430 phydev->adjust_link(phydev->attached_dev);
2431
2432 return 0;
2433 }
2434
2435 static int
2436 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2437 {
2438 if (phydev->mdio.addr == 0)
2439 return 0;
2440
2441 return genphy_config_aneg(phydev);
2442 }
2443
2444 static const u32 ar8xxx_phy_ids[] = {
2445 0x004dd033,
2446 0x004dd034, /* AR8327 */
2447 0x004dd036, /* AR8337 */
2448 0x004dd041,
2449 0x004dd042,
2450 0x004dd043, /* AR8236 */
2451 };
2452
2453 static bool
2454 ar8xxx_phy_match(u32 phy_id)
2455 {
2456 int i;
2457
2458 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2459 if (phy_id == ar8xxx_phy_ids[i])
2460 return true;
2461
2462 return false;
2463 }
2464
2465 static bool
2466 ar8xxx_is_possible(struct mii_bus *bus)
2467 {
2468 unsigned int i, found_phys = 0;
2469
2470 for (i = 0; i < 5; i++) {
2471 u32 phy_id;
2472
2473 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2474 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2475 if (ar8xxx_phy_match(phy_id)) {
2476 found_phys++;
2477 } else if (phy_id) {
2478 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2479 dev_name(&bus->dev), i, phy_id);
2480 }
2481 }
2482 return !!found_phys;
2483 }
2484
2485 static int
2486 ar8xxx_phy_probe(struct phy_device *phydev)
2487 {
2488 struct ar8xxx_priv *priv;
2489 struct switch_dev *swdev;
2490 int ret;
2491
2492 /* skip PHYs at unused adresses */
2493 if (phydev->mdio.addr != 0 && phydev->mdio.addr != 3 && phydev->mdio.addr != 4)
2494 return -ENODEV;
2495
2496 if (!ar8xxx_is_possible(phydev->mdio.bus))
2497 return -ENODEV;
2498
2499 mutex_lock(&ar8xxx_dev_list_lock);
2500 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2501 if (priv->mii_bus == phydev->mdio.bus)
2502 goto found;
2503
2504 priv = ar8xxx_create();
2505 if (priv == NULL) {
2506 ret = -ENOMEM;
2507 goto unlock;
2508 }
2509
2510 priv->mii_bus = phydev->mdio.bus;
2511 priv->pdev = &phydev->mdio.dev;
2512
2513 ret = ar8xxx_id_chip(priv);
2514 if (ret)
2515 goto free_priv;
2516
2517 ret = ar8xxx_probe_switch(priv);
2518 if (ret)
2519 goto free_priv;
2520
2521 swdev = &priv->dev;
2522 swdev->alias = dev_name(&priv->mii_bus->dev);
2523 ret = register_switch(swdev, NULL);
2524 if (ret)
2525 goto free_priv;
2526
2527 pr_info("%s: %s rev. %u switch registered on %s\n",
2528 swdev->devname, swdev->name, priv->chip_rev,
2529 dev_name(&priv->mii_bus->dev));
2530
2531 list_add(&priv->list, &ar8xxx_dev_list);
2532
2533 found:
2534 priv->use_count++;
2535
2536 if (phydev->mdio.addr == 0) {
2537 if (ar8xxx_has_gige(priv)) {
2538 phydev->supported = SUPPORTED_1000baseT_Full;
2539 phydev->advertising = ADVERTISED_1000baseT_Full;
2540 } else {
2541 phydev->supported = SUPPORTED_100baseT_Full;
2542 phydev->advertising = ADVERTISED_100baseT_Full;
2543 }
2544
2545 if (priv->chip->config_at_probe) {
2546 priv->phy = phydev;
2547
2548 ret = ar8xxx_start(priv);
2549 if (ret)
2550 goto err_unregister_switch;
2551 }
2552 } else {
2553 if (ar8xxx_has_gige(priv)) {
2554 phydev->supported |= SUPPORTED_1000baseT_Full;
2555 phydev->advertising |= ADVERTISED_1000baseT_Full;
2556 }
2557 if (priv->chip->phy_rgmii_set)
2558 priv->chip->phy_rgmii_set(priv, phydev);
2559 }
2560
2561 phydev->priv = priv;
2562
2563 mutex_unlock(&ar8xxx_dev_list_lock);
2564
2565 return 0;
2566
2567 err_unregister_switch:
2568 if (--priv->use_count)
2569 goto unlock;
2570
2571 unregister_switch(&priv->dev);
2572
2573 free_priv:
2574 ar8xxx_free(priv);
2575 unlock:
2576 mutex_unlock(&ar8xxx_dev_list_lock);
2577 return ret;
2578 }
2579
2580 static void
2581 ar8xxx_phy_detach(struct phy_device *phydev)
2582 {
2583 struct net_device *dev = phydev->attached_dev;
2584
2585 if (!dev)
2586 return;
2587
2588 dev->phy_ptr = NULL;
2589 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2590 dev->eth_mangle_rx = NULL;
2591 dev->eth_mangle_tx = NULL;
2592 }
2593
2594 static void
2595 ar8xxx_phy_remove(struct phy_device *phydev)
2596 {
2597 struct ar8xxx_priv *priv = phydev->priv;
2598
2599 if (WARN_ON(!priv))
2600 return;
2601
2602 phydev->priv = NULL;
2603
2604 mutex_lock(&ar8xxx_dev_list_lock);
2605
2606 if (--priv->use_count > 0) {
2607 mutex_unlock(&ar8xxx_dev_list_lock);
2608 return;
2609 }
2610
2611 list_del(&priv->list);
2612 mutex_unlock(&ar8xxx_dev_list_lock);
2613
2614 unregister_switch(&priv->dev);
2615 ar8xxx_mib_stop(priv);
2616 ar8xxx_free(priv);
2617 }
2618
2619 static int
2620 ar8xxx_phy_soft_reset(struct phy_device *phydev)
2621 {
2622 /* we don't need an extra reset */
2623 return 0;
2624 }
2625
2626 static struct phy_driver ar8xxx_phy_driver[] = {
2627 {
2628 .phy_id = 0x004d0000,
2629 .name = "Atheros AR8216/AR8236/AR8316",
2630 .phy_id_mask = 0xffff0000,
2631 .features = PHY_BASIC_FEATURES,
2632 .probe = ar8xxx_phy_probe,
2633 .remove = ar8xxx_phy_remove,
2634 .detach = ar8xxx_phy_detach,
2635 .config_init = ar8xxx_phy_config_init,
2636 .config_aneg = ar8xxx_phy_config_aneg,
2637 .read_status = ar8xxx_phy_read_status,
2638 .soft_reset = ar8xxx_phy_soft_reset,
2639 }
2640 };
2641
2642 static const struct of_device_id ar8xxx_mdiodev_of_match[] = {
2643 {
2644 .compatible = "qca,ar7240sw",
2645 .data = &ar7240sw_chip,
2646 }, {
2647 .compatible = "qca,ar8229",
2648 .data = &ar8229_chip,
2649 }, {
2650 .compatible = "qca,ar8236",
2651 .data = &ar8236_chip,
2652 }, {
2653 .compatible = "qca,ar8327",
2654 .data = &ar8327_chip,
2655 },
2656 { /* sentinel */ },
2657 };
2658
2659 static int
2660 ar8xxx_mdiodev_probe(struct mdio_device *mdiodev)
2661 {
2662 const struct of_device_id *match;
2663 struct ar8xxx_priv *priv;
2664 struct switch_dev *swdev;
2665 struct device_node *mdio_node;
2666 int ret;
2667
2668 match = of_match_device(ar8xxx_mdiodev_of_match, &mdiodev->dev);
2669 if (!match)
2670 return -EINVAL;
2671
2672 priv = ar8xxx_create();
2673 if (priv == NULL)
2674 return -ENOMEM;
2675
2676 priv->mii_bus = mdiodev->bus;
2677 priv->pdev = &mdiodev->dev;
2678 priv->chip = (const struct ar8xxx_chip *) match->data;
2679
2680 ret = ar8xxx_read_id(priv);
2681 if (ret)
2682 goto free_priv;
2683
2684 ret = ar8xxx_probe_switch(priv);
2685 if (ret)
2686 goto free_priv;
2687
2688 if (priv->chip->phy_read && priv->chip->phy_write) {
2689 priv->sw_mii_bus = devm_mdiobus_alloc(&mdiodev->dev);
2690 priv->sw_mii_bus->name = "ar8xxx-mdio";
2691 priv->sw_mii_bus->read = ar8xxx_phy_read;
2692 priv->sw_mii_bus->write = ar8xxx_phy_write;
2693 priv->sw_mii_bus->priv = priv;
2694 priv->sw_mii_bus->parent = &mdiodev->dev;
2695 snprintf(priv->sw_mii_bus->id, MII_BUS_ID_SIZE, "%s",
2696 dev_name(&mdiodev->dev));
2697 mdio_node = of_get_child_by_name(priv->pdev->of_node, "mdio-bus");
2698 ret = of_mdiobus_register(priv->sw_mii_bus, mdio_node);
2699 if (ret)
2700 goto free_priv;
2701 }
2702
2703 swdev = &priv->dev;
2704 swdev->alias = dev_name(&mdiodev->dev);
2705
2706 if (of_property_read_bool(priv->pdev->of_node, "qca,phy4-mii-enable")) {
2707 priv->port4_phy = true;
2708 swdev->ports--;
2709 }
2710
2711 ret = register_switch(swdev, NULL);
2712 if (ret)
2713 goto free_priv;
2714
2715 pr_info("%s: %s rev. %u switch registered on %s\n",
2716 swdev->devname, swdev->name, priv->chip_rev,
2717 dev_name(&priv->mii_bus->dev));
2718
2719 mutex_lock(&ar8xxx_dev_list_lock);
2720 list_add(&priv->list, &ar8xxx_dev_list);
2721 mutex_unlock(&ar8xxx_dev_list_lock);
2722
2723 priv->use_count++;
2724
2725 ret = ar8xxx_start(priv);
2726 if (ret)
2727 goto err_unregister_switch;
2728
2729 dev_set_drvdata(&mdiodev->dev, priv);
2730
2731 return 0;
2732
2733 err_unregister_switch:
2734 if (--priv->use_count)
2735 return ret;
2736
2737 unregister_switch(&priv->dev);
2738
2739 free_priv:
2740 ar8xxx_free(priv);
2741 return ret;
2742 }
2743
2744 static void
2745 ar8xxx_mdiodev_remove(struct mdio_device *mdiodev)
2746 {
2747 struct ar8xxx_priv *priv = dev_get_drvdata(&mdiodev->dev);
2748
2749 if (WARN_ON(!priv))
2750 return;
2751
2752 mutex_lock(&ar8xxx_dev_list_lock);
2753
2754 if (--priv->use_count > 0) {
2755 mutex_unlock(&ar8xxx_dev_list_lock);
2756 return;
2757 }
2758
2759 list_del(&priv->list);
2760 mutex_unlock(&ar8xxx_dev_list_lock);
2761
2762 unregister_switch(&priv->dev);
2763 ar8xxx_mib_stop(priv);
2764 if(priv->sw_mii_bus)
2765 mdiobus_unregister(priv->sw_mii_bus);
2766 ar8xxx_free(priv);
2767 }
2768
2769 static struct mdio_driver ar8xxx_mdio_driver = {
2770 .probe = ar8xxx_mdiodev_probe,
2771 .remove = ar8xxx_mdiodev_remove,
2772 .mdiodrv.driver = {
2773 .name = "ar8xxx-switch",
2774 .of_match_table = ar8xxx_mdiodev_of_match,
2775 },
2776 };
2777
2778 static int __init ar8216_init(void)
2779 {
2780 int ret;
2781
2782 ret = phy_drivers_register(ar8xxx_phy_driver,
2783 ARRAY_SIZE(ar8xxx_phy_driver),
2784 THIS_MODULE);
2785 if (ret)
2786 return ret;
2787
2788 ret = mdio_driver_register(&ar8xxx_mdio_driver);
2789 if (ret)
2790 phy_drivers_unregister(ar8xxx_phy_driver,
2791 ARRAY_SIZE(ar8xxx_phy_driver));
2792
2793 return ret;
2794 }
2795 module_init(ar8216_init);
2796
2797 static void __exit ar8216_exit(void)
2798 {
2799 mdio_driver_unregister(&ar8xxx_mdio_driver);
2800 phy_drivers_unregister(ar8xxx_phy_driver,
2801 ARRAY_SIZE(ar8xxx_phy_driver));
2802 }
2803 module_exit(ar8216_exit);
2804
2805 MODULE_LICENSE("GPL");
OpenWrt Source Repository