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generic: ar8216: don't use platform_data in ar8327_init_port
[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include "ar8216.h"
37
38 /* size of the vlan table */
39 #define AR8X16_MAX_VLANS 128
40 #define AR8X16_PROBE_RETRIES 10
41 #define AR8X16_MAX_PORTS 8
42
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
44
45 struct ar8xxx_priv;
46
47 #define AR8XXX_CAP_GIGE BIT(0)
48 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
49
50 enum {
51 AR8XXX_VER_AR8216 = 0x01,
52 AR8XXX_VER_AR8236 = 0x03,
53 AR8XXX_VER_AR8316 = 0x10,
54 AR8XXX_VER_AR8327 = 0x12,
55 };
56
57 struct ar8xxx_mib_desc {
58 unsigned int size;
59 unsigned int offset;
60 const char *name;
61 };
62
63 struct ar8xxx_chip {
64 unsigned long caps;
65
66 int (*hw_init)(struct ar8xxx_priv *priv);
67 void (*init_globals)(struct ar8xxx_priv *priv);
68 void (*init_port)(struct ar8xxx_priv *priv, int port);
69 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 egress,
70 u32 ingress, u32 members, u32 pvid);
71 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
72 int (*atu_flush)(struct ar8xxx_priv *priv);
73 void (*vtu_flush)(struct ar8xxx_priv *priv);
74 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
75
76 const struct ar8xxx_mib_desc *mib_decs;
77 unsigned num_mibs;
78 };
79
80 struct ar8327_data {
81 u32 port0_status;
82 u32 port6_status;
83 };
84
85 struct ar8xxx_priv {
86 struct switch_dev dev;
87 struct mii_bus *mii_bus;
88 struct phy_device *phy;
89 u32 (*read)(struct ar8xxx_priv *priv, int reg);
90 void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
91 const struct net_device_ops *ndo_old;
92 struct net_device_ops ndo;
93 struct mutex reg_mutex;
94 u8 chip_ver;
95 u8 chip_rev;
96 const struct ar8xxx_chip *chip;
97 union {
98 struct ar8327_data ar8327;
99 } chip_data;
100 bool initialized;
101 bool port4_phy;
102 char buf[2048];
103
104 bool init;
105 bool mii_lo_first;
106
107 struct mutex mib_lock;
108 struct delayed_work mib_work;
109 int mib_next_port;
110 u64 *mib_stats;
111
112 struct list_head list;
113 unsigned int use_count;
114
115 /* all fields below are cleared on reset */
116 bool vlan;
117 u16 vlan_id[AR8X16_MAX_VLANS];
118 u8 vlan_table[AR8X16_MAX_VLANS];
119 u8 vlan_tagged;
120 u16 pvid[AR8X16_MAX_PORTS];
121 };
122
123 #define MIB_DESC(_s , _o, _n) \
124 { \
125 .size = (_s), \
126 .offset = (_o), \
127 .name = (_n), \
128 }
129
130 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
131 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
132 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
133 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
134 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
135 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
136 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
137 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
138 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
139 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
140 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
141 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
142 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
143 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
144 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
145 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
146 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
147 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
148 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
149 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
150 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
151 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
152 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
153 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
154 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
155 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
156 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
157 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
158 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
159 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
160 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
161 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
162 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
163 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
164 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
165 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
166 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
167 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
168 };
169
170 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
171 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
172 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
173 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
174 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
175 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
176 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
177 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
178 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
179 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
180 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
181 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
182 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
183 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
184 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
185 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
186 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
187 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
188 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
189 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
190 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
191 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
192 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
193 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
194 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
195 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
196 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
197 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
198 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
199 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
200 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
201 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
202 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
203 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
204 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
205 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
206 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
207 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
208 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
209 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
210 };
211
212 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
213 static LIST_HEAD(ar8xxx_dev_list);
214
215 static inline struct ar8xxx_priv *
216 swdev_to_ar8xxx(struct switch_dev *swdev)
217 {
218 return container_of(swdev, struct ar8xxx_priv, dev);
219 }
220
221 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
222 {
223 return priv->chip->caps & AR8XXX_CAP_GIGE;
224 }
225
226 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
227 {
228 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
229 }
230
231 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
232 {
233 return priv->chip_ver == AR8XXX_VER_AR8216;
234 }
235
236 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
237 {
238 return priv->chip_ver == AR8XXX_VER_AR8236;
239 }
240
241 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
242 {
243 return priv->chip_ver == AR8XXX_VER_AR8316;
244 }
245
246 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
247 {
248 return priv->chip_ver == AR8XXX_VER_AR8327;
249 }
250
251 static inline void
252 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
253 {
254 regaddr >>= 1;
255 *r1 = regaddr & 0x1e;
256
257 regaddr >>= 5;
258 *r2 = regaddr & 0x7;
259
260 regaddr >>= 3;
261 *page = regaddr & 0x1ff;
262 }
263
264 static u32
265 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
266 {
267 struct mii_bus *bus = priv->mii_bus;
268 u16 r1, r2, page;
269 u16 lo, hi;
270
271 split_addr((u32) reg, &r1, &r2, &page);
272
273 mutex_lock(&bus->mdio_lock);
274
275 bus->write(bus, 0x18, 0, page);
276 usleep_range(1000, 2000); /* wait for the page switch to propagate */
277 lo = bus->read(bus, 0x10 | r2, r1);
278 hi = bus->read(bus, 0x10 | r2, r1 + 1);
279
280 mutex_unlock(&bus->mdio_lock);
281
282 return (hi << 16) | lo;
283 }
284
285 static void
286 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
287 {
288 struct mii_bus *bus = priv->mii_bus;
289 u16 r1, r2, r3;
290 u16 lo, hi;
291
292 split_addr((u32) reg, &r1, &r2, &r3);
293 lo = val & 0xffff;
294 hi = (u16) (val >> 16);
295
296 mutex_lock(&bus->mdio_lock);
297
298 bus->write(bus, 0x18, 0, r3);
299 usleep_range(1000, 2000); /* wait for the page switch to propagate */
300 if (priv->mii_lo_first) {
301 bus->write(bus, 0x10 | r2, r1, lo);
302 bus->write(bus, 0x10 | r2, r1 + 1, hi);
303 } else {
304 bus->write(bus, 0x10 | r2, r1 + 1, hi);
305 bus->write(bus, 0x10 | r2, r1, lo);
306 }
307
308 mutex_unlock(&bus->mdio_lock);
309 }
310
311 static void
312 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
313 u16 dbg_addr, u16 dbg_data)
314 {
315 struct mii_bus *bus = priv->mii_bus;
316
317 mutex_lock(&bus->mdio_lock);
318 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
319 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
320 mutex_unlock(&bus->mdio_lock);
321 }
322
323 static void
324 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
325 {
326 struct mii_bus *bus = priv->mii_bus;
327
328 mutex_lock(&bus->mdio_lock);
329 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
330 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
331 mutex_unlock(&bus->mdio_lock);
332 }
333
334 static u32
335 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
336 {
337 u32 v;
338
339 lockdep_assert_held(&priv->reg_mutex);
340
341 v = priv->read(priv, reg);
342 v &= ~mask;
343 v |= val;
344 priv->write(priv, reg, v);
345
346 return v;
347 }
348
349 static inline void
350 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
351 {
352 u32 v;
353
354 lockdep_assert_held(&priv->reg_mutex);
355
356 v = priv->read(priv, reg);
357 v |= val;
358 priv->write(priv, reg, v);
359 }
360
361 static int
362 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
363 unsigned timeout)
364 {
365 int i;
366
367 for (i = 0; i < timeout; i++) {
368 u32 t;
369
370 t = priv->read(priv, reg);
371 if ((t & mask) == val)
372 return 0;
373
374 usleep_range(1000, 2000);
375 }
376
377 return -ETIMEDOUT;
378 }
379
380 static int
381 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
382 {
383 unsigned mib_func;
384 int ret;
385
386 lockdep_assert_held(&priv->mib_lock);
387
388 if (chip_is_ar8327(priv))
389 mib_func = AR8327_REG_MIB_FUNC;
390 else
391 mib_func = AR8216_REG_MIB_FUNC;
392
393 mutex_lock(&priv->reg_mutex);
394 /* Capture the hardware statistics for all ports */
395 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
396 mutex_unlock(&priv->reg_mutex);
397
398 /* Wait for the capturing to complete. */
399 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
400 if (ret)
401 goto out;
402
403 ret = 0;
404
405 out:
406 return ret;
407 }
408
409 static int
410 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
411 {
412 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
413 }
414
415 static int
416 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
417 {
418 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
419 }
420
421 static void
422 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
423 {
424 unsigned int base;
425 u64 *mib_stats;
426 int i;
427
428 WARN_ON(port >= priv->dev.ports);
429
430 lockdep_assert_held(&priv->mib_lock);
431
432 if (chip_is_ar8327(priv))
433 base = AR8327_REG_PORT_STATS_BASE(port);
434 else if (chip_is_ar8236(priv) ||
435 chip_is_ar8316(priv))
436 base = AR8236_REG_PORT_STATS_BASE(port);
437 else
438 base = AR8216_REG_PORT_STATS_BASE(port);
439
440 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
441 for (i = 0; i < priv->chip->num_mibs; i++) {
442 const struct ar8xxx_mib_desc *mib;
443 u64 t;
444
445 mib = &priv->chip->mib_decs[i];
446 t = priv->read(priv, base + mib->offset);
447 if (mib->size == 2) {
448 u64 hi;
449
450 hi = priv->read(priv, base + mib->offset + 4);
451 t |= hi << 32;
452 }
453
454 if (flush)
455 mib_stats[i] = 0;
456 else
457 mib_stats[i] += t;
458 }
459 }
460
461 static void
462 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
463 struct switch_port_link *link)
464 {
465 u32 status;
466 u32 speed;
467
468 memset(link, '\0', sizeof(*link));
469
470 status = priv->chip->read_port_status(priv, port);
471
472 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
473 if (link->aneg) {
474 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
475 if (!link->link)
476 return;
477 } else {
478 link->link = true;
479 }
480
481 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
482 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
483 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
484
485 speed = (status & AR8216_PORT_STATUS_SPEED) >>
486 AR8216_PORT_STATUS_SPEED_S;
487
488 switch (speed) {
489 case AR8216_PORT_SPEED_10M:
490 link->speed = SWITCH_PORT_SPEED_10;
491 break;
492 case AR8216_PORT_SPEED_100M:
493 link->speed = SWITCH_PORT_SPEED_100;
494 break;
495 case AR8216_PORT_SPEED_1000M:
496 link->speed = SWITCH_PORT_SPEED_1000;
497 break;
498 default:
499 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
500 break;
501 }
502 }
503
504 static struct sk_buff *
505 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
506 {
507 struct ar8xxx_priv *priv = dev->phy_ptr;
508 unsigned char *buf;
509
510 if (unlikely(!priv))
511 goto error;
512
513 if (!priv->vlan)
514 goto send;
515
516 if (unlikely(skb_headroom(skb) < 2)) {
517 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
518 goto error;
519 }
520
521 buf = skb_push(skb, 2);
522 buf[0] = 0x10;
523 buf[1] = 0x80;
524
525 send:
526 return skb;
527
528 error:
529 dev_kfree_skb_any(skb);
530 return NULL;
531 }
532
533 static void
534 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
535 {
536 struct ar8xxx_priv *priv;
537 unsigned char *buf;
538 int port, vlan;
539
540 priv = dev->phy_ptr;
541 if (!priv)
542 return;
543
544 /* don't strip the header if vlan mode is disabled */
545 if (!priv->vlan)
546 return;
547
548 /* strip header, get vlan id */
549 buf = skb->data;
550 skb_pull(skb, 2);
551
552 /* check for vlan header presence */
553 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
554 return;
555
556 port = buf[0] & 0xf;
557
558 /* no need to fix up packets coming from a tagged source */
559 if (priv->vlan_tagged & (1 << port))
560 return;
561
562 /* lookup port vid from local table, the switch passes an invalid vlan id */
563 vlan = priv->vlan_id[priv->pvid[port]];
564
565 buf[14 + 2] &= 0xf0;
566 buf[14 + 2] |= vlan >> 8;
567 buf[15 + 2] = vlan & 0xff;
568 }
569
570 static int
571 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
572 {
573 int timeout = 20;
574 u32 t = 0;
575
576 while (1) {
577 t = priv->read(priv, reg);
578 if ((t & mask) == val)
579 return 0;
580
581 if (timeout-- <= 0)
582 break;
583
584 udelay(10);
585 }
586
587 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
588 (unsigned int) reg, t, mask, val);
589 return -ETIMEDOUT;
590 }
591
592 static void
593 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
594 {
595 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
596 return;
597 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
598 val &= AR8216_VTUDATA_MEMBER;
599 val |= AR8216_VTUDATA_VALID;
600 priv->write(priv, AR8216_REG_VTU_DATA, val);
601 }
602 op |= AR8216_VTU_ACTIVE;
603 priv->write(priv, AR8216_REG_VTU, op);
604 }
605
606 static void
607 ar8216_vtu_flush(struct ar8xxx_priv *priv)
608 {
609 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
610 }
611
612 static void
613 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
614 {
615 u32 op;
616
617 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
618 ar8216_vtu_op(priv, op, port_mask);
619 }
620
621 static int
622 ar8216_atu_flush(struct ar8xxx_priv *priv)
623 {
624 int ret;
625
626 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
627 if (!ret)
628 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
629
630 return ret;
631 }
632
633 static u32
634 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
635 {
636 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
637 }
638
639 static void
640 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
641 u32 members, u32 pvid)
642 {
643 u32 header;
644
645 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
646 header = AR8216_PORT_CTRL_HEADER;
647 else
648 header = 0;
649
650 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
651 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
652 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
653 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
654 AR8216_PORT_CTRL_LEARN | header |
655 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
656 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
657
658 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
659 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
660 AR8216_PORT_VLAN_DEFAULT_ID,
661 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
662 (ingress << AR8216_PORT_VLAN_MODE_S) |
663 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
664 }
665
666 static int
667 ar8216_hw_init(struct ar8xxx_priv *priv)
668 {
669 return 0;
670 }
671
672 static void
673 ar8216_init_globals(struct ar8xxx_priv *priv)
674 {
675 /* standard atheros magic */
676 priv->write(priv, 0x38, 0xc000050e);
677
678 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
679 AR8216_GCTRL_MTU, 1518 + 8 + 2);
680 }
681
682 static void
683 ar8216_init_port(struct ar8xxx_priv *priv, int port)
684 {
685 /* Enable port learning and tx */
686 priv->write(priv, AR8216_REG_PORT_CTRL(port),
687 AR8216_PORT_CTRL_LEARN |
688 (4 << AR8216_PORT_CTRL_STATE_S));
689
690 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
691
692 if (port == AR8216_PORT_CPU) {
693 priv->write(priv, AR8216_REG_PORT_STATUS(port),
694 AR8216_PORT_STATUS_LINK_UP |
695 (ar8xxx_has_gige(priv) ?
696 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
697 AR8216_PORT_STATUS_TXMAC |
698 AR8216_PORT_STATUS_RXMAC |
699 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
700 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
701 AR8216_PORT_STATUS_DUPLEX);
702 } else {
703 priv->write(priv, AR8216_REG_PORT_STATUS(port),
704 AR8216_PORT_STATUS_LINK_AUTO);
705 }
706 }
707
708 static const struct ar8xxx_chip ar8216_chip = {
709 .caps = AR8XXX_CAP_MIB_COUNTERS,
710
711 .hw_init = ar8216_hw_init,
712 .init_globals = ar8216_init_globals,
713 .init_port = ar8216_init_port,
714 .setup_port = ar8216_setup_port,
715 .read_port_status = ar8216_read_port_status,
716 .atu_flush = ar8216_atu_flush,
717 .vtu_flush = ar8216_vtu_flush,
718 .vtu_load_vlan = ar8216_vtu_load_vlan,
719
720 .num_mibs = ARRAY_SIZE(ar8216_mibs),
721 .mib_decs = ar8216_mibs,
722 };
723
724 static void
725 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
726 u32 members, u32 pvid)
727 {
728 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
729 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
730 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
731 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
732 AR8216_PORT_CTRL_LEARN |
733 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
734 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
735
736 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
737 AR8236_PORT_VLAN_DEFAULT_ID,
738 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
739
740 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
741 AR8236_PORT_VLAN2_VLAN_MODE |
742 AR8236_PORT_VLAN2_MEMBER,
743 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
744 (members << AR8236_PORT_VLAN2_MEMBER_S));
745 }
746
747 static int
748 ar8236_hw_init(struct ar8xxx_priv *priv)
749 {
750 int i;
751 struct mii_bus *bus;
752
753 if (priv->initialized)
754 return 0;
755
756 /* Initialize the PHYs */
757 bus = priv->mii_bus;
758 for (i = 0; i < 5; i++) {
759 mdiobus_write(bus, i, MII_ADVERTISE,
760 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
761 ADVERTISE_PAUSE_ASYM);
762 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
763 }
764 msleep(1000);
765
766 priv->initialized = true;
767 return 0;
768 }
769
770 static void
771 ar8236_init_globals(struct ar8xxx_priv *priv)
772 {
773 /* enable jumbo frames */
774 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
775 AR8316_GCTRL_MTU, 9018 + 8 + 2);
776
777 /* Enable MIB counters */
778 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
779 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
780 AR8236_MIB_EN);
781 }
782
783 static const struct ar8xxx_chip ar8236_chip = {
784 .caps = AR8XXX_CAP_MIB_COUNTERS,
785 .hw_init = ar8236_hw_init,
786 .init_globals = ar8236_init_globals,
787 .init_port = ar8216_init_port,
788 .setup_port = ar8236_setup_port,
789 .read_port_status = ar8216_read_port_status,
790 .atu_flush = ar8216_atu_flush,
791 .vtu_flush = ar8216_vtu_flush,
792 .vtu_load_vlan = ar8216_vtu_load_vlan,
793
794 .num_mibs = ARRAY_SIZE(ar8236_mibs),
795 .mib_decs = ar8236_mibs,
796 };
797
798 static int
799 ar8316_hw_init(struct ar8xxx_priv *priv)
800 {
801 int i;
802 u32 val, newval;
803 struct mii_bus *bus;
804
805 val = priv->read(priv, AR8316_REG_POSTRIP);
806
807 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
808 if (priv->port4_phy) {
809 /* value taken from Ubiquiti RouterStation Pro */
810 newval = 0x81461bea;
811 pr_info("ar8316: Using port 4 as PHY\n");
812 } else {
813 newval = 0x01261be2;
814 pr_info("ar8316: Using port 4 as switch port\n");
815 }
816 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
817 /* value taken from AVM Fritz!Box 7390 sources */
818 newval = 0x010e5b71;
819 } else {
820 /* no known value for phy interface */
821 pr_err("ar8316: unsupported mii mode: %d.\n",
822 priv->phy->interface);
823 return -EINVAL;
824 }
825
826 if (val == newval)
827 goto out;
828
829 priv->write(priv, AR8316_REG_POSTRIP, newval);
830
831 if (priv->port4_phy &&
832 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
833 /* work around for phy4 rgmii mode */
834 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
835 /* rx delay */
836 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
837 /* tx delay */
838 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
839 msleep(1000);
840 }
841
842 /* Initialize the ports */
843 bus = priv->mii_bus;
844 for (i = 0; i < 5; i++) {
845 /* initialize the port itself */
846 mdiobus_write(bus, i, MII_ADVERTISE,
847 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
848 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
849 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
850 }
851
852 msleep(1000);
853
854 out:
855 priv->initialized = true;
856 return 0;
857 }
858
859 static void
860 ar8316_init_globals(struct ar8xxx_priv *priv)
861 {
862 /* standard atheros magic */
863 priv->write(priv, 0x38, 0xc000050e);
864
865 /* enable cpu port to receive multicast and broadcast frames */
866 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
867
868 /* enable jumbo frames */
869 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
870 AR8316_GCTRL_MTU, 9018 + 8 + 2);
871
872 /* Enable MIB counters */
873 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
874 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
875 AR8236_MIB_EN);
876 }
877
878 static const struct ar8xxx_chip ar8316_chip = {
879 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
880 .hw_init = ar8316_hw_init,
881 .init_globals = ar8316_init_globals,
882 .init_port = ar8216_init_port,
883 .setup_port = ar8216_setup_port,
884 .read_port_status = ar8216_read_port_status,
885 .atu_flush = ar8216_atu_flush,
886 .vtu_flush = ar8216_vtu_flush,
887 .vtu_load_vlan = ar8216_vtu_load_vlan,
888
889 .num_mibs = ARRAY_SIZE(ar8236_mibs),
890 .mib_decs = ar8236_mibs,
891 };
892
893 static u32
894 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
895 {
896 u32 t;
897
898 if (!cfg)
899 return 0;
900
901 t = 0;
902 switch (cfg->mode) {
903 case AR8327_PAD_NC:
904 break;
905
906 case AR8327_PAD_MAC2MAC_MII:
907 t = AR8327_PAD_MAC_MII_EN;
908 if (cfg->rxclk_sel)
909 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
910 if (cfg->txclk_sel)
911 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
912 break;
913
914 case AR8327_PAD_MAC2MAC_GMII:
915 t = AR8327_PAD_MAC_GMII_EN;
916 if (cfg->rxclk_sel)
917 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
918 if (cfg->txclk_sel)
919 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
920 break;
921
922 case AR8327_PAD_MAC_SGMII:
923 t = AR8327_PAD_SGMII_EN;
924
925 /*
926 * WAR for the QUalcomm Atheros AP136 board.
927 * It seems that RGMII TX/RX delay settings needs to be
928 * applied for SGMII mode as well, The ethernet is not
929 * reliable without this.
930 */
931 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
932 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
933 if (cfg->rxclk_delay_en)
934 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
935 if (cfg->txclk_delay_en)
936 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
937
938 if (cfg->sgmii_delay_en)
939 t |= AR8327_PAD_SGMII_DELAY_EN;
940
941 break;
942
943 case AR8327_PAD_MAC2PHY_MII:
944 t = AR8327_PAD_PHY_MII_EN;
945 if (cfg->rxclk_sel)
946 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
947 if (cfg->txclk_sel)
948 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
949 break;
950
951 case AR8327_PAD_MAC2PHY_GMII:
952 t = AR8327_PAD_PHY_GMII_EN;
953 if (cfg->pipe_rxclk_sel)
954 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
955 if (cfg->rxclk_sel)
956 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
957 if (cfg->txclk_sel)
958 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
959 break;
960
961 case AR8327_PAD_MAC_RGMII:
962 t = AR8327_PAD_RGMII_EN;
963 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
964 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
965 if (cfg->rxclk_delay_en)
966 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
967 if (cfg->txclk_delay_en)
968 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
969 break;
970
971 case AR8327_PAD_PHY_GMII:
972 t = AR8327_PAD_PHYX_GMII_EN;
973 break;
974
975 case AR8327_PAD_PHY_RGMII:
976 t = AR8327_PAD_PHYX_RGMII_EN;
977 break;
978
979 case AR8327_PAD_PHY_MII:
980 t = AR8327_PAD_PHYX_MII_EN;
981 break;
982 }
983
984 return t;
985 }
986
987 static void
988 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
989 {
990 switch (priv->chip_rev) {
991 case 1:
992 /* For 100M waveform */
993 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
994 /* Turn on Gigabit clock */
995 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
996 break;
997
998 case 2:
999 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1000 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1001 /* fallthrough */
1002 case 4:
1003 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1004 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1005
1006 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1007 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1008 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1009 break;
1010 }
1011 }
1012
1013 static u32
1014 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1015 {
1016 u32 t;
1017
1018 if (!cfg->force_link)
1019 return AR8216_PORT_STATUS_LINK_AUTO;
1020
1021 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1022 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1023 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1024 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1025
1026 switch (cfg->speed) {
1027 case AR8327_PORT_SPEED_10:
1028 t |= AR8216_PORT_SPEED_10M;
1029 break;
1030 case AR8327_PORT_SPEED_100:
1031 t |= AR8216_PORT_SPEED_100M;
1032 break;
1033 case AR8327_PORT_SPEED_1000:
1034 t |= AR8216_PORT_SPEED_1000M;
1035 break;
1036 }
1037
1038 return t;
1039 }
1040
1041 static int
1042 ar8327_hw_init(struct ar8xxx_priv *priv)
1043 {
1044 struct ar8327_platform_data *pdata;
1045 struct ar8327_led_cfg *led_cfg;
1046 struct ar8327_data *data;
1047 struct mii_bus *bus;
1048 u32 pos, new_pos;
1049 u32 t;
1050 int i;
1051
1052 pdata = priv->phy->dev.platform_data;
1053 if (!pdata)
1054 return -EINVAL;
1055
1056 data = &priv->chip_data.ar8327;
1057
1058 data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1059 data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1060
1061 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1062 priv->write(priv, AR8327_REG_PAD0_MODE, t);
1063 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1064 priv->write(priv, AR8327_REG_PAD5_MODE, t);
1065 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1066 priv->write(priv, AR8327_REG_PAD6_MODE, t);
1067
1068 pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1069 new_pos = pos;
1070
1071 led_cfg = pdata->led_cfg;
1072 if (led_cfg) {
1073 if (led_cfg->open_drain)
1074 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1075 else
1076 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1077
1078 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1079 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1080 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1081 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1082 }
1083
1084 if (new_pos != pos) {
1085 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1086 priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1087 }
1088
1089 bus = priv->mii_bus;
1090 for (i = 0; i < AR8327_NUM_PHYS; i++) {
1091 ar8327_phy_fixup(priv, i);
1092
1093 /* start aneg on the PHY */
1094 mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
1095 ADVERTISE_PAUSE_CAP |
1096 ADVERTISE_PAUSE_ASYM);
1097 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
1098 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1099 }
1100
1101 msleep(1000);
1102
1103 return 0;
1104 }
1105
1106 static void
1107 ar8327_init_globals(struct ar8xxx_priv *priv)
1108 {
1109 u32 t;
1110
1111 /* enable CPU port and disable mirror port */
1112 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1113 AR8327_FWD_CTRL0_MIRROR_PORT;
1114 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1115
1116 /* forward multicast and broadcast frames to CPU */
1117 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1118 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1119 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1120 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1121
1122 /* setup MTU */
1123 ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1124 AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
1125
1126 /* Enable MIB counters */
1127 ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1128 AR8327_MODULE_EN_MIB);
1129 }
1130
1131 static void
1132 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1133 {
1134 u32 t;
1135
1136 if (port == AR8216_PORT_CPU)
1137 t = priv->chip_data.ar8327.port0_status;
1138 else if (port == 6)
1139 t = priv->chip_data.ar8327.port6_status;
1140 else
1141 t = AR8216_PORT_STATUS_LINK_AUTO;
1142
1143 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1144 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1145
1146 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1147 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1148 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1149
1150 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1151 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1152
1153 t = AR8327_PORT_LOOKUP_LEARN;
1154 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1155 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1156 }
1157
1158 static u32
1159 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1160 {
1161 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1162 }
1163
1164 static int
1165 ar8327_atu_flush(struct ar8xxx_priv *priv)
1166 {
1167 int ret;
1168
1169 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1170 AR8327_ATU_FUNC_BUSY, 0);
1171 if (!ret)
1172 priv->write(priv, AR8327_REG_ATU_FUNC,
1173 AR8327_ATU_FUNC_OP_FLUSH);
1174
1175 return ret;
1176 }
1177
1178 static void
1179 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1180 {
1181 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1182 AR8327_VTU_FUNC1_BUSY, 0))
1183 return;
1184
1185 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1186 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1187
1188 op |= AR8327_VTU_FUNC1_BUSY;
1189 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1190 }
1191
1192 static void
1193 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1194 {
1195 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1196 }
1197
1198 static void
1199 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1200 {
1201 u32 op;
1202 u32 val;
1203 int i;
1204
1205 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1206 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1207 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1208 u32 mode;
1209
1210 if ((port_mask & BIT(i)) == 0)
1211 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1212 else if (priv->vlan == 0)
1213 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1214 else if (priv->vlan_tagged & BIT(i))
1215 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1216 else
1217 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1218
1219 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1220 }
1221 ar8327_vtu_op(priv, op, val);
1222 }
1223
1224 static void
1225 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
1226 u32 members, u32 pvid)
1227 {
1228 u32 t;
1229 u32 mode;
1230
1231 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1232 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1233 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1234
1235 mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1236 switch (egress) {
1237 case AR8216_OUT_KEEP:
1238 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1239 break;
1240 case AR8216_OUT_STRIP_VLAN:
1241 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
1242 break;
1243 case AR8216_OUT_ADD_VLAN:
1244 mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
1245 break;
1246 }
1247
1248 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1249 t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
1250 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1251
1252 t = members;
1253 t |= AR8327_PORT_LOOKUP_LEARN;
1254 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1255 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1256 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1257 }
1258
1259 static const struct ar8xxx_chip ar8327_chip = {
1260 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1261 .hw_init = ar8327_hw_init,
1262 .init_globals = ar8327_init_globals,
1263 .init_port = ar8327_init_port,
1264 .setup_port = ar8327_setup_port,
1265 .read_port_status = ar8327_read_port_status,
1266 .atu_flush = ar8327_atu_flush,
1267 .vtu_flush = ar8327_vtu_flush,
1268 .vtu_load_vlan = ar8327_vtu_load_vlan,
1269
1270 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1271 .mib_decs = ar8236_mibs,
1272 };
1273
1274 static int
1275 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1276 struct switch_val *val)
1277 {
1278 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1279 priv->vlan = !!val->value.i;
1280 return 0;
1281 }
1282
1283 static int
1284 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1285 struct switch_val *val)
1286 {
1287 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1288 val->value.i = priv->vlan;
1289 return 0;
1290 }
1291
1292
1293 static int
1294 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1295 {
1296 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1297
1298 /* make sure no invalid PVIDs get set */
1299
1300 if (vlan >= dev->vlans)
1301 return -EINVAL;
1302
1303 priv->pvid[port] = vlan;
1304 return 0;
1305 }
1306
1307 static int
1308 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1309 {
1310 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1311 *vlan = priv->pvid[port];
1312 return 0;
1313 }
1314
1315 static int
1316 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1317 struct switch_val *val)
1318 {
1319 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1320 priv->vlan_id[val->port_vlan] = val->value.i;
1321 return 0;
1322 }
1323
1324 static int
1325 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1326 struct switch_val *val)
1327 {
1328 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1329 val->value.i = priv->vlan_id[val->port_vlan];
1330 return 0;
1331 }
1332
1333 static int
1334 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1335 struct switch_port_link *link)
1336 {
1337 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1338
1339 ar8216_read_port_link(priv, port, link);
1340 return 0;
1341 }
1342
1343 static int
1344 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1345 {
1346 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1347 u8 ports = priv->vlan_table[val->port_vlan];
1348 int i;
1349
1350 val->len = 0;
1351 for (i = 0; i < dev->ports; i++) {
1352 struct switch_port *p;
1353
1354 if (!(ports & (1 << i)))
1355 continue;
1356
1357 p = &val->value.ports[val->len++];
1358 p->id = i;
1359 if (priv->vlan_tagged & (1 << i))
1360 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1361 else
1362 p->flags = 0;
1363 }
1364 return 0;
1365 }
1366
1367 static int
1368 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1369 {
1370 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1371 u8 *vt = &priv->vlan_table[val->port_vlan];
1372 int i, j;
1373
1374 *vt = 0;
1375 for (i = 0; i < val->len; i++) {
1376 struct switch_port *p = &val->value.ports[i];
1377
1378 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1379 priv->vlan_tagged |= (1 << p->id);
1380 } else {
1381 priv->vlan_tagged &= ~(1 << p->id);
1382 priv->pvid[p->id] = val->port_vlan;
1383
1384 /* make sure that an untagged port does not
1385 * appear in other vlans */
1386 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1387 if (j == val->port_vlan)
1388 continue;
1389 priv->vlan_table[j] &= ~(1 << p->id);
1390 }
1391 }
1392
1393 *vt |= 1 << p->id;
1394 }
1395 return 0;
1396 }
1397
1398 static int
1399 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1400 {
1401 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1402 u8 portmask[AR8X16_MAX_PORTS];
1403 int i, j;
1404
1405 mutex_lock(&priv->reg_mutex);
1406 /* flush all vlan translation unit entries */
1407 priv->chip->vtu_flush(priv);
1408
1409 memset(portmask, 0, sizeof(portmask));
1410 if (!priv->init) {
1411 /* calculate the port destination masks and load vlans
1412 * into the vlan translation unit */
1413 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1414 u8 vp = priv->vlan_table[j];
1415
1416 if (!vp)
1417 continue;
1418
1419 for (i = 0; i < dev->ports; i++) {
1420 u8 mask = (1 << i);
1421 if (vp & mask)
1422 portmask[i] |= vp & ~mask;
1423 }
1424
1425 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1426 priv->vlan_table[j]);
1427 }
1428 } else {
1429 /* vlan disabled:
1430 * isolate all ports, but connect them to the cpu port */
1431 for (i = 0; i < dev->ports; i++) {
1432 if (i == AR8216_PORT_CPU)
1433 continue;
1434
1435 portmask[i] = 1 << AR8216_PORT_CPU;
1436 portmask[AR8216_PORT_CPU] |= (1 << i);
1437 }
1438 }
1439
1440 /* update the port destination mask registers and tag settings */
1441 for (i = 0; i < dev->ports; i++) {
1442 int egress, ingress;
1443 int pvid;
1444
1445 if (priv->vlan) {
1446 pvid = priv->vlan_id[priv->pvid[i]];
1447 if (priv->vlan_tagged & (1 << i))
1448 egress = AR8216_OUT_ADD_VLAN;
1449 else
1450 egress = AR8216_OUT_STRIP_VLAN;
1451 ingress = AR8216_IN_SECURE;
1452 } else {
1453 pvid = i;
1454 egress = AR8216_OUT_KEEP;
1455 ingress = AR8216_IN_PORT_ONLY;
1456 }
1457
1458 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
1459 pvid);
1460 }
1461 mutex_unlock(&priv->reg_mutex);
1462 return 0;
1463 }
1464
1465 static int
1466 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1467 {
1468 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1469 int i;
1470
1471 mutex_lock(&priv->reg_mutex);
1472 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1473 offsetof(struct ar8xxx_priv, vlan));
1474
1475 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1476 priv->vlan_id[i] = i;
1477
1478 /* Configure all ports */
1479 for (i = 0; i < dev->ports; i++)
1480 priv->chip->init_port(priv, i);
1481
1482 priv->chip->init_globals(priv);
1483 mutex_unlock(&priv->reg_mutex);
1484
1485 return ar8xxx_sw_hw_apply(dev);
1486 }
1487
1488 static int
1489 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1490 const struct switch_attr *attr,
1491 struct switch_val *val)
1492 {
1493 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1494 unsigned int len;
1495 int ret;
1496
1497 if (!ar8xxx_has_mib_counters(priv))
1498 return -EOPNOTSUPP;
1499
1500 mutex_lock(&priv->mib_lock);
1501
1502 len = priv->dev.ports * priv->chip->num_mibs *
1503 sizeof(*priv->mib_stats);
1504 memset(priv->mib_stats, '\0', len);
1505 ret = ar8xxx_mib_flush(priv);
1506 if (ret)
1507 goto unlock;
1508
1509 ret = 0;
1510
1511 unlock:
1512 mutex_unlock(&priv->mib_lock);
1513 return ret;
1514 }
1515
1516 static int
1517 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1518 const struct switch_attr *attr,
1519 struct switch_val *val)
1520 {
1521 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1522 int port;
1523 int ret;
1524
1525 if (!ar8xxx_has_mib_counters(priv))
1526 return -EOPNOTSUPP;
1527
1528 port = val->port_vlan;
1529 if (port >= dev->ports)
1530 return -EINVAL;
1531
1532 mutex_lock(&priv->mib_lock);
1533 ret = ar8xxx_mib_capture(priv);
1534 if (ret)
1535 goto unlock;
1536
1537 ar8xxx_mib_fetch_port_stat(priv, port, true);
1538
1539 ret = 0;
1540
1541 unlock:
1542 mutex_unlock(&priv->mib_lock);
1543 return ret;
1544 }
1545
1546 static int
1547 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1548 const struct switch_attr *attr,
1549 struct switch_val *val)
1550 {
1551 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1552 const struct ar8xxx_chip *chip = priv->chip;
1553 u64 *mib_stats;
1554 int port;
1555 int ret;
1556 char *buf = priv->buf;
1557 int i, len = 0;
1558
1559 if (!ar8xxx_has_mib_counters(priv))
1560 return -EOPNOTSUPP;
1561
1562 port = val->port_vlan;
1563 if (port >= dev->ports)
1564 return -EINVAL;
1565
1566 mutex_lock(&priv->mib_lock);
1567 ret = ar8xxx_mib_capture(priv);
1568 if (ret)
1569 goto unlock;
1570
1571 ar8xxx_mib_fetch_port_stat(priv, port, false);
1572
1573 len += snprintf(buf + len, sizeof(priv->buf) - len,
1574 "Port %d MIB counters\n",
1575 port);
1576
1577 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1578 for (i = 0; i < chip->num_mibs; i++)
1579 len += snprintf(buf + len, sizeof(priv->buf) - len,
1580 "%-12s: %llu\n",
1581 chip->mib_decs[i].name,
1582 mib_stats[i]);
1583
1584 val->value.s = buf;
1585 val->len = len;
1586
1587 ret = 0;
1588
1589 unlock:
1590 mutex_unlock(&priv->mib_lock);
1591 return ret;
1592 }
1593
1594 static struct switch_attr ar8xxx_sw_attr_globals[] = {
1595 {
1596 .type = SWITCH_TYPE_INT,
1597 .name = "enable_vlan",
1598 .description = "Enable VLAN mode",
1599 .set = ar8xxx_sw_set_vlan,
1600 .get = ar8xxx_sw_get_vlan,
1601 .max = 1
1602 },
1603 {
1604 .type = SWITCH_TYPE_NOVAL,
1605 .name = "reset_mibs",
1606 .description = "Reset all MIB counters",
1607 .set = ar8xxx_sw_set_reset_mibs,
1608 },
1609
1610 };
1611
1612 static struct switch_attr ar8xxx_sw_attr_port[] = {
1613 {
1614 .type = SWITCH_TYPE_NOVAL,
1615 .name = "reset_mib",
1616 .description = "Reset single port MIB counters",
1617 .set = ar8xxx_sw_set_port_reset_mib,
1618 },
1619 {
1620 .type = SWITCH_TYPE_STRING,
1621 .name = "mib",
1622 .description = "Get port's MIB counters",
1623 .set = NULL,
1624 .get = ar8xxx_sw_get_port_mib,
1625 },
1626 };
1627
1628 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
1629 {
1630 .type = SWITCH_TYPE_INT,
1631 .name = "vid",
1632 .description = "VLAN ID (0-4094)",
1633 .set = ar8xxx_sw_set_vid,
1634 .get = ar8xxx_sw_get_vid,
1635 .max = 4094,
1636 },
1637 };
1638
1639 static const struct switch_dev_ops ar8xxx_sw_ops = {
1640 .attr_global = {
1641 .attr = ar8xxx_sw_attr_globals,
1642 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1643 },
1644 .attr_port = {
1645 .attr = ar8xxx_sw_attr_port,
1646 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1647 },
1648 .attr_vlan = {
1649 .attr = ar8xxx_sw_attr_vlan,
1650 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1651 },
1652 .get_port_pvid = ar8xxx_sw_get_pvid,
1653 .set_port_pvid = ar8xxx_sw_set_pvid,
1654 .get_vlan_ports = ar8xxx_sw_get_ports,
1655 .set_vlan_ports = ar8xxx_sw_set_ports,
1656 .apply_config = ar8xxx_sw_hw_apply,
1657 .reset_switch = ar8xxx_sw_reset_switch,
1658 .get_port_link = ar8xxx_sw_get_port_link,
1659 };
1660
1661 static int
1662 ar8xxx_id_chip(struct ar8xxx_priv *priv)
1663 {
1664 u32 val;
1665 u16 id;
1666 int i;
1667
1668 val = priv->read(priv, AR8216_REG_CTRL);
1669 if (val == ~0)
1670 return -ENODEV;
1671
1672 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1673 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1674 u16 t;
1675
1676 val = priv->read(priv, AR8216_REG_CTRL);
1677 if (val == ~0)
1678 return -ENODEV;
1679
1680 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1681 if (t != id)
1682 return -ENODEV;
1683 }
1684
1685 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1686 priv->chip_rev = (id & AR8216_CTRL_REVISION);
1687
1688 switch (priv->chip_ver) {
1689 case AR8XXX_VER_AR8216:
1690 priv->chip = &ar8216_chip;
1691 break;
1692 case AR8XXX_VER_AR8236:
1693 priv->chip = &ar8236_chip;
1694 break;
1695 case AR8XXX_VER_AR8316:
1696 priv->chip = &ar8316_chip;
1697 break;
1698 case AR8XXX_VER_AR8327:
1699 priv->mii_lo_first = true;
1700 priv->chip = &ar8327_chip;
1701 break;
1702 default:
1703 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1704 priv->chip_ver, priv->chip_rev);
1705
1706 return -ENODEV;
1707 }
1708
1709 return 0;
1710 }
1711
1712 static void
1713 ar8xxx_mib_work_func(struct work_struct *work)
1714 {
1715 struct ar8xxx_priv *priv;
1716 int err;
1717
1718 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
1719
1720 mutex_lock(&priv->mib_lock);
1721
1722 err = ar8xxx_mib_capture(priv);
1723 if (err)
1724 goto next_port;
1725
1726 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1727
1728 next_port:
1729 priv->mib_next_port++;
1730 if (priv->mib_next_port >= priv->dev.ports)
1731 priv->mib_next_port = 0;
1732
1733 mutex_unlock(&priv->mib_lock);
1734 schedule_delayed_work(&priv->mib_work,
1735 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1736 }
1737
1738 static int
1739 ar8xxx_mib_init(struct ar8xxx_priv *priv)
1740 {
1741 unsigned int len;
1742
1743 if (!ar8xxx_has_mib_counters(priv))
1744 return 0;
1745
1746 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1747
1748 len = priv->dev.ports * priv->chip->num_mibs *
1749 sizeof(*priv->mib_stats);
1750 priv->mib_stats = kzalloc(len, GFP_KERNEL);
1751
1752 if (!priv->mib_stats)
1753 return -ENOMEM;
1754
1755 return 0;
1756 }
1757
1758 static void
1759 ar8xxx_mib_start(struct ar8xxx_priv *priv)
1760 {
1761 if (!ar8xxx_has_mib_counters(priv))
1762 return;
1763
1764 schedule_delayed_work(&priv->mib_work,
1765 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1766 }
1767
1768 static void
1769 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
1770 {
1771 if (!ar8xxx_has_mib_counters(priv))
1772 return;
1773
1774 cancel_delayed_work(&priv->mib_work);
1775 }
1776
1777 static struct ar8xxx_priv *
1778 ar8xxx_create(void)
1779 {
1780 struct ar8xxx_priv *priv;
1781
1782 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
1783 if (priv == NULL)
1784 return NULL;
1785
1786 mutex_init(&priv->reg_mutex);
1787 mutex_init(&priv->mib_lock);
1788 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1789
1790 return priv;
1791 }
1792
1793 static void
1794 ar8xxx_free(struct ar8xxx_priv *priv)
1795 {
1796 kfree(priv->mib_stats);
1797 kfree(priv);
1798 }
1799
1800 static struct ar8xxx_priv *
1801 ar8xxx_create_mii(struct mii_bus *bus)
1802 {
1803 struct ar8xxx_priv *priv;
1804
1805 priv = ar8xxx_create();
1806 if (priv) {
1807 priv->mii_bus = bus;
1808 priv->read = ar8xxx_mii_read;
1809 priv->write = ar8xxx_mii_write;
1810 }
1811
1812 return priv;
1813 }
1814
1815 static int
1816 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
1817 {
1818 struct switch_dev *swdev;
1819 int ret;
1820
1821 ret = ar8xxx_id_chip(priv);
1822 if (ret)
1823 return ret;
1824
1825 swdev = &priv->dev;
1826 swdev->cpu_port = AR8216_PORT_CPU;
1827 swdev->ops = &ar8xxx_sw_ops;
1828
1829 if (chip_is_ar8316(priv)) {
1830 swdev->name = "Atheros AR8316";
1831 swdev->vlans = AR8X16_MAX_VLANS;
1832 swdev->ports = AR8216_NUM_PORTS;
1833 } else if (chip_is_ar8236(priv)) {
1834 swdev->name = "Atheros AR8236";
1835 swdev->vlans = AR8216_NUM_VLANS;
1836 swdev->ports = AR8216_NUM_PORTS;
1837 } else if (chip_is_ar8327(priv)) {
1838 swdev->name = "Atheros AR8327";
1839 swdev->vlans = AR8X16_MAX_VLANS;
1840 swdev->ports = AR8327_NUM_PORTS;
1841 } else {
1842 swdev->name = "Atheros AR8216";
1843 swdev->vlans = AR8216_NUM_VLANS;
1844 swdev->ports = AR8216_NUM_PORTS;
1845 }
1846
1847 ret = ar8xxx_mib_init(priv);
1848 if (ret)
1849 return ret;
1850
1851 return 0;
1852 }
1853
1854 static int
1855 ar8xxx_phy_config_init(struct phy_device *phydev)
1856 {
1857 struct ar8xxx_priv *priv = phydev->priv;
1858 struct net_device *dev = phydev->attached_dev;
1859 int ret;
1860
1861 if (WARN_ON(!priv))
1862 return -ENODEV;
1863
1864 priv->phy = phydev;
1865
1866 if (phydev->addr != 0) {
1867 if (chip_is_ar8316(priv)) {
1868 /* switch device has been initialized, reinit */
1869 priv->dev.ports = (AR8216_NUM_PORTS - 1);
1870 priv->initialized = false;
1871 priv->port4_phy = true;
1872 ar8316_hw_init(priv);
1873 return 0;
1874 }
1875
1876 return 0;
1877 }
1878
1879 priv->init = true;
1880
1881 ret = priv->chip->hw_init(priv);
1882 if (ret)
1883 return ret;
1884
1885 ret = ar8xxx_sw_reset_switch(&priv->dev);
1886 if (ret)
1887 return ret;
1888
1889 /* VID fixup only needed on ar8216 */
1890 if (chip_is_ar8216(priv)) {
1891 dev->phy_ptr = priv;
1892 dev->priv_flags |= IFF_NO_IP_ALIGN;
1893 dev->eth_mangle_rx = ar8216_mangle_rx;
1894 dev->eth_mangle_tx = ar8216_mangle_tx;
1895 }
1896
1897 priv->init = false;
1898
1899 ar8xxx_mib_start(priv);
1900
1901 return 0;
1902 }
1903
1904 static int
1905 ar8xxx_phy_read_status(struct phy_device *phydev)
1906 {
1907 struct ar8xxx_priv *priv = phydev->priv;
1908 struct switch_port_link link;
1909 int ret;
1910
1911 if (phydev->addr != 0)
1912 return genphy_read_status(phydev);
1913
1914 ar8216_read_port_link(priv, phydev->addr, &link);
1915 phydev->link = !!link.link;
1916 if (!phydev->link)
1917 return 0;
1918
1919 switch (link.speed) {
1920 case SWITCH_PORT_SPEED_10:
1921 phydev->speed = SPEED_10;
1922 break;
1923 case SWITCH_PORT_SPEED_100:
1924 phydev->speed = SPEED_100;
1925 break;
1926 case SWITCH_PORT_SPEED_1000:
1927 phydev->speed = SPEED_1000;
1928 break;
1929 default:
1930 phydev->speed = 0;
1931 }
1932 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1933
1934 /* flush the address translation unit */
1935 mutex_lock(&priv->reg_mutex);
1936 ret = priv->chip->atu_flush(priv);
1937 mutex_unlock(&priv->reg_mutex);
1938
1939 phydev->state = PHY_RUNNING;
1940 netif_carrier_on(phydev->attached_dev);
1941 phydev->adjust_link(phydev->attached_dev);
1942
1943 return ret;
1944 }
1945
1946 static int
1947 ar8xxx_phy_config_aneg(struct phy_device *phydev)
1948 {
1949 if (phydev->addr == 0)
1950 return 0;
1951
1952 return genphy_config_aneg(phydev);
1953 }
1954
1955 static const u32 ar8xxx_phy_ids[] = {
1956 0x004dd033,
1957 0x004dd041,
1958 0x004dd042,
1959 };
1960
1961 static bool
1962 ar8xxx_phy_match(u32 phy_id)
1963 {
1964 int i;
1965
1966 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
1967 if (phy_id == ar8xxx_phy_ids[i])
1968 return true;
1969
1970 return false;
1971 }
1972
1973 static bool
1974 ar8xxx_is_possible(struct mii_bus *bus)
1975 {
1976 unsigned i;
1977
1978 for (i = 0; i < 4; i++) {
1979 u32 phy_id;
1980
1981 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
1982 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
1983 if (!ar8xxx_phy_match(phy_id)) {
1984 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
1985 dev_name(&bus->dev), i, phy_id);
1986 return false;
1987 }
1988 }
1989
1990 return true;
1991 }
1992
1993 static int
1994 ar8xxx_phy_probe(struct phy_device *phydev)
1995 {
1996 struct ar8xxx_priv *priv;
1997 struct switch_dev *swdev;
1998 int ret;
1999
2000 /* skip PHYs at unused adresses */
2001 if (phydev->addr != 0 && phydev->addr != 4)
2002 return -ENODEV;
2003
2004 if (!ar8xxx_is_possible(phydev->bus))
2005 return -ENODEV;
2006
2007 mutex_lock(&ar8xxx_dev_list_lock);
2008 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2009 if (priv->mii_bus == phydev->bus)
2010 goto found;
2011
2012 priv = ar8xxx_create_mii(phydev->bus);
2013 if (priv == NULL) {
2014 ret = -ENOMEM;
2015 goto unlock;
2016 }
2017
2018 ret = ar8xxx_probe_switch(priv);
2019 if (ret)
2020 goto free_priv;
2021
2022 swdev = &priv->dev;
2023 swdev->alias = dev_name(&priv->mii_bus->dev);
2024 ret = register_switch(swdev, NULL);
2025 if (ret)
2026 goto free_priv;
2027
2028 pr_info("%s: %s switch registered on %s\n",
2029 swdev->devname, swdev->name, dev_name(&priv->mii_bus->dev));
2030
2031 found:
2032 if (phydev->addr == 0) {
2033 if (ar8xxx_has_gige(priv)) {
2034 phydev->supported = SUPPORTED_1000baseT_Full;
2035 phydev->advertising = ADVERTISED_1000baseT_Full;
2036 } else {
2037 phydev->supported = SUPPORTED_100baseT_Full;
2038 phydev->advertising = ADVERTISED_100baseT_Full;
2039 }
2040 } else {
2041 if (ar8xxx_has_gige(priv)) {
2042 phydev->supported |= SUPPORTED_1000baseT_Full;
2043 phydev->advertising |= ADVERTISED_1000baseT_Full;
2044 }
2045 }
2046
2047 phydev->priv = priv;
2048 priv->use_count++;
2049
2050 list_add(&priv->list, &ar8xxx_dev_list);
2051
2052 mutex_unlock(&ar8xxx_dev_list_lock);
2053
2054 return 0;
2055
2056 free_priv:
2057 ar8xxx_free(priv);
2058 unlock:
2059 mutex_unlock(&ar8xxx_dev_list_lock);
2060 return ret;
2061 }
2062
2063 static void
2064 ar8xxx_phy_detach(struct phy_device *phydev)
2065 {
2066 struct net_device *dev = phydev->attached_dev;
2067
2068 if (!dev)
2069 return;
2070
2071 dev->phy_ptr = NULL;
2072 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2073 dev->eth_mangle_rx = NULL;
2074 dev->eth_mangle_tx = NULL;
2075 }
2076
2077 static void
2078 ar8xxx_phy_remove(struct phy_device *phydev)
2079 {
2080 struct ar8xxx_priv *priv = phydev->priv;
2081
2082 if (WARN_ON(!priv))
2083 return;
2084
2085 phydev->priv = NULL;
2086 if (--priv->use_count > 0)
2087 return;
2088
2089 mutex_lock(&ar8xxx_dev_list_lock);
2090 list_del(&priv->list);
2091 mutex_unlock(&ar8xxx_dev_list_lock);
2092
2093 unregister_switch(&priv->dev);
2094 ar8xxx_mib_stop(priv);
2095 ar8xxx_free(priv);
2096 }
2097
2098 static struct phy_driver ar8xxx_phy_driver = {
2099 .phy_id = 0x004d0000,
2100 .name = "Atheros AR8216/AR8236/AR8316",
2101 .phy_id_mask = 0xffff0000,
2102 .features = PHY_BASIC_FEATURES,
2103 .probe = ar8xxx_phy_probe,
2104 .remove = ar8xxx_phy_remove,
2105 .detach = ar8xxx_phy_detach,
2106 .config_init = ar8xxx_phy_config_init,
2107 .config_aneg = ar8xxx_phy_config_aneg,
2108 .read_status = ar8xxx_phy_read_status,
2109 .driver = { .owner = THIS_MODULE },
2110 };
2111
2112 int __init
2113 ar8xxx_init(void)
2114 {
2115 return phy_driver_register(&ar8xxx_phy_driver);
2116 }
2117
2118 void __exit
2119 ar8xxx_exit(void)
2120 {
2121 phy_driver_unregister(&ar8xxx_phy_driver);
2122 }
2123
2124 module_init(ar8xxx_init);
2125 module_exit(ar8xxx_exit);
2126 MODULE_LICENSE("GPL");
2127
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