target/linux/mediatek/patches-4.14/0125-phy-phy-mtk-tphy-add-set_mode-callback.patch

   1 From d42ebed1aa669c5a897ec0aa5e1ede8d9069894a Mon Sep 17 00:00:00 2001
   2 From: Chunfeng Yun <chunfeng.yun@mediatek.com>
   3 Date: Thu, 21 Sep 2017 18:31:49 +0800
   4 Subject: [PATCH 125/224] phy: phy-mtk-tphy: add set_mode callback
   5
   6 This is used to force PHY with USB OTG function to enter a specific
   7 mode, and override OTG IDPIN(or IDDIG) signal.
   8
   9 Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
  10 Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  11 ---
  12  drivers/phy/mediatek/phy-mtk-tphy.c | 39 +++++++++++++++++++++++++++++++++++++
  13  1 file changed, 39 insertions(+)
  14
  15 diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
  16 index 721a2a1c97ef..402385f2562a 100644
  17 --- a/drivers/phy/mediatek/phy-mtk-tphy.c
  18 +++ b/drivers/phy/mediatek/phy-mtk-tphy.c
  19 @@ -96,9 +96,11 @@
  20
  21  #define U3P_U2PHYDTM1          0x06C
  22  #define P2C_RG_UART_EN                 BIT(16)
  23 +#define P2C_FORCE_IDDIG                BIT(9)
  24  #define P2C_RG_VBUSVALID               BIT(5)
  25  #define P2C_RG_SESSEND                 BIT(4)
  26  #define P2C_RG_AVALID                  BIT(2)
  27 +#define P2C_RG_IDDIG                   BIT(1)
  28
  29  #define U3P_U3_CHIP_GPIO_CTLD          0x0c
  30  #define P3C_REG_IP_SW_RST              BIT(31)
  31 @@ -585,6 +587,31 @@ static void u2_phy_instance_exit(struct mtk_tphy *tphy,
  32         }
  33  }
  34
  35 +static void u2_phy_instance_set_mode(struct mtk_tphy *tphy,
  36 +                                    struct mtk_phy_instance *instance,
  37 +                                    enum phy_mode mode)
  38 +{
  39 +       struct u2phy_banks *u2_banks = &instance->u2_banks;
  40 +       u32 tmp;
  41 +
  42 +       tmp = readl(u2_banks->com + U3P_U2PHYDTM1);
  43 +       switch (mode) {
  44 +       case PHY_MODE_USB_DEVICE:
  45 +               tmp |= P2C_FORCE_IDDIG | P2C_RG_IDDIG;
  46 +               break;
  47 +       case PHY_MODE_USB_HOST:
  48 +               tmp |= P2C_FORCE_IDDIG;
  49 +               tmp &= ~P2C_RG_IDDIG;
  50 +               break;
  51 +       case PHY_MODE_USB_OTG:
  52 +               tmp &= ~(P2C_FORCE_IDDIG | P2C_RG_IDDIG);
  53 +               break;
  54 +       default:
  55 +               return;
  56 +       }
  57 +       writel(tmp, u2_banks->com + U3P_U2PHYDTM1);
  58 +}
  59 +
  60  static void pcie_phy_instance_init(struct mtk_tphy *tphy,
  61         struct mtk_phy_instance *instance)
  62  {
  63 @@ -881,6 +908,17 @@ static int mtk_phy_exit(struct phy *phy)
  64         return 0;
  65  }
  66
  67 +static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode)
  68 +{
  69 +       struct mtk_phy_instance *instance = phy_get_drvdata(phy);
  70 +       struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
  71 +
  72 +       if (instance->type == PHY_TYPE_USB2)
  73 +               u2_phy_instance_set_mode(tphy, instance, mode);
  74 +
  75 +       return 0;
  76 +}
  77 +
  78  static struct phy *mtk_phy_xlate(struct device *dev,
  79                                         struct of_phandle_args *args)
  80  {
  81 @@ -931,6 +969,7 @@ static const struct phy_ops mtk_tphy_ops = {
  82         .exit           = mtk_phy_exit,
  83         .power_on       = mtk_phy_power_on,
  84         .power_off      = mtk_phy_power_off,
  85 +       .set_mode       = mtk_phy_set_mode,
  86         .owner          = THIS_MODULE,
  87  };
  88
  89 --
  90 2.11.0
  91