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mediatek: backport upstream mediatek patches
[openwrt/openwrt.git] / target / linux / mediatek / patches-4.14 / 0183-ASoC-mediatek-update-clock-related-properties-of-MT2.patch
1 From d5b391bb7208c8a7b6b874c1357d3cd110537167 Mon Sep 17 00:00:00 2001
2 From: Ryder Lee <ryder.lee@mediatek.com>
3 Date: Tue, 2 Jan 2018 19:47:21 +0800
4 Subject: [PATCH 183/224] ASoC: mediatek: update clock related properties of
5 MT2701 AFE
6
7 Add 'assigned-clocks*' properties which are used to initialize default
8 domain sources of audio system. we could configure different sets of
9 input clocks through DTS now. Hence driver no longer cares about that.
10
11 Also we change some 'clock-names' to make them more generic so that
12 other chips can reuse gracefully.
13
14 Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
15 Signed-off-by: Mark Brown <broonie@kernel.org>
16 ---
17 .../devicetree/bindings/sound/mt2701-afe-pcm.txt | 207 +++++++++------------
18 1 file changed, 91 insertions(+), 116 deletions(-)
19
20 diff --git a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
21 index 77a57f84bed4..0450baad2813 100644
22 --- a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
23 +++ b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
24 @@ -6,51 +6,44 @@ Required properties:
25 - interrupts: should contain AFE and ASYS interrupts
26 - interrupt-names: should be "afe" and "asys"
27 - power-domains: should define the power domain
28 +- clocks: Must contain an entry for each entry in clock-names
29 + See ../clocks/clock-bindings.txt for details
30 - clock-names: should have these clock names:
31 - "infra_sys_audio_clk",
32 "top_audio_mux1_sel",
33 "top_audio_mux2_sel",
34 - "top_audio_mux1_div",
35 - "top_audio_mux2_div",
36 - "top_audio_48k_timing",
37 - "top_audio_44k_timing",
38 - "top_audpll_mux_sel",
39 - "top_apll_sel",
40 - "top_aud1_pll_98M",
41 - "top_aud2_pll_90M",
42 - "top_hadds2_pll_98M",
43 - "top_hadds2_pll_294M",
44 - "top_audpll",
45 - "top_audpll_d4",
46 - "top_audpll_d8",
47 - "top_audpll_d16",
48 - "top_audpll_d24",
49 - "top_audintbus_sel",
50 - "clk_26m",
51 - "top_syspll1_d4",
52 - "top_aud_k1_src_sel",
53 - "top_aud_k2_src_sel",
54 - "top_aud_k3_src_sel",
55 - "top_aud_k4_src_sel",
56 - "top_aud_k5_src_sel",
57 - "top_aud_k6_src_sel",
58 - "top_aud_k1_src_div",
59 - "top_aud_k2_src_div",
60 - "top_aud_k3_src_div",
61 - "top_aud_k4_src_div",
62 - "top_aud_k5_src_div",
63 - "top_aud_k6_src_div",
64 - "top_aud_i2s1_mclk",
65 - "top_aud_i2s2_mclk",
66 - "top_aud_i2s3_mclk",
67 - "top_aud_i2s4_mclk",
68 - "top_aud_i2s5_mclk",
69 - "top_aud_i2s6_mclk",
70 - "top_asm_m_sel",
71 - "top_asm_h_sel",
72 - "top_univpll2_d4",
73 - "top_univpll2_d2",
74 - "top_syspll_d5";
75 + "i2s0_src_sel",
76 + "i2s1_src_sel",
77 + "i2s2_src_sel",
78 + "i2s3_src_sel",
79 + "i2s0_src_div",
80 + "i2s1_src_div",
81 + "i2s2_src_div",
82 + "i2s3_src_div",
83 + "i2s0_mclk_en",
84 + "i2s1_mclk_en",
85 + "i2s2_mclk_en",
86 + "i2s3_mclk_en",
87 + "i2so0_hop_ck",
88 + "i2so1_hop_ck",
89 + "i2so2_hop_ck",
90 + "i2so3_hop_ck",
91 + "i2si0_hop_ck",
92 + "i2si1_hop_ck",
93 + "i2si2_hop_ck",
94 + "i2si3_hop_ck",
95 + "asrc0_out_ck",
96 + "asrc1_out_ck",
97 + "asrc2_out_ck",
98 + "asrc3_out_ck",
99 + "audio_afe_pd",
100 + "audio_afe_conn_pd",
101 + "audio_a1sys_pd",
102 + "audio_a2sys_pd",
103 + "audio_mrgif_pd";
104 +- assigned-clocks: list of input clocks and dividers for the audio system.
105 + See ../clocks/clock-bindings.txt for details.
106 +- assigned-clocks-parents: parent of input clocks of assigned clocks.
107 +- assigned-clock-rates: list of clock frequencies of assigned clocks.
108
109 Example:
110
111 @@ -62,93 +55,75 @@ Example:
112 <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
113 interrupt-names = "afe", "asys";
114 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
115 - clocks = <&infracfg CLK_INFRA_AUDIO>,
116 - <&topckgen CLK_TOP_AUD_MUX1_SEL>,
117 + clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
118 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
119 - <&topckgen CLK_TOP_AUD_MUX1_DIV>,
120 - <&topckgen CLK_TOP_AUD_MUX2_DIV>,
121 - <&topckgen CLK_TOP_AUD_48K_TIMING>,
122 - <&topckgen CLK_TOP_AUD_44K_TIMING>,
123 - <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
124 - <&topckgen CLK_TOP_APLL_SEL>,
125 - <&topckgen CLK_TOP_AUD1PLL_98M>,
126 - <&topckgen CLK_TOP_AUD2PLL_90M>,
127 - <&topckgen CLK_TOP_HADDS2PLL_98M>,
128 - <&topckgen CLK_TOP_HADDS2PLL_294M>,
129 - <&topckgen CLK_TOP_AUDPLL>,
130 - <&topckgen CLK_TOP_AUDPLL_D4>,
131 - <&topckgen CLK_TOP_AUDPLL_D8>,
132 - <&topckgen CLK_TOP_AUDPLL_D16>,
133 - <&topckgen CLK_TOP_AUDPLL_D24>,
134 - <&topckgen CLK_TOP_AUDINTBUS_SEL>,
135 - <&clk26m>,
136 - <&topckgen CLK_TOP_SYSPLL1_D4>,
137 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
138 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
139 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
140 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
141 - <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
142 - <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
143 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
144 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
145 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
146 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
147 - <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
148 - <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
149 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
150 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
151 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
152 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
153 - <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
154 - <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
155 - <&topckgen CLK_TOP_ASM_M_SEL>,
156 - <&topckgen CLK_TOP_ASM_H_SEL>,
157 - <&topckgen CLK_TOP_UNIVPLL2_D4>,
158 - <&topckgen CLK_TOP_UNIVPLL2_D2>,
159 - <&topckgen CLK_TOP_SYSPLL_D5>;
160 + <&audiosys CLK_AUD_I2SO1>,
161 + <&audiosys CLK_AUD_I2SO2>,
162 + <&audiosys CLK_AUD_I2SO3>,
163 + <&audiosys CLK_AUD_I2SO4>,
164 + <&audiosys CLK_AUD_I2SIN1>,
165 + <&audiosys CLK_AUD_I2SIN2>,
166 + <&audiosys CLK_AUD_I2SIN3>,
167 + <&audiosys CLK_AUD_I2SIN4>,
168 + <&audiosys CLK_AUD_ASRCO1>,
169 + <&audiosys CLK_AUD_ASRCO2>,
170 + <&audiosys CLK_AUD_ASRCO3>,
171 + <&audiosys CLK_AUD_ASRCO4>,
172 + <&audiosys CLK_AUD_AFE>,
173 + <&audiosys CLK_AUD_AFE_CONN>,
174 + <&audiosys CLK_AUD_A1SYS>,
175 + <&audiosys CLK_AUD_A2SYS>,
176 + <&audiosys CLK_AUD_AFE_MRGIF>;
177
178 - clock-names = "infra_sys_audio_clk",
179 - "top_audio_mux1_sel",
180 + clock-names = "top_audio_mux1_sel",
181 "top_audio_mux2_sel",
182 - "top_audio_mux1_div",
183 - "top_audio_mux2_div",
184 - "top_audio_48k_timing",
185 - "top_audio_44k_timing",
186 - "top_audpll_mux_sel",
187 - "top_apll_sel",
188 - "top_aud1_pll_98M",
189 - "top_aud2_pll_90M",
190 - "top_hadds2_pll_98M",
191 - "top_hadds2_pll_294M",
192 - "top_audpll",
193 - "top_audpll_d4",
194 - "top_audpll_d8",
195 - "top_audpll_d16",
196 - "top_audpll_d24",
197 - "top_audintbus_sel",
198 - "clk_26m",
199 - "top_syspll1_d4",
200 - "top_aud_k1_src_sel",
201 - "top_aud_k2_src_sel",
202 - "top_aud_k3_src_sel",
203 - "top_aud_k4_src_sel",
204 - "top_aud_k5_src_sel",
205 - "top_aud_k6_src_sel",
206 - "top_aud_k1_src_div",
207 - "top_aud_k2_src_div",
208 - "top_aud_k3_src_div",
209 - "top_aud_k4_src_div",
210 - "top_aud_k5_src_div",
211 - "top_aud_k6_src_div",
212 - "top_aud_i2s1_mclk",
213 - "top_aud_i2s2_mclk",
214 - "top_aud_i2s3_mclk",
215 - "top_aud_i2s4_mclk",
216 - "top_aud_i2s5_mclk",
217 - "top_aud_i2s6_mclk",
218 - "top_asm_m_sel",
219 - "top_asm_h_sel",
220 - "top_univpll2_d4",
221 - "top_univpll2_d2",
222 - "top_syspll_d5";
223 + "i2s0_src_sel",
224 + "i2s1_src_sel",
225 + "i2s2_src_sel",
226 + "i2s3_src_sel",
227 + "i2s0_src_div",
228 + "i2s1_src_div",
229 + "i2s2_src_div",
230 + "i2s3_src_div",
231 + "i2s0_mclk_en",
232 + "i2s1_mclk_en",
233 + "i2s2_mclk_en",
234 + "i2s3_mclk_en",
235 + "i2so0_hop_ck",
236 + "i2so1_hop_ck",
237 + "i2so2_hop_ck",
238 + "i2so3_hop_ck",
239 + "i2si0_hop_ck",
240 + "i2si1_hop_ck",
241 + "i2si2_hop_ck",
242 + "i2si3_hop_ck",
243 + "asrc0_out_ck",
244 + "asrc1_out_ck",
245 + "asrc2_out_ck",
246 + "asrc3_out_ck",
247 + "audio_afe_pd",
248 + "audio_afe_conn_pd",
249 + "audio_a1sys_pd",
250 + "audio_a2sys_pd",
251 + "audio_mrgif_pd";
252 +
253 + assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
254 + <&topckgen CLK_TOP_AUD_MUX2_SEL>,
255 + <&topckgen CLK_TOP_AUD_MUX1_DIV>,
256 + <&topckgen CLK_TOP_AUD_MUX2_DIV>;
257 + assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
258 + <&topckgen CLK_TOP_AUD2PLL_90M>;
259 + assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
260 };
261 --
262 2.11.0
263
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