target/linux/mediatek/patches-4.14/0213-arm64-dts-mt7622-add-PMIC-MT6380-related-nodes.patch

   1 From 78e92290c8c9511d0d540dfd0450e64169f08c20 Mon Sep 17 00:00:00 2001
   2 From: Sean Wang <sean.wang@mediatek.com>
   3 Date: Mon, 5 Feb 2018 22:44:44 +0800
   4 Subject: [PATCH 213/224] arm64: dts: mt7622: add PMIC MT6380 related nodes
   5
   6 Enable pwrap and MT6380 on mt7622-rfb1 board. Also add all mt6380
   7 regulator nodes in an alone file to allow similar boards using MT6380
   8 able to resue the configuration.
   9
  10 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
  11 Cc: Mark Brown <broonie@kernel.org>
  12 Cc: Matthias Brugger <matthias.bgg@gmail.com>
  13 Cc: Philippe Ombredanne <pombredanne@nexb.com>
  14 Acked-by: Philippe Ombredanne <pombredanne@nexb.com>
  15 ---
  16  arch/arm64/boot/dts/mediatek/mt6380.dtsi     | 86 ++++++++++++++++++++++++++++
  17  arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts |  8 +++
  18  arch/arm64/boot/dts/mediatek/mt7622.dtsi     | 12 ++++
  19  3 files changed, 106 insertions(+)
  20  create mode 100644 arch/arm64/boot/dts/mediatek/mt6380.dtsi
  21
  22 diff --git a/arch/arm64/boot/dts/mediatek/mt6380.dtsi b/arch/arm64/boot/dts/mediatek/mt6380.dtsi
  23 new file mode 100644
  24 index 000000000000..53b335d2de5f
  25 --- /dev/null
  26 +++ b/arch/arm64/boot/dts/mediatek/mt6380.dtsi
  27 @@ -0,0 +1,86 @@
  28 +// SPDX-License-Identifier: GPL-2.0
  29 +/*
  30 + * dts file for MediaTek MT6380 regulator
  31 + *
  32 + * Copyright (c) 2018 MediaTek Inc.
  33 + * Author: Chenglin Xu <chenglin.xu@mediatek.com>
  34 + *        Sean Wang <sean.wang@mediatek.com>
  35 + */
  36 +
  37 +&pwrap {
  38 +       regulators {
  39 +               compatible = "mediatek,mt6380-regulator";
  40 +
  41 +               mt6380_vcpu_reg: buck-vcore1 {
  42 +                       regulator-name = "vcore1";
  43 +                       regulator-min-microvolt = < 600000>;
  44 +                       regulator-max-microvolt = <1393750>;
  45 +                       regulator-ramp-delay = <6250>;
  46 +                       regulator-always-on;
  47 +                       regulator-boot-on;
  48 +               };
  49 +
  50 +               mt6380_vcore_reg: buck-vcore {
  51 +                       regulator-name = "vcore";
  52 +                       regulator-min-microvolt = <600000>;
  53 +                       regulator-max-microvolt = <1393750>;
  54 +                       regulator-ramp-delay = <6250>;
  55 +                       regulator-always-on;
  56 +                       regulator-boot-on;
  57 +               };
  58 +
  59 +               mt6380_vrf_reg: buck-vrf {
  60 +                       regulator-name = "vrf";
  61 +                       regulator-min-microvolt = <1200000>;
  62 +                       regulator-max-microvolt = <1575000>;
  63 +                       regulator-ramp-delay = <0>;
  64 +                       regulator-always-on;
  65 +                       regulator-boot-on;
  66 +               };
  67 +
  68 +               mt6380_vm_reg: ldo-vm {
  69 +                       regulator-name = "vm";
  70 +                       regulator-min-microvolt = <1050000>;
  71 +                       regulator-max-microvolt = <1400000>;
  72 +                       regulator-ramp-delay = <0>;
  73 +                       regulator-always-on;
  74 +                       regulator-boot-on;
  75 +               };
  76 +
  77 +               mt6380_va_reg: ldo-va {
  78 +                       regulator-name = "va";
  79 +                       regulator-min-microvolt = <2200000>;
  80 +                       regulator-max-microvolt = <3300000>;
  81 +                       regulator-ramp-delay = <0>;
  82 +                       regulator-always-on;
  83 +                       regulator-boot-on;
  84 +               };
  85 +
  86 +               mt6380_vphy_reg: ldo-vphy {
  87 +                       regulator-name = "vphy";
  88 +                       regulator-min-microvolt = <1800000>;
  89 +                       regulator-max-microvolt = <1800000>;
  90 +                       regulator-ramp-delay = <0>;
  91 +                       regulator-always-on;
  92 +                       regulator-boot-on;
  93 +               };
  94 +
  95 +               mt6380_vddr_reg: ldo-vddr {
  96 +                       regulator-name = "vddr";
  97 +                       regulator-min-microvolt = <1240000>;
  98 +                       regulator-max-microvolt = <1840000>;
  99 +                       regulator-ramp-delay = <0>;
 100 +                       regulator-always-on;
 101 +                       regulator-boot-on;
 102 +               };
 103 +
 104 +               mt6380_vt_reg: ldo-vt {
 105 +                       regulator-name = "vt";
 106 +                       regulator-min-microvolt = <2200000>;
 107 +                       regulator-max-microvolt = <3300000>;
 108 +                       regulator-ramp-delay = <0>;
 109 +                       regulator-always-on;
 110 +                       regulator-boot-on;
 111 +               };
 112 +       };
 113 +};
 114 diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
 115 index fc8ef78a0a34..42bd3a4c9a93 100644
 116 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
 117 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
 118 @@ -10,6 +10,7 @@
 119  #include <dt-bindings/input/input.h>
 120
 121  #include "mt7622.dtsi"
 122 +#include "mt6380.dtsi"
 123
 124  / {
 125         model = "MediaTek MT7622 RFB1 board";
 126 @@ -222,6 +223,13 @@
 127         };
 128  };
 129
 130 +&pwrap {
 131 +       pinctrl-names = "default";
 132 +       pinctrl-0 = <&pmic_bus_pins>;
 133 +
 134 +       status = "okay";
 135 +};
 136 +
 137  &uart0 {
 138         status = "okay";
 139  };
 140 diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 141 index 8211bf72ccaa..c387c4cb7d3e 100644
 142 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 143 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 144 @@ -102,6 +102,18 @@
 145                 #reset-cells = <1>;
 146         };
 147
 148 +       pwrap: pwrap@10001000 {
 149 +               compatible = "mediatek,mt7622-pwrap";
 150 +               reg = <0 0x10001000 0 0x250>;
 151 +               reg-names = "pwrap";
 152 +               clocks = <&infracfg CLK_INFRA_PMIC_PD>,<&pwrap_clk>;
 153 +               clock-names = "spi","wrap";
 154 +               resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
 155 +               reset-names = "pwrap";
 156 +               interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 157 +               status = "disabled";
 158 +       };
 159 +
 160         pericfg: pericfg@10002000 {
 161                 compatible = "mediatek,mt7622-pericfg",
 162                              "syscon";
 163 --
 164 2.11.0
 165