target/linux/mediatek/patches-4.14/0221-arm64-dts-mt7622-add-usb-device-nodes.patch

   1 From 3e23988f5c9c5d54732eda1e8017409ef223048b Mon Sep 17 00:00:00 2001
   2 From: Chunfeng Yun <chunfeng.yun@mediatek.com>
   3 Date: Fri, 12 Jan 2018 12:28:31 +0800
   4 Subject: [PATCH 221/224] arm64: dts: mt7622: add usb device nodes
   5
   6 add xhci node and usb3 phy nodes
   7
   8 Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
   9 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
  10 Tested-by: Jumin Li <jumin.li@mediatek.com>
  11 ---
  12  arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 28 +++++++++++++++
  13  arch/arm64/boot/dts/mediatek/mt7622.dtsi     | 51 ++++++++++++++++++++++++++++
  14  2 files changed, 79 insertions(+)
  15
  16 diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  17 index 6715ffa5c15e..cc89e2e3c597 100644
  18 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  19 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  20 @@ -52,6 +52,24 @@
  21         memory {
  22                 reg = <0 0x40000000 0 0x3F000000>;
  23         };
  24 +
  25 +       reg_3p3v: regulator-3p3v {
  26 +               compatible = "regulator-fixed";
  27 +               regulator-name = "fixed-3.3V";
  28 +               regulator-min-microvolt = <3300000>;
  29 +               regulator-max-microvolt = <3300000>;
  30 +               regulator-boot-on;
  31 +               regulator-always-on;
  32 +       };
  33 +
  34 +       reg_5v: regulator-5v {
  35 +               compatible = "regulator-fixed";
  36 +               regulator-name = "fixed-5V";
  37 +               regulator-min-microvolt = <5000000>;
  38 +               regulator-max-microvolt = <5000000>;
  39 +               regulator-boot-on;
  40 +               regulator-always-on;
  41 +       };
  42  };
  43
  44  &pcie {
  45 @@ -343,6 +361,16 @@
  46         status = "okay";
  47  };
  48
  49 +&ssusb {
  50 +       vusb33-supply = <&reg_3p3v>;
  51 +       vbus-supply = <&reg_5v>;
  52 +       status = "okay";
  53 +};
  54 +
  55 +&u3phy {
  56 +       status = "okay";
  57 +};
  58 +
  59  &uart0 {
  60         pinctrl-names = "default";
  61         pinctrl-0 = <&uart0_pins>;
  62 diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  63 index 881bc17f8f0d..bad1e997359a 100644
  64 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  65 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  66 @@ -535,6 +535,57 @@
  67                 #reset-cells = <1>;
  68         };
  69
  70 +       ssusb: usb@1a0c0000 {
  71 +               compatible = "mediatek,mt7622-xhci",
  72 +                            "mediatek,mtk-xhci";
  73 +               reg = <0 0x1a0c0000 0 0x01000>,
  74 +                     <0 0x1a0c4700 0 0x0100>;
  75 +               reg-names = "mac", "ippc";
  76 +               interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
  77 +               power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
  78 +               clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
  79 +                        <&ssusbsys CLK_SSUSB_REF_EN>,
  80 +                        <&ssusbsys CLK_SSUSB_MCU_EN>,
  81 +                        <&ssusbsys CLK_SSUSB_DMA_EN>;
  82 +               clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
  83 +               phys = <&u2port0 PHY_TYPE_USB2>,
  84 +                      <&u3port0 PHY_TYPE_USB3>,
  85 +                      <&u2port1 PHY_TYPE_USB2>;
  86 +
  87 +               status = "disabled";
  88 +       };
  89 +
  90 +       u3phy: usb-phy@1a0c4000 {
  91 +               compatible = "mediatek,mt7622-u3phy",
  92 +                            "mediatek,generic-tphy-v1";
  93 +               reg = <0 0x1a0c4000 0 0x700>;
  94 +               #address-cells = <2>;
  95 +               #size-cells = <2>;
  96 +               ranges;
  97 +               status = "disabled";
  98 +
  99 +               u2port0: usb-phy@1a0c4800 {
 100 +                       reg = <0 0x1a0c4800 0 0x0100>;
 101 +                       #phy-cells = <1>;
 102 +                       clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
 103 +                       clock-names = "ref";
 104 +               };
 105 +
 106 +               u3port0: usb-phy@1a0c4900 {
 107 +                       reg = <0 0x1a0c4900 0 0x0700>;
 108 +                       #phy-cells = <1>;
 109 +                       clocks = <&clk25m>;
 110 +                       clock-names = "ref";
 111 +               };
 112 +
 113 +               u2port1: usb-phy@1a0c5000 {
 114 +                       reg = <0 0x1a0c5000 0 0x0100>;
 115 +                       #phy-cells = <1>;
 116 +                       clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
 117 +                       clock-names = "ref";
 118 +               };
 119 +       };
 120 +
 121         pciesys: pciesys@1a100800 {
 122                 compatible = "mediatek,mt7622-pciesys",
 123                              "syscon";
 124 --
 125 2.11.0
 126