target/linux/mvebu/patches-4.14/503-cpufreq-Add-DVFS-support-for-Armada-37xx.patch

   1 From 92ce45fb875d7c3e021cc454482fe0687ff54f29 Mon Sep 17 00:00:00 2001
   2 From: Gregory CLEMENT <gregory.clement@free-electrons.com>
   3 Date: Thu, 14 Dec 2017 16:00:05 +0100
   4 Subject: cpufreq: Add DVFS support for Armada 37xx
   5
   6 This patch adds DVFS support for the Armada 37xx SoCs
   7
   8 There are up to four CPU frequency loads for Armada 37xx controlled by
   9 the hardware.
  10
  11 This driver associates the CPU load level to a frequency, then the
  12 hardware will switch while selecting a load level.
  13
  14 The hardware also can associate a voltage for each level (AVS support)
  15 but it is not yet supported
  16
  17 Tested-by: Andre Heider <a.heider@gmail.com>
  18 Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
  19 Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
  20 Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
  21 ---
  22  drivers/cpufreq/Kconfig.arm           |   7 +
  23  drivers/cpufreq/Makefile              |   1 +
  24  drivers/cpufreq/armada-37xx-cpufreq.c | 241 ++++++++++++++++++++++++++++++++++
  25  3 files changed, 249 insertions(+)
  26  create mode 100644 drivers/cpufreq/armada-37xx-cpufreq.c
  27
  28 --- a/drivers/cpufreq/Kconfig.arm
  29 +++ b/drivers/cpufreq/Kconfig.arm
  30 @@ -2,6 +2,13 @@
  31  # ARM CPU Frequency scaling drivers
  32  #
  33
  34 +config ARM_ARMADA_37XX_CPUFREQ
  35 +       tristate "Armada 37xx CPUFreq support"
  36 +       depends on ARCH_MVEBU
  37 +       help
  38 +         This adds the CPUFreq driver support for Marvell Armada 37xx SoCs.
  39 +         The Armada 37xx PMU supports 4 frequency and VDD levels.
  40 +
  41  # big LITTLE core layer and glue drivers
  42  config ARM_BIG_LITTLE_CPUFREQ
  43         tristate "Generic ARM big LITTLE CPUfreq driver"
  44 --- a/drivers/cpufreq/Makefile
  45 +++ b/drivers/cpufreq/Makefile
  46 @@ -52,6 +52,7 @@ obj-$(CONFIG_ARM_BIG_LITTLE_CPUFREQ)  +=
  47  # LITTLE drivers, so that it is probed last.
  48  obj-$(CONFIG_ARM_DT_BL_CPUFREQ)                += arm_big_little_dt.o
  49
  50 +obj-$(CONFIG_ARM_ARMADA_37XX_CPUFREQ)  += armada-37xx-cpufreq.o
  51  obj-$(CONFIG_ARM_BRCMSTB_AVS_CPUFREQ)  += brcmstb-avs-cpufreq.o
  52  obj-$(CONFIG_ARCH_DAVINCI)             += davinci-cpufreq.o
  53  obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ)   += exynos5440-cpufreq.o
  54 --- /dev/null
  55 +++ b/drivers/cpufreq/armada-37xx-cpufreq.c
  56 @@ -0,0 +1,241 @@
  57 +// SPDX-License-Identifier: GPL-2.0+
  58 +/*
  59 + * CPU frequency scaling support for Armada 37xx platform.
  60 + *
  61 + * Copyright (C) 2017 Marvell
  62 + *
  63 + * Gregory CLEMENT <gregory.clement@free-electrons.com>
  64 + */
  65 +
  66 +#include <linux/clk.h>
  67 +#include <linux/cpu.h>
  68 +#include <linux/cpufreq.h>
  69 +#include <linux/err.h>
  70 +#include <linux/interrupt.h>
  71 +#include <linux/io.h>
  72 +#include <linux/mfd/syscon.h>
  73 +#include <linux/module.h>
  74 +#include <linux/of_address.h>
  75 +#include <linux/of_device.h>
  76 +#include <linux/of_irq.h>
  77 +#include <linux/platform_device.h>
  78 +#include <linux/pm_opp.h>
  79 +#include <linux/regmap.h>
  80 +#include <linux/slab.h>
  81 +
  82 +/* Power management in North Bridge register set */
  83 +#define ARMADA_37XX_NB_L0L1    0x18
  84 +#define ARMADA_37XX_NB_L2L3    0x1C
  85 +#define  ARMADA_37XX_NB_TBG_DIV_OFF    13
  86 +#define  ARMADA_37XX_NB_TBG_DIV_MASK   0x7
  87 +#define  ARMADA_37XX_NB_CLK_SEL_OFF    11
  88 +#define  ARMADA_37XX_NB_CLK_SEL_MASK   0x1
  89 +#define  ARMADA_37XX_NB_CLK_SEL_TBG    0x1
  90 +#define  ARMADA_37XX_NB_TBG_SEL_OFF    9
  91 +#define  ARMADA_37XX_NB_TBG_SEL_MASK   0x3
  92 +#define  ARMADA_37XX_NB_VDD_SEL_OFF    6
  93 +#define  ARMADA_37XX_NB_VDD_SEL_MASK   0x3
  94 +#define  ARMADA_37XX_NB_CONFIG_SHIFT   16
  95 +#define ARMADA_37XX_NB_DYN_MOD 0x24
  96 +#define  ARMADA_37XX_NB_CLK_SEL_EN     BIT(26)
  97 +#define  ARMADA_37XX_NB_TBG_EN         BIT(28)
  98 +#define  ARMADA_37XX_NB_DIV_EN         BIT(29)
  99 +#define  ARMADA_37XX_NB_VDD_EN         BIT(30)
 100 +#define  ARMADA_37XX_NB_DFS_EN         BIT(31)
 101 +#define ARMADA_37XX_NB_CPU_LOAD 0x30
 102 +#define  ARMADA_37XX_NB_CPU_LOAD_MASK  0x3
 103 +#define  ARMADA_37XX_DVFS_LOAD_0       0
 104 +#define  ARMADA_37XX_DVFS_LOAD_1       1
 105 +#define  ARMADA_37XX_DVFS_LOAD_2       2
 106 +#define  ARMADA_37XX_DVFS_LOAD_3       3
 107 +
 108 +/*
 109 + * On Armada 37xx the Power management manages 4 level of CPU load,
 110 + * each level can be associated with a CPU clock source, a CPU
 111 + * divider, a VDD level, etc...
 112 + */
 113 +#define LOAD_LEVEL_NR  4
 114 +
 115 +struct armada_37xx_dvfs {
 116 +       u32 cpu_freq_max;
 117 +       u8 divider[LOAD_LEVEL_NR];
 118 +};
 119 +
 120 +static struct armada_37xx_dvfs armada_37xx_dvfs[] = {
 121 +       {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} },
 122 +       {.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
 123 +       {.cpu_freq_max = 800*1000*1000,  .divider = {1, 2, 3, 4} },
 124 +       {.cpu_freq_max = 600*1000*1000,  .divider = {2, 4, 5, 6} },
 125 +};
 126 +
 127 +static struct armada_37xx_dvfs *armada_37xx_cpu_freq_info_get(u32 freq)
 128 +{
 129 +       int i;
 130 +
 131 +       for (i = 0; i < ARRAY_SIZE(armada_37xx_dvfs); i++) {
 132 +               if (freq == armada_37xx_dvfs[i].cpu_freq_max)
 133 +                       return &armada_37xx_dvfs[i];
 134 +       }
 135 +
 136 +       pr_err("Unsupported CPU frequency %d MHz\n", freq/1000000);
 137 +       return NULL;
 138 +}
 139 +
 140 +/*
 141 + * Setup the four level managed by the hardware. Once the four level
 142 + * will be configured then the DVFS will be enabled.
 143 + */
 144 +static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
 145 +                                                struct clk *clk, u8 *divider)
 146 +{
 147 +       int load_lvl;
 148 +       struct clk *parent;
 149 +
 150 +       for (load_lvl = 0; load_lvl < LOAD_LEVEL_NR; load_lvl++) {
 151 +               unsigned int reg, mask, val, offset = 0;
 152 +
 153 +               if (load_lvl <= ARMADA_37XX_DVFS_LOAD_1)
 154 +                       reg = ARMADA_37XX_NB_L0L1;
 155 +               else
 156 +                       reg = ARMADA_37XX_NB_L2L3;
 157 +
 158 +               if (load_lvl == ARMADA_37XX_DVFS_LOAD_0 ||
 159 +                   load_lvl == ARMADA_37XX_DVFS_LOAD_2)
 160 +                       offset += ARMADA_37XX_NB_CONFIG_SHIFT;
 161 +
 162 +               /* Set cpu clock source, for all the level we use TBG */
 163 +               val = ARMADA_37XX_NB_CLK_SEL_TBG << ARMADA_37XX_NB_CLK_SEL_OFF;
 164 +               mask = (ARMADA_37XX_NB_CLK_SEL_MASK
 165 +                       << ARMADA_37XX_NB_CLK_SEL_OFF);
 166 +
 167 +               /*
 168 +                * Set cpu divider based on the pre-computed array in
 169 +                * order to have balanced step.
 170 +                */
 171 +               val |= divider[load_lvl] << ARMADA_37XX_NB_TBG_DIV_OFF;
 172 +               mask |= (ARMADA_37XX_NB_TBG_DIV_MASK
 173 +                       << ARMADA_37XX_NB_TBG_DIV_OFF);
 174 +
 175 +               /* Set VDD divider which is actually the load level. */
 176 +               val |= load_lvl << ARMADA_37XX_NB_VDD_SEL_OFF;
 177 +               mask |= (ARMADA_37XX_NB_VDD_SEL_MASK
 178 +                       << ARMADA_37XX_NB_VDD_SEL_OFF);
 179 +
 180 +               val <<= offset;
 181 +               mask <<= offset;
 182 +
 183 +               regmap_update_bits(base, reg, mask, val);
 184 +       }
 185 +
 186 +       /*
 187 +        * Set cpu clock source, for all the level we keep the same
 188 +        * clock source that the one already configured. For this one
 189 +        * we need to use the clock framework
 190 +        */
 191 +       parent = clk_get_parent(clk);
 192 +       clk_set_parent(clk, parent);
 193 +}
 194 +
 195 +static void __init armada37xx_cpufreq_disable_dvfs(struct regmap *base)
 196 +{
 197 +       unsigned int reg = ARMADA_37XX_NB_DYN_MOD,
 198 +               mask = ARMADA_37XX_NB_DFS_EN;
 199 +
 200 +       regmap_update_bits(base, reg, mask, 0);
 201 +}
 202 +
 203 +static void __init armada37xx_cpufreq_enable_dvfs(struct regmap *base)
 204 +{
 205 +       unsigned int val, reg = ARMADA_37XX_NB_CPU_LOAD,
 206 +               mask = ARMADA_37XX_NB_CPU_LOAD_MASK;
 207 +
 208 +       /* Start with the highest load (0) */
 209 +       val = ARMADA_37XX_DVFS_LOAD_0;
 210 +       regmap_update_bits(base, reg, mask, val);
 211 +
 212 +       /* Now enable DVFS for the CPUs */
 213 +       reg = ARMADA_37XX_NB_DYN_MOD;
 214 +       mask =  ARMADA_37XX_NB_CLK_SEL_EN | ARMADA_37XX_NB_TBG_EN |
 215 +               ARMADA_37XX_NB_DIV_EN | ARMADA_37XX_NB_VDD_EN |
 216 +               ARMADA_37XX_NB_DFS_EN;
 217 +
 218 +       regmap_update_bits(base, reg, mask, mask);
 219 +}
 220 +
 221 +static int __init armada37xx_cpufreq_driver_init(void)
 222 +{
 223 +       struct armada_37xx_dvfs *dvfs;
 224 +       struct platform_device *pdev;
 225 +       unsigned int cur_frequency;
 226 +       struct regmap *nb_pm_base;
 227 +       struct device *cpu_dev;
 228 +       int load_lvl, ret;
 229 +       struct clk *clk;
 230 +
 231 +       nb_pm_base =
 232 +               syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");
 233 +
 234 +       if (IS_ERR(nb_pm_base))
 235 +               return -ENODEV;
 236 +
 237 +       /* Before doing any configuration on the DVFS first, disable it */
 238 +       armada37xx_cpufreq_disable_dvfs(nb_pm_base);
 239 +
 240 +       /*
 241 +        * On CPU 0 register the operating points supported (which are
 242 +        * the nominal CPU frequency and full integer divisions of
 243 +        * it).
 244 +        */
 245 +       cpu_dev = get_cpu_device(0);
 246 +       if (!cpu_dev) {
 247 +               dev_err(cpu_dev, "Cannot get CPU\n");
 248 +               return -ENODEV;
 249 +       }
 250 +
 251 +       clk = clk_get(cpu_dev, 0);
 252 +       if (IS_ERR(clk)) {
 253 +               dev_err(cpu_dev, "Cannot get clock for CPU0\n");
 254 +               return PTR_ERR(clk);
 255 +       }
 256 +
 257 +       /* Get nominal (current) CPU frequency */
 258 +       cur_frequency = clk_get_rate(clk);
 259 +       if (!cur_frequency) {
 260 +               dev_err(cpu_dev, "Failed to get clock rate for CPU\n");
 261 +               return -EINVAL;
 262 +       }
 263 +
 264 +       dvfs = armada_37xx_cpu_freq_info_get(cur_frequency);
 265 +       if (!dvfs)
 266 +               return -EINVAL;
 267 +
 268 +       armada37xx_cpufreq_dvfs_setup(nb_pm_base, clk, dvfs->divider);
 269 +
 270 +       for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
 271 +            load_lvl++) {
 272 +               unsigned long freq = cur_frequency / dvfs->divider[load_lvl];
 273 +
 274 +               ret = dev_pm_opp_add(cpu_dev, freq, 0);
 275 +               if (ret) {
 276 +                       /* clean-up the already added opp before leaving */
 277 +                       while (load_lvl-- > ARMADA_37XX_DVFS_LOAD_0) {
 278 +                               freq = cur_frequency / dvfs->divider[load_lvl];
 279 +                               dev_pm_opp_remove(cpu_dev, freq);
 280 +                       }
 281 +                       return ret;
 282 +               }
 283 +       }
 284 +
 285 +       /* Now that everything is setup, enable the DVFS at hardware level */
 286 +       armada37xx_cpufreq_enable_dvfs(nb_pm_base);
 287 +
 288 +       pdev = platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
 289 +
 290 +       return PTR_ERR_OR_ZERO(pdev);
 291 +}
 292 +/* late_initcall, to guarantee the driver is loaded after A37xx clock driver */
 293 +late_initcall(armada37xx_cpufreq_driver_init);
 294 +
 295 +MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
 296 +MODULE_DESCRIPTION("Armada 37xx cpufreq driver");
 297 +MODULE_LICENSE("GPL");