target/linux/ramips/dts/ZBT-APE522II.dts

   1 /dts-v1/;
   2
   3 #include "mt7620a.dtsi"
   4
   5 #include <dt-bindings/input/input.h>
   6
   7 / {
   8         compatible = "zbtlink,zbt-ape522ii", "ralink,mt7620a-soc";
   9         model = "ZBT-APE522II";
  10
  11         chosen {
  12                 bootargs = "console=ttyS0,115200";
  13         };
  14
  15         gpio-leds {
  16                 compatible = "gpio-leds";
  17
  18                 sys1 {
  19                         label = "zbt-ape522ii:green:sys1";
  20                         gpios = <&gpio0 11 1>;
  21                 };
  22
  23                 sys2 {
  24                         label = "zbt-ape522ii:green:sys2";
  25                         gpios = <&gpio0 12 1>;
  26                 };
  27
  28                 sys3 {
  29                         label = "zbt-ape522ii:green:sys3";
  30                         gpios = <&gpio0 9 1>;
  31                 };
  32
  33                 sys4 {
  34                         label = "zbt-ape522ii:green:sys4";
  35                         gpios = <&gpio0 14 1>;
  36                 };
  37
  38                 wlan2g4 {
  39                         label = "zbt-ape522ii:green:wlan2g4";
  40                         gpios = <&gpio3 0 1>;
  41                 };
  42         };
  43
  44         gpio-keys-polled {
  45                 compatible = "gpio-keys-polled";
  46                 #address-cells = <1>;
  47                 #size-cells = <0>;
  48                 poll-interval = <20>;
  49
  50                 reset {
  51                         label = "reset";
  52                         gpios = <&gpio0 2 0>;
  53                         linux,code = <KEY_RESTART>;
  54                 };
  55         };
  56 };
  57
  58 &gpio0 {
  59         status = "okay";
  60 };
  61
  62 &gpio1 {
  63         status = "okay";
  64 };
  65
  66 &gpio2 {
  67         status = "okay";
  68 };
  69
  70 &gpio3 {
  71         status = "okay";
  72 };
  73
  74 &spi0 {
  75         status = "okay";
  76
  77         m25p80@0 {
  78                 #address-cells = <1>;
  79                 #size-cells = <1>;
  80                 compatible = "jedec,spi-nor";
  81                 reg = <0>;
  82                 spi-max-frequency = <10000000>;
  83
  84                 partition@0 {
  85                         label = "u-boot";
  86                         reg = <0x0 0x30000>;
  87                 };
  88
  89                 partition@30000 {
  90                         label = "u-boot-env";
  91                         reg = <0x30000 0x10000>;
  92                         read-only;
  93                 };
  94
  95                 factory: partition@40000 {
  96                         label = "factory";
  97                         reg = <0x40000 0x10000>;
  98                         read-only;
  99                 };
 100
 101                 partition@50000 {
 102                         label = "firmware";
 103                         reg = <0x50000 0xf80000>;
 104                 };
 105         };
 106 };
 107
 108 &ethernet {
 109         pinctrl-names = "default";
 110         pinctrl-0 = <&ephy_pins>;
 111         mtd-mac-address = <&factory 0x4>;
 112         mediatek,portmap = "wllll";
 113 };
 114
 115 &wmac {
 116         ralink,mtd-eeprom = <&factory 0>;
 117 };
 118
 119 &pcie {
 120         status = "okay";
 121
 122         pcie-bridge {
 123                 mt76@0,0 {
 124                         reg = <0x0000 0 0 0 0>;
 125                         device_type = "pci";
 126                         mediatek,mtd-eeprom = <&factory 0x8000>;
 127                         ieee80211-freq-limit = <5000000 6000000>;
 128                 };
 129         };
 130 };
 131
 132 &pinctrl {
 133         state_default: pinctrl0 {
 134                 gpio {
 135                         ralink,group = "wled", "i2c", "uartf", "wdt";
 136                         ralink,function = "gpio";
 137                 };
 138
 139                 pa {
 140                         ralink,group = "pa";
 141                         ralink,function = "pa";
 142                 };
 143         };
 144 };