ramips: improve support for STORYLiNK SAP-G3200U3
[openwrt/openwrt.git] / target / linux / ramips / dts / mt7620a_edimax_br-6478ac-v2.dts
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2016 Rohan Murch <rohan.murch@gmail.com>
4 * Copyright (C) 2016 Hans Ulli Kroll <ulli.kroll@googlemail.com>
5 * Copyright (C) 2017 James McKenzie <openwrt@madingley.org>
6 */
7
8 #include "mt7620a.dtsi"
9
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/mtd/partitions/uimage.h>
14
15 / {
16 compatible = "edimax,br-6478ac-v2", "ralink,mt7620a-soc";
17 model = "Edimax BR-6478AC v2";
18
19 aliases {
20 led-boot = &led_power;
21 led-failsafe = &led_power;
22 led-running = &led_power;
23 led-upgrade = &led_power;
24 };
25
26 keys {
27 compatible = "gpio-keys";
28
29 reset_wps {
30 label = "reset_wps";
31 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
32 linux,code = <KEY_RESTART>;
33 };
34 };
35
36 leds {
37 compatible = "gpio-leds";
38
39 led_power: power {
40 function = LED_FUNCTION_POWER;
41 color = <LED_COLOR_ID_WHITE>;
42 gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
43 };
44
45 internet {
46 label = "blue:internet";
47 gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
48 };
49
50 wlan {
51 function = LED_FUNCTION_WLAN;
52 color = <LED_COLOR_ID_BLUE>;
53 gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
54 };
55
56 usb {
57 function = LED_FUNCTION_USB;
58 color = <LED_COLOR_ID_BLUE>;
59 gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
60 trigger-sources = <&ohci_port1>, <&ehci_port1>;
61 linux,default-trigger = "usbport";
62 };
63 };
64
65 gpio_export {
66 compatible = "gpio-export";
67 #size-cells = <0>;
68 usb-power {
69 gpio-export,name="usb-power";
70 gpio-export,output=<1>;
71 gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
72 };
73 };
74 };
75
76 &gpio2 {
77 status = "okay";
78 };
79
80 &spi0 {
81 status = "okay";
82
83 flash@0 {
84 compatible = "jedec,spi-nor";
85 reg = <0>;
86 spi-max-frequency = <10000000>;
87
88 partitions {
89 compatible = "fixed-partitions";
90 #address-cells = <1>;
91 #size-cells = <1>;
92
93 partition@0 {
94 label = "u-boot";
95 reg = <0x0 0x30000>;
96 read-only;
97 };
98
99 partition@30000 {
100 label = "u-boot-env";
101 reg = <0x30000 0x10000>;
102 read-only;
103 };
104
105 partition@40000 {
106 label = "factory";
107 reg = <0x40000 0x10000>;
108 read-only;
109
110 nvmem-layout {
111 compatible = "fixed-layout";
112 #address-cells = <1>;
113 #size-cells = <1>;
114
115 eeprom_factory_0: eeprom@0 {
116 reg = <0x0 0x200>;
117 };
118
119 eeprom_factory_8000: eeprom@8000 {
120 reg = <0x8000 0x200>;
121 };
122
123 macaddr_factory_4: macaddr@4 {
124 reg = <0x4 0x6>;
125 };
126 };
127 };
128
129 partition@50000 {
130 label = "cimage";
131 reg = <0x50000 0x20000>;
132 read-only;
133 };
134
135 partition@70000 {
136 compatible = "openwrt,uimage", "denx,uimage";
137 openwrt,offset = <FW_EDIMAX_OFFSET>;
138 openwrt,partition-magic = <FW_MAGIC_EDIMAX>;
139 label = "firmware";
140 reg = <0x00070000 0x00790000>;
141 };
142 };
143 };
144 };
145
146 &state_default {
147 gpio {
148 groups = "i2c", "uartf", "nd_sd";
149 function = "gpio";
150 };
151 };
152
153 &ethernet {
154 pinctrl-names = "default";
155 pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
156
157 nvmem-cells = <&macaddr_factory_4>;
158 nvmem-cell-names = "mac-address";
159
160 mediatek,portmap = "wllll";
161
162 port@5 {
163 status = "okay";
164 mediatek,fixed-link = <1000 1 1 1>;
165 phy-mode = "rgmii";
166 };
167
168 mdio-bus {
169 status = "okay";
170
171 phy0: ethernet-phy@0 {
172 reg = <0>;
173 phy-mode = "rgmii";
174 };
175
176 phy1: ethernet-phy@1 {
177 reg = <1>;
178 phy-mode = "rgmii";
179 };
180
181 phy2: ethernet-phy@2 {
182 reg = <2>;
183 phy-mode = "rgmii";
184 };
185
186 phy3: ethernet-phy@3 {
187 reg = <3>;
188 phy-mode = "rgmii";
189 };
190
191 phy4: ethernet-phy@4 {
192 reg = <4>;
193 phy-mode = "rgmii";
194 };
195
196 phy1f: ethernet-phy@1f {
197 reg = <0x1f>;
198 phy-mode = "rgmii";
199 };
200 };
201 };
202
203 &gsw {
204 mediatek,ephy-base = /bits/ 8 <12>;
205 };
206
207 &wmac {
208 nvmem-cells = <&eeprom_factory_0>;
209 nvmem-cell-names = "eeprom";
210 };
211
212 &pcie {
213 status = "okay";
214 };
215
216 &pcie0 {
217 wifi@0,0 {
218 reg = <0x0000 0 0 0 0>;
219 nvmem-cells = <&eeprom_factory_8000>;
220 nvmem-cell-names = "eeprom";
221 ieee80211-freq-limit = <5000000 6000000>;
222 };
223 };
224
225 &ehci {
226 status = "okay";
227 };
228
229 &ohci {
230 status = "okay";
231 };