ramips: Add hex prefix (0x) to dtsi reg properties where needed.
[openwrt/openwrt.git] / target / linux / ramips / dts / mt7628an.dtsi
1 / {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "ralink,mtk7628an-soc";
5
6 cpus {
7 cpu@0 {
8 compatible = "mips,mips24KEc";
9 };
10 };
11
12 chosen {
13 bootargs = "console=ttyS0,57600";
14 };
15
16 aliases {
17 serial0 = &uartlite;
18 };
19
20 cpuintc: cpuintc@0 {
21 #address-cells = <0>;
22 #interrupt-cells = <1>;
23 interrupt-controller;
24 compatible = "mti,cpu-interrupt-controller";
25 };
26
27 palmbus@10000000 {
28 compatible = "palmbus";
29 reg = <0x10000000 0x200000>;
30 ranges = <0x0 0x10000000 0x1FFFFF>;
31
32 #address-cells = <1>;
33 #size-cells = <1>;
34
35 sysc@0 {
36 compatible = "ralink,mt7620a-sysc";
37 reg = <0x0 0x100>;
38 };
39
40 watchdog@120 {
41 compatible = "ralink,mt7628an-wdt", "mtk,mt7621-wdt";
42 reg = <0x120 0x10>;
43
44 resets = <&rstctrl 8>;
45 reset-names = "wdt";
46
47 interrupt-parent = <&intc>;
48 interrupts = <24>;
49 };
50
51 intc: intc@200 {
52 compatible = "ralink,mt7628an-intc", "ralink,rt2880-intc";
53 reg = <0x200 0x100>;
54
55 resets = <&rstctrl 9>;
56 reset-names = "intc";
57
58 interrupt-controller;
59 #interrupt-cells = <1>;
60
61 interrupt-parent = <&cpuintc>;
62 interrupts = <2>;
63
64 ralink,intc-registers = <0x9c 0xa0
65 0x6c 0xa4
66 0x80 0x78>;
67 };
68
69 memc@300 {
70 compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
71 reg = <0x300 0x100>;
72
73 resets = <&rstctrl 20>;
74 reset-names = "mc";
75
76 interrupt-parent = <&intc>;
77 interrupts = <3>;
78 };
79
80 gpio@600 {
81 #address-cells = <1>;
82 #size-cells = <0>;
83
84 compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
85 reg = <0x600 0x100>;
86
87 interrupt-parent = <&intc>;
88 interrupts = <6>;
89
90 gpio0: bank@0 {
91 reg = <0>;
92 compatible = "mtk,mt7621-gpio-bank";
93 gpio-controller;
94 #gpio-cells = <2>;
95 };
96
97 gpio1: bank@1 {
98 reg = <1>;
99 compatible = "mtk,mt7621-gpio-bank";
100 gpio-controller;
101 #gpio-cells = <2>;
102 };
103
104 gpio2: bank@2 {
105 reg = <2>;
106 compatible = "mtk,mt7621-gpio-bank";
107 gpio-controller;
108 #gpio-cells = <2>;
109 };
110 };
111
112 i2c@900 {
113 compatible = "mediatek,mt7628-i2c";
114 reg = <0x900 0x100>;
115
116 resets = <&rstctrl 16>;
117 reset-names = "i2c";
118
119 #address-cells = <1>;
120 #size-cells = <0>;
121
122 status = "disabled";
123
124 pinctrl-names = "default";
125 pinctrl-0 = <&i2c_pins>;
126 };
127
128 i2s@a00 {
129 compatible = "ralink,mt7620a-i2s";
130 reg = <0xa00 0x100>;
131
132 resets = <&rstctrl 17>;
133 reset-names = "i2s";
134
135 interrupt-parent = <&intc>;
136 interrupts = <10>;
137
138 dmas = <&gdma 2>,
139 <&gdma 3>;
140 dma-names = "tx", "rx";
141
142 status = "disabled";
143 };
144
145 spi@b00 {
146 compatible = "ralink,mt7621-spi";
147 reg = <0xb00 0x100>;
148
149 resets = <&rstctrl 18>;
150 reset-names = "spi";
151
152 #address-cells = <1>;
153 #size-cells = <0>;
154
155 pinctrl-names = "default";
156 pinctrl-0 = <&spi_pins>;
157
158 status = "disabled";
159 };
160
161 uartlite: uartlite@c00 {
162 compatible = "ns16550a";
163 reg = <0xc00 0x100>;
164
165 reg-shift = <2>;
166 reg-io-width = <4>;
167 no-loopback-test;
168
169 resets = <&rstctrl 12>;
170 reset-names = "uartl";
171
172 interrupt-parent = <&intc>;
173 interrupts = <20>;
174
175 pinctrl-names = "default";
176 pinctrl-0 = <&uart0_pins>;
177 };
178
179 uart1@d00 {
180 compatible = "ns16550a";
181 reg = <0xd00 0x100>;
182
183 reg-shift = <2>;
184 reg-io-width = <4>;
185 no-loopback-test;
186
187 resets = <&rstctrl 19>;
188 reset-names = "uart1";
189
190 interrupt-parent = <&intc>;
191 interrupts = <21>;
192
193 pinctrl-names = "default";
194 pinctrl-0 = <&uart1_pins>;
195
196 status = "disabled";
197 };
198
199 uart2: uart2@e00 {
200 compatible = "ns16550a";
201 reg = <0xe00 0x100>;
202
203 reg-shift = <2>;
204 reg-io-width = <4>;
205 no-loopback-test;
206
207 resets = <&rstctrl 20>;
208 reset-names = "uart2";
209
210 interrupt-parent = <&intc>;
211 interrupts = <22>;
212
213 pinctrl-names = "default";
214 pinctrl-0 = <&uart2_pins>;
215
216 status = "disabled";
217 };
218
219 pwm@5000 {
220 compatible = "mediatek,mt7628-pwm";
221 reg = <0x5000 0x1000>;
222
223 resets = <&rstctrl 31>;
224 reset-names = "pwm";
225
226 pinctrl-names = "default";
227 pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>;
228
229 status = "disabled";
230 };
231
232 pcm@2000 {
233 compatible = "ralink,mt7620a-pcm";
234 reg = <0x2000 0x800>;
235
236 resets = <&rstctrl 11>;
237 reset-names = "pcm";
238
239 interrupt-parent = <&intc>;
240 interrupts = <4>;
241
242 status = "disabled";
243 };
244
245 gdma: gdma@2800 {
246 compatible = "ralink,mt7620a-gdma", "ralink,rt2880-gdma";
247 reg = <0x2800 0x800>;
248
249 resets = <&rstctrl 14>;
250 reset-names = "dma";
251
252 interrupt-parent = <&intc>;
253 interrupts = <7>;
254
255 #dma-cells = <1>;
256 #dma-channels = <16>;
257 #dma-requests = <16>;
258
259 status = "disabled";
260 };
261 };
262
263 pinctrl {
264 compatible = "ralink,rt2880-pinmux";
265 pinctrl-names = "default";
266 pinctrl-0 = <&state_default>;
267
268 state_default: pinctrl0 {
269 };
270
271 spi_pins: spi {
272 spi {
273 ralink,group = "spi";
274 ralink,function = "spi";
275 };
276 };
277
278 spi_cs1_pins: spi_cs1 {
279 spi_cs1 {
280 ralink,group = "spi cs1";
281 ralink,function = "spi cs1";
282 };
283 };
284
285 i2c_pins: i2c {
286 i2c {
287 ralink,group = "i2c";
288 ralink,function = "i2c";
289 };
290 };
291
292 uart0_pins: uartlite {
293 uartlite {
294 ralink,group = "uart0";
295 ralink,function = "uart0";
296 };
297 };
298
299 uart1_pins: uart1 {
300 uart1 {
301 ralink,group = "uart1";
302 ralink,function = "uart1";
303 };
304 };
305
306 uart2_pins: uart2 {
307 uart2 {
308 ralink,group = "uart2";
309 ralink,function = "uart2";
310 };
311 };
312
313 sdxc_pins: sdxc {
314 sdxc {
315 ralink,group = "sdmode";
316 ralink,function = "sdxc";
317 };
318 };
319
320 pwm0_pins: pwm0 {
321 pwm0 {
322 ralink,group = "pwm0";
323 ralink,function = "pwm0";
324 };
325 };
326
327 pwm1_pins: pwm1 {
328 pwm1 {
329 ralink,group = "pwm1";
330 ralink,function = "pwm1";
331 };
332 };
333
334 pcm_i2s_pins: i2s {
335 i2s {
336 ralink,group = "i2s";
337 ralink,function = "pcm";
338 };
339 };
340 };
341
342 rstctrl: rstctrl {
343 compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
344 #reset-cells = <1>;
345 };
346
347 usbphy: usbphy@10120000 {
348 compatible = "ralink,mt7628an-usbphy", "mediatek,mt7620-usbphy";
349 reg = <0x10120000 0x4000>;
350 #phy-cells = <1>;
351
352 resets = <&rstctrl 22 &rstctrl 25>;
353 reset-names = "host", "device";
354 };
355
356 sdhci@10130000 {
357 compatible = "ralink,mt7620-sdhci";
358 reg = <0x10130000 0x4000>;
359
360 interrupt-parent = <&intc>;
361 interrupts = <14>;
362
363 pinctrl-names = "default";
364 pinctrl-0 = <&sdxc_pins>;
365
366 status = "disabled";
367 };
368
369 ehci@101c0000 {
370 compatible = "generic-ehci";
371 reg = <0x101c0000 0x1000>;
372
373 phys = <&usbphy 1>;
374 phy-names = "usb";
375
376 interrupt-parent = <&intc>;
377 interrupts = <18>;
378 };
379
380 ohci@101c1000 {
381 compatible = "generic-ohci";
382 reg = <0x101c1000 0x1000>;
383
384 phys = <&usbphy 1>;
385 phy-names = "usb";
386
387 interrupt-parent = <&intc>;
388 interrupts = <18>;
389 };
390
391 ethernet@10100000 {
392 compatible = "ralink,rt5350-eth";
393 reg = <0x10100000 0x10000>;
394
395 interrupt-parent = <&cpuintc>;
396 interrupts = <5>;
397
398 resets = <&rstctrl 21 &rstctrl 23>;
399 reset-names = "fe", "esw";
400
401 mediatek,switch = <&esw>;
402 };
403
404 esw: esw@10110000 {
405 compatible = "ralink,rt3050-esw";
406 reg = <0x10110000 0x8000>;
407
408 resets = <&rstctrl 23>;
409 reset-names = "esw";
410
411 interrupt-parent = <&intc>;
412 interrupts = <17>;
413 };
414
415 pcie@10140000 {
416 compatible = "mediatek,mt7620-pci";
417 reg = <0x10140000 0x100
418 0x10142000 0x100>;
419
420 #address-cells = <3>;
421 #size-cells = <2>;
422
423 resets = <&rstctrl 26>;
424 reset-names = "pcie0";
425
426 interrupt-parent = <&cpuintc>;
427 interrupts = <4>;
428
429 status = "disabled";
430
431 device_type = "pci";
432
433 bus-range = <0 255>;
434 ranges = <
435 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
436 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
437 >;
438
439 pcie-bridge {
440 reg = <0x0000 0 0 0 0>;
441
442 #address-cells = <3>;
443 #size-cells = <2>;
444
445 device_type = "pci";
446 };
447 };
448
449 wmac: wmac@10300000 {
450 compatible = "mediatek,mt7628-wmac";
451 reg = <0x10300000 0x100000>;
452
453 interrupt-parent = <&cpuintc>;
454 interrupts = <6>;
455
456 status = "disabled";
457
458 mediatek,mtd-eeprom = <&factory 0x0000>;
459 mediatek,5ghz = <0>;
460 };
461 };