// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-#include <dt-bindings/clock/ath79-clk.h>
+
#include "ath79.dtsi"
/ {
};
};
+ extosc: ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "ref";
+ clock-frequency = <40000000>;
+ };
+
ahb: ahb {
apb {
ddr_ctrl: memory-controller@18000000 {
reg-io-width = <4>;
reg-shift = <2>;
no-loopback-test;
-
- status = "disabled";
};
gpio: gpio@18040000 {
compatible = "qca,ar7240-gpio",
"qca,ar7100-gpio";
- reg = <0x18040000 0x30>;
+ reg = <0x18040000 0x28>;
interrupts = <2>;
ngpios = <18>;
#interrupt-cells = <2>;
};
+ pinmux: pinmux@18040028 {
+ compatible = "pinctrl-single";
+
+ reg = <0x18040028 0x8>;
+
+ pinctrl-single,bit-per-mux;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x1>;
+ #pinctrl-cells = <2>;
+
+ jtag_disable_pins: pinmux_jtag_disable_pins {
+ pinctrl-single,bits = <0x0 0x1 0x1>;
+ };
+
+ switch_led_disable_pins: pinmux_switch_led_disable_pins {
+ pinctrl-single,bits = <0x0 0x0 0xf8>;
+ };
+
+ clks_disable_pins: pinmux_clks_disable_pins {
+ pinctrl-single,bits = <0x0 0x0 0x81f00>;
+ };
+ };
+
pll: pll-controller@18050000 {
- compatible = "qca,ar7240-pll",
- "qca,ar7240-pll";
- reg = <0x18050000 0x20>;
+ compatible = "qca,ar7240-pll", "syscon";
+ reg = <0x18050000 0x3c>;
+ clocks = <&extosc>;
clock-names = "ref";
- /* The board must provides the ref clock */
#clock-cells = <1>;
clock-output-names = "cpu", "ddr", "ahb";
#reset-cells = <1>;
};
- pcie: pcie-controller@180c0000 {
+ pcie: pcie@180c0000 {
compatible = "qcom,ar7240-pci";
#address-cells = <3>;
#size-cells = <2>;
interrupt-parent = <&cpuintc>;
interrupts = <2>;
+ resets = <&rst 6>, <&rst 7>;
+ reset-names = "hc", "phy";
+
+ device_type = "pci";
+
interrupt-controller;
#interrupt-cells = <1>;