+/* interrupt controller */
+#define IRQ_STATUS_REG 0x00 /* Read */
+#define IRQ_ENABLE_REG 0x08 /* Read/Write */
+#define IRQ_DISABLE_REG 0x0C /* Write */
+
+#define IRQ_MASK 0xffff
+
+static inline void intc_write_reg(u32 val, unsigned int reg)
+{
+ void __iomem *base = (void __iomem *)KSEG1ADDR(ADM8668_INTC_BASE);
+
+ __raw_writel(val, base + reg);
+}
+
+static inline u32 intc_read_reg(unsigned int reg)
+{
+ void __iomem *base = (void __iomem *)KSEG1ADDR(ADM8668_INTC_BASE);
+
+ return __raw_readl(base + reg);
+}
+