ipq40xx: add target
authorJohn Crispin <john@phrozen.org>
Wed, 21 Feb 2018 19:40:50 +0000 (20:40 +0100)
committerMathias Kresin <dev@kresin.me>
Wed, 14 Mar 2018 18:04:50 +0000 (19:04 +0100)
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: Mathias Kresin <dev@kresin.me>
Signed-off-by: John Crispin <john@phrozen.org>
58 files changed:
package/boot/uboot-envtools/Makefile
package/boot/uboot-envtools/files/ipq [deleted file]
package/boot/uboot-envtools/files/ipq40xx [new file with mode: 0644]
package/boot/uboot-envtools/files/ipq806x [new file with mode: 0644]
package/boot/uboot-fritz4040/Makefile
package/firmware/ipq-wifi/Makefile
package/kernel/mac80211/Makefile
target/linux/ipq40xx/Makefile [new file with mode: 0644]
target/linux/ipq40xx/base-files/etc/board.d/01_leds [new file with mode: 0755]
target/linux/ipq40xx/base-files/etc/board.d/02_network [new file with mode: 0755]
target/linux/ipq40xx/base-files/etc/diag.sh [new file with mode: 0755]
target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata [new file with mode: 0644]
target/linux/ipq40xx/base-files/etc/inittab [new file with mode: 0644]
target/linux/ipq40xx/base-files/lib/upgrade/openmesh.sh [new file with mode: 0644]
target/linux/ipq40xx/base-files/lib/upgrade/platform.sh [new file with mode: 0644]
target/linux/ipq40xx/config-4.14 [new file with mode: 0644]
target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4019-a42.dts [new file with mode: 0644]
target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts [new file with mode: 0644]
target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi [new file with mode: 0644]
target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4019-bus.dtsi [new file with mode: 0644]
target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4019-fritz4040.dts [new file with mode: 0644]
target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4019-gl-b1300.dts [new file with mode: 0644]
target/linux/ipq40xx/image/Makefile [new file with mode: 0644]
target/linux/ipq40xx/modules.mk [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/017-qcom-ipq4019-add-cpu-operating-points-for-cpufreq-su.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/030-mtd-nand-Use-standard-large-page-OOB-layout-when-usi.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/031-mtd-nand-use-usual-return-values-for-the-erase-hook.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/040-dmaengine-qcom-bam-Process-multiple-pending-descript.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/050-0002-mtd-nand-qcom-add-command-elements-in-BAM-transactio.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/050-0003-mtd-nand-qcom-support-for-command-descriptor-formati.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/050-0004-mtd-nand-provide-several-helpers-to-do-common-NAND-o.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/050-0005-mtd-nand-force-drivers-to-explicitly-send-READ-PROG-.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/050-0006-mtd-nand-qcom-Add-a-NULL-check-for-devm_kasprintf.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/059-ARM-cpuidle-Add-cpuidle-support-for-QCOM-cpus.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/069-arm-boot-add-dts-files.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/070-qcom-spm-fix-probe-order.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/101-ARM-dts-ipq4019-Add-a-few-peripheral-nodes.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/102-ARM-dts-ipq4019-fix-PCI-range.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/104-mtd-nand-add-Winbond-manufacturer-and-chip.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/105-mtd-nor-add-mx25l25635f.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/305-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/306-qcom-ipq4019-add-USB-nodes-to-ipq4019-SoC-device-tre.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/307-ARM-qcom-Add-IPQ4019-SoC-support.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/310-msm-adhoc-bus-support.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/605-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/700-net-add-qualcomm-mdio-and-phy.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/701-dts-ipq4019-add-mdio-node.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/702-dts-ipq4019-add-PHY-switch-nodes.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/710-net-add-qualcomm-essedma-ethernet-driver.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/711-dts-ipq4019-add-ethernet-essedma-node.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/820-qcom-ipq4019-Add-IPQ4019-USB-HS-SS-PHY-drivers.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/830-usb-dwc3-register-qca-ipq4019-dwc3-in-dwc3-of-simple.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/850-soc-add-qualcomm-syscon.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/864-03-dts-ipq4019-ap-dk01-add-tcsr-config-to-dtsi.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/864-05-dts-ipq4019-ap-dk01-remove-spi-chip-node-from-dtsi.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/864-07-dts-ipq4019-ap-dk01.1-c1-add-spi-and-ram-nodes.patch [new file with mode: 0644]
target/linux/ipq40xx/patches-4.14/864-08-dts-ipq4019-ap-dk01.1-c1-add-compatible-string.patch [new file with mode: 0644]
target/linux/ipq40xx/profiles/00-default.mk [new file with mode: 0644]

index 57a2ec5..442cf3f 100644 (file)
@@ -88,9 +88,13 @@ ifneq ($(CONFIG_TARGET_imx6),)
        $(INSTALL_DIR) $(1)/etc/uci-defaults
        $(INSTALL_DATA) ./files/imx6 $(1)/etc/uci-defaults/30_uboot-envtools
 endif
+ifneq ($(CONFIG_TARGET_ipq40xx),)
+       $(INSTALL_DIR) $(1)/etc/uci-defaults
+       $(INSTALL_DATA) ./files/ipq40xx $(1)/etc/uci-defaults/30_uboot-envtools
+endif
 ifneq ($(CONFIG_TARGET_ipq806x),)
        $(INSTALL_DIR) $(1)/etc/uci-defaults
-       $(INSTALL_DATA) ./files/ipq $(1)/etc/uci-defaults/30_uboot-envtools
+       $(INSTALL_DATA) ./files/ipq806x $(1)/etc/uci-defaults/30_uboot-envtools
 endif
 ifneq ($(CONFIG_TARGET_kirkwood),)
        $(INSTALL_DIR) $(1)/etc/uci-defaults
diff --git a/package/boot/uboot-envtools/files/ipq b/package/boot/uboot-envtools/files/ipq
deleted file mode 100644 (file)
index 441ba48..0000000
+++ /dev/null
@@ -1,52 +0,0 @@
-#!/bin/sh
-#
-# Copyright (C) 2016 LEDE
-#
-
-[ -e /etc/config/ubootenv ] && exit 0
-
-touch /etc/config/ubootenv
-
-. /lib/uboot-envtools.sh
-. /lib/functions.sh
-
-board=$(board_name)
-
-ubootenv_mtdinfo () {
-       UBOOTENV_PART=$(cat /proc/mtd | grep APPSBLENV)
-       mtd_dev=$(echo $UBOOTENV_PART | awk '{print $1}' | sed 's/:$//')
-       mtd_size=$(echo $UBOOTENV_PART | awk '{print "0x"$2}')
-       mtd_erase=$(echo $UBOOTENV_PART | awk '{print "0x"$3}')
-       nor_flash=$(find /sys/bus/spi/devices/*/mtd -name ${mtd_dev})
-
-       if [ -n "$nor_flash" ]; then
-               ubootenv_size=$mtd_size
-       else
-               # size is fixed to 0x40000 in u-boot
-               ubootenv_size=0x40000
-       fi
-
-       sectors=$(( $ubootenv_size / $mtd_erase ))
-       echo /dev/$mtd_dev 0x0 $ubootenv_size $mtd_erase $sectors
-}
-
-case "$board" in
-linksys,ea8500)
-       ubootenv_add_uci_config "/dev/mtd10" "0x0" "0x20000" "0x20000"
-       ;;
-openmesh,a42)
-       ubootenv_add_uci_config "/dev/mtd5" "0x0" "0x10000" "0x10000"
-       ;;
-qcom,ipq8064-ap148 |\
-qcom,ipq8064-db149)
-       ubootenv_add_uci_config $(ubootenv_mtdinfo)
-       ;;
-zyxel,nbg6817)
-       ubootenv_add_uci_config "/dev/mtdblock9" "0x0" "0x10000" "0x10000"
-       ;;
-esac
-
-config_load ubootenv
-config_foreach ubootenv_add_app_config ubootenv
-
-exit 0
diff --git a/package/boot/uboot-envtools/files/ipq40xx b/package/boot/uboot-envtools/files/ipq40xx
new file mode 100644 (file)
index 0000000..4eae506
--- /dev/null
@@ -0,0 +1,42 @@
+#!/bin/sh
+#
+# Copyright (C) 2016 LEDE
+#
+
+[ -e /etc/config/ubootenv ] && exit 0
+
+touch /etc/config/ubootenv
+
+. /lib/uboot-envtools.sh
+. /lib/functions.sh
+
+board=$(board_name)
+
+ubootenv_mtdinfo () {
+       UBOOTENV_PART=$(cat /proc/mtd | grep APPSBLENV)
+       mtd_dev=$(echo $UBOOTENV_PART | awk '{print $1}' | sed 's/:$//')
+       mtd_size=$(echo $UBOOTENV_PART | awk '{print "0x"$2}')
+       mtd_erase=$(echo $UBOOTENV_PART | awk '{print "0x"$3}')
+       nor_flash=$(find /sys/bus/spi/devices/*/mtd -name ${mtd_dev})
+
+       if [ -n "$nor_flash" ]; then
+               ubootenv_size=$mtd_size
+       else
+               # size is fixed to 0x40000 in u-boot
+               ubootenv_size=0x40000
+       fi
+
+       sectors=$(( $ubootenv_size / $mtd_erase ))
+       echo /dev/$mtd_dev 0x0 $ubootenv_size $mtd_erase $sectors
+}
+
+case "$board" in
+openmesh,a42)
+       ubootenv_add_uci_config "/dev/mtd5" "0x0" "0x10000" "0x10000"
+       ;;
+esac
+
+config_load ubootenv
+config_foreach ubootenv_add_app_config ubootenv
+
+exit 0
diff --git a/package/boot/uboot-envtools/files/ipq806x b/package/boot/uboot-envtools/files/ipq806x
new file mode 100644 (file)
index 0000000..4618aac
--- /dev/null
@@ -0,0 +1,49 @@
+#!/bin/sh
+#
+# Copyright (C) 2016 LEDE
+#
+
+[ -e /etc/config/ubootenv ] && exit 0
+
+touch /etc/config/ubootenv
+
+. /lib/uboot-envtools.sh
+. /lib/functions.sh
+
+board=$(board_name)
+
+ubootenv_mtdinfo () {
+       UBOOTENV_PART=$(cat /proc/mtd | grep APPSBLENV)
+       mtd_dev=$(echo $UBOOTENV_PART | awk '{print $1}' | sed 's/:$//')
+       mtd_size=$(echo $UBOOTENV_PART | awk '{print "0x"$2}')
+       mtd_erase=$(echo $UBOOTENV_PART | awk '{print "0x"$3}')
+       nor_flash=$(find /sys/bus/spi/devices/*/mtd -name ${mtd_dev})
+
+       if [ -n "$nor_flash" ]; then
+               ubootenv_size=$mtd_size
+       else
+               # size is fixed to 0x40000 in u-boot
+               ubootenv_size=0x40000
+       fi
+
+       sectors=$(( $ubootenv_size / $mtd_erase ))
+       echo /dev/$mtd_dev 0x0 $ubootenv_size $mtd_erase $sectors
+}
+
+case "$board" in
+linksys,ea8500)
+       ubootenv_add_uci_config "/dev/mtd10" "0x0" "0x20000" "0x20000"
+       ;;
+qcom,ipq8064-ap148 |\
+qcom,ipq8064-db149)
+       ubootenv_add_uci_config $(ubootenv_mtdinfo)
+       ;;
+zyxel,nbg6817)
+       ubootenv_add_uci_config "/dev/mtdblock9" "0x0" "0x10000" "0x10000"
+       ;;
+esac
+
+config_load ubootenv
+config_foreach ubootenv_add_app_config ubootenv
+
+exit 0
index 65d70e0..77d6fdc 100644 (file)
@@ -20,7 +20,7 @@ include $(INCLUDE_DIR)/u-boot.mk
 include $(INCLUDE_DIR)/package.mk
 
 define U-Boot/Default
-  BUILD_TARGET:=ipq806x
+  BUILD_TARGET:=ipq40xx
   UBOOT_IMAGE:=uboot-fritz4040.bin
 endef
 
index cc29d32..3f929bc 100644 (file)
@@ -20,7 +20,7 @@ define Package/ipq-wifi-default
   SUBMENU:=ath10k IPQ4019 Boarddata
   SECTION:=firmware
   CATEGORY:=Firmware
-  DEPENDS:=@TARGET_ipq806x +ath10k-firmware-qca4019
+  DEPENDS:=@TARGET_ipq40xx +ath10k-firmware-qca4019
   TITLE:=Custom Board
 endef
 
index 6ea07fd..22ed841 100644 (file)
@@ -1584,7 +1584,7 @@ config-$(CONFIG_PACKAGE_ATH_SPECTRAL) += ATH9K_COMMON_SPECTRAL ATH10K_SPECTRAL
 config-$(call config_package,ath9k) += ATH9K
 config-$(call config_package,ath9k-common) += ATH9K_COMMON
 config-$(CONFIG_TARGET_ar71xx) += ATH9K_AHB
-config-$(CONFIG_TARGET_ipq806x) += ATH10K_AHB
+config-$(CONFIG_TARGET_ipq40xx) += ATH10K_AHB
 config-$(CONFIG_PCI) += ATH9K_PCI
 config-$(CONFIG_ATH_USER_REGD) += ATH_USER_REGD
 config-$(CONFIG_ATH9K_SUPPORT_PCOEM) += ATH9K_PCOEM
diff --git a/target/linux/ipq40xx/Makefile b/target/linux/ipq40xx/Makefile
new file mode 100644 (file)
index 0000000..390426c
--- /dev/null
@@ -0,0 +1,21 @@
+include $(TOPDIR)/rules.mk
+
+ARCH:=arm
+BOARD:=ipq40xx
+BOARDNAME:=Qualcomm Atheros IPQ40XX
+FEATURES:=squashfs fpu
+CPU_TYPE:=cortex-a7
+CPU_SUBTYPE:=neon-vfpv4
+MAINTAINER:=John Crispin <john@phrozen.org>
+
+KERNEL_PATCHVER:=4.14
+
+KERNELNAME:=zImage Image dtbs
+
+include $(INCLUDE_DIR)/target.mk
+DEFAULT_PACKAGES += \
+       kmod-leds-gpio kmod-gpio-button-hotplug swconfig \
+       kmod-ath10k wpad-mini \
+       kmod-usb3 kmod-usb-dwc3-of-simple kmod-usb-phy-qcom-dwc3 \
+
+$(eval $(call BuildTarget))
diff --git a/target/linux/ipq40xx/base-files/etc/board.d/01_leds b/target/linux/ipq40xx/base-files/etc/board.d/01_leds
new file mode 100755 (executable)
index 0000000..31c6e32
--- /dev/null
@@ -0,0 +1,28 @@
+#!/bin/sh
+#
+# Copyright (C) 2015 OpenWrt.org
+#
+
+. /lib/functions/uci-defaults.sh
+
+board_config_update
+
+board=$(board_name)
+boardname="${board##*,}"
+
+case "$board" in
+avm,fritzbox-4040)
+       ucidef_set_led_wlan "wlan" "WLAN" "fritz4040:green:wlan" "phy0tpt" "phy1tpt"
+       ucidef_set_led_netdev "wan" "WAN" "fritz4040:green:wan" "eth1"
+       ucidef_set_led_switch "lan" "LAN" "fritz4040:green:lan" "switch0" "0x1e"
+       ;;
+glinet,gl-b1300)
+       ucidef_set_led_wlan "wlan" "WLAN" "${boardname}:green:wlan" "phy0tpt"
+       ;;
+*)
+       ;;
+esac
+
+board_config_flush
+
+exit 0
diff --git a/target/linux/ipq40xx/base-files/etc/board.d/02_network b/target/linux/ipq40xx/base-files/etc/board.d/02_network
new file mode 100755 (executable)
index 0000000..37f81a3
--- /dev/null
@@ -0,0 +1,31 @@
+#!/bin/sh
+#
+# Copyright (c) 2015 The Linux Foundation. All rights reserved.
+# Copyright (c) 2011-2015 OpenWrt.org
+#
+
+. /lib/functions/uci-defaults.sh
+. /lib/functions/system.sh
+
+board_config_update
+
+board=$(board_name)
+
+case "$board" in
+avm,fritzbox-4040)
+       ucidef_set_interfaces_lan_wan "eth0" "eth1"
+       ucidef_add_switch "switch0" \
+               "0u@eth0" "1:lan" "2:lan" "3:lan" "4:lan"
+       ;;
+glinet,gl-b1300 |\
+openmesh,a42)
+       ucidef_set_interfaces_lan_wan "eth1" "eth0"
+       ;;
+*)
+       echo "Unsupported hardware. Network interfaces not intialized"
+       ;;
+esac
+
+board_config_flush
+
+exit 0
diff --git a/target/linux/ipq40xx/base-files/etc/diag.sh b/target/linux/ipq40xx/base-files/etc/diag.sh
new file mode 100755 (executable)
index 0000000..4cfe632
--- /dev/null
@@ -0,0 +1,43 @@
+#!/bin/sh
+
+. /lib/functions/leds.sh
+
+boot="$(get_dt_led boot)"
+failsafe="$(get_dt_led failsafe)"
+running="$(get_dt_led running)"
+upgrade="$(get_dt_led upgrade)"
+
+set_state() {
+       status_led="$boot"
+
+       case "$1" in
+       preinit)
+               status_led_blink_preinit
+               ;;
+       failsafe)
+               status_led_off
+               [ -n "$running" ] && {
+                       status_led="$running"
+                       status_led_off
+               }
+               status_led="$failsafe"
+               status_led_blink_failsafe
+               ;;
+       preinit_regular)
+               status_led_blink_preinit_regular
+               ;;
+       upgrade)
+               [ -n "$running" ] && {
+                       status_led="$upgrade"
+                       status_led_blink_preinit_regular
+               }
+               ;;
+       done)
+               status_led_off
+               [ -n "$running" ] && {
+                       status_led="$running"
+                       status_led_on
+               }
+               ;;
+       esac
+}
diff --git a/target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
new file mode 100644 (file)
index 0000000..33ea9b4
--- /dev/null
@@ -0,0 +1,62 @@
+#!/bin/sh
+
+ath10kcal_die() {
+       echo "ath10cal: " "$*"
+       exit 1
+}
+
+ath10kcal_extract() {
+       local part=$1
+       local offset=$2
+       local count=$3
+       local mtd
+
+       mtd=$(find_mtd_chardev $part)
+       [ -n "$mtd" ] || \
+               ath10kcal_die "no mtd device found for partition $part"
+
+       dd if=$mtd of=/lib/firmware/$FIRMWARE bs=1 skip=$offset count=$count 2>/dev/null || \
+               ath10kcal_die "failed to extract calibration data from $mtd"
+}
+
+[ -e /lib/firmware/$FIRMWARE ] && exit 0
+
+. /lib/functions.sh
+. /lib/functions/system.sh
+
+board=$(board_name)
+
+
+case "$FIRMWARE" in
+"ath10k/pre-cal-ahb-a000000.wifi.bin")
+       case "$board" in
+       avm,fritzbox-4040)
+               /usr/bin/fritz_cal_extract -i 1 -s 0x400 -e 0x207 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader_config")
+               ;;
+       glinet,gl-b1300 |\
+       qcom,ap-dk01.1-c1)
+               ath10kcal_extract "ART" 4096 12064
+               ;;
+       openmesh,a42)
+               ath10kcal_extract "0:ART" 4096 12064
+               ;;
+       esac
+       ;;
+"ath10k/pre-cal-ahb-a800000.wifi.bin")
+       case "$board" in
+       avm,fritzbox-4040)
+               /usr/bin/fritz_cal_extract -i 1 -s 0x400 -e 0x208 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader_config")
+               ;;
+       glinet,gl-b1300 |\
+       qcom,ap-dk01.1-c1)
+               ath10kcal_extract "ART" 20480 12064
+               ;;
+       openmesh,a42)
+               ath10kcal_extract "0:ART" 20480 12064
+               ;;
+       esac
+       ;;
+*)
+       exit 1
+       ;;
+esac
diff --git a/target/linux/ipq40xx/base-files/etc/inittab b/target/linux/ipq40xx/base-files/etc/inittab
new file mode 100644 (file)
index 0000000..809bba5
--- /dev/null
@@ -0,0 +1,4 @@
+# Copyright (c) 2013 The Linux Foundation. All rights reserved.
+::sysinit:/etc/init.d/rcS S boot
+::shutdown:/etc/init.d/rcS K shutdown
+ttyMSM0::askfirst:/usr/libexec/login.sh
diff --git a/target/linux/ipq40xx/base-files/lib/upgrade/openmesh.sh b/target/linux/ipq40xx/base-files/lib/upgrade/openmesh.sh
new file mode 100644 (file)
index 0000000..71ab247
--- /dev/null
@@ -0,0 +1,110 @@
+# The U-Boot loader of the OpenMesh devices requires image sizes and
+# checksums to be provided in the U-Boot environment.
+# The OpenMesh devices come with 2 main partitions - while one is active
+# sysupgrade will flash the other. The boot order is changed to boot the
+# newly flashed partition. If the new partition can't be booted due to
+# upgrade failures the previously used partition is loaded.
+
+platform_do_upgrade_openmesh() {
+       local tar_file="$1"
+       local restore_backup
+       local primary_kernel_mtd
+
+       local setenv_script="/tmp/fw_env_upgrade"
+
+       local kernel_mtd="$(find_mtd_index $PART_NAME)"
+       local kernel_offset="$(cat /sys/class/mtd/mtd${kernel_mtd}/offset)"
+       local total_size="$(cat /sys/class/mtd/mtd${kernel_mtd}/size)"
+
+       # detect to which flash region the new image is written to.
+       #
+       # 1. check what is the mtd index for the first flash region on this
+       #    device
+       # 2. check if the target partition ("inactive") has the mtd index of
+       #    the first flash region
+       #
+       #    - when it is: the new bootseq will be 1,2 and the first region is
+       #      modified
+       #    - when it isnt: bootseq will be 2,1 and the second region is
+       #      modified
+       #
+       # The detection has to be done via the hardcoded mtd partition because
+       # the current boot might be done with the fallback region. Let us
+       # assume that the current bootseq is 1,2. The bootloader detected that
+       # the image in flash region 1 is corrupt and thus switches to flash
+       # region 2. The bootseq in the u-boot-env is now still the same and
+       # the sysupgrade code can now only rely on the actual mtd indexes and
+       # not the bootseq variable to detect the currently booted flash
+       # region/image.
+       #
+       # In the above example, an implementation which uses bootseq ("1,2") to
+       # detect the currently booted image would assume that region 1 is booted
+       # and then overwrite the variables for the wrong flash region (aka the
+       # one which isn't modified). This could result in a device which doesn't
+       # boot anymore to Linux until it was reflashed with ap51-flash.
+       local next_boot_part="1"
+       case "$(board_name)" in
+       openmesh,a42)
+               primary_kernel_mtd=8
+               ;;
+       *)
+               echo "failed to detect primary kernel mtd partition for board"
+               return 1
+               ;;
+       esac
+       [ "$kernel_mtd" = "$primary_kernel_mtd" ] || next_boot_part="2"
+
+       local board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')
+       board_dir=${board_dir%/}
+
+       local kernel_length=$(tar xf $tar_file ${board_dir}/kernel -O | wc -c)
+       local rootfs_length=$(tar xf $tar_file ${board_dir}/root -O | wc -c)
+       # rootfs without EOF marker
+       rootfs_length=$((rootfs_length-4))
+
+       local kernel_md5=$(tar xf $tar_file ${board_dir}/kernel -O | md5sum); kernel_md5="${kernel_md5%% *}"
+       # md5 checksum of rootfs with EOF marker
+       local rootfs_md5=$(tar xf $tar_file ${board_dir}/root -O | dd bs=1 count=$rootfs_length | md5sum); rootfs_md5="${rootfs_md5%% *}"
+
+       #
+       # add tar support to get_image() to use default_do_upgrade() instead?
+       #
+
+       # take care of restoring a saved config
+       [ "$SAVE_CONFIG" -eq 1 ] && restore_backup="${MTD_CONFIG_ARGS} -j ${CONF_TAR}"
+
+       # write concatinated kernel + rootfs to flash
+       tar xf $tar_file ${board_dir}/kernel ${board_dir}/root -O | \
+               mtd $restore_backup write - $PART_NAME
+
+       # prepare new u-boot env
+       if [ "$next_boot_part" = "1" ]; then
+               echo "bootseq 1,2" > $setenv_script
+       else
+               echo "bootseq 2,1" > $setenv_script
+       fi
+
+       printf "kernel_size_%i 0x%08x\n" $next_boot_part $kernel_length >> $setenv_script
+       printf "vmlinux_start_addr 0x%08x\n" ${kernel_offset} >> $setenv_script
+       printf "vmlinux_size 0x%08x\n" ${kernel_length} >> $setenv_script
+       printf "vmlinux_checksum %s\n" ${kernel_md5} >> $setenv_script
+
+       printf "rootfs_size_%i 0x%08x\n" $next_boot_part $((total_size-kernel_length)) >> $setenv_script
+       printf "rootfs_start_addr 0x%08x\n" $((kernel_offset+kernel_length)) >> $setenv_script
+       printf "rootfs_size 0x%08x\n" ${rootfs_length} >> $setenv_script
+       printf "rootfs_checksum %s\n" ${rootfs_md5} >> $setenv_script
+
+       # store u-boot env changes
+       fw_setenv -s $setenv_script || {
+               echo "failed to update U-Boot environment"
+               return 1
+       }
+}
+
+# create /var/lock for the lock "fw_setenv.lock" of fw_setenv
+# the rest is copied using ipq806x's RAMFS_COPY_BIN and RAMFS_COPY_DATA
+platform_add_ramfs_ubootenv()
+{
+       mkdir -p $RAM_ROOT/var/lock
+}
+append sysupgrade_pre_upgrade platform_add_ramfs_ubootenv
diff --git a/target/linux/ipq40xx/base-files/lib/upgrade/platform.sh b/target/linux/ipq40xx/base-files/lib/upgrade/platform.sh
new file mode 100644 (file)
index 0000000..defa04d
--- /dev/null
@@ -0,0 +1,27 @@
+PART_NAME=firmware
+REQUIRE_IMAGE_METADATA=1
+
+RAMFS_COPY_BIN='fw_printenv fw_setenv'
+RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'
+
+platform_check_image() {
+       return 0;
+}
+
+platform_do_upgrade() {
+       case "$(board_name)" in
+       openmesh,a42)
+               PART_NAME="inactive"
+               platform_do_upgrade_openmesh "$ARGV"
+               ;;
+       *)
+               default_do_upgrade "$ARGV"
+               ;;
+       esac
+}
+
+blink_led() {
+       . /etc/diag.sh; set_state upgrade
+}
+
+append sysupgrade_pre_upgrade blink_led
diff --git a/target/linux/ipq40xx/config-4.14 b/target/linux/ipq40xx/config-4.14
new file mode 100644 (file)
index 0000000..b530157
--- /dev/null
@@ -0,0 +1,484 @@
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_APQ_GCC_8084 is not set
+# CONFIG_APQ_MMCC_8084 is not set
+CONFIG_AR40XX_PHY=y
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_ARCH_HAS_SET_MEMORY=y
+CONFIG_ARCH_HAS_SG_CHAIN=y
+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
+CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_IPQ40XX=y
+# CONFIG_ARCH_MDM9615 is not set
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+# CONFIG_ARCH_MSM8960 is not set
+# CONFIG_ARCH_MSM8974 is not set
+# CONFIG_ARCH_MSM8X60 is not set
+CONFIG_ARCH_MULTIPLATFORM=y
+# CONFIG_ARCH_MULTI_CPU_AUTO is not set
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_QCOM=y
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+# CONFIG_ARCH_WANTS_THP_SWAP is not set
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+# CONFIG_ARM_ATAG_DTB_COMPAT is not set
+CONFIG_ARM_CPUIDLE=y
+CONFIG_ARM_CPU_SUSPEND=y
+# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+# CONFIG_ARM_LPAE is not set
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_QCOM_CPUIDLE=y
+# CONFIG_ARM_SMMU is not set
+# CONFIG_ARM_SP805_WATCHDOG is not set
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_AT803X_PHY=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BOUNCE=y
+CONFIG_BUS_TOPOLOGY_ADHOC=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_QCOM=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_QCOM=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRYPTO_ACOMP2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DEV_QCE=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_NULL2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CRYPTO_XTS=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+# CONFIG_DEBUG_UART_8250 is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+# CONFIG_DMA_NOOP_OPS is not set
+CONFIG_DMA_OF=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+# CONFIG_DMA_VIRT_OPS is not set
+# CONFIG_DRM_LIB_RANDOM is not set
+CONFIG_DTC=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_ESSEDMA=y
+CONFIG_EXPORTFS=y
+CONFIG_EXTCON=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FUTEX_PI=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_WATCHDOG=y
+# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
+# CONFIG_GRO_CELLS is not set
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_HAVE_ARCH_BITREVERSE=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+CONFIG_HAVE_ARM_SMCCC=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_HAVE_EBPF_JIT=y
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_OPTPROBES=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SMP=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_UID16=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HIGHMEM=y
+# CONFIG_HIGHPTE is not set
+CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_QCOM=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_MSM=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_QUP=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IOMMU_HELPER=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IPQ_GCC_4019=y
+# CONFIG_IPQ_GCC_806X is not set
+# CONFIG_IPQ_GCC_8074 is not set
+# CONFIG_IPQ_LCC_806X is not set
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_GPIO=y
+CONFIG_MDIO_IPQ40XX=y
+# CONFIG_MDM_GCC_9615 is not set
+# CONFIG_MDM_LCC_9615 is not set
+# CONFIG_MFD_QCOM_RPM is not set
+# CONFIG_MFD_SPMI_PMIC is not set
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGHT_HAVE_PCI=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MSM_BUS_SCALING=y
+# CONFIG_MSM_GCC_8660 is not set
+# CONFIG_MSM_GCC_8916 is not set
+# CONFIG_MSM_GCC_8960 is not set
+# CONFIG_MSM_GCC_8974 is not set
+# CONFIG_MSM_GCC_8994 is not set
+# CONFIG_MSM_GCC_8996 is not set
+# CONFIG_MSM_LCC_8960 is not set
+# CONFIG_MSM_MMCC_8960 is not set
+# CONFIG_MSM_MMCC_8974 is not set
+# CONFIG_MSM_MMCC_8996 is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_QCOM=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+# CONFIG_MTD_UBI_FASTMAP is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MULTI_IRQ_HANDLER=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEON=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_QCA8K=y
+CONFIG_NET_DSA_TAG_QCA=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NLS=y
+CONFIG_NO_BOOTMEM=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=4
+CONFIG_NVMEM=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OPTEE=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_QCOM=y
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+# CONFIG_PHY_QCOM_APQ8064_SATA is not set
+# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
+# CONFIG_PHY_QCOM_QMP is not set
+# CONFIG_PHY_QCOM_QUSB2 is not set
+# CONFIG_PHY_QCOM_UFS is not set
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_APQ8064 is not set
+# CONFIG_PINCTRL_APQ8084 is not set
+CONFIG_PINCTRL_IPQ4019=y
+# CONFIG_PINCTRL_IPQ8064 is not set
+# CONFIG_PINCTRL_IPQ8074 is not set
+# CONFIG_PINCTRL_MDM9615 is not set
+CONFIG_PINCTRL_MSM=y
+# CONFIG_PINCTRL_MSM8660 is not set
+# CONFIG_PINCTRL_MSM8916 is not set
+# CONFIG_PINCTRL_MSM8960 is not set
+# CONFIG_PINCTRL_MSM8994 is not set
+# CONFIG_PINCTRL_MSM8996 is not set
+# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
+# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
+CONFIG_PM_OPP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_MSM=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_QCOM_BAM_DMA=y
+# CONFIG_QCOM_EBI2 is not set
+# CONFIG_QCOM_GSBI is not set
+# CONFIG_QCOM_IOMMU is not set
+CONFIG_QCOM_PM=y
+CONFIG_QCOM_QFPROM=y
+CONFIG_QCOM_SCM=y
+CONFIG_QCOM_SCM_32=y
+CONFIG_QCOM_SMEM=y
+# CONFIG_QCOM_SMP2P is not set
+# CONFIG_QCOM_SMSM is not set
+CONFIG_QCOM_TCSR=y
+# CONFIG_QCOM_TSENS is not set
+CONFIG_QCOM_WDT=y
+# CONFIG_QRTR is not set
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+CONFIG_RCU_NEED_SEGCBLIST=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_QCOM_SPMI is not set
+CONFIG_REGULATOR_VCTRL=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+# CONFIG_RPMSG_QCOM_SMD is not set
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_CMOS is not set
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+# CONFIG_SCHED_INFO is not set
+# CONFIG_SCSI_DMA is not set
+CONFIG_SERIAL_8250_FSL=y
+# CONFIG_SERIAL_AMBA_PL011 is not set
+CONFIG_SERIAL_MSM=y
+CONFIG_SERIAL_MSM_CONSOLE=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_QUP=y
+CONFIG_SPMI=y
+CONFIG_SPMI_MSM_PMIC_ARB=y
+CONFIG_SRCU=y
+CONFIG_SWCONFIG=y
+CONFIG_SWCONFIG_LEDS=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_TEE=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_OF=y
+CONFIG_THIN_ARCHIVES=y
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+# CONFIG_USB_EHCI_HCD is not set
+CONFIG_USB_IPQ4019_PHY=y
+CONFIG_USB_PHY=y
+# CONFIG_USB_QCOM_8X16_PHY is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_VDSO=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
diff --git a/target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4019-a42.dts b/target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4019-a42.dts
new file mode 100644 (file)
index 0000000..887be99
--- /dev/null
@@ -0,0 +1,244 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017, Sven Eckelmann <sven.eckelmann@openmesh.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+#include "qcom-ipq4019-bus.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+       model = "OpenMesh A42";
+       compatible = "openmesh,a42", "qcom,ipq4019";
+
+       reserved-memory {
+               #address-cells = <0x1>;
+               #size-cells = <0x1>;
+               ranges;
+
+               rsvd1@87000000 {
+                       reg = <0x87000000 0x500000>;
+                       no-map;
+               };
+
+               wifi_dump@87500000 {
+                       reg = <0x87500000 0x600000>;
+                       no-map;
+               };
+
+               rsvd2@87B00000 {
+                       reg = <0x87b00000 0x500000>;
+                       no-map;
+               };
+       };
+
+       soc {
+               tcsr@194b000 {
+                       /* select hostmode */
+                       compatible = "qcom,tcsr";
+                       reg = <0x194b000 0x100>;
+                       qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+                       status = "ok";
+               };
+
+               ess_tcsr@1953000 {
+                       compatible = "qcom,tcsr";
+                       reg = <0x1953000 0x1000>;
+                       qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+               };
+
+               tcsr@1949000 {
+                       compatible = "qcom,tcsr";
+                       reg = <0x1949000 0x100>;
+                       qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+               };
+
+               tcsr@1957000 {
+                       compatible = "qcom,tcsr";
+                       reg = <0x1957000 0x100>;
+                       qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+               };
+
+               pinctrl@1000000 {
+                       serial_pins: serial_pinmux {
+                               mux {
+                                       pins = "gpio60", "gpio61";
+                                       function = "blsp_uart0";
+                                       bias-disable;
+                               };
+                       };
+
+                       spi_0_pins: spi_0_pinmux {
+                               pinmux {
+                                       function = "blsp_spi0";
+                                       pins = "gpio55", "gpio56", "gpio57";
+                               };
+                               pinmux_cs {
+                                       function = "gpio";
+                                       pins = "gpio54";
+                               };
+                               pinconf {
+                                       pins = "gpio55", "gpio56", "gpio57";
+                                       drive-strength = <12>;
+                                       bias-disable;
+                               };
+                               pinconf_cs {
+                                       pins = "gpio54";
+                                       drive-strength = <2>;
+                                       bias-disable;
+                                       output-high;
+                               };
+                       };
+               };
+
+               blsp_dma: dma@7884000 {
+                       status = "ok";
+               };
+
+               spi_0: spi@78b5000 {
+                       pinctrl-0 = <&spi_0_pins>;
+                       pinctrl-names = "default";
+                       status = "ok";
+                       cs-gpios = <&tlmm 54 0>;
+
+                       m25p80@0 {
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               compatible = "jedec,spi-nor";
+                               reg = <0>;
+                               spi-max-frequency = <24000000>;
+
+                               /* partitions are passed via bootloader */
+                       };
+               };
+
+               serial@78af000 {
+                       pinctrl-0 = <&serial_pins>;
+                       pinctrl-names = "default";
+                       status = "ok";
+               };
+
+               cryptobam: dma@8e04000 {
+                       status = "ok";
+               };
+
+               crypto@8e3a000 {
+                       status = "ok";
+               };
+
+               watchdog@b017000 {
+                       status = "ok";
+               };
+
+               usb2_hs_phy: hsphy@a8000 {
+                       status = "ok";
+               };
+
+               usb2: usb2@60f8800 {
+                       status = "ok";
+               };
+
+               mdio@90000 {
+                       status = "okay";
+               };
+
+               ess-switch@c000000 {
+                       status = "okay";
+               };
+
+               ess-psgmii@98000 {
+                       status = "okay";
+               };
+
+               edma@c080000 {
+                       status = "okay";
+               };
+
+               wifi@a000000 {
+                       status = "okay";
+                       qcom,ath10k-calibration-variant = "OM-A42";
+               };
+
+               wifi@a800000 {
+                       status = "okay";
+                       qcom,ath10k-calibration-variant = "OM-A42";
+               };
+       };
+
+       gpio-keys {
+               compatible = "gpio-keys";
+
+               reset {
+                       label = "reset";
+                       gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_RESTART>;
+               };
+       };
+
+       aliases {
+               led-boot = &power;
+               led-failsafe = &power;
+               led-running = &power;
+               led-upgrade = &power;
+       };
+
+       gpio-leds {
+               compatible = "gpio-leds";
+
+               red {
+                       label = "a42:red:status";
+                       gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "default-off";
+               };
+
+               power: green {
+                       label = "a42:green:status";
+                       gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
+               };
+
+               blue {
+                       label = "a42:blue:status";
+                       gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "default-off";
+               };
+       };
+
+       watchdog {
+               compatible = "linux,wdt-gpio";
+               gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
+               hw_algo = "toggle";
+               /* hw_margin_ms is actually 300s but driver limits it to 60s */
+               hw_margin_ms = <60000>;
+               always-running;
+       };
+};
+
+&gmac0 {
+       qcom,phy_mdio_addr = <4>;
+       qcom,poll_required = <1>;
+       qcom,forced_speed = <1000>;
+       qcom,forced_duplex = <1>;
+       vlan_tag = <2 0x20>;
+};
+
+&gmac1 {
+       qcom,phy_mdio_addr = <3>;
+       qcom,poll_required = <1>;
+       qcom,forced_speed = <1000>;
+       qcom,forced_duplex = <1>;
+       vlan_tag = <1 0x10>;
+};
diff --git a/target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts b/target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
new file mode 100644 (file)
index 0000000..47202d2
--- /dev/null
@@ -0,0 +1,21 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+       model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK04.1-C1";
+};
diff --git a/target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
new file mode 100644 (file)
index 0000000..99fe8af
--- /dev/null
@@ -0,0 +1,176 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+
+/ {
+       model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
+       compatible = "qcom,ipq4019";
+
+       soc {
+               pinctrl@1000000 {
+                       serial_0_pins: serial_pinmux {
+                               mux {
+                                       pins = "gpio16", "gpio17";
+                                       function = "blsp_uart0";
+                                       bias-disable;
+                               };
+                       };
+
+                       serial_1_pins: serial1_pinmux {
+                               mux {
+                                       pins = "gpio8", "gpio9";
+                                       function = "blsp_uart1";
+                                       bias-disable;
+                               };
+                       };
+
+                       spi_0_pins: spi_0_pinmux {
+                               pinmux {
+                                       function = "blsp_spi0";
+                                       pins = "gpio13", "gpio14", "gpio15";
+                               };
+                               pinmux_cs {
+                                       function = "gpio";
+                                       pins = "gpio12";
+                               };
+                               pinconf {
+                                       pins = "gpio13", "gpio14", "gpio15";
+                                       drive-strength = <12>;
+                                       bias-disable;
+                               };
+                               pinconf_cs {
+                                       pins = "gpio12";
+                                       drive-strength = <2>;
+                                       bias-disable;
+                                       output-high;
+                               };
+                       };
+
+                       i2c_0_pins: i2c_0_pinmux {
+                               pinmux {
+                                       function = "blsp_i2c0";
+                                       pins = "gpio10", "gpio11";
+                               };
+                               pinconf {
+                                       pins = "gpio10", "gpio11";
+                                       drive-strength = <16>;
+                                       bias-disable;
+                               };
+                       };
+
+                       nand_pins: nand_pins {
+
+                               pullups {
+                                       pins = "gpio52", "gpio53", "gpio58",
+                                               "gpio59";
+                                       function = "qpic";
+                                       bias-pull-up;
+                               };
+
+                               pulldowns {
+                                       pins = "gpio54", "gpio55", "gpio56",
+                                               "gpio57", "gpio60", "gpio61",
+                                               "gpio62", "gpio63", "gpio64",
+                                               "gpio65", "gpio66", "gpio67",
+                                               "gpio68", "gpio69";
+                                       function = "qpic";
+                                       bias-pull-down;
+                               };
+                       };
+               };
+
+               blsp_dma: dma@7884000 {
+                       status = "ok";
+               };
+
+               spi_0: spi@78b5000 {
+                       pinctrl-0 = <&spi_0_pins>;
+                       pinctrl-names = "default";
+                       status = "ok";
+                       cs-gpios = <&tlmm 12 0>;
+
+                       mx25l25635e@0 {
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               reg = <0>;
+                               compatible = "mx25l25635e";
+                               spi-max-frequency = <24000000>;
+                       };
+               };
+
+               i2c_0: i2c@78b7000 { /* BLSP1 QUP2 */
+                       pinctrl-0 = <&i2c_0_pins>;
+                       pinctrl-names = "default";
+
+                       status = "ok";
+               };
+
+               serial@78af000 {
+                       pinctrl-0 = <&serial_0_pins>;
+                       pinctrl-names = "default";
+                       status = "ok";
+               };
+
+               serial@78b0000 {
+                       pinctrl-0 = <&serial_1_pins>;
+                       pinctrl-names = "default";
+                       status = "ok";
+               };
+
+               usb3_ss_phy: ssphy@9a000 {
+                       status = "ok";
+               };
+
+               usb3_hs_phy: hsphy@a6000 {
+                       status = "ok";
+               };
+
+               usb3: usb3@8af8800 {
+                       status = "ok";
+               };
+
+               usb2_hs_phy: hsphy@a8000 {
+                       status = "ok";
+               };
+
+               usb2: usb2@60f8800 {
+                       status = "ok";
+               };
+
+               cryptobam: dma@8e04000 {
+                       status = "ok";
+               };
+
+               crypto@8e3a000 {
+                       status = "ok";
+               };
+
+               watchdog@b017000 {
+                       status = "ok";
+               };
+
+               qpic_bam: dma@7984000 {
+                       status = "ok";
+               };
+
+               nand: qpic-nand@79b0000 {
+                       pinctrl-0 = <&nand_pins>;
+                       pinctrl-names = "default";
+                       status = "ok";
+               };
+       };
+};
diff --git a/target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4019-bus.dtsi b/target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4019-bus.dtsi
new file mode 100644 (file)
index 0000000..1695059
--- /dev/null
@@ -0,0 +1,1142 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+/ {
+
+soc {
+       ad_hoc_bus: ad-hoc-bus {
+               compatible = "qcom,msm-bus-device";
+               reg = <0x580000 0x14000>,
+                       <0x500000 0x11000>;
+               reg-names = "snoc-base", "pcnoc-base";
+
+               /*Buses*/
+
+               fab_pcnoc: fab-pcnoc {
+                       cell-id = <MSM_BUS_FAB_PERIPH_NOC>;
+                       label = "fab-pcnoc";
+                       qcom,fab-dev;
+                       qcom,base-name = "pcnoc-base";
+                       qcom,bypass-qos-prg;
+                       qcom,bus-type = <1>;
+                       qcom,qos-off = <0x1000>;
+                       qcom,base-offset = <0x0>;
+                       clocks = <>;
+               };
+
+               fab_snoc: fab-snoc {
+                       cell-id = <MSM_BUS_FAB_SYS_NOC>;
+                       label = "fab-snoc";
+                       qcom,fab-dev;
+                       qcom,base-name = "snoc-base";
+                       qcom,bypass-qos-prg;
+                       qcom,bus-type = <1>;
+                       qcom,qos-off = <0x80>;
+                       qcom,base-offset = <0x0>;
+                       clocks = <>;
+               };
+
+               /*Masters*/
+
+               mas_blsp_bam: mas-blsp-bam {
+                       cell-id = <MSM_BUS_MASTER_BLSP_BAM>;
+                       label = "mas-blsp-bam";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&pcnoc_m_0>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_BLSP_BAM>;
+                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
+                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
+                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
+                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
+                                &slv_srif &slv_prng &slv_qdss_cfg
+                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
+                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
+                                &slv_boot_rom &slv_security &slv_spdm
+                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
+                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
+                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
+                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
+                                &slv_sdcc_cfg &slv_snoc_cfg>;
+               };
+
+               mas_usb2_bam: mas-usb2-bam {
+                       cell-id = <MSM_BUS_MASTER_USB2_BAM>;
+                       label = "mas-usb2-bam";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,qport = <15>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&slv_pcnoc_snoc>;
+                       qcom,prio1 = <1>;
+                       qcom,prio0 = <1>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_USB2_BAM>;
+                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
+                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
+                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
+                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
+                                &slv_srif &slv_prng &slv_qdss_cfg
+                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
+                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
+                                &slv_boot_rom &slv_security &slv_spdm
+                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
+                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
+                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
+                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
+                                &slv_sdcc_cfg &slv_snoc_cfg>;
+               };
+
+               mas_adss_dma0: mas-adss-dma0 {
+                       cell-id = <MSM_BUS_MASTER_ADDS_DMA0>;
+                       label = "mas-adss-dma0";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&pcnoc_m_1>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_ADSS_DMA0>;
+                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
+                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
+                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
+                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
+                                &slv_srif &slv_prng &slv_qdss_cfg
+                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
+                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
+                                &slv_boot_rom &slv_security &slv_spdm
+                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
+                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
+                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
+                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
+                                &slv_sdcc_cfg &slv_snoc_cfg>;
+               };
+
+               mas_adss_dma1: mas-adss-dma1 {
+                       cell-id = <MSM_BUS_MASTER_ADDS_DMA1>;
+                       label = "mas-adss-dma1";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&pcnoc_m_1>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_ADSS_DMA1>;
+                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
+                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
+                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
+                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
+                                &slv_srif &slv_prng &slv_qdss_cfg
+                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
+                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
+                                &slv_boot_rom &slv_security &slv_spdm
+                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
+                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
+                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
+                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
+                                &slv_sdcc_cfg &slv_snoc_cfg>;
+               };
+
+               mas_adss_dma2: mas-adss-dma2 {
+                       cell-id = <MSM_BUS_MASTER_ADDS_DMA2>;
+                       label = "mas-adss-dma2";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&pcnoc_m_1>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_ADSS_DMA2>;
+                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
+                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
+                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
+                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
+                                &slv_srif &slv_prng &slv_qdss_cfg
+                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
+                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
+                                &slv_boot_rom &slv_security &slv_spdm
+                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
+                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
+                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
+                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
+                                &slv_sdcc_cfg &slv_snoc_cfg>;
+               };
+
+               mas_adss_dma3: mas-adss-dma3 {
+                       cell-id = <MSM_BUS_MASTER_ADDS_DMA3>;
+                       label = "mas-adss-dma3";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&pcnoc_m_1>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_ADSS_DMA3>;
+                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
+                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
+                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
+                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
+                                &slv_srif &slv_prng &slv_qdss_cfg
+                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
+                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
+                                &slv_boot_rom &slv_security &slv_spdm
+                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
+                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
+                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
+                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
+                                &slv_sdcc_cfg &slv_snoc_cfg>;
+               };
+
+               mas_qpic_bam: mas-qpic-bam {
+                       cell-id = <MSM_BUS_MASTER_QPIC_BAM>;
+                       label = "mas-qpic-bam";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&pcnoc_m_0>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_QPIC_BAM>;
+                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
+                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
+                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
+                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
+                                &slv_srif &slv_prng &slv_qdss_cfg
+                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
+                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
+                                &slv_boot_rom &slv_security &slv_spdm
+                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
+                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
+                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
+                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
+                                &slv_sdcc_cfg &slv_snoc_cfg>;
+               };
+
+               mas_spdm: mas-spdm {
+                       cell-id = <MSM_BUS_MASTER_SPDM>;
+                       label = "mas-spdm";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&pcnoc_m_0>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_SPDM>;
+                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
+                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
+                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
+                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
+                                &slv_srif &slv_prng &slv_qdss_cfg
+                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
+                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
+                                &slv_boot_rom &slv_security &slv_spdm
+                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
+                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
+                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
+                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
+                                &slv_sdcc_cfg &slv_snoc_cfg>;
+               };
+
+               mas_pcnoc_cfg: mas-pcnoc-cfg {
+                       cell-id = <MSM_BUS_MASTER_PNOC_CFG>;
+                       label = "mas-pcnoc-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&slv_srvc_pcnoc>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_CFG>;
+               };
+
+               mas_tic: mas-tic {
+                       cell-id = <MSM_BUS_MASTER_TIC>;
+                       label = "mas-tic";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&pcnoc_int_0 &slv_pcnoc_snoc>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_TIC>;
+               };
+
+               mas_sdcc_bam: mas-sdcc-bam {
+                       cell-id = <MSM_BUS_MASTER_SDCC_BAM>;
+                       label = "mas-sdcc-bam";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,qport = <14>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&slv_pcnoc_snoc>;
+                       qcom,prio1 = <0>;
+                       qcom,prio0 = <0>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_SDCC_BAM>;
+                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
+                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
+                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
+                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
+                                &slv_srif &slv_prng &slv_qdss_cfg
+                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
+                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
+                                &slv_boot_rom &slv_security &slv_spdm
+                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
+                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
+                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
+                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
+                                &slv_sdcc_cfg &slv_snoc_cfg>;
+               };
+
+               mas_snoc_pcnoc: mas-snoc-pcnoc {
+                       cell-id = <MSM_BUS_SNOC_PNOC_MAS>;
+                       label = "mas-snoc-pcnoc";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,qport = <16>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&pcnoc_int_0>;
+                       qcom,prio1 = <0>;
+                       qcom,prio0 = <0>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_SNOC_PCNOC>;
+               };
+
+               mas_qdss_dap: mas-qdss-dap {
+                       cell-id = <MSM_BUS_MASTER_QDSS_DAP>;
+                       label = "mas-qdss-dap";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&pcnoc_int_0 &slv_pcnoc_snoc>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_QDSS_DAP>;
+               };
+
+               mas_ddrc_snoc: mas-ddrc-snoc {
+                       cell-id = <MSM_BUS_MASTER_DDRC_SNOC>;
+                       label = "mas-ddrc-snoc";
+                       qcom,buswidth = <16>;
+                       qcom,ap-owned;
+                       qcom,connections = <&snoc_int_0 &snoc_int_1
+                                &slv_pcie>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_DDRC_SNOC>;
+                       qcom,blacklist = <&slv_snoc_ddrc_m1 &slv_srvc_snoc>;
+               };
+
+               mas_wss_0: mas-wss-0 {
+                       cell-id = <MSM_BUS_MASTER_WSS_0>;
+                       label = "mas-wss-0";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,qport = <26>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&snoc_int_0 &slv_snoc_ddrc_m1>;
+                       qcom,prio1 = <0>;
+                       qcom,prio0 = <0>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_WSS_0>;
+                       qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_pcie
+                                &slv_wss1_cfg &slv_wss0_cfg &slv_crypto_cfg
+                                &slv_srvc_snoc>;
+               };
+
+               mas_wss_1: mas-wss-1 {
+                       cell-id = <MSM_BUS_MASTER_WSS_1>;
+                       label = "mas-wss-1";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,qport = <27>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&snoc_int_0 &slv_snoc_ddrc_m1>;
+                       qcom,prio1 = <0>;
+                       qcom,prio0 = <0>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_WSS_1>;
+                       qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_pcie
+                                &slv_wss1_cfg &slv_wss0_cfg &slv_crypto_cfg
+                                &slv_srvc_snoc>;
+               };
+
+               mas_crypto: mas-crypto {
+                       cell-id = <MSM_BUS_MASTER_CRYPTO>;
+                       label = "mas-crypto";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,qport = <5>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&snoc_int_0 &snoc_int_1
+                                &slv_snoc_ddrc_m1>;
+                       qcom,prio1 = <0>;
+                       qcom,prio0 = <0>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_CRYPTO>;
+                       qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_a7ss
+                                &slv_pcie &slv_qdss_stm &slv_crypto_cfg
+                                &slv_srvc_snoc>;
+               };
+
+               mas_ess: mas-ess {
+                       cell-id = <MSM_BUS_MASTER_ESS>;
+                       label = "mas-ess";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,qport = <44>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&snoc_int_0 &slv_snoc_ddrc_m1>;
+                       qcom,prio1 = <0>;
+                       qcom,prio0 = <0>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_ESS>;
+                       qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_a7ss
+                                &slv_pcie &slv_qdss_stm &slv_wss1_cfg
+                                &slv_wss0_cfg &slv_crypto_cfg &slv_srvc_snoc>;
+               };
+
+               mas_pcie: mas-pcie {
+                       cell-id = <MSM_BUS_MASTER_PCIE>;
+                       label = "mas-pcie";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,qport = <6>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&snoc_int_0 &slv_snoc_ddrc_m1>;
+                       qcom,prio1 = <0>;
+                       qcom,prio0 = <0>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCIE>;
+                       qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_pcie
+                                &slv_qdss_stm &slv_wss1_cfg &slv_wss0_cfg
+                                &slv_crypto_cfg &slv_srvc_snoc>;
+               };
+
+               mas_usb3: mas-usb3 {
+                       cell-id = <MSM_BUS_MASTER_USB3>;
+                       label = "mas-usb3";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,qport = <7>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&snoc_int_0 &slv_snoc_ddrc_m1>;
+                       qcom,prio1 = <0>;
+                       qcom,prio0 = <0>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_USB3>;
+                       qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_a7ss
+                                &slv_pcie &slv_qdss_stm &slv_wss1_cfg
+                                &slv_wss0_cfg &slv_crypto_cfg &slv_srvc_snoc>;
+               };
+
+               mas_qdss_etr: mas-qdss-etr {
+                       cell-id = <MSM_BUS_MASTER_QDSS_ETR>;
+                       label = "mas-qdss-etr";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,qport = <544>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&qdss_int>;
+                       qcom,prio1 = <0>;
+                       qcom,prio0 = <0>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_QDSS_ETR>;
+                       qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_a7ss
+                                &slv_pcie &slv_qdss_stm &slv_wss1_cfg
+                                &slv_wss0_cfg &slv_crypto_cfg &slv_srvc_snoc>;
+               };
+
+               mas_qdss_bamndp: mas-qdss-bamndp {
+                       cell-id = <MSM_BUS_MASTER_QDSS_BAMNDP>;
+                       label = "mas-qdss-bamndp";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,qport = <576>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&qdss_int>;
+                       qcom,prio1 = <0>;
+                       qcom,prio0 = <0>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_QDSS_BAMNDP>;
+                       qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_a7ss
+                                &slv_pcie &slv_qdss_stm &slv_wss1_cfg
+                                &slv_wss0_cfg &slv_crypto_cfg &slv_srvc_snoc>;
+               };
+
+               mas_pcnoc_snoc: mas-pcnoc-snoc {
+                       cell-id = <MSM_BUS_PNOC_SNOC_MAS>;
+                       label = "mas-pcnoc-snoc";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,qport = <384>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&snoc_int_0 &snoc_int_1
+                                &slv_snoc_ddrc_m1>;
+                       qcom,prio1 = <0>;
+                       qcom,prio0 = <0>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PNOC_SNOC>;
+                       qcom,blacklist = <&slv_srvc_snoc>;
+               };
+
+               mas_snoc_cfg: mas-snoc-cfg {
+                       cell-id = <MSM_BUS_MASTER_QDSS_SNOC_CFG>;
+                       label = "mas-snoc-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&slv_srvc_snoc>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_QDSS_SNOC_CFG>;
+               };
+
+               /*Internal nodes*/
+
+
+               pcnoc_m_0: pcnoc-m-0 {
+                       cell-id = <MSM_BUS_PNOC_M_0>;
+                       label = "pcnoc-m-0";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,qport = <12>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&slv_pcnoc_snoc>;
+                       qcom,prio1 = <1>;
+                       qcom,prio0 = <1>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_M_0>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_M_0>;
+               };
+
+               pcnoc_m_1: pcnoc-m-1 {
+                       cell-id = <MSM_BUS_PNOC_M_1>;
+                       label = "pcnoc-m-1";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,qport = <13>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&slv_pcnoc_snoc>;
+                       qcom,prio1 = <1>;
+                       qcom,prio0 = <1>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_M_1>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_M_1>;
+               };
+
+               pcnoc_int_0: pcnoc-int-0 {
+                       cell-id = <MSM_BUS_PNOC_INT_0>;
+                       label = "pcnoc-int-0";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,connections = < &pcnoc_s_1 &pcnoc_s_2 &pcnoc_s_0
+                                &pcnoc_s_4 &pcnoc_s_5
+                                &pcnoc_s_6 &pcnoc_s_7
+                                &pcnoc_s_8 &pcnoc_s_9
+                                &pcnoc_s_3>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_0>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_0>;
+               };
+
+               pcnoc_s_0: pcnoc-s-0 {
+                       cell-id = <MSM_BUS_PNOC_SLV_0>;
+                       label = "pcnoc-s-0";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&slv_clk_ctl &slv_tcsr &slv_security
+                                &slv_tlmm>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_0>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_0>;
+               };
+
+               pcnoc_s_1: pcnoc-s-1 {
+                       cell-id = <MSM_BUS_PNOC_SLV_1>;
+                       label = "pcnoc-s-1";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = < &slv_prng_apu_cfg &slv_prng&slv_imem_cfg>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_1>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_1>;
+               };
+
+               pcnoc_s_2: pcnoc-s-2 {
+                       cell-id = <MSM_BUS_PNOC_SLV_2>;
+                       label = "pcnoc-s-2";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = < &slv_spdm &slv_pcnoc_mpu_cfg &slv_pcnoc_cfg
+                               &slv_boot_rom>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_2>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_2>;
+               };
+
+               pcnoc_s_3: pcnoc-s-3 {
+                       cell-id = <MSM_BUS_PNOC_SLV_3>;
+                       label = "pcnoc-s-3";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = < &slv_qdss_cfg&slv_gcnt &slv_snoc_cfg
+                                &slv_snoc_mpu_cfg>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_3>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_3>;
+               };
+
+               pcnoc_s_4: pcnoc-s-4 {
+                       cell-id = <MSM_BUS_PNOC_SLV_4>;
+                       label = "pcnoc-s-4";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&slv_adss_cfg &slv_adss_vmidmt_cfg &slv_adss_apu>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_4>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_4>;
+               };
+
+               pcnoc_s_5: pcnoc-s-5 {
+                       cell-id = <MSM_BUS_PNOC_SLV_5>;
+                       label = "pcnoc-s-5";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&slv_qhss_apu_cfg &slv_fephy_cfg &slv_mdio
+                                &slv_srif>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_5>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_5>;
+               };
+
+               pcnoc_s_6: pcnoc-s-6 {
+                       cell-id = <MSM_BUS_PNOC_SLV_6>;
+                       label = "pcnoc-s-6";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = < &slv_ddrc_mpu0_cfg &slv_ddrc_apu_cfg &slv_ddrc_mpu2_cfg
+                               &slv_ddrc_cfg &slv_ddrc_mpu1_cfg>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_6>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_6>;
+               };
+
+               pcnoc_s_7: pcnoc-s-7 {
+                       cell-id = <MSM_BUS_PNOC_SLV_7>;
+                       label = "pcnoc-s-7";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = < &slv_ess_apu_cfg &slv_usb2_cfg&slv_ess_vmidmt_cfg>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_7>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_7>;
+               };
+
+               pcnoc_s_8: pcnoc-s-8 {
+                       cell-id = <MSM_BUS_PNOC_SLV_8>;
+                       label = "pcnoc-s-8";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = < &slv_sdcc_cfg &slv_qpic_cfg&slv_blsp_cfg>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_8>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_8>;
+               };
+
+               pcnoc_s_9: pcnoc-s-9 {
+                       cell-id = <MSM_BUS_PNOC_SLV_9>;
+                       label = "pcnoc-s-9";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = < &slv_wss1_apu_cfg &slv_wss1_vmidmt_cfg&slv_wss0_vmidmt_cfg
+                                &slv_wss0_apu_cfg>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_9>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_9>;
+               };
+
+               snoc_int_0: snoc-int-0 {
+                       cell-id = <MSM_BUS_SNOC_INT_0>;
+                       label = "snoc-int-0";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,connections = < &slv_ocimem&slv_qdss_stm>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_SNOC_INT_0>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_INT_0>;
+               };
+
+               snoc_int_1: snoc-int-1 {
+                       cell-id = <MSM_BUS_SNOC_INT_1>;
+                       label = "snoc-int-1";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,connections = < &slv_crypto_cfg &slv_a7ss &slv_ess_cfg
+                                &slv_usb3_cfg &slv_wss1_cfg
+                               &slv_wss0_cfg>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_SNOC_INT_1>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_INT_1>;
+               };
+
+               qdss_int: qdss-int {
+                       cell-id = <MSM_BUS_SNOC_QDSS_INT>;
+                       label = "qdss-int";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,connections = <&snoc_int_0 &slv_snoc_ddrc_m1>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_QDSS_INT>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_INT>;
+               };
+               /*Slaves*/
+
+               slv_clk_ctl:slv-clk-ctl {
+                       cell-id = <MSM_BUS_SLAVE_CLK_CTL>;
+                       label = "slv-clk-ctl";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_CLK_CTL>;
+               };
+
+               slv_security:slv-security {
+                       cell-id = <MSM_BUS_SLAVE_SECURITY>;
+                       label = "slv-security";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_SECURITY>;
+               };
+
+               slv_tcsr:slv-tcsr {
+                       cell-id = <MSM_BUS_SLAVE_TCSR>;
+                       label = "slv-tcsr";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_TCSR>;
+               };
+
+               slv_tlmm:slv-tlmm {
+                       cell-id = <MSM_BUS_SLAVE_TLMM>;
+                       label = "slv-tlmm";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_TLMM>;
+               };
+
+               slv_imem_cfg:slv-imem-cfg {
+                       cell-id = <MSM_BUS_SLAVE_IMEM_CFG>;
+                       label = "slv-imem-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_IMEM_CFG>;
+               };
+
+               slv_prng:slv-prng {
+                       cell-id = <MSM_BUS_SLAVE_PRNG>;
+                       label = "slv-prng";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PRNG>;
+               };
+
+               slv_prng_apu_cfg:slv-prng-apu-cfg {
+                       cell-id = <MSM_BUS_SLAVE_PRNG_APU_CFG>;
+                       label = "slv-prng-apu-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PRNG_APU_CFG>;
+               };
+
+               slv_boot_rom:slv-boot-rom {
+                       cell-id = <MSM_BUS_SLAVE_BOOT_ROM>;
+                       label = "slv-boot-rom";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_BOOT_ROM>;
+               };
+
+               slv_spdm:slv-spdm {
+                       cell-id = <MSM_BUS_SLAVE_SPDM_WRAPPER>;
+                       label = "slv-spdm";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_SPDM_WRAPPER>;
+               };
+
+               slv_pcnoc_cfg:slv-pcnoc-cfg {
+                       cell-id = <MSM_BUS_SLAVE_PNOC_CFG>;
+                       label = "slv-pcnoc-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PNOC_CFG>;
+               };
+
+               slv_pcnoc_mpu_cfg:slv-pcnoc-mpu-cfg {
+                       cell-id = <MSM_BUS_SLAVE_PERIPH_MPU_CFG>;
+                       label = "slv-pcnoc-mpu-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PERIPH_MPU_CFG>;
+               };
+
+               slv_gcnt:slv-gcnt {
+                       cell-id = <MSM_BUS_SLAVE_GCNT>;
+                       label = "slv-gcnt";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_GCNT>;
+               };
+
+               slv_qdss_cfg:slv-qdss-cfg {
+                       cell-id = <MSM_BUS_SLAVE_QDSS_CFG>;
+                       label = "slv-qdss-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_CFG>;
+               };
+
+               slv_snoc_cfg:slv-snoc-cfg {
+                       cell-id = <MSM_BUS_SLAVE_SNOC_CFG>;
+                       label = "slv-snoc-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_CFG>;
+               };
+
+               slv_snoc_mpu_cfg:slv-snoc-mpu-cfg {
+                       cell-id = <MSM_BUS_SLAVE_SNOC_MPU_CFG>;
+                       label = "slv-snoc-mpu-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_MPU_CFG>;
+               };
+
+               slv_adss_cfg:slv-adss-cfg {
+                       cell-id = <MSM_BUS_SLAVE_ADSS_CFG>;
+                       label = "slv-adss-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_ADSS_CFG>;
+               };
+
+               slv_adss_apu:slv-adss-apu {
+                       cell-id = <MSM_BUS_SLAVE_ADSS_VMIDMT_CFG>;
+                       label = "slv-adss-apu";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_ADSS_APU>;
+               };
+
+               slv_adss_vmidmt_cfg:slv-adss-vmidmt-cfg {
+                       cell-id = <MSM_BUS_SLAVE_ADSS_VMIDMT_CFG>;
+                       label = "slv-adss-vmidmt-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_ADSS_VMIDMT_CFG>;
+               };
+
+               slv_qhss_apu_cfg:slv-qhss-apu-cfg {
+                       cell-id = <MSM_BUS_SLAVE_QHSS_APU_CFG>;
+                       label = "slv-qhss-apu-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_QHSS_APU_CFG>;
+               };
+
+               slv_mdio:slv-mdio {
+                       cell-id = <MSM_BUS_SLAVE_MDIO>;
+                       label = "slv-mdio";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_MDIO>;
+               };
+
+               slv_fephy_cfg:slv-fephy-cfg {
+                       cell-id = <MSM_BUS_SLAVE_FEPHY_CFG>;
+                       label = "slv-fephy-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_FEPHY_CFG>;
+               };
+
+               slv_srif:slv-srif {
+                       cell-id = <MSM_BUS_SLAVE_SRIF>;
+                       label = "slv-srif";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_SRIF>;
+               };
+
+               slv_ddrc_cfg:slv-ddrc-cfg {
+                       cell-id = <MSM_BUS_SLAVE_DDRC_CFG>;
+                       label = "slv-ddrc-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_DDRC_CFG>;
+               };
+
+               slv_ddrc_apu_cfg:slv-ddrc-apu-cfg {
+                       cell-id = <MSM_BUS_SLAVE_DDRC_APU_CFG>;
+                       label = "slv-ddrc-apu-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_DDRC_APU_CFG>;
+               };
+
+               slv_ddrc_mpu0_cfg:slv-ddrc-mpu0-cfg {
+                       cell-id = <MSM_BUS_SLAVE_MPU0_CFG>;
+                       label = "slv-ddrc-mpu0-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_DDRC_MPU0_CFG>;
+               };
+
+               slv_ddrc_mpu1_cfg:slv-ddrc-mpu1-cfg {
+                       cell-id = <MSM_BUS_SLAVE_MPU1_CFG>;
+                       label = "slv-ddrc-mpu1-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_DDRC_MPU1_CFG>;
+               };
+
+               slv_ddrc_mpu2_cfg:slv-ddrc-mpu2-cfg {
+                       cell-id = <MSM_BUS_SLAVE_MPU2_CFG>;
+                       label = "slv-ddrc-mpu2-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_DDRC_MPU2_CFG>;
+               };
+
+               slv_ess_vmidmt_cfg:slv-ess-vmidmt-cfg {
+                       cell-id = <MSM_BUS_SLAVE_ESS_VMIDMT_CFG>;
+                       label = "slv-ess-vmidmt-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_ESS_VMIDMT_CFG>;
+               };
+
+               slv_ess_apu_cfg:slv-ess-apu-cfg {
+                       cell-id = <MSM_BUS_SLAVE_ESS_APU_CFG>;
+                       label = "slv-ess-apu-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_ESS_APU_CFG>;
+               };
+
+               slv_usb2_cfg:slv-usb2-cfg {
+                       cell-id = <MSM_BUS_SLAVE_USB2_CFG>;
+                       label = "slv-usb2-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_USB2_CFG>;
+               };
+
+               slv_blsp_cfg:slv-blsp-cfg {
+                       cell-id = <MSM_BUS_SLAVE_BLSP_CFG>;
+                       label = "slv-blsp-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_BLSP_CFG>;
+               };
+
+               slv_qpic_cfg:slv-qpic-cfg {
+                       cell-id = <MSM_BUS_SLAVE_QPIC_CFG>;
+                       label = "slv-qpic-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_QPIC_CFG>;
+               };
+
+               slv_sdcc_cfg:slv-sdcc-cfg {
+                       cell-id = <MSM_BUS_SLAVE_SDCC_CFG>;
+                       label = "slv-sdcc-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_CFG>;
+               };
+
+               slv_wss0_vmidmt_cfg:slv-wss0-vmidmt-cfg {
+                       cell-id = <MSM_BUS_SLAVE_WSS0_VMIDMT_CFG>;
+                       label = "slv-wss0-vmidmt-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_WSS0_VMIDMT_CFG>;
+               };
+
+               slv_wss0_apu_cfg:slv-wss0-apu-cfg {
+                       cell-id = <MSM_BUS_SLAVE_WSS0_APU_CFG>;
+                       label = "slv-wss0-apu-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_WSS0_APU_CFG>;
+               };
+
+               slv_wss1_vmidmt_cfg:slv-wss1-vmidmt-cfg {
+                       cell-id = <MSM_BUS_SLAVE_WSS1_VMIDMT_CFG>;
+                       label = "slv-wss1-vmidmt-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_WSS1_VMIDMT_CFG>;
+               };
+
+               slv_wss1_apu_cfg:slv-wss1-apu-cfg {
+                       cell-id = <MSM_BUS_SLAVE_WSS1_APU_CFG>;
+                       label = "slv-wss1-apu-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_WSS1_APU_CFG>;
+               };
+
+               slv_pcnoc_snoc:slv-pcnoc-snoc {
+                       cell-id = <MSM_BUS_PNOC_SNOC_SLV>;
+                       label = "slv-pcnoc-snoc";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_SNOC>;
+               };
+
+               slv_srvc_pcnoc:slv-srvc-pcnoc {
+                       cell-id = <MSM_BUS_SLAVE_SRVC_PCNOC>;
+                       label = "slv-srvc-pcnoc";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_SRVC_PCNOC>;
+               };
+
+               slv_snoc_ddrc_m1:slv-snoc-ddrc-m1 {
+                       cell-id = <MSM_BUS_SLAVE_SNOC_DDRC>;
+                       label = "slv-snoc-ddrc-m1";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_DDRC>;
+               };
+
+               slv_a7ss:slv-a7ss {
+                       cell-id = <MSM_BUS_SLAVE_A7SS>;
+                       label = "slv-a7ss";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_A7SS>;
+               };
+
+               slv_ocimem:slv-ocimem {
+                       cell-id = <MSM_BUS_SLAVE_OCIMEM>;
+                       label = "slv-ocimem";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_OCIMEM>;
+               };
+
+               slv_wss0_cfg:slv-wss0-cfg {
+                       cell-id = <MSM_BUS_SLAVE_WSS0_CFG>;
+                       label = "slv-wss0-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_WSS0_CFG>;
+               };
+
+               slv_wss1_cfg:slv-wss1-cfg {
+                       cell-id = <MSM_BUS_SLAVE_WSS1_CFG>;
+                       label = "slv-wss1-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_WSS1_CFG>;
+               };
+
+               slv_pcie:slv-pcie {
+                       cell-id = <MSM_BUS_SLAVE_PCIE>;
+                       label = "slv-pcie";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCIE>;
+               };
+
+               slv_usb3_cfg:slv-usb3-cfg {
+                       cell-id = <MSM_BUS_SLAVE_USB3_CFG>;
+                       label = "slv-usb3-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_USB3_CFG>;
+               };
+
+               slv_crypto_cfg:slv-crypto-cfg {
+                       cell-id = <MSM_BUS_SLAVE_CRYPTO_CFG>;
+                       label = "slv-crypto-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_CRYPTO_CFG>;
+               };
+
+               slv_ess_cfg:slv-ess-cfg {
+                       cell-id = <MSM_BUS_SLAVE_ESS_CFG>;
+                       label = "slv-ess-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_ESS_CFG>;
+               };
+
+               slv_qdss_stm:slv-qdss-stm {
+                       cell-id = <MSM_BUS_SLAVE_QDSS_STM>;
+                       label = "slv-qdss-stm";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_STM>;
+               };
+
+               slv_srvc_snoc:slv-srvc-snoc {
+                       cell-id = <MSM_BUS_SLAVE_SRVC_SNOC>;
+                       label = "slv-srvc-snoc";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_SRVC_SNOC>;
+               };
+       };
+};
+
+};
diff --git a/target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4019-fritz4040.dts b/target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4019-fritz4040.dts
new file mode 100644 (file)
index 0000000..f5ca3d5
--- /dev/null
@@ -0,0 +1,322 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+#include "qcom-ipq4019-bus.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+       model = "AVM FRITZ!Box 4040";
+       compatible = "avm,fritzbox-4040", "qcom,ipq4019";
+
+       aliases {
+               led-boot = &power;
+               led-failsafe = &flash;
+               led-running = &power;
+               led-upgrade = &flash;
+       };
+
+       reserved-memory {
+               #address-cells = <0x1>;
+               #size-cells = <0x1>;
+               ranges;
+
+               tz_apps@87b80000 {
+                       reg = <0x87b80000 0x280000>;
+                       reusable;
+               };
+
+               smem@87e00000 {
+                       reg = <0x87e00000 0x080000>;
+                       no-map;
+               };
+
+               tz@87e80000 {
+                       reg = <0x87e80000 0x180000>;
+                       no-map;
+               };
+       };
+
+       soc {
+               mdio@90000 {
+                       status = "okay";
+               };
+
+               ess-psgmii@98000 {
+                       status = "okay";
+               };
+
+               tcsr@1949000 {
+                       compatible = "qcom,tcsr";
+                       reg = <0x1949000 0x100>;
+                       qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+               };
+
+               tcsr@194b000 {
+                       compatible = "qcom,tcsr";
+                       reg = <0x194b000 0x100>;
+                       qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+               };
+
+               ess_tcsr@1953000 {
+                       compatible = "qcom,tcsr";
+                       reg = <0x1953000 0x1000>;
+                       qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+               };
+
+               tcsr@1957000 {
+                       compatible = "qcom,tcsr";
+                       reg = <0x1957000 0x100>;
+                       qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+               };
+
+               usb2@60f8800 {
+                       status = "ok";
+               };
+
+               serial@78af000 {
+                       pinctrl-0 = <&serial_pins>;
+                       pinctrl-names = "default";
+                       status = "ok";
+               };
+
+               usb3@8af8800 {
+                       status = "ok";
+               };
+
+               crypto@8e3a000 {
+                       status = "ok";
+               };
+
+               wifi@a000000 {
+                       status = "okay";
+               };
+
+               wifi@a800000 {
+                       status = "okay";
+               };
+
+               watchdog@b017000 {
+                       status = "ok";
+               };
+
+               qca8075: ess-switch@c000000 {
+                       status = "okay";
+
+                       #gpio-cells = <2>;
+                       gpio-controller;
+
+                       enable-usb-power {
+                               gpio-hog;
+                               line-name = "enable USB3 power";
+                               gpios = <7 GPIO_ACTIVE_HIGH>;
+                               output-high;
+                       };
+               };
+
+               edma@c080000 {
+                       status = "okay";
+               };
+       };
+
+       gpio-keys {
+               compatible = "gpio-keys";
+
+               wlan {
+                       label = "wlan";
+                       gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_RFKILL>;
+               };
+
+               wps {
+                       label = "wps";
+                       gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_WPS_BUTTON>;
+               };
+       };
+
+       gpio-leds {
+               compatible = "gpio-leds";
+
+               wlan {
+                       label = "fritz4040:green:wlan";
+                       gpios = <&qca8075 1 GPIO_ACTIVE_HIGH>;
+               };
+
+               panic: info_red {
+                       label = "fritz4040:red:info";
+                       gpios = <&qca8075 3 GPIO_ACTIVE_HIGH>;
+                       panic-indicator;
+               };
+
+               wan {
+                       label = "fritz4040:green:wan";
+                       gpios = <&qca8075 5 GPIO_ACTIVE_HIGH>;
+               };
+
+               power: power {
+                       label = "fritz4040:green:power";
+                       gpios = <&qca8075 11 GPIO_ACTIVE_HIGH>;
+               };
+
+               lan {
+                       label = "fritz4040:green:lan";
+                       gpios = <&qca8075 13 GPIO_ACTIVE_HIGH>;
+               };
+
+               flash: info_amber {
+                       label = "fritz4040:amber:info";
+                       gpios = <&qca8075 15 GPIO_ACTIVE_HIGH>;
+               };
+       };
+};
+
+&tlmm {
+       serial_pins: serial_pinmux {
+               mux {
+                       pins = "gpio60", "gpio61";
+                       function = "blsp_uart0";
+                       bias-disable;
+               };
+       };
+
+       spi_0_pins: spi_0_pinmux {
+               mux {
+                       function = "blsp_spi0";
+                       pins = "gpio55", "gpio56", "gpio57";
+                       drive-strength = <12>;
+                       bias-disable;
+               };
+
+               mux_cs {
+                       function = "gpio";
+                       pins = "gpio54";
+                       drive-strength = <2>;
+                       bias-disable;
+                       output-high;
+               };
+       };
+};
+
+&cryptobam {
+       status = "ok";
+};
+
+&blsp_dma {
+       status = "ok";
+};
+
+&spi_0 { /* BLSP1 QUP1 */
+       pinctrl-0 = <&spi_0_pins>;
+       pinctrl-names = "default";
+       status = "ok";
+       cs-gpios = <&tlmm 54 0>;
+
+       mx25l25635f@0 {
+               compatible = "jedec,spi-nor";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <0>;
+               spi-max-frequency = <24000000>;
+               status = "ok";
+               m25p,fast-read;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition0@0 {
+                               label = "SBL1";
+                               reg = <0x00000000 0x00040000>;
+                               read-only;
+                       };
+                       partition1@40000 {
+                               label = "MIBIB";
+                               reg = <0x00040000 0x00020000>;
+                               read-only;
+                       };
+                       partition2@60000 {
+                               label = "QSEE";
+                               reg = <0x00060000 0x00060000>;
+                               read-only;
+                       };
+                       partition3@c0000 {
+                               label = "CDT";
+                               reg = <0x000c0000 0x00010000>;
+                               read-only;
+                       };
+                       partition4@d0000 {
+                               label = "DDRPARAMS";
+                               reg = <0x000d0000 0x00010000>;
+                               read-only;
+                       };
+                       partition5@e0000 {
+                               label = "APPSBLENV"; /* uboot env - empty */
+                               reg = <0x000e0000 0x00010000>;
+                               read-only;
+                       };
+                       partition6@f0000 {
+                               label = "urlader"; /* APPSBL */
+                               reg = <0x000f0000 0x0002dc000>;
+                               read-only;
+                       };
+                       partition7@11dc00 {
+                               /* make a backup of this partition! */
+                               label = "urlader_config";
+                               reg = <0x0011dc00 0x00002400>;
+                               read-only;
+                       };
+                       partition8@120000 {
+                               label = "tffs1";
+                               reg = <0x00120000 0x00080000>;
+                               read-only;
+                       };
+                       partition9@1a0000 {
+                               label = "tffs2";
+                               reg = <0x001a0000 0x00080000>;
+                               read-only;
+                       };
+                       partition10@220000 {
+                               label = "uboot";
+                               reg = <0x00220000 0x00080000>;
+                               read-only;
+                       };
+                       partition11@2A0000 {
+                               label = "firmware";
+                               reg = <0x002a0000 0x01c60000>;
+                       };
+                       partition12@1f00000 {
+                               label = "jffs2";
+                               reg = <0x01f00000 0x00100000>;
+                       };
+               };
+       };
+};
+
+&usb3_ss_phy {
+       status = "ok";
+};
+
+&usb3_hs_phy {
+       status = "ok";
+};
+
+&usb2_hs_phy {
+       status = "ok";
+};
diff --git a/target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4019-gl-b1300.dts b/target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4019-gl-b1300.dts
new file mode 100644 (file)
index 0000000..53824e3
--- /dev/null
@@ -0,0 +1,316 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+       model = "GL.iNet GL-B1300";
+       compatible = "glinet,gl-b1300", "qcom,ipq4019";
+
+       memory {
+               device_type = "memory";
+               reg = <0x80000000 0x10000000>;
+       };
+
+       reserved-memory {
+               #address-cells = <0x1>;
+               #size-cells = <0x1>;
+               ranges;
+
+               apps_bl@87000000 {
+                       reg = <0x87000000 0x400000>;
+                       no-map;
+               };
+
+               sbl@87400000 {
+                       reg = <0x87400000 0x100000>;
+                       no-map;
+               };
+
+               cnss_debug@87500000 {
+                       reg = <0x87500000 0x600000>;
+                       no-map;
+               };
+
+               cpu_context_dump@87b00000 {
+                       reg = <0x87b00000 0x080000>;
+                       no-map;
+               };
+
+               tz_apps@87b80000 {
+                       reg = <0x87b80000 0x280000>;
+                       no-map;
+               };
+
+               smem@87e00000 {
+                       reg = <0x87e00000 0x080000>;
+                       no-map;
+               };
+
+               tz@87e80000 {
+                       reg = <0x87e80000 0x180000>;
+                       no-map;
+               };
+       };
+
+       soc {
+               tcsr@194b000 {
+                       /* select hostmode */
+                       compatible = "qcom,tcsr";
+                       reg = <0x194b000 0x100>;
+                       qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+                       status = "ok";
+               };
+
+               ess_tcsr@1953000 {
+                       compatible = "qcom,tcsr";
+                       reg = <0x1953000 0x1000>;
+                       qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+               };
+
+               tcsr@1949000 {
+                       compatible = "qcom,tcsr";
+                       reg = <0x1949000 0x100>;
+                       qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+               };
+
+               tcsr@1957000 {
+                       compatible = "qcom,tcsr";
+                       reg = <0x1957000 0x100>;
+                       qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+               };
+
+               pinctrl@1000000 {
+                       serial_pins: serial_pinmux {
+                               mux {
+                                       pins = "gpio60", "gpio61";
+                                       function = "blsp_uart0";
+                                       bias-disable;
+                               };
+                       };
+
+                       spi_0_pins: spi_0_pinmux {
+                               pinmux {
+                                       function = "blsp_spi0";
+                                       pins = "gpio55", "gpio56", "gpio57";
+                               };
+                               pinmux_cs {
+                                       function = "gpio";
+                                       pins = "gpio54";
+                               };
+                               pinconf {
+                                       pins = "gpio55", "gpio56", "gpio57";
+                                       drive-strength = <12>;
+                                       bias-disable;
+                               };
+                               pinconf_cs {
+                                       pins = "gpio54";
+                                       drive-strength = <2>;
+                                       bias-disable;
+                                       output-high;
+                               };
+                       };
+               };
+
+               blsp_dma: dma@7884000 {
+                       status = "ok";
+               };
+
+               spi_0: spi@78b5000 {
+                       pinctrl-0 = <&spi_0_pins>;
+                       pinctrl-names = "default";
+                       status = "ok";
+                       cs-gpios = <&tlmm 54 0>;
+               };
+
+               serial@78af000 {
+                       pinctrl-0 = <&serial_pins>;
+                       pinctrl-names = "default";
+                       status = "ok";
+               };
+
+               cryptobam: dma@8e04000 {
+                       status = "ok";
+               };
+
+               crypto@8e3a000 {
+                       status = "ok";
+               };
+
+               watchdog@b017000 {
+                       status = "ok";
+               };
+
+               usb3_ss_phy: ssphy@9a000 {
+                       status = "ok";
+               };
+
+               usb3_hs_phy: hsphy@a6000 {
+                       status = "ok";
+               };
+
+               usb3: usb3@8af8800 {
+                       status = "ok";
+               };
+
+               usb2_hs_phy: hsphy@a8000 {
+                       status = "ok";
+               };
+
+               usb2: usb2@60f8800 {
+                       status = "ok";
+               };
+
+               mdio@90000 {
+                       status = "okay";
+               };
+
+               ess-switch@c000000 {
+                       status = "okay";
+               };
+
+               ess-psgmii@98000 {
+                       status = "okay";
+               };
+
+               edma@c080000 {
+                       status = "okay";
+               };
+
+               wifi@a000000 {
+                       status = "okay";
+               };
+
+               wifi@a800000 {
+                       status = "okay";
+               };
+       };
+
+       gpio-keys {
+               compatible = "gpio-keys";
+
+               wps {
+                       label = "wps";
+                       gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_WPS_BUTTON>;
+               };
+               reset {
+                       label = "reset";
+                       gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_RESTART>;
+               };
+       };
+
+       gpio-leds {
+               compatible = "gpio-leds";
+
+               power {
+                       label = "gl-b1300:green:power";
+                       gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
+                       default-state = "on";
+               };
+               mesh {
+                       label = "gl-b1300:green:mesh";
+                       gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+               };
+               wlan {
+                       label = "gl-b1300:green:wlan";
+                       gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
+               };
+       };
+};
+
+&spi_0 {
+       mx25l25635f@0 {
+               compatible = "mx25l25635f", "jedec,spi-nor";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               reg = <0>;
+               spi-max-frequency = <24000000>;
+
+               SBL1@0 {
+                       label = "SBL1";
+                       reg = <0x0 0x40000>;
+                       read-only;
+               };
+               MIBIB@40000 {
+                       label = "MIBIB";
+                       reg = <0x40000 0x20000>;
+                       read-only;
+               };
+               QSEE@60000 {
+                       label = "QSEE";
+                       reg = <0x60000 0x60000>;
+                       read-only;
+               };
+               CDT@c0000 {
+                       label = "CDT";
+                       reg = <0xc0000 0x10000>;
+                       read-only;
+               };
+               DDRPARAMS@d0000 {
+                       label = "DDRPARAMS";
+                       reg = <0xd0000 0x10000>;
+                       read-only;
+               };
+               APPSBLENV@e0000 {
+                       label = "APPSBLENV";
+                       reg = <0xe0000 0x10000>;
+                       read-only;
+               };
+               APPSBL@f0000 {
+                       label = "APPSBL";
+                       reg = <0xf0000 0x80000>;
+                       read-only;
+               };
+               ART@170000 {
+                       label = "ART";
+                       reg = <0x170000 0x10000>;
+                       read-only;
+               };
+               kernel@180000 {
+                       label = "kernel";
+                       reg = <0x180000 0x400000>;
+               };
+               rootfs@580000 {
+                       label = "rootfs";
+                       reg = <0x580000 0x1a80000>;
+               };
+               firmware@180000 {
+                       label = "firmware";
+                       reg = <0x180000 0x1e80000>;
+               };
+       };
+};
+
+&gmac0 {
+       qcom,phy_mdio_addr = <4>;
+       qcom,poll_required = <1>;
+       qcom,forced_speed = <1000>;
+       qcom,forced_duplex = <1>;
+       vlan_tag = <2 0x20>;
+};
+
+&gmac1 {
+       qcom,phy_mdio_addr = <3>;
+       qcom,poll_required = <1>;
+       qcom,forced_speed = <1000>;
+       qcom,forced_duplex = <1>;
+       vlan_tag = <1 0x10>;
+};
\ No newline at end of file
diff --git a/target/linux/ipq40xx/image/Makefile b/target/linux/ipq40xx/image/Makefile
new file mode 100644 (file)
index 0000000..e584b6f
--- /dev/null
@@ -0,0 +1,104 @@
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/image.mk
+
+define Device/Default
+       PROFILES := Default
+       KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)
+       KERNEL_INITRAMFS_PREFIX := $$(IMG_PREFIX)-$(1)-initramfs
+       KERNEL_PREFIX := $$(IMAGE_PREFIX)
+       KERNEL_LOADADDR := 0x80208000
+       SUPPORTED_DEVICES := $(subst _,$(comma),$(1))
+       IMAGE/sysupgrade.bin = sysupgrade-tar | append-metadata
+       IMAGE/sysupgrade.bin/squashfs :=
+endef
+
+define Device/FitImage
+       KERNEL_SUFFIX := -fit-uImage.itb
+       KERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb
+       KERNEL_NAME := Image
+endef
+
+define Device/FitImageLzma
+       KERNEL_SUFFIX := -fit-uImage.itb
+       KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb
+       KERNEL_NAME := Image
+endef
+
+define Device/UbiFit
+       KERNEL_IN_UBI := 1
+       IMAGES := nand-factory.ubi nand-sysupgrade.bin
+       IMAGE/nand-factory.ubi := append-ubi
+       IMAGE/nand-sysupgrade.bin := sysupgrade-tar | append-metadata
+endef
+
+define Device/avm_fritzbox-4040
+       $(call Device/FitImageLzma)
+       DEVICE_DTS := qcom-ipq4019-fritz4040
+       BLOCKSIZE := 4k
+       PAGESIZE := 256
+       BOARD_NAME := fritz4040
+       DEVICE_TITLE := AVM Fritz!Box 4040
+       IMAGE_SIZE := 29753344
+       IMAGES = sysupgrade.bin
+       IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
+       DEVICE_PACKAGES := ipq-wifi-avm_fritzbox-4040 fritz-tffs fritz-caldata u-boot-fritz4040
+endef
+TARGET_DEVICES += avm_fritzbox-4040
+
+define Device/glinet_gl-b1300
+       DEVICE_TITLE := GL.iNet GL-B1300
+       BOARD_NAME := gl-b1300
+       DEVICE_DTS := qcom-ipq4019-gl-b1300
+       KERNEL_INSTALL := 1
+       KERNEL_SIZE := 4096k
+       IMAGE_SIZE := 26624k
+       $(call Device/FitImage)
+       IMAGES := sysupgrade.bin
+       IMAGE/sysupgrade.bin := append-kernel | pad-to $$$${KERNEL_SIZE} | append-rootfs | pad-rootfs | append-metadata
+       DEVICE_PACKAGES := ipq-wifi-glinet_gl-b1300
+endef
+TARGET_DEVICES += glinet_gl-b1300
+
+define Device/openmesh_a42
+       $(call Device/FitImageLzma)
+       DEVICE_DTS := qcom-ipq4019-a42
+       BLOCKSIZE := 64k
+       SUPPORTED_DEVICES := openmesh,a42
+       DEVICE_TITLE := OpenMesh A42
+       KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb | pad-to $$(BLOCKSIZE)
+       IMAGE_SIZE := 15616k
+       IMAGES = factory.bin sysupgrade.bin
+       IMAGE/factory.bin := append-rootfs | pad-rootfs | openmesh-image ce_type=A42
+       IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-rootfs | sysupgrade-tar rootfs=$$$$@ | append-metadata
+       DEVICE_PACKAGES := ath10k-firmware-qca4019 uboot-envtools
+endef
+TARGET_DEVICES += openmesh_a42
+
+define Device/qcom_ap-dk01.1-c1
+       DEVICE_TITLE := QCA AP-DK01.1-C1
+       BOARD_NAME := ap-dk01.1-c1
+       DEVICE_DTS := qcom-ipq4019-ap.dk01.1-c1
+       KERNEL_INSTALL := 1
+       KERNEL_SIZE := 4096k
+       IMAGE_SIZE := 26624k
+       $(call Device/FitImage)
+       IMAGES := sysupgrade.bin
+       IMAGE/sysupgrade.bin := append-kernel | pad-to $$$${KERNEL_SIZE} | append-rootfs | pad-rootfs | append-metadata
+       DEVICE_PACKAGES := ath10k-firmware-qca4019
+endef
+TARGET_DEVICES += qcom_ap-dk01.1-c1
+
+define Device/qcom_ap-dk04.1-c1
+       $(call Device/FitImage)
+       $(call Device/UbiFit)
+       DEVICE_DTS := qcom-ipq4019-ap.dk04.1-c1
+       KERNEL_INSTALL := 1
+       KERNEL_SIZE := 4048k
+       BLOCKSIZE := 128k
+       PAGESIZE := 2048
+       BOARD_NAME := ap-dk04.1-c1
+       DEVICE_TITLE := QCA AP-DK04.1-C1
+endef
+TARGET_DEVICES += qcom_ap-dk04.1-c1
+
+$(eval $(call BuildImage))
diff --git a/target/linux/ipq40xx/modules.mk b/target/linux/ipq40xx/modules.mk
new file mode 100644 (file)
index 0000000..43f3c9c
--- /dev/null
@@ -0,0 +1,33 @@
+define KernelPackage/usb-dwc3-of-simple
+  TITLE:=DWC3 USB simple OF driver
+  DEPENDS:=+kmod-usb-dwc3
+  KCONFIG:= CONFIG_USB_DWC3_OF_SIMPLE
+  FILES:= $(LINUX_DIR)/drivers/usb/dwc3/dwc3-of-simple.ko
+  AUTOLOAD:=$(call AutoLoad,53,dwc3-of-simple,1)
+  $(call AddDepends/usb)
+endef
+
+define KernelPackage/usb-dwc3-of-simple/description
+ This driver provides generic platform glue for the integrated DesignWare
+ USB3 IP Core.
+endef
+
+$(eval $(call KernelPackage,usb-dwc3-of-simple))
+
+define KernelPackage/usb-phy-qcom-dwc3
+  TITLE:=DWC3 USB QCOM PHY driver
+  DEPENDS:=@TARGET_ipq806x +kmod-usb-dwc3-of-simple
+  KCONFIG:= CONFIG_PHY_QCOM_DWC3
+  FILES:= \
+    $(LINUX_DIR)/drivers/phy/phy-qcom-dwc3.ko@lt4.13 \
+    $(LINUX_DIR)/drivers/phy/qualcomm/phy-qcom-dwc3.ko@ge4.13
+  AUTOLOAD:=$(call AutoLoad,45,phy-qcom-dwc3,1)
+  $(call AddDepends/usb)
+endef
+
+define KernelPackage/usb-phy-qcom-dwc3/description
+ This driver provides support for the integrated DesignWare
+ USB3 IP Core within the QCOM SoCs.
+endef
+
+$(eval $(call KernelPackage,usb-phy-qcom-dwc3))
diff --git a/target/linux/ipq40xx/patches-4.14/017-qcom-ipq4019-add-cpu-operating-points-for-cpufreq-su.patch b/target/linux/ipq40xx/patches-4.14/017-qcom-ipq4019-add-cpu-operating-points-for-cpufreq-su.patch
new file mode 100644 (file)
index 0000000..138a2dd
--- /dev/null
@@ -0,0 +1,77 @@
+From 18c3b42575a154343831aec0637aab00e19440e1 Mon Sep 17 00:00:00 2001
+From: Matthew McClintock <mmcclint@codeaurora.org>
+Date: Thu, 17 Mar 2016 15:01:09 -0500
+Subject: [PATCH 17/69] qcom: ipq4019: add cpu operating points for cpufreq
+ support
+
+This adds some operating points for cpu frequeny scaling
+
+Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 34 ++++++++++++++++++++++++++--------
+ 1 file changed, 26 insertions(+), 8 deletions(-)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -40,14 +40,7 @@
+                       reg = <0x0>;
+                       clocks = <&gcc GCC_APPS_CLK_SRC>;
+                       clock-frequency = <0>;
+-                      operating-points = <
+-                              /* kHz  uV (fixed) */
+-                              48000   1100000
+-                              200000  1100000
+-                              500000  1100000
+-                              666000  1100000
+-                      >;
+-                      clock-latency = <256000>;
++                      operating-points-v2 = <&cpu0_opp_table>;
+               };
+               cpu@1 {
+@@ -59,6 +52,7 @@
+                       reg = <0x1>;
+                       clocks = <&gcc GCC_APPS_CLK_SRC>;
+                       clock-frequency = <0>;
++                      operating-points-v2 = <&cpu0_opp_table>;
+               };
+               cpu@2 {
+@@ -70,6 +64,7 @@
+                       reg = <0x2>;
+                       clocks = <&gcc GCC_APPS_CLK_SRC>;
+                       clock-frequency = <0>;
++                      operating-points-v2 = <&cpu0_opp_table>;
+               };
+               cpu@3 {
+@@ -81,6 +76,29 @@
+                       reg = <0x3>;
+                       clocks = <&gcc GCC_APPS_CLK_SRC>;
+                       clock-frequency = <0>;
++                      operating-points-v2 = <&cpu0_opp_table>;
++              };
++      };
++
++      cpu0_opp_table: opp_table0 {
++              compatible = "operating-points-v2";
++              opp-shared;
++
++              opp-48000000 {
++                      opp-hz = /bits/ 64 <48000000>;
++                      clock-latency-ns = <256000>;
++              };
++              opp-200000000 {
++                      opp-hz = /bits/ 64 <200000000>;
++                      clock-latency-ns = <256000>;
++              };
++              opp-500000000 {
++                      opp-hz = /bits/ 64 <500000000>;
++                      clock-latency-ns = <256000>;
++              };
++              opp-716800000 {
++                      opp-hz = /bits/ 64 <716800000>;
++                      clock-latency-ns = <256000>;
+               };
+       };
diff --git a/target/linux/ipq40xx/patches-4.14/030-mtd-nand-Use-standard-large-page-OOB-layout-when-usi.patch b/target/linux/ipq40xx/patches-4.14/030-mtd-nand-Use-standard-large-page-OOB-layout-when-usi.patch
new file mode 100644 (file)
index 0000000..479a890
--- /dev/null
@@ -0,0 +1,47 @@
+From 882fd1577cbe7812ae3a48988180c5f0fda475ca Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal@free-electrons.com>
+Date: Sat, 26 Aug 2017 17:19:15 +0200
+Subject: [PATCH] mtd: nand: Use standard large page OOB layout when using
+ NAND_ECC_NONE
+
+Use the core's large page OOB layout functions when not reserving any
+space for ECC bytes in the OOB layout. Fix ->nand_ooblayout_ecc_lp()
+to return -ERANGE instead of a zero length in this case.
+
+Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
+Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
+---
+ drivers/mtd/nand/nand_base.c | 15 ++++++++++++++-
+ 1 file changed, 14 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/nand/nand_base.c
++++ b/drivers/mtd/nand/nand_base.c
+@@ -115,7 +115,7 @@ static int nand_ooblayout_ecc_lp(struct
+       struct nand_chip *chip = mtd_to_nand(mtd);
+       struct nand_ecc_ctrl *ecc = &chip->ecc;
+-      if (section)
++      if (section || !ecc->total)
+               return -ERANGE;
+       oobregion->length = ecc->total;
+@@ -4707,6 +4707,19 @@ int nand_scan_tail(struct mtd_info *mtd)
+                       mtd_set_ooblayout(mtd, &nand_ooblayout_lp_hamming_ops);
+                       break;
+               default:
++                      /*
++                       * Expose the whole OOB area to users if ECC_NONE
++                       * is passed. We could do that for all kind of
++                       * ->oobsize, but we must keep the old large/small
++                       * page with ECC layout when ->oobsize <= 128 for
++                       * compatibility reasons.
++                       */
++                      if (ecc->mode == NAND_ECC_NONE) {
++                              mtd_set_ooblayout(mtd,
++                                              &nand_ooblayout_lp_ops);
++                              break;
++                      }
++
+                       WARN(1, "No oob scheme defined for oobsize %d\n",
+                               mtd->oobsize);
+                       ret = -EINVAL;
diff --git a/target/linux/ipq40xx/patches-4.14/031-mtd-nand-use-usual-return-values-for-the-erase-hook.patch b/target/linux/ipq40xx/patches-4.14/031-mtd-nand-use-usual-return-values-for-the-erase-hook.patch
new file mode 100644 (file)
index 0000000..67ffb19
--- /dev/null
@@ -0,0 +1,48 @@
+From eb94555e9e97c9983461214046b4d72c4ab4ba70 Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal@free-electrons.com>
+Date: Thu, 30 Nov 2017 18:01:28 +0100
+Subject: [PATCH] mtd: nand: use usual return values for the ->erase() hook
+
+Avoid using specific defined values for checking returned status of the
+->erase() hook. Instead, use usual negative error values on failure,
+zero otherwise.
+
+Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
+Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
+---
+ drivers/mtd/nand/denali.c    |  2 +-
+ drivers/mtd/nand/docg4.c     |  7 ++++++-
+ drivers/mtd/nand/nand_base.c | 10 ++++++++--
+ 3 files changed, 15 insertions(+), 4 deletions(-)
+
+--- a/drivers/mtd/nand/nand_base.c
++++ b/drivers/mtd/nand/nand_base.c
+@@ -2989,11 +2989,17 @@ out:
+ static int single_erase(struct mtd_info *mtd, int page)
+ {
+       struct nand_chip *chip = mtd_to_nand(mtd);
++      int status;
++
+       /* Send commands to erase a block */
+       chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
+       chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
+-      return chip->waitfunc(mtd, chip);
++      status = chip->waitfunc(mtd, chip);
++      if (status < 0)
++              return status;
++
++      return status & NAND_STATUS_FAIL ? -EIO : 0;
+ }
+ /**
+@@ -3077,7 +3083,7 @@ int nand_erase_nand(struct mtd_info *mtd
+               status = chip->erase(mtd, page & chip->pagemask);
+               /* See if block erase succeeded */
+-              if (status & NAND_STATUS_FAIL) {
++              if (status) {
+                       pr_debug("%s: failed erase, page 0x%08x\n",
+                                       __func__, page);
+                       instr->state = MTD_ERASE_FAILED;
diff --git a/target/linux/ipq40xx/patches-4.14/040-dmaengine-qcom-bam-Process-multiple-pending-descript.patch b/target/linux/ipq40xx/patches-4.14/040-dmaengine-qcom-bam-Process-multiple-pending-descript.patch
new file mode 100644 (file)
index 0000000..dca516e
--- /dev/null
@@ -0,0 +1,395 @@
+From 6b4faeac05bc0b91616b921191cb054d1376f3b4 Mon Sep 17 00:00:00 2001
+From: Sricharan R <sricharan@codeaurora.org>
+Date: Mon, 28 Aug 2017 20:30:24 +0530
+Subject: [PATCH] dmaengine: qcom-bam: Process multiple pending descriptors
+
+The bam dmaengine has a circular FIFO to which we
+add hw descriptors that describes the transaction.
+The FIFO has space for about 4096 hw descriptors.
+
+Currently we add one descriptor and wait for it to
+complete with interrupt and then add the next pending
+descriptor. In this way, the FIFO is underutilized
+since only one descriptor is processed at a time, although
+there is space in FIFO for the BAM to process more.
+
+Instead keep adding descriptors to FIFO till its full,
+that allows BAM to continue to work on the next descriptor
+immediately after signalling completion interrupt for the
+previous descriptor.
+
+Also when the client has not set the DMA_PREP_INTERRUPT for
+a descriptor, then do not configure BAM to trigger a interrupt
+upon completion of that descriptor. This way we get a interrupt
+only for the descriptor for which DMA_PREP_INTERRUPT was
+requested and there signal completion of all the previous completed
+descriptors. So we still do callbacks for all requested descriptors,
+but just that the number of interrupts are reduced.
+
+CURRENT:
+
+            ------      -------   ---------------
+            |DES 0|     |DESC 1|  |DESC 2 + INT |
+            ------      -------   ---------------
+               |           |            |
+               |           |            |
+INTERRUPT:   (INT)       (INT)       (INT)
+CALLBACK:     (CB)        (CB)         (CB)
+
+               MTD_SPEEDTEST READ PAGE: 3560 KiB/s
+               MTD_SPEEDTEST WRITE PAGE: 2664 KiB/s
+               IOZONE READ: 2456 KB/s
+               IOZONE WRITE: 1230 KB/s
+
+       bam dma interrupts (after tests): 96508
+
+CHANGE:
+
+        ------  -------    -------------
+        |DES 0| |DESC 1   |DESC 2 + INT |
+        ------  -------   --------------
+                               |
+                               |
+                             (INT)
+                             (CB for 0, 1, 2)
+
+               MTD_SPEEDTEST READ PAGE: 3860 KiB/s
+               MTD_SPEEDTEST WRITE PAGE: 2837 KiB/s
+               IOZONE READ: 2677 KB/s
+               IOZONE WRITE: 1308 KB/s
+
+       bam dma interrupts (after tests): 58806
+
+Signed-off-by: Sricharan R <sricharan@codeaurora.org>
+Reviewed-by: Andy Gross <andy.gross@linaro.org>
+Tested-by: Abhishek Sahu <absahu@codeaurora.org>
+Signed-off-by: Vinod Koul <vinod.koul@intel.com>
+---
+ drivers/dma/qcom/bam_dma.c | 169 +++++++++++++++++++++++++++++----------------
+ 1 file changed, 109 insertions(+), 60 deletions(-)
+
+--- a/drivers/dma/qcom/bam_dma.c
++++ b/drivers/dma/qcom/bam_dma.c
+@@ -46,6 +46,7 @@
+ #include <linux/of_address.h>
+ #include <linux/of_irq.h>
+ #include <linux/of_dma.h>
++#include <linux/circ_buf.h>
+ #include <linux/clk.h>
+ #include <linux/dmaengine.h>
+ #include <linux/pm_runtime.h>
+@@ -78,6 +79,8 @@ struct bam_async_desc {
+       struct bam_desc_hw *curr_desc;
++      /* list node for the desc in the bam_chan list of descriptors */
++      struct list_head desc_node;
+       enum dma_transfer_direction dir;
+       size_t length;
+       struct bam_desc_hw desc[0];
+@@ -347,6 +350,8 @@ static const struct reg_offset_data bam_
+ #define BAM_DESC_FIFO_SIZE    SZ_32K
+ #define MAX_DESCRIPTORS (BAM_DESC_FIFO_SIZE / sizeof(struct bam_desc_hw) - 1)
+ #define BAM_FIFO_SIZE (SZ_32K - 8)
++#define IS_BUSY(chan) (CIRC_SPACE(bchan->tail, bchan->head,\
++                       MAX_DESCRIPTORS + 1) == 0)
+ struct bam_chan {
+       struct virt_dma_chan vc;
+@@ -356,8 +361,6 @@ struct bam_chan {
+       /* configuration from device tree */
+       u32 id;
+-      struct bam_async_desc *curr_txd;        /* current running dma */
+-
+       /* runtime configuration */
+       struct dma_slave_config slave;
+@@ -372,6 +375,8 @@ struct bam_chan {
+       unsigned int initialized;       /* is the channel hw initialized? */
+       unsigned int paused;            /* is the channel paused? */
+       unsigned int reconfigure;       /* new slave config? */
++      /* list of descriptors currently processed */
++      struct list_head desc_list;
+       struct list_head node;
+ };
+@@ -539,7 +544,7 @@ static void bam_free_chan(struct dma_cha
+       vchan_free_chan_resources(to_virt_chan(chan));
+-      if (bchan->curr_txd) {
++      if (!list_empty(&bchan->desc_list)) {
+               dev_err(bchan->bdev->dev, "Cannot free busy channel\n");
+               goto err;
+       }
+@@ -632,8 +637,6 @@ static struct dma_async_tx_descriptor *b
+       if (flags & DMA_PREP_INTERRUPT)
+               async_desc->flags |= DESC_FLAG_EOT;
+-      else
+-              async_desc->flags |= DESC_FLAG_INT;
+       async_desc->num_desc = num_alloc;
+       async_desc->curr_desc = async_desc->desc;
+@@ -684,14 +687,16 @@ err_out:
+ static int bam_dma_terminate_all(struct dma_chan *chan)
+ {
+       struct bam_chan *bchan = to_bam_chan(chan);
++      struct bam_async_desc *async_desc, *tmp;
+       unsigned long flag;
+       LIST_HEAD(head);
+       /* remove all transactions, including active transaction */
+       spin_lock_irqsave(&bchan->vc.lock, flag);
+-      if (bchan->curr_txd) {
+-              list_add(&bchan->curr_txd->vd.node, &bchan->vc.desc_issued);
+-              bchan->curr_txd = NULL;
++      list_for_each_entry_safe(async_desc, tmp,
++                               &bchan->desc_list, desc_node) {
++              list_add(&async_desc->vd.node, &bchan->vc.desc_issued);
++              list_del(&async_desc->desc_node);
+       }
+       vchan_get_all_descriptors(&bchan->vc, &head);
+@@ -763,9 +768,9 @@ static int bam_resume(struct dma_chan *c
+  */
+ static u32 process_channel_irqs(struct bam_device *bdev)
+ {
+-      u32 i, srcs, pipe_stts;
++      u32 i, srcs, pipe_stts, offset, avail;
+       unsigned long flags;
+-      struct bam_async_desc *async_desc;
++      struct bam_async_desc *async_desc, *tmp;
+       srcs = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_EE));
+@@ -785,27 +790,40 @@ static u32 process_channel_irqs(struct b
+               writel_relaxed(pipe_stts, bam_addr(bdev, i, BAM_P_IRQ_CLR));
+               spin_lock_irqsave(&bchan->vc.lock, flags);
+-              async_desc = bchan->curr_txd;
+-              if (async_desc) {
+-                      async_desc->num_desc -= async_desc->xfer_len;
+-                      async_desc->curr_desc += async_desc->xfer_len;
+-                      bchan->curr_txd = NULL;
++              offset = readl_relaxed(bam_addr(bdev, i, BAM_P_SW_OFSTS)) &
++                                     P_SW_OFSTS_MASK;
++              offset /= sizeof(struct bam_desc_hw);
++
++              /* Number of bytes available to read */
++              avail = CIRC_CNT(offset, bchan->head, MAX_DESCRIPTORS + 1);
++
++              list_for_each_entry_safe(async_desc, tmp,
++                                       &bchan->desc_list, desc_node) {
++                      /* Not enough data to read */
++                      if (avail < async_desc->xfer_len)
++                              break;
+                       /* manage FIFO */
+                       bchan->head += async_desc->xfer_len;
+                       bchan->head %= MAX_DESCRIPTORS;
++                      async_desc->num_desc -= async_desc->xfer_len;
++                      async_desc->curr_desc += async_desc->xfer_len;
++                      avail -= async_desc->xfer_len;
++
+                       /*
+-                       * if complete, process cookie.  Otherwise
++                       * if complete, process cookie. Otherwise
+                        * push back to front of desc_issued so that
+                        * it gets restarted by the tasklet
+                        */
+-                      if (!async_desc->num_desc)
++                      if (!async_desc->num_desc) {
+                               vchan_cookie_complete(&async_desc->vd);
+-                      else
++                      } else {
+                               list_add(&async_desc->vd.node,
+-                                      &bchan->vc.desc_issued);
++                                       &bchan->vc.desc_issued);
++                      }
++                      list_del(&async_desc->desc_node);
+               }
+               spin_unlock_irqrestore(&bchan->vc.lock, flags);
+@@ -867,6 +885,7 @@ static enum dma_status bam_tx_status(str
+               struct dma_tx_state *txstate)
+ {
+       struct bam_chan *bchan = to_bam_chan(chan);
++      struct bam_async_desc *async_desc;
+       struct virt_dma_desc *vd;
+       int ret;
+       size_t residue = 0;
+@@ -882,11 +901,17 @@ static enum dma_status bam_tx_status(str
+       spin_lock_irqsave(&bchan->vc.lock, flags);
+       vd = vchan_find_desc(&bchan->vc, cookie);
+-      if (vd)
++      if (vd) {
+               residue = container_of(vd, struct bam_async_desc, vd)->length;
+-      else if (bchan->curr_txd && bchan->curr_txd->vd.tx.cookie == cookie)
+-              for (i = 0; i < bchan->curr_txd->num_desc; i++)
+-                      residue += bchan->curr_txd->curr_desc[i].size;
++      } else {
++              list_for_each_entry(async_desc, &bchan->desc_list, desc_node) {
++                      if (async_desc->vd.tx.cookie != cookie)
++                              continue;
++
++                      for (i = 0; i < async_desc->num_desc; i++)
++                              residue += async_desc->curr_desc[i].size;
++              }
++      }
+       spin_unlock_irqrestore(&bchan->vc.lock, flags);
+@@ -927,63 +952,86 @@ static void bam_start_dma(struct bam_cha
+ {
+       struct virt_dma_desc *vd = vchan_next_desc(&bchan->vc);
+       struct bam_device *bdev = bchan->bdev;
+-      struct bam_async_desc *async_desc;
++      struct bam_async_desc *async_desc = NULL;
+       struct bam_desc_hw *desc;
+       struct bam_desc_hw *fifo = PTR_ALIGN(bchan->fifo_virt,
+                                       sizeof(struct bam_desc_hw));
+       int ret;
++      unsigned int avail;
++      struct dmaengine_desc_callback cb;
+       lockdep_assert_held(&bchan->vc.lock);
+       if (!vd)
+               return;
+-      list_del(&vd->node);
+-
+-      async_desc = container_of(vd, struct bam_async_desc, vd);
+-      bchan->curr_txd = async_desc;
+-
+       ret = pm_runtime_get_sync(bdev->dev);
+       if (ret < 0)
+               return;
+-      /* on first use, initialize the channel hardware */
+-      if (!bchan->initialized)
+-              bam_chan_init_hw(bchan, async_desc->dir);
+-
+-      /* apply new slave config changes, if necessary */
+-      if (bchan->reconfigure)
+-              bam_apply_new_config(bchan, async_desc->dir);
++      while (vd && !IS_BUSY(bchan)) {
++              list_del(&vd->node);
+-      desc = bchan->curr_txd->curr_desc;
++              async_desc = container_of(vd, struct bam_async_desc, vd);
+-      if (async_desc->num_desc > MAX_DESCRIPTORS)
+-              async_desc->xfer_len = MAX_DESCRIPTORS;
+-      else
+-              async_desc->xfer_len = async_desc->num_desc;
++              /* on first use, initialize the channel hardware */
++              if (!bchan->initialized)
++                      bam_chan_init_hw(bchan, async_desc->dir);
+-      /* set any special flags on the last descriptor */
+-      if (async_desc->num_desc == async_desc->xfer_len)
+-              desc[async_desc->xfer_len - 1].flags |=
+-                                      cpu_to_le16(async_desc->flags);
+-      else
+-              desc[async_desc->xfer_len - 1].flags |=
+-                                      cpu_to_le16(DESC_FLAG_INT);
++              /* apply new slave config changes, if necessary */
++              if (bchan->reconfigure)
++                      bam_apply_new_config(bchan, async_desc->dir);
++
++              desc = async_desc->curr_desc;
++              avail = CIRC_SPACE(bchan->tail, bchan->head,
++                                 MAX_DESCRIPTORS + 1);
++
++              if (async_desc->num_desc > avail)
++                      async_desc->xfer_len = avail;
++              else
++                      async_desc->xfer_len = async_desc->num_desc;
++
++              /* set any special flags on the last descriptor */
++              if (async_desc->num_desc == async_desc->xfer_len)
++                      desc[async_desc->xfer_len - 1].flags |=
++                                              cpu_to_le16(async_desc->flags);
+-      if (bchan->tail + async_desc->xfer_len > MAX_DESCRIPTORS) {
+-              u32 partial = MAX_DESCRIPTORS - bchan->tail;
++              vd = vchan_next_desc(&bchan->vc);
+-              memcpy(&fifo[bchan->tail], desc,
+-                              partial * sizeof(struct bam_desc_hw));
+-              memcpy(fifo, &desc[partial], (async_desc->xfer_len - partial) *
++              dmaengine_desc_get_callback(&async_desc->vd.tx, &cb);
++
++              /*
++               * An interrupt is generated at this desc, if
++               *  - FIFO is FULL.
++               *  - No more descriptors to add.
++               *  - If a callback completion was requested for this DESC,
++               *     In this case, BAM will deliver the completion callback
++               *     for this desc and continue processing the next desc.
++               */
++              if (((avail <= async_desc->xfer_len) || !vd ||
++                   dmaengine_desc_callback_valid(&cb)) &&
++                  !(async_desc->flags & DESC_FLAG_EOT))
++                      desc[async_desc->xfer_len - 1].flags |=
++                              cpu_to_le16(DESC_FLAG_INT);
++
++              if (bchan->tail + async_desc->xfer_len > MAX_DESCRIPTORS) {
++                      u32 partial = MAX_DESCRIPTORS - bchan->tail;
++
++                      memcpy(&fifo[bchan->tail], desc,
++                             partial * sizeof(struct bam_desc_hw));
++                      memcpy(fifo, &desc[partial],
++                             (async_desc->xfer_len - partial) *
+                               sizeof(struct bam_desc_hw));
+-      } else {
+-              memcpy(&fifo[bchan->tail], desc,
+-                      async_desc->xfer_len * sizeof(struct bam_desc_hw));
+-      }
++              } else {
++                      memcpy(&fifo[bchan->tail], desc,
++                             async_desc->xfer_len *
++                             sizeof(struct bam_desc_hw));
++              }
+-      bchan->tail += async_desc->xfer_len;
+-      bchan->tail %= MAX_DESCRIPTORS;
++              bchan->tail += async_desc->xfer_len;
++              bchan->tail %= MAX_DESCRIPTORS;
++              list_add_tail(&async_desc->desc_node, &bchan->desc_list);
++      }
+       /* ensure descriptor writes and dma start not reordered */
+       wmb();
+@@ -1012,7 +1060,7 @@ static void dma_tasklet(unsigned long da
+               bchan = &bdev->channels[i];
+               spin_lock_irqsave(&bchan->vc.lock, flags);
+-              if (!list_empty(&bchan->vc.desc_issued) && !bchan->curr_txd)
++              if (!list_empty(&bchan->vc.desc_issued) && !IS_BUSY(bchan))
+                       bam_start_dma(bchan);
+               spin_unlock_irqrestore(&bchan->vc.lock, flags);
+       }
+@@ -1033,7 +1081,7 @@ static void bam_issue_pending(struct dma
+       spin_lock_irqsave(&bchan->vc.lock, flags);
+       /* if work pending and idle, start a transaction */
+-      if (vchan_issue_pending(&bchan->vc) && !bchan->curr_txd)
++      if (vchan_issue_pending(&bchan->vc) && !IS_BUSY(bchan))
+               bam_start_dma(bchan);
+       spin_unlock_irqrestore(&bchan->vc.lock, flags);
+@@ -1133,6 +1181,7 @@ static void bam_channel_init(struct bam_
+       vchan_init(&bchan->vc, &bdev->common);
+       bchan->vc.desc_free = bam_dma_free_desc;
++      INIT_LIST_HEAD(&bchan->desc_list);
+ }
+ static const struct of_device_id bam_of_match[] = {
diff --git a/target/linux/ipq40xx/patches-4.14/050-0002-mtd-nand-qcom-add-command-elements-in-BAM-transactio.patch b/target/linux/ipq40xx/patches-4.14/050-0002-mtd-nand-qcom-add-command-elements-in-BAM-transactio.patch
new file mode 100644 (file)
index 0000000..1a32cc3
--- /dev/null
@@ -0,0 +1,89 @@
+From 8c4cdce8b1ab044a2ee1d86d5a086f67e32b3c10 Mon Sep 17 00:00:00 2001
+From: Abhishek Sahu <absahu@codeaurora.org>
+Date: Mon, 25 Sep 2017 13:21:25 +0530
+Subject: [PATCH 2/7] mtd: nand: qcom: add command elements in BAM transaction
+
+All the QPIC register read/write through BAM DMA requires
+command descriptor which contains the array of command elements.
+
+Reviewed-by: Archit Taneja <architt@codeaurora.org>
+Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
+Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
+---
+ drivers/mtd/nand/qcom_nandc.c | 19 ++++++++++++++++++-
+ 1 file changed, 18 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/nand/qcom_nandc.c
++++ b/drivers/mtd/nand/qcom_nandc.c
+@@ -22,6 +22,7 @@
+ #include <linux/of.h>
+ #include <linux/of_device.h>
+ #include <linux/delay.h>
++#include <linux/dma/qcom_bam_dma.h>
+ /* NANDc reg offsets */
+ #define       NAND_FLASH_CMD                  0x00
+@@ -199,6 +200,7 @@ nandc_set_reg(nandc, NAND_READ_LOCATION_
+  */
+ #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
++#define QPIC_PER_CW_CMD_ELEMENTS      32
+ #define QPIC_PER_CW_CMD_SGL           32
+ #define QPIC_PER_CW_DATA_SGL          8
+@@ -221,8 +223,13 @@ nandc_set_reg(nandc, NAND_READ_LOCATION_
+ /*
+  * This data type corresponds to the BAM transaction which will be used for all
+  * NAND transfers.
++ * @bam_ce - the array of BAM command elements
+  * @cmd_sgl - sgl for NAND BAM command pipe
+  * @data_sgl - sgl for NAND BAM consumer/producer pipe
++ * @bam_ce_pos - the index in bam_ce which is available for next sgl
++ * @bam_ce_start - the index in bam_ce which marks the start position ce
++ *               for current sgl. It will be used for size calculation
++ *               for current sgl
+  * @cmd_sgl_pos - current index in command sgl.
+  * @cmd_sgl_start - start index in command sgl.
+  * @tx_sgl_pos - current index in data sgl for tx.
+@@ -231,8 +238,11 @@ nandc_set_reg(nandc, NAND_READ_LOCATION_
+  * @rx_sgl_start - start index in data sgl for rx.
+  */
+ struct bam_transaction {
++      struct bam_cmd_element *bam_ce;
+       struct scatterlist *cmd_sgl;
+       struct scatterlist *data_sgl;
++      u32 bam_ce_pos;
++      u32 bam_ce_start;
+       u32 cmd_sgl_pos;
+       u32 cmd_sgl_start;
+       u32 tx_sgl_pos;
+@@ -462,7 +472,8 @@ alloc_bam_transaction(struct qcom_nand_c
+       bam_txn_size =
+               sizeof(*bam_txn) + num_cw *
+-              ((sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
++              ((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) +
++              (sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
+               (sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL));
+       bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL);
+@@ -472,6 +483,10 @@ alloc_bam_transaction(struct qcom_nand_c
+       bam_txn = bam_txn_buf;
+       bam_txn_buf += sizeof(*bam_txn);
++      bam_txn->bam_ce = bam_txn_buf;
++      bam_txn_buf +=
++              sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS * num_cw;
++
+       bam_txn->cmd_sgl = bam_txn_buf;
+       bam_txn_buf +=
+               sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL * num_cw;
+@@ -489,6 +504,8 @@ static void clear_bam_transaction(struct
+       if (!nandc->props->is_bam)
+               return;
++      bam_txn->bam_ce_pos = 0;
++      bam_txn->bam_ce_start = 0;
+       bam_txn->cmd_sgl_pos = 0;
+       bam_txn->cmd_sgl_start = 0;
+       bam_txn->tx_sgl_pos = 0;
diff --git a/target/linux/ipq40xx/patches-4.14/050-0003-mtd-nand-qcom-support-for-command-descriptor-formati.patch b/target/linux/ipq40xx/patches-4.14/050-0003-mtd-nand-qcom-support-for-command-descriptor-formati.patch
new file mode 100644 (file)
index 0000000..8dd209b
--- /dev/null
@@ -0,0 +1,201 @@
+From 8d6b6d7e135e9bbfc923d34a45cb0e72695e63ed Mon Sep 17 00:00:00 2001
+From: Abhishek Sahu <absahu@codeaurora.org>
+Date: Mon, 25 Sep 2017 13:21:26 +0530
+Subject: [PATCH 3/7] mtd: nand: qcom: support for command descriptor formation
+
+1. Add the function for command descriptor preparation which will
+   be used only by BAM DMA and it will form the DMA descriptors
+   containing command elements
+2. DMA_PREP_CMD flag should be used for forming command DMA
+   descriptors
+
+Reviewed-by: Archit Taneja <architt@codeaurora.org>
+Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
+Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
+---
+ drivers/mtd/nand/qcom_nandc.c | 108 +++++++++++++++++++++++++++++++++++-------
+ 1 file changed, 92 insertions(+), 16 deletions(-)
+
+--- a/drivers/mtd/nand/qcom_nandc.c
++++ b/drivers/mtd/nand/qcom_nandc.c
+@@ -200,6 +200,14 @@ nandc_set_reg(nandc, NAND_READ_LOCATION_
+  */
+ #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
++/* Returns the NAND register physical address */
++#define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
++
++/* Returns the dma address for reg read buffer */
++#define reg_buf_dma_addr(chip, vaddr) \
++      ((chip)->reg_read_dma + \
++      ((uint8_t *)(vaddr) - (uint8_t *)(chip)->reg_read_buf))
++
+ #define QPIC_PER_CW_CMD_ELEMENTS      32
+ #define QPIC_PER_CW_CMD_SGL           32
+ #define QPIC_PER_CW_DATA_SGL          8
+@@ -317,7 +325,8 @@ struct nandc_regs {
+  *                            controller
+  * @dev:                      parent device
+  * @base:                     MMIO base
+- * @base_dma:                 physical base address of controller registers
++ * @base_phys:                        physical base address of controller registers
++ * @base_dma:                 dma base address of controller registers
+  * @core_clk:                 controller clock
+  * @aon_clk:                  another controller clock
+  *
+@@ -350,6 +359,7 @@ struct qcom_nand_controller {
+       struct device *dev;
+       void __iomem *base;
++      phys_addr_t base_phys;
+       dma_addr_t base_dma;
+       struct clk *core_clk;
+@@ -751,6 +761,66 @@ static int prepare_bam_async_desc(struct
+ }
+ /*
++ * Prepares the command descriptor for BAM DMA which will be used for NAND
++ * register reads and writes. The command descriptor requires the command
++ * to be formed in command element type so this function uses the command
++ * element from bam transaction ce array and fills the same with required
++ * data. A single SGL can contain multiple command elements so
++ * NAND_BAM_NEXT_SGL will be used for starting the separate SGL
++ * after the current command element.
++ */
++static int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
++                               int reg_off, const void *vaddr,
++                               int size, unsigned int flags)
++{
++      int bam_ce_size;
++      int i, ret;
++      struct bam_cmd_element *bam_ce_buffer;
++      struct bam_transaction *bam_txn = nandc->bam_txn;
++
++      bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_pos];
++
++      /* fill the command desc */
++      for (i = 0; i < size; i++) {
++              if (read)
++                      bam_prep_ce(&bam_ce_buffer[i],
++                                  nandc_reg_phys(nandc, reg_off + 4 * i),
++                                  BAM_READ_COMMAND,
++                                  reg_buf_dma_addr(nandc,
++                                                   (__le32 *)vaddr + i));
++              else
++                      bam_prep_ce_le32(&bam_ce_buffer[i],
++                                       nandc_reg_phys(nandc, reg_off + 4 * i),
++                                       BAM_WRITE_COMMAND,
++                                       *((__le32 *)vaddr + i));
++      }
++
++      bam_txn->bam_ce_pos += size;
++
++      /* use the separate sgl after this command */
++      if (flags & NAND_BAM_NEXT_SGL) {
++              bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_start];
++              bam_ce_size = (bam_txn->bam_ce_pos -
++                              bam_txn->bam_ce_start) *
++                              sizeof(struct bam_cmd_element);
++              sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos],
++                         bam_ce_buffer, bam_ce_size);
++              bam_txn->cmd_sgl_pos++;
++              bam_txn->bam_ce_start = bam_txn->bam_ce_pos;
++
++              if (flags & NAND_BAM_NWD) {
++                      ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
++                                                   DMA_PREP_FENCE |
++                                                   DMA_PREP_CMD);
++                      if (ret)
++                              return ret;
++              }
++      }
++
++      return 0;
++}
++
++/*
+  * Prepares the data descriptor for BAM DMA which will be used for NAND
+  * data reads and writes.
+  */
+@@ -868,19 +938,22 @@ static int read_reg_dma(struct qcom_nand
+ {
+       bool flow_control = false;
+       void *vaddr;
+-      int size;
+-      if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
+-              flow_control = true;
++      vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
++      nandc->reg_read_pos += num_regs;
+       if (first == NAND_DEV_CMD_VLD || first == NAND_DEV_CMD1)
+               first = dev_cmd_reg_addr(nandc, first);
+-      size = num_regs * sizeof(u32);
+-      vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
+-      nandc->reg_read_pos += num_regs;
++      if (nandc->props->is_bam)
++              return prep_bam_dma_desc_cmd(nandc, true, first, vaddr,
++                                           num_regs, flags);
++
++      if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
++              flow_control = true;
+-      return prep_adm_dma_desc(nandc, true, first, vaddr, size, flow_control);
++      return prep_adm_dma_desc(nandc, true, first, vaddr,
++                               num_regs * sizeof(u32), flow_control);
+ }
+ /*
+@@ -897,13 +970,9 @@ static int write_reg_dma(struct qcom_nan
+       bool flow_control = false;
+       struct nandc_regs *regs = nandc->regs;
+       void *vaddr;
+-      int size;
+       vaddr = offset_to_nandc_reg(regs, first);
+-      if (first == NAND_FLASH_CMD)
+-              flow_control = true;
+-
+       if (first == NAND_ERASED_CW_DETECT_CFG) {
+               if (flags & NAND_ERASED_CW_SET)
+                       vaddr = &regs->erased_cw_detect_cfg_set;
+@@ -920,10 +989,15 @@ static int write_reg_dma(struct qcom_nan
+       if (first == NAND_DEV_CMD_VLD_RESTORE || first == NAND_DEV_CMD_VLD)
+               first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD);
+-      size = num_regs * sizeof(u32);
++      if (nandc->props->is_bam)
++              return prep_bam_dma_desc_cmd(nandc, false, first, vaddr,
++                                           num_regs, flags);
++
++      if (first == NAND_FLASH_CMD)
++              flow_control = true;
+-      return prep_adm_dma_desc(nandc, false, first, vaddr, size,
+-                               flow_control);
++      return prep_adm_dma_desc(nandc, false, first, vaddr,
++                               num_regs * sizeof(u32), flow_control);
+ }
+ /*
+@@ -1187,7 +1261,8 @@ static int submit_descs(struct qcom_nand
+               }
+               if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) {
+-                      r = prepare_bam_async_desc(nandc, nandc->cmd_chan, 0);
++                      r = prepare_bam_async_desc(nandc, nandc->cmd_chan,
++                                                 DMA_PREP_CMD);
+                       if (r)
+                               return r;
+               }
+@@ -2722,6 +2797,7 @@ static int qcom_nandc_probe(struct platf
+       if (IS_ERR(nandc->base))
+               return PTR_ERR(nandc->base);
++      nandc->base_phys = res->start;
+       nandc->base_dma = phys_to_dma(dev, (phys_addr_t)res->start);
+       nandc->core_clk = devm_clk_get(dev, "core");
diff --git a/target/linux/ipq40xx/patches-4.14/050-0004-mtd-nand-provide-several-helpers-to-do-common-NAND-o.patch b/target/linux/ipq40xx/patches-4.14/050-0004-mtd-nand-provide-several-helpers-to-do-common-NAND-o.patch
new file mode 100644 (file)
index 0000000..7cbbcf5
--- /dev/null
@@ -0,0 +1,1586 @@
+commit 97d90da8a886949f09bb4754843fb0b504956ad2
+Author: Boris Brezillon <boris.brezillon@free-electrons.com>
+Date:   Thu Nov 30 18:01:29 2017 +0100
+
+    mtd: nand: provide several helpers to do common NAND operations
+    
+    This is part of the process of removing direct calls to ->cmdfunc()
+    outside of the core in order to introduce a better interface to execute
+    NAND operations.
+    
+    Here we provide several helpers and make use of them to remove all
+    direct calls to ->cmdfunc(). This way, we can easily modify those
+    helpers to make use of the new ->exec_op() interface when available.
+    
+    Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
+    [miquel.raynal@free-electrons.com: rebased and fixed some conflicts]
+    Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
+    Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+
+--- a/drivers/mtd/nand/nand_base.c
++++ b/drivers/mtd/nand/nand_base.c
+@@ -561,14 +561,19 @@ static int nand_block_markbad_lowlevel(s
+ static int nand_check_wp(struct mtd_info *mtd)
+ {
+       struct nand_chip *chip = mtd_to_nand(mtd);
++      u8 status;
++      int ret;
+       /* Broken xD cards report WP despite being writable */
+       if (chip->options & NAND_BROKEN_XD)
+               return 0;
+       /* Check the WP bit */
+-      chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
+-      return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
++      ret = nand_status_op(chip, &status);
++      if (ret)
++              return ret;
++
++      return status & NAND_STATUS_WP ? 0 : 1;
+ }
+ /**
+@@ -667,10 +672,17 @@ EXPORT_SYMBOL_GPL(nand_wait_ready);
+ static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
+ {
+       register struct nand_chip *chip = mtd_to_nand(mtd);
++      int ret;
+       timeo = jiffies + msecs_to_jiffies(timeo);
+       do {
+-              if ((chip->read_byte(mtd) & NAND_STATUS_READY))
++              u8 status;
++
++              ret = nand_read_data_op(chip, &status, sizeof(status), true);
++              if (ret)
++                      return;
++
++              if (status & NAND_STATUS_READY)
+                       break;
+               touch_softlockup_watchdog();
+       } while (time_before(jiffies, timeo));
+@@ -1016,7 +1028,15 @@ static void panic_nand_wait(struct mtd_i
+                       if (chip->dev_ready(mtd))
+                               break;
+               } else {
+-                      if (chip->read_byte(mtd) & NAND_STATUS_READY)
++                      int ret;
++                      u8 status;
++
++                      ret = nand_read_data_op(chip, &status, sizeof(status),
++                                              true);
++                      if (ret)
++                              return;
++
++                      if (status & NAND_STATUS_READY)
+                               break;
+               }
+               mdelay(1);
+@@ -1033,8 +1053,9 @@ static void panic_nand_wait(struct mtd_i
+ static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
+ {
+-      int status;
+       unsigned long timeo = 400;
++      u8 status;
++      int ret;
+       /*
+        * Apply this short delay always to ensure that we do wait tWB in any
+@@ -1042,7 +1063,9 @@ static int nand_wait(struct mtd_info *mt
+        */
+       ndelay(100);
+-      chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
++      ret = nand_status_op(chip, NULL);
++      if (ret)
++              return ret;
+       if (in_interrupt() || oops_in_progress)
+               panic_nand_wait(mtd, chip, timeo);
+@@ -1053,14 +1076,22 @@ static int nand_wait(struct mtd_info *mt
+                               if (chip->dev_ready(mtd))
+                                       break;
+                       } else {
+-                              if (chip->read_byte(mtd) & NAND_STATUS_READY)
++                              ret = nand_read_data_op(chip, &status,
++                                                      sizeof(status), true);
++                              if (ret)
++                                      return ret;
++
++                              if (status & NAND_STATUS_READY)
+                                       break;
+                       }
+                       cond_resched();
+               } while (time_before(jiffies, timeo));
+       }
+-      status = (int)chip->read_byte(mtd);
++      ret = nand_read_data_op(chip, &status, sizeof(status), true);
++      if (ret)
++              return ret;
++
+       /* This can happen if in case of timeout or buggy dev_ready */
+       WARN_ON(!(status & NAND_STATUS_READY));
+       return status;
+@@ -1215,6 +1246,516 @@ static void nand_release_data_interface(
+ }
+ /**
++ * nand_read_page_op - Do a READ PAGE operation
++ * @chip: The NAND chip
++ * @page: page to read
++ * @offset_in_page: offset within the page
++ * @buf: buffer used to store the data
++ * @len: length of the buffer
++ *
++ * This function issues a READ PAGE operation.
++ * This function does not select/unselect the CS line.
++ *
++ * Returns 0 on success, a negative error code otherwise.
++ */
++int nand_read_page_op(struct nand_chip *chip, unsigned int page,
++                    unsigned int offset_in_page, void *buf, unsigned int len)
++{
++      struct mtd_info *mtd = nand_to_mtd(chip);
++
++      if (len && !buf)
++              return -EINVAL;
++
++      if (offset_in_page + len > mtd->writesize + mtd->oobsize)
++              return -EINVAL;
++
++      chip->cmdfunc(mtd, NAND_CMD_READ0, offset_in_page, page);
++      if (len)
++              chip->read_buf(mtd, buf, len);
++
++      return 0;
++}
++EXPORT_SYMBOL_GPL(nand_read_page_op);
++
++/**
++ * nand_read_param_page_op - Do a READ PARAMETER PAGE operation
++ * @chip: The NAND chip
++ * @page: parameter page to read
++ * @buf: buffer used to store the data
++ * @len: length of the buffer
++ *
++ * This function issues a READ PARAMETER PAGE operation.
++ * This function does not select/unselect the CS line.
++ *
++ * Returns 0 on success, a negative error code otherwise.
++ */
++static int nand_read_param_page_op(struct nand_chip *chip, u8 page, void *buf,
++                                 unsigned int len)
++{
++      struct mtd_info *mtd = nand_to_mtd(chip);
++      unsigned int i;
++      u8 *p = buf;
++
++      if (len && !buf)
++              return -EINVAL;
++
++      chip->cmdfunc(mtd, NAND_CMD_PARAM, page, -1);
++      for (i = 0; i < len; i++)
++              p[i] = chip->read_byte(mtd);
++
++      return 0;
++}
++
++/**
++ * nand_change_read_column_op - Do a CHANGE READ COLUMN operation
++ * @chip: The NAND chip
++ * @offset_in_page: offset within the page
++ * @buf: buffer used to store the data
++ * @len: length of the buffer
++ * @force_8bit: force 8-bit bus access
++ *
++ * This function issues a CHANGE READ COLUMN operation.
++ * This function does not select/unselect the CS line.
++ *
++ * Returns 0 on success, a negative error code otherwise.
++ */
++int nand_change_read_column_op(struct nand_chip *chip,
++                             unsigned int offset_in_page, void *buf,
++                             unsigned int len, bool force_8bit)
++{
++      struct mtd_info *mtd = nand_to_mtd(chip);
++
++      if (len && !buf)
++              return -EINVAL;
++
++      if (offset_in_page + len > mtd->writesize + mtd->oobsize)
++              return -EINVAL;
++
++      chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset_in_page, -1);
++      if (len)
++              chip->read_buf(mtd, buf, len);
++
++      return 0;
++}
++EXPORT_SYMBOL_GPL(nand_change_read_column_op);
++
++/**
++ * nand_read_oob_op - Do a READ OOB operation
++ * @chip: The NAND chip
++ * @page: page to read
++ * @offset_in_oob: offset within the OOB area
++ * @buf: buffer used to store the data
++ * @len: length of the buffer
++ *
++ * This function issues a READ OOB operation.
++ * This function does not select/unselect the CS line.
++ *
++ * Returns 0 on success, a negative error code otherwise.
++ */
++int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
++                   unsigned int offset_in_oob, void *buf, unsigned int len)
++{
++      struct mtd_info *mtd = nand_to_mtd(chip);
++
++      if (len && !buf)
++              return -EINVAL;
++
++      if (offset_in_oob + len > mtd->oobsize)
++              return -EINVAL;
++
++      chip->cmdfunc(mtd, NAND_CMD_READOOB, offset_in_oob, page);
++      if (len)
++              chip->read_buf(mtd, buf, len);
++
++      return 0;
++}
++EXPORT_SYMBOL_GPL(nand_read_oob_op);
++
++/**
++ * nand_prog_page_begin_op - starts a PROG PAGE operation
++ * @chip: The NAND chip
++ * @page: page to write
++ * @offset_in_page: offset within the page
++ * @buf: buffer containing the data to write to the page
++ * @len: length of the buffer
++ *
++ * This function issues the first half of a PROG PAGE operation.
++ * This function does not select/unselect the CS line.
++ *
++ * Returns 0 on success, a negative error code otherwise.
++ */
++int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
++                          unsigned int offset_in_page, const void *buf,
++                          unsigned int len)
++{
++      struct mtd_info *mtd = nand_to_mtd(chip);
++
++      if (len && !buf)
++              return -EINVAL;
++
++      if (offset_in_page + len > mtd->writesize + mtd->oobsize)
++              return -EINVAL;
++
++      chip->cmdfunc(mtd, NAND_CMD_SEQIN, offset_in_page, page);
++
++      if (buf)
++              chip->write_buf(mtd, buf, len);
++
++      return 0;
++}
++EXPORT_SYMBOL_GPL(nand_prog_page_begin_op);
++
++/**
++ * nand_prog_page_end_op - ends a PROG PAGE operation
++ * @chip: The NAND chip
++ *
++ * This function issues the second half of a PROG PAGE operation.
++ * This function does not select/unselect the CS line.
++ *
++ * Returns 0 on success, a negative error code otherwise.
++ */
++int nand_prog_page_end_op(struct nand_chip *chip)
++{
++      struct mtd_info *mtd = nand_to_mtd(chip);
++      int status;
++
++      chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
++
++      status = chip->waitfunc(mtd, chip);
++      if (status & NAND_STATUS_FAIL)
++              return -EIO;
++
++      return 0;
++}
++EXPORT_SYMBOL_GPL(nand_prog_page_end_op);
++
++/**
++ * nand_prog_page_op - Do a full PROG PAGE operation
++ * @chip: The NAND chip
++ * @page: page to write
++ * @offset_in_page: offset within the page
++ * @buf: buffer containing the data to write to the page
++ * @len: length of the buffer
++ *
++ * This function issues a full PROG PAGE operation.
++ * This function does not select/unselect the CS line.
++ *
++ * Returns 0 on success, a negative error code otherwise.
++ */
++int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
++                    unsigned int offset_in_page, const void *buf,
++                    unsigned int len)
++{
++      struct mtd_info *mtd = nand_to_mtd(chip);
++      int status;
++
++      if (!len || !buf)
++              return -EINVAL;
++
++      if (offset_in_page + len > mtd->writesize + mtd->oobsize)
++              return -EINVAL;
++
++      chip->cmdfunc(mtd, NAND_CMD_SEQIN, offset_in_page, page);
++      chip->write_buf(mtd, buf, len);
++      chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
++
++      status = chip->waitfunc(mtd, chip);
++      if (status & NAND_STATUS_FAIL)
++              return -EIO;
++
++      return 0;
++}
++EXPORT_SYMBOL_GPL(nand_prog_page_op);
++
++/**
++ * nand_change_write_column_op - Do a CHANGE WRITE COLUMN operation
++ * @chip: The NAND chip
++ * @offset_in_page: offset within the page
++ * @buf: buffer containing the data to send to the NAND
++ * @len: length of the buffer
++ * @force_8bit: force 8-bit bus access
++ *
++ * This function issues a CHANGE WRITE COLUMN operation.
++ * This function does not select/unselect the CS line.
++ *
++ * Returns 0 on success, a negative error code otherwise.
++ */
++int nand_change_write_column_op(struct nand_chip *chip,
++                              unsigned int offset_in_page,
++                              const void *buf, unsigned int len,
++                              bool force_8bit)
++{
++      struct mtd_info *mtd = nand_to_mtd(chip);
++
++      if (len && !buf)
++              return -EINVAL;
++
++      if (offset_in_page + len > mtd->writesize + mtd->oobsize)
++              return -EINVAL;
++
++      chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset_in_page, -1);
++      if (len)
++              chip->write_buf(mtd, buf, len);
++
++      return 0;
++}
++EXPORT_SYMBOL_GPL(nand_change_write_column_op);
++
++/**
++ * nand_readid_op - Do a READID operation
++ * @chip: The NAND chip
++ * @addr: address cycle to pass after the READID command
++ * @buf: buffer used to store the ID
++ * @len: length of the buffer
++ *
++ * This function sends a READID command and reads back the ID returned by the
++ * NAND.
++ * This function does not select/unselect the CS line.
++ *
++ * Returns 0 on success, a negative error code otherwise.
++ */
++int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
++                 unsigned int len)
++{
++      struct mtd_info *mtd = nand_to_mtd(chip);
++      unsigned int i;
++      u8 *id = buf;
++
++      if (len && !buf)
++              return -EINVAL;
++
++      chip->cmdfunc(mtd, NAND_CMD_READID, addr, -1);
++
++      for (i = 0; i < len; i++)
++              id[i] = chip->read_byte(mtd);
++
++      return 0;
++}
++EXPORT_SYMBOL_GPL(nand_readid_op);
++
++/**
++ * nand_status_op - Do a STATUS operation
++ * @chip: The NAND chip
++ * @status: out variable to store the NAND status
++ *
++ * This function sends a STATUS command and reads back the status returned by
++ * the NAND.
++ * This function does not select/unselect the CS line.
++ *
++ * Returns 0 on success, a negative error code otherwise.
++ */
++int nand_status_op(struct nand_chip *chip, u8 *status)
++{
++      struct mtd_info *mtd = nand_to_mtd(chip);
++
++      chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
++      if (status)
++              *status = chip->read_byte(mtd);
++
++      return 0;
++}
++EXPORT_SYMBOL_GPL(nand_status_op);
++
++/**
++ * nand_exit_status_op - Exit a STATUS operation
++ * @chip: The NAND chip
++ *
++ * This function sends a READ0 command to cancel the effect of the STATUS
++ * command to avoid reading only the status until a new read command is sent.
++ *
++ * This function does not select/unselect the CS line.
++ *
++ * Returns 0 on success, a negative error code otherwise.
++ */
++int nand_exit_status_op(struct nand_chip *chip)
++{
++      struct mtd_info *mtd = nand_to_mtd(chip);
++
++      chip->cmdfunc(mtd, NAND_CMD_READ0, -1, -1);
++
++      return 0;
++}
++EXPORT_SYMBOL_GPL(nand_exit_status_op);
++
++/**
++ * nand_erase_op - Do an erase operation
++ * @chip: The NAND chip
++ * @eraseblock: block to erase
++ *
++ * This function sends an ERASE command and waits for the NAND to be ready
++ * before returning.
++ * This function does not select/unselect the CS line.
++ *
++ * Returns 0 on success, a negative error code otherwise.
++ */
++int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock)
++{
++      struct mtd_info *mtd = nand_to_mtd(chip);
++      unsigned int page = eraseblock <<
++                          (chip->phys_erase_shift - chip->page_shift);
++      int status;
++
++      chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
++      chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
++
++      status = chip->waitfunc(mtd, chip);
++      if (status < 0)
++              return status;
++
++      if (status & NAND_STATUS_FAIL)
++              return -EIO;
++
++      return 0;
++}
++EXPORT_SYMBOL_GPL(nand_erase_op);
++
++/**
++ * nand_set_features_op - Do a SET FEATURES operation
++ * @chip: The NAND chip
++ * @feature: feature id
++ * @data: 4 bytes of data
++ *
++ * This function sends a SET FEATURES command and waits for the NAND to be
++ * ready before returning.
++ * This function does not select/unselect the CS line.
++ *
++ * Returns 0 on success, a negative error code otherwise.
++ */
++static int nand_set_features_op(struct nand_chip *chip, u8 feature,
++                              const void *data)
++{
++      struct mtd_info *mtd = nand_to_mtd(chip);
++      const u8 *params = data;
++      int i, status;
++
++      chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, feature, -1);
++      for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
++              chip->write_byte(mtd, params[i]);
++
++      status = chip->waitfunc(mtd, chip);
++      if (status & NAND_STATUS_FAIL)
++              return -EIO;
++
++      return 0;
++}
++
++/**
++ * nand_get_features_op - Do a GET FEATURES operation
++ * @chip: The NAND chip
++ * @feature: feature id
++ * @data: 4 bytes of data
++ *
++ * This function sends a GET FEATURES command and waits for the NAND to be
++ * ready before returning.
++ * This function does not select/unselect the CS line.
++ *
++ * Returns 0 on success, a negative error code otherwise.
++ */
++static int nand_get_features_op(struct nand_chip *chip, u8 feature,
++                              void *data)
++{
++      struct mtd_info *mtd = nand_to_mtd(chip);
++      u8 *params = data;
++      int i;
++
++      chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, feature, -1);
++      for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
++              params[i] = chip->read_byte(mtd);
++
++      return 0;
++}
++
++/**
++ * nand_reset_op - Do a reset operation
++ * @chip: The NAND chip
++ *
++ * This function sends a RESET command and waits for the NAND to be ready
++ * before returning.
++ * This function does not select/unselect the CS line.
++ *
++ * Returns 0 on success, a negative error code otherwise.
++ */
++int nand_reset_op(struct nand_chip *chip)
++{
++      struct mtd_info *mtd = nand_to_mtd(chip);
++
++      chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
++
++      return 0;
++}
++EXPORT_SYMBOL_GPL(nand_reset_op);
++
++/**
++ * nand_read_data_op - Read data from the NAND
++ * @chip: The NAND chip
++ * @buf: buffer used to store the data
++ * @len: length of the buffer
++ * @force_8bit: force 8-bit bus access
++ *
++ * This function does a raw data read on the bus. Usually used after launching
++ * another NAND operation like nand_read_page_op().
++ * This function does not select/unselect the CS line.
++ *
++ * Returns 0 on success, a negative error code otherwise.
++ */
++int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
++                    bool force_8bit)
++{
++      struct mtd_info *mtd = nand_to_mtd(chip);
++
++      if (!len || !buf)
++              return -EINVAL;
++
++      if (force_8bit) {
++              u8 *p = buf;
++              unsigned int i;
++
++              for (i = 0; i < len; i++)
++                      p[i] = chip->read_byte(mtd);
++      } else {
++              chip->read_buf(mtd, buf, len);
++      }
++
++      return 0;
++}
++EXPORT_SYMBOL_GPL(nand_read_data_op);
++
++/**
++ * nand_write_data_op - Write data from the NAND
++ * @chip: The NAND chip
++ * @buf: buffer containing the data to send on the bus
++ * @len: length of the buffer
++ * @force_8bit: force 8-bit bus access
++ *
++ * This function does a raw data write on the bus. Usually used after launching
++ * another NAND operation like nand_write_page_begin_op().
++ * This function does not select/unselect the CS line.
++ *
++ * Returns 0 on success, a negative error code otherwise.
++ */
++int nand_write_data_op(struct nand_chip *chip, const void *buf,
++                     unsigned int len, bool force_8bit)
++{
++      struct mtd_info *mtd = nand_to_mtd(chip);
++
++      if (!len || !buf)
++              return -EINVAL;
++
++      if (force_8bit) {
++              const u8 *p = buf;
++              unsigned int i;
++
++              for (i = 0; i < len; i++)
++                      chip->write_byte(mtd, p[i]);
++      } else {
++              chip->write_buf(mtd, buf, len);
++      }
++
++      return 0;
++}
++EXPORT_SYMBOL_GPL(nand_write_data_op);
++
++/**
+  * nand_reset - Reset and initialize a NAND device
+  * @chip: The NAND chip
+  * @chipnr: Internal die id
+@@ -1235,8 +1776,10 @@ int nand_reset(struct nand_chip *chip, i
+        * interface settings, hence this weird ->select_chip() dance.
+        */
+       chip->select_chip(mtd, chipnr);
+-      chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
++      ret = nand_reset_op(chip);
+       chip->select_chip(mtd, -1);
++      if (ret)
++              return ret;
+       chip->select_chip(mtd, chipnr);
+       ret = nand_setup_data_interface(chip, chipnr);
+@@ -1392,9 +1935,19 @@ EXPORT_SYMBOL(nand_check_erased_ecc_chun
+ int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+                      uint8_t *buf, int oob_required, int page)
+ {
+-      chip->read_buf(mtd, buf, mtd->writesize);
+-      if (oob_required)
+-              chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
++      int ret;
++
++      ret = nand_read_data_op(chip, buf, mtd->writesize, false);
++      if (ret)
++              return ret;
++
++      if (oob_required) {
++              ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize,
++                                      false);
++              if (ret)
++                      return ret;
++      }
++
+       return 0;
+ }
+ EXPORT_SYMBOL(nand_read_page_raw);
+@@ -1416,29 +1969,46 @@ static int nand_read_page_raw_syndrome(s
+       int eccsize = chip->ecc.size;
+       int eccbytes = chip->ecc.bytes;
+       uint8_t *oob = chip->oob_poi;
+-      int steps, size;
++      int steps, size, ret;
+       for (steps = chip->ecc.steps; steps > 0; steps--) {
+-              chip->read_buf(mtd, buf, eccsize);
++              ret = nand_read_data_op(chip, buf, eccsize, false);
++              if (ret)
++                      return ret;
++
+               buf += eccsize;
+               if (chip->ecc.prepad) {
+-                      chip->read_buf(mtd, oob, chip->ecc.prepad);
++                      ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
++                                              false);
++                      if (ret)
++                              return ret;
++
+                       oob += chip->ecc.prepad;
+               }
+-              chip->read_buf(mtd, oob, eccbytes);
++              ret = nand_read_data_op(chip, oob, eccbytes, false);
++              if (ret)
++                      return ret;
++
+               oob += eccbytes;
+               if (chip->ecc.postpad) {
+-                      chip->read_buf(mtd, oob, chip->ecc.postpad);
++                      ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
++                                              false);
++                      if (ret)
++                              return ret;
++
+                       oob += chip->ecc.postpad;
+               }
+       }
+       size = mtd->oobsize - (oob - chip->oob_poi);
+-      if (size)
+-              chip->read_buf(mtd, oob, size);
++      if (size) {
++              ret = nand_read_data_op(chip, oob, size, false);
++              if (ret)
++                      return ret;
++      }
+       return 0;
+ }
+@@ -1527,7 +2097,9 @@ static int nand_read_subpage(struct mtd_
+               chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
+       p = bufpoi + data_col_addr;
+-      chip->read_buf(mtd, p, datafrag_len);
++      ret = nand_read_data_op(chip, p, datafrag_len, false);
++      if (ret)
++              return ret;
+       /* Calculate ECC */
+       for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
+@@ -1545,8 +2117,11 @@ static int nand_read_subpage(struct mtd_
+               gaps = 1;
+       if (gaps) {
+-              chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
+-              chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
++              ret = nand_change_read_column_op(chip, mtd->writesize,
++                                               chip->oob_poi, mtd->oobsize,
++                                               false);
++              if (ret)
++                      return ret;
+       } else {
+               /*
+                * Send the command to read the particular ECC bytes take care
+@@ -1560,9 +2135,12 @@ static int nand_read_subpage(struct mtd_
+                   (busw - 1))
+                       aligned_len++;
+-              chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
+-                            mtd->writesize + aligned_pos, -1);
+-              chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
++              ret = nand_change_read_column_op(chip,
++                                               mtd->writesize + aligned_pos,
++                                               &chip->oob_poi[aligned_pos],
++                                               aligned_len, false);
++              if (ret)
++                      return ret;
+       }
+       ret = mtd_ooblayout_get_eccbytes(mtd, chip->buffers->ecccode,
+@@ -1619,10 +2197,17 @@ static int nand_read_page_hwecc(struct m
+       for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+               chip->ecc.hwctl(mtd, NAND_ECC_READ);
+-              chip->read_buf(mtd, p, eccsize);
++
++              ret = nand_read_data_op(chip, p, eccsize, false);
++              if (ret)
++                      return ret;
++
+               chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+       }
+-      chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
++
++      ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false);
++      if (ret)
++              return ret;
+       ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
+                                        chip->ecc.total);
+@@ -1681,9 +2266,13 @@ static int nand_read_page_hwecc_oob_firs
+       unsigned int max_bitflips = 0;
+       /* Read the OOB area first */
+-      chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
+-      chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+-      chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
++      ret = nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
++      if (ret)
++              return ret;
++
++      ret = nand_read_page_op(chip, page, 0, NULL, 0);
++      if (ret)
++              return ret;
+       ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
+                                        chip->ecc.total);
+@@ -1694,7 +2283,11 @@ static int nand_read_page_hwecc_oob_firs
+               int stat;
+               chip->ecc.hwctl(mtd, NAND_ECC_READ);
+-              chip->read_buf(mtd, p, eccsize);
++
++              ret = nand_read_data_op(chip, p, eccsize, false);
++              if (ret)
++                      return ret;
++
+               chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+               stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
+@@ -1731,7 +2324,7 @@ static int nand_read_page_hwecc_oob_firs
+ static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
+                                  uint8_t *buf, int oob_required, int page)
+ {
+-      int i, eccsize = chip->ecc.size;
++      int ret, i, eccsize = chip->ecc.size;
+       int eccbytes = chip->ecc.bytes;
+       int eccsteps = chip->ecc.steps;
+       int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
+@@ -1743,21 +2336,36 @@ static int nand_read_page_syndrome(struc
+               int stat;
+               chip->ecc.hwctl(mtd, NAND_ECC_READ);
+-              chip->read_buf(mtd, p, eccsize);
++
++              ret = nand_read_data_op(chip, p, eccsize, false);
++              if (ret)
++                      return ret;
+               if (chip->ecc.prepad) {
+-                      chip->read_buf(mtd, oob, chip->ecc.prepad);
++                      ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
++                                              false);
++                      if (ret)
++                              return ret;
++
+                       oob += chip->ecc.prepad;
+               }
+               chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
+-              chip->read_buf(mtd, oob, eccbytes);
++
++              ret = nand_read_data_op(chip, oob, eccbytes, false);
++              if (ret)
++                      return ret;
++
+               stat = chip->ecc.correct(mtd, p, oob, NULL);
+               oob += eccbytes;
+               if (chip->ecc.postpad) {
+-                      chip->read_buf(mtd, oob, chip->ecc.postpad);
++                      ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
++                                              false);
++                      if (ret)
++                              return ret;
++
+                       oob += chip->ecc.postpad;
+               }
+@@ -1781,8 +2389,11 @@ static int nand_read_page_syndrome(struc
+       /* Calculate remaining oob bytes */
+       i = mtd->oobsize - (oob - chip->oob_poi);
+-      if (i)
+-              chip->read_buf(mtd, oob, i);
++      if (i) {
++              ret = nand_read_data_op(chip, oob, i, false);
++              if (ret)
++                      return ret;
++      }
+       return max_bitflips;
+ }
+@@ -1903,8 +2514,11 @@ static int nand_do_read_ops(struct mtd_i
+                                                __func__, buf);
+ read_retry:
+-                      if (nand_standard_page_accessors(&chip->ecc))
+-                              chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
++                      if (nand_standard_page_accessors(&chip->ecc)) {
++                              ret = nand_read_page_op(chip, page, 0, NULL, 0);
++                              if (ret)
++                                      break;
++                      }
+                       /*
+                        * Now read the page into the buffer.  Absent an error,
+@@ -2063,9 +2677,7 @@ static int nand_read(struct mtd_info *mt
+  */
+ int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page)
+ {
+-      chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
+-      chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+-      return 0;
++      return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
+ }
+ EXPORT_SYMBOL(nand_read_oob_std);
+@@ -2083,25 +2695,43 @@ int nand_read_oob_syndrome(struct mtd_in
+       int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
+       int eccsize = chip->ecc.size;
+       uint8_t *bufpoi = chip->oob_poi;
+-      int i, toread, sndrnd = 0, pos;
++      int i, toread, sndrnd = 0, pos, ret;
++
++      ret = nand_read_page_op(chip, page, chip->ecc.size, NULL, 0);
++      if (ret)
++              return ret;
+-      chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
+       for (i = 0; i < chip->ecc.steps; i++) {
+               if (sndrnd) {
++                      int ret;
++
+                       pos = eccsize + i * (eccsize + chunk);
+                       if (mtd->writesize > 512)
+-                              chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
++                              ret = nand_change_read_column_op(chip, pos,
++                                                               NULL, 0,
++                                                               false);
+                       else
+-                              chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
++                              ret = nand_read_page_op(chip, page, pos, NULL,
++                                                      0);
++
++                      if (ret)
++                              return ret;
+               } else
+                       sndrnd = 1;
+               toread = min_t(int, length, chunk);
+-              chip->read_buf(mtd, bufpoi, toread);
++
++              ret = nand_read_data_op(chip, bufpoi, toread, false);
++              if (ret)
++                      return ret;
++
+               bufpoi += toread;
+               length -= toread;
+       }
+-      if (length > 0)
+-              chip->read_buf(mtd, bufpoi, length);
++      if (length > 0) {
++              ret = nand_read_data_op(chip, bufpoi, length, false);
++              if (ret)
++                      return ret;
++      }
+       return 0;
+ }
+@@ -2115,18 +2745,8 @@ EXPORT_SYMBOL(nand_read_oob_syndrome);
+  */
+ int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page)
+ {
+-      int status = 0;
+-      const uint8_t *buf = chip->oob_poi;
+-      int length = mtd->oobsize;
+-
+-      chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
+-      chip->write_buf(mtd, buf, length);
+-      /* Send command to program the OOB data */
+-      chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+-
+-      status = chip->waitfunc(mtd, chip);
+-
+-      return status & NAND_STATUS_FAIL ? -EIO : 0;
++      return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
++                               mtd->oobsize);
+ }
+ EXPORT_SYMBOL(nand_write_oob_std);
+@@ -2142,7 +2762,7 @@ int nand_write_oob_syndrome(struct mtd_i
+ {
+       int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
+       int eccsize = chip->ecc.size, length = mtd->oobsize;
+-      int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
++      int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps;
+       const uint8_t *bufpoi = chip->oob_poi;
+       /*
+@@ -2156,7 +2776,10 @@ int nand_write_oob_syndrome(struct mtd_i
+       } else
+               pos = eccsize;
+-      chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
++      ret = nand_prog_page_begin_op(chip, page, pos, NULL, 0);
++      if (ret)
++              return ret;
++
+       for (i = 0; i < steps; i++) {
+               if (sndcmd) {
+                       if (mtd->writesize <= 512) {
+@@ -2165,28 +2788,40 @@ int nand_write_oob_syndrome(struct mtd_i
+                               len = eccsize;
+                               while (len > 0) {
+                                       int num = min_t(int, len, 4);
+-                                      chip->write_buf(mtd, (uint8_t *)&fill,
+-                                                      num);
++
++                                      ret = nand_write_data_op(chip, &fill,
++                                                               num, false);
++                                      if (ret)
++                                              return ret;
++
+                                       len -= num;
+                               }
+                       } else {
+                               pos = eccsize + i * (eccsize + chunk);
+-                              chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
++                              ret = nand_change_write_column_op(chip, pos,
++                                                                NULL, 0,
++                                                                false);
++                              if (ret)
++                                      return ret;
+                       }
+               } else
+                       sndcmd = 1;
+               len = min_t(int, length, chunk);
+-              chip->write_buf(mtd, bufpoi, len);
++
++              ret = nand_write_data_op(chip, bufpoi, len, false);
++              if (ret)
++                      return ret;
++
+               bufpoi += len;
+               length -= len;
+       }
+-      if (length > 0)
+-              chip->write_buf(mtd, bufpoi, length);
+-
+-      chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+-      status = chip->waitfunc(mtd, chip);
++      if (length > 0) {
++              ret = nand_write_data_op(chip, bufpoi, length, false);
++              if (ret)
++                      return ret;
++      }
+-      return status & NAND_STATUS_FAIL ? -EIO : 0;
++      return nand_prog_page_end_op(chip);
+ }
+ EXPORT_SYMBOL(nand_write_oob_syndrome);
+@@ -2341,9 +2976,18 @@ static int nand_read_oob(struct mtd_info
+ int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+                       const uint8_t *buf, int oob_required, int page)
+ {
+-      chip->write_buf(mtd, buf, mtd->writesize);
+-      if (oob_required)
+-              chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
++      int ret;
++
++      ret = nand_write_data_op(chip, buf, mtd->writesize, false);
++      if (ret)
++              return ret;
++
++      if (oob_required) {
++              ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize,
++                                       false);
++              if (ret)
++                      return ret;
++      }
+       return 0;
+ }
+@@ -2367,29 +3011,46 @@ static int nand_write_page_raw_syndrome(
+       int eccsize = chip->ecc.size;
+       int eccbytes = chip->ecc.bytes;
+       uint8_t *oob = chip->oob_poi;
+-      int steps, size;
++      int steps, size, ret;
+       for (steps = chip->ecc.steps; steps > 0; steps--) {
+-              chip->write_buf(mtd, buf, eccsize);
++              ret = nand_write_data_op(chip, buf, eccsize, false);
++              if (ret)
++                      return ret;
++
+               buf += eccsize;
+               if (chip->ecc.prepad) {
+-                      chip->write_buf(mtd, oob, chip->ecc.prepad);
++                      ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
++                                               false);
++                      if (ret)
++                              return ret;
++
+                       oob += chip->ecc.prepad;
+               }
+-              chip->write_buf(mtd, oob, eccbytes);
++              ret = nand_write_data_op(chip, oob, eccbytes, false);
++              if (ret)
++                      return ret;
++
+               oob += eccbytes;
+               if (chip->ecc.postpad) {
+-                      chip->write_buf(mtd, oob, chip->ecc.postpad);
++                      ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
++                                               false);
++                      if (ret)
++                              return ret;
++
+                       oob += chip->ecc.postpad;
+               }
+       }
+       size = mtd->oobsize - (oob - chip->oob_poi);
+-      if (size)
+-              chip->write_buf(mtd, oob, size);
++      if (size) {
++              ret = nand_write_data_op(chip, oob, size, false);
++              if (ret)
++                      return ret;
++      }
+       return 0;
+ }
+@@ -2443,7 +3104,11 @@ static int nand_write_page_hwecc(struct
+       for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+               chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+-              chip->write_buf(mtd, p, eccsize);
++
++              ret = nand_write_data_op(chip, p, eccsize, false);
++              if (ret)
++                      return ret;
++
+               chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+       }
+@@ -2452,7 +3117,9 @@ static int nand_write_page_hwecc(struct
+       if (ret)
+               return ret;
+-      chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
++      ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
++      if (ret)
++              return ret;
+       return 0;
+ }
+@@ -2488,7 +3155,9 @@ static int nand_write_subpage_hwecc(stru
+               chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+               /* write data (untouched subpages already masked by 0xFF) */
+-              chip->write_buf(mtd, buf, ecc_size);
++              ret = nand_write_data_op(chip, buf, ecc_size, false);
++              if (ret)
++                      return ret;
+               /* mask ECC of un-touched subpages by padding 0xFF */
+               if ((step < start_step) || (step > end_step))
+@@ -2515,7 +3184,9 @@ static int nand_write_subpage_hwecc(stru
+               return ret;
+       /* write OOB buffer to NAND device */
+-      chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
++      ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
++      if (ret)
++              return ret;
+       return 0;
+ }
+@@ -2542,31 +3213,49 @@ static int nand_write_page_syndrome(stru
+       int eccsteps = chip->ecc.steps;
+       const uint8_t *p = buf;
+       uint8_t *oob = chip->oob_poi;
++      int ret;
+       for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+-
+               chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+-              chip->write_buf(mtd, p, eccsize);
++
++              ret = nand_write_data_op(chip, p, eccsize, false);
++              if (ret)
++                      return ret;
+               if (chip->ecc.prepad) {
+-                      chip->write_buf(mtd, oob, chip->ecc.prepad);
++                      ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
++                                               false);
++                      if (ret)
++                              return ret;
++
+                       oob += chip->ecc.prepad;
+               }
+               chip->ecc.calculate(mtd, p, oob);
+-              chip->write_buf(mtd, oob, eccbytes);
++
++              ret = nand_write_data_op(chip, oob, eccbytes, false);
++              if (ret)
++                      return ret;
++
+               oob += eccbytes;
+               if (chip->ecc.postpad) {
+-                      chip->write_buf(mtd, oob, chip->ecc.postpad);
++                      ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
++                                               false);
++                      if (ret)
++                              return ret;
++
+                       oob += chip->ecc.postpad;
+               }
+       }
+       /* Calculate remaining oob bytes */
+       i = mtd->oobsize - (oob - chip->oob_poi);
+-      if (i)
+-              chip->write_buf(mtd, oob, i);
++      if (i) {
++              ret = nand_write_data_op(chip, oob, i, false);
++              if (ret)
++                      return ret;
++      }
+       return 0;
+ }
+@@ -2594,8 +3283,11 @@ static int nand_write_page(struct mtd_in
+       else
+               subpage = 0;
+-      if (nand_standard_page_accessors(&chip->ecc))
+-              chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
++      if (nand_standard_page_accessors(&chip->ecc)) {
++              status = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
++              if (status)
++                      return status;
++      }
+       if (unlikely(raw))
+               status = chip->ecc.write_page_raw(mtd, chip, buf,
+@@ -2610,13 +3302,8 @@ static int nand_write_page(struct mtd_in
+       if (status < 0)
+               return status;
+-      if (nand_standard_page_accessors(&chip->ecc)) {
+-              chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+-
+-              status = chip->waitfunc(mtd, chip);
+-              if (status & NAND_STATUS_FAIL)
+-                      return -EIO;
+-      }
++      if (nand_standard_page_accessors(&chip->ecc))
++              return nand_prog_page_end_op(chip);
+       return 0;
+ }
+@@ -2989,17 +3676,12 @@ out:
+ static int single_erase(struct mtd_info *mtd, int page)
+ {
+       struct nand_chip *chip = mtd_to_nand(mtd);
+-      int status;
++      unsigned int eraseblock;
+       /* Send commands to erase a block */
+-      chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
+-      chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
+-
+-      status = chip->waitfunc(mtd, chip);
+-      if (status < 0)
+-              return status;
++      eraseblock = page >> (chip->phys_erase_shift - chip->page_shift);
+-      return status & NAND_STATUS_FAIL ? -EIO : 0;
++      return nand_erase_op(chip, eraseblock);
+ }
+ /**
+@@ -3226,22 +3908,12 @@ static int nand_max_bad_blocks(struct mt
+ static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
+                       int addr, uint8_t *subfeature_param)
+ {
+-      int status;
+-      int i;
+-
+       if (!chip->onfi_version ||
+           !(le16_to_cpu(chip->onfi_params.opt_cmd)
+             & ONFI_OPT_CMD_SET_GET_FEATURES))
+               return -EINVAL;
+-      chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
+-      for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
+-              chip->write_byte(mtd, subfeature_param[i]);
+-
+-      status = chip->waitfunc(mtd, chip);
+-      if (status & NAND_STATUS_FAIL)
+-              return -EIO;
+-      return 0;
++      return nand_set_features_op(chip, addr, subfeature_param);
+ }
+ /**
+@@ -3254,17 +3926,12 @@ static int nand_onfi_set_features(struct
+ static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
+                       int addr, uint8_t *subfeature_param)
+ {
+-      int i;
+-
+       if (!chip->onfi_version ||
+           !(le16_to_cpu(chip->onfi_params.opt_cmd)
+             & ONFI_OPT_CMD_SET_GET_FEATURES))
+               return -EINVAL;
+-      chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
+-      for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
+-              *subfeature_param++ = chip->read_byte(mtd);
+-      return 0;
++      return nand_get_features_op(chip, addr, subfeature_param);
+ }
+ /**
+@@ -3407,12 +4074,11 @@ static u16 onfi_crc16(u16 crc, u8 const
+ static int nand_flash_detect_ext_param_page(struct nand_chip *chip,
+                                           struct nand_onfi_params *p)
+ {
+-      struct mtd_info *mtd = nand_to_mtd(chip);
+       struct onfi_ext_param_page *ep;
+       struct onfi_ext_section *s;
+       struct onfi_ext_ecc_info *ecc;
+       uint8_t *cursor;
+-      int ret = -EINVAL;
++      int ret;
+       int len;
+       int i;
+@@ -3422,14 +4088,18 @@ static int nand_flash_detect_ext_param_p
+               return -ENOMEM;
+       /* Send our own NAND_CMD_PARAM. */
+-      chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
++      ret = nand_read_param_page_op(chip, 0, NULL, 0);
++      if (ret)
++              goto ext_out;
+       /* Use the Change Read Column command to skip the ONFI param pages. */
+-      chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
+-                      sizeof(*p) * p->num_of_param_pages , -1);
++      ret = nand_change_read_column_op(chip,
++                                       sizeof(*p) * p->num_of_param_pages,
++                                       ep, len, true);
++      if (ret)
++              goto ext_out;
+-      /* Read out the Extended Parameter Page. */
+-      chip->read_buf(mtd, (uint8_t *)ep, len);
++      ret = -EINVAL;
+       if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
+               != le16_to_cpu(ep->crc))) {
+               pr_debug("fail in the CRC.\n");
+@@ -3482,19 +4152,23 @@ static int nand_flash_detect_onfi(struct
+ {
+       struct mtd_info *mtd = nand_to_mtd(chip);
+       struct nand_onfi_params *p = &chip->onfi_params;
+-      int i, j;
+-      int val;
++      char id[4];
++      int i, ret, val;
+       /* Try ONFI for unknown chip or LP */
+-      chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
+-      if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
+-              chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
++      ret = nand_readid_op(chip, 0x20, id, sizeof(id));
++      if (ret || strncmp(id, "ONFI", 4))
++              return 0;
++
++      ret = nand_read_param_page_op(chip, 0, NULL, 0);
++      if (ret)
+               return 0;
+-      chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
+       for (i = 0; i < 3; i++) {
+-              for (j = 0; j < sizeof(*p); j++)
+-                      ((uint8_t *)p)[j] = chip->read_byte(mtd);
++              ret = nand_read_data_op(chip, p, sizeof(*p), true);
++              if (ret)
++                      return 0;
++
+               if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
+                               le16_to_cpu(p->crc)) {
+                       break;
+@@ -3585,20 +4259,22 @@ static int nand_flash_detect_jedec(struc
+       struct mtd_info *mtd = nand_to_mtd(chip);
+       struct nand_jedec_params *p = &chip->jedec_params;
+       struct jedec_ecc_info *ecc;
+-      int val;
+-      int i, j;
++      char id[5];
++      int i, val, ret;
+       /* Try JEDEC for unknown chip or LP */
+-      chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
+-      if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
+-              chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
+-              chip->read_byte(mtd) != 'C')
++      ret = nand_readid_op(chip, 0x40, id, sizeof(id));
++      if (ret || strncmp(id, "JEDEC", sizeof(id)))
++              return 0;
++
++      ret = nand_read_param_page_op(chip, 0x40, NULL, 0);
++      if (ret)
+               return 0;
+-      chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
+       for (i = 0; i < 3; i++) {
+-              for (j = 0; j < sizeof(*p); j++)
+-                      ((uint8_t *)p)[j] = chip->read_byte(mtd);
++              ret = nand_read_data_op(chip, p, sizeof(*p), true);
++              if (ret)
++                      return 0;
+               if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
+                               le16_to_cpu(p->crc))
+@@ -3877,8 +4553,7 @@ static int nand_detect(struct nand_chip
+ {
+       const struct nand_manufacturer *manufacturer;
+       struct mtd_info *mtd = nand_to_mtd(chip);
+-      int busw;
+-      int i;
++      int busw, ret;
+       u8 *id_data = chip->id.data;
+       u8 maf_id, dev_id;
+@@ -3886,17 +4561,21 @@ static int nand_detect(struct nand_chip
+        * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
+        * after power-up.
+        */
+-      nand_reset(chip, 0);
++      ret = nand_reset(chip, 0);
++      if (ret)
++              return ret;
+       /* Select the device */
+       chip->select_chip(mtd, 0);
+       /* Send the command for reading device ID */
+-      chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
++      ret = nand_readid_op(chip, 0, id_data, 2);
++      if (ret)
++              return ret;
+       /* Read manufacturer and device IDs */
+-      maf_id = chip->read_byte(mtd);
+-      dev_id = chip->read_byte(mtd);
++      maf_id = id_data[0];
++      dev_id = id_data[1];
+       /*
+        * Try again to make sure, as some systems the bus-hold or other
+@@ -3905,11 +4584,10 @@ static int nand_detect(struct nand_chip
+        * not match, ignore the device completely.
+        */
+-      chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+-
+       /* Read entire ID string */
+-      for (i = 0; i < ARRAY_SIZE(chip->id.data); i++)
+-              id_data[i] = chip->read_byte(mtd);
++      ret = nand_readid_op(chip, 0, id_data, sizeof(chip->id.data));
++      if (ret)
++              return ret;
+       if (id_data[0] != maf_id || id_data[1] != dev_id) {
+               pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
+@@ -4233,15 +4911,16 @@ int nand_scan_ident(struct mtd_info *mtd
+       /* Check for a chip array */
+       for (i = 1; i < maxchips; i++) {
++              u8 id[2];
++
+               /* See comment in nand_get_flash_type for reset */
+               nand_reset(chip, i);
+               chip->select_chip(mtd, i);
+               /* Send the command for reading device ID */
+-              chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
++              nand_readid_op(chip, 0, id, sizeof(id));
+               /* Read manufacturer and device IDs */
+-              if (nand_maf_id != chip->read_byte(mtd) ||
+-                  nand_dev_id != chip->read_byte(mtd)) {
++              if (nand_maf_id != id[0] || nand_dev_id != id[1]) {
+                       chip->select_chip(mtd, -1);
+                       break;
+               }
+--- a/drivers/mtd/nand/qcom_nandc.c
++++ b/drivers/mtd/nand/qcom_nandc.c
+@@ -1990,7 +1990,7 @@ static int qcom_nandc_write_oob(struct m
+       struct nand_ecc_ctrl *ecc = &chip->ecc;
+       u8 *oob = chip->oob_poi;
+       int data_size, oob_size;
+-      int ret, status = 0;
++      int ret;
+       host->use_ecc = true;
+@@ -2027,11 +2027,7 @@ static int qcom_nandc_write_oob(struct m
+               return -EIO;
+       }
+-      chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+-
+-      status = chip->waitfunc(mtd, chip);
+-
+-      return status & NAND_STATUS_FAIL ? -EIO : 0;
++      return nand_prog_page_end_op(chip);
+ }
+ static int qcom_nandc_block_bad(struct mtd_info *mtd, loff_t ofs)
+@@ -2081,7 +2077,7 @@ static int qcom_nandc_block_markbad(stru
+       struct qcom_nand_host *host = to_qcom_nand_host(chip);
+       struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
+       struct nand_ecc_ctrl *ecc = &chip->ecc;
+-      int page, ret, status = 0;
++      int page, ret;
+       clear_read_regs(nandc);
+       clear_bam_transaction(nandc);
+@@ -2114,11 +2110,7 @@ static int qcom_nandc_block_markbad(stru
+               return -EIO;
+       }
+-      chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+-
+-      status = chip->waitfunc(mtd, chip);
+-
+-      return status & NAND_STATUS_FAIL ? -EIO : 0;
++      return nand_prog_page_end_op(chip);
+ }
+ /*
+--- a/include/linux/mtd/rawnand.h
++++ b/include/linux/mtd/rawnand.h
+@@ -1313,6 +1313,35 @@ int nand_write_page_raw(struct mtd_info
+ /* Reset and initialize a NAND device */
+ int nand_reset(struct nand_chip *chip, int chipnr);
++/* NAND operation helpers */
++int nand_reset_op(struct nand_chip *chip);
++int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
++                 unsigned int len);
++int nand_status_op(struct nand_chip *chip, u8 *status);
++int nand_exit_status_op(struct nand_chip *chip);
++int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock);
++int nand_read_page_op(struct nand_chip *chip, unsigned int page,
++                    unsigned int offset_in_page, void *buf, unsigned int len);
++int nand_change_read_column_op(struct nand_chip *chip,
++                             unsigned int offset_in_page, void *buf,
++                             unsigned int len, bool force_8bit);
++int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
++                   unsigned int offset_in_page, void *buf, unsigned int len);
++int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
++                          unsigned int offset_in_page, const void *buf,
++                          unsigned int len);
++int nand_prog_page_end_op(struct nand_chip *chip);
++int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
++                    unsigned int offset_in_page, const void *buf,
++                    unsigned int len);
++int nand_change_write_column_op(struct nand_chip *chip,
++                              unsigned int offset_in_page, const void *buf,
++                              unsigned int len, bool force_8bit);
++int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
++                    bool force_8bit);
++int nand_write_data_op(struct nand_chip *chip, const void *buf,
++                     unsigned int len, bool force_8bit);
++
+ /* Free resources held by the NAND device */
+ void nand_cleanup(struct nand_chip *chip);
diff --git a/target/linux/ipq40xx/patches-4.14/050-0005-mtd-nand-force-drivers-to-explicitly-send-READ-PROG-.patch b/target/linux/ipq40xx/patches-4.14/050-0005-mtd-nand-force-drivers-to-explicitly-send-READ-PROG-.patch
new file mode 100644 (file)
index 0000000..e7e2e79
--- /dev/null
@@ -0,0 +1,94 @@
+From 25f815f66a141436df8a4c45e5d2765272aea2ac Mon Sep 17 00:00:00 2001
+From: Boris Brezillon <boris.brezillon@free-electrons.com>
+Date: Thu, 30 Nov 2017 18:01:30 +0100
+Subject: [PATCH 5/7] mtd: nand: force drivers to explicitly send READ/PROG
+ commands
+
+The core currently send the READ0 and SEQIN+PAGEPROG commands in
+nand_do_read/write_ops(). This is inconsistent with
+->read/write_oob[_raw]() hooks behavior which are expected to send
+these commands.
+
+There's already a flag (NAND_ECC_CUSTOM_PAGE_ACCESS) to inform the core
+that a specific controller wants to send the READ/SEQIN+PAGEPROG
+commands on its own, but it's an opt-in flag, and existing drivers are
+unlikely to be updated to pass it.
+
+Moreover, some controllers cannot dissociate the READ/PAGEPROG commands
+from the associated data transfer and ECC engine activation, and
+developers have to hack things in their ->cmdfunc() implementation to
+handle such complex cases, or have to accept the perf penalty of sending
+twice the same command.
+To address this problem we are planning on adding a new interface which
+is passed all information about a NAND operation (including the amount
+of data to transfer) and replacing all calls to ->cmdfunc() to calls to
+this new ->exec_op() hook. But, in order to do that, we need to have all
+->cmdfunc() calls placed near their associated ->read/write_buf/byte()
+calls.
+
+Modify the core and relevant drivers to make NAND_ECC_CUSTOM_PAGE_ACCESS
+the default case, and remove this flag.
+
+Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
+[miquel.raynal@free-electrons.com: tested, fixed and rebased on nand/next]
+Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
+Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+---
+ drivers/mtd/nand/qcom_nandc.c | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+--- a/drivers/mtd/nand/qcom_nandc.c
++++ b/drivers/mtd/nand/qcom_nandc.c
+@@ -1725,6 +1725,7 @@ static int qcom_nandc_read_page(struct m
+       u8 *data_buf, *oob_buf = NULL;
+       int ret;
++      nand_read_page_op(chip, page, 0, NULL, 0);
+       data_buf = buf;
+       oob_buf = oob_required ? chip->oob_poi : NULL;
+@@ -1750,6 +1751,7 @@ static int qcom_nandc_read_page_raw(stru
+       int i, ret;
+       int read_loc;
++      nand_read_page_op(chip, page, 0, NULL, 0);
+       data_buf = buf;
+       oob_buf = chip->oob_poi;
+@@ -1850,6 +1852,8 @@ static int qcom_nandc_write_page(struct
+       u8 *data_buf, *oob_buf;
+       int i, ret;
++      nand_prog_page_begin_op(chip, page, 0, NULL, 0);
++
+       clear_read_regs(nandc);
+       clear_bam_transaction(nandc);
+@@ -1902,6 +1906,9 @@ static int qcom_nandc_write_page(struct
+       free_descs(nandc);
++      if (!ret)
++              ret = nand_prog_page_end_op(chip);
++
+       return ret;
+ }
+@@ -1916,6 +1923,7 @@ static int qcom_nandc_write_page_raw(str
+       u8 *data_buf, *oob_buf;
+       int i, ret;
++      nand_prog_page_begin_op(chip, page, 0, NULL, 0);
+       clear_read_regs(nandc);
+       clear_bam_transaction(nandc);
+@@ -1970,6 +1978,9 @@ static int qcom_nandc_write_page_raw(str
+       free_descs(nandc);
++      if (!ret)
++              ret = nand_prog_page_end_op(chip);
++
+       return ret;
+ }
diff --git a/target/linux/ipq40xx/patches-4.14/050-0006-mtd-nand-qcom-Add-a-NULL-check-for-devm_kasprintf.patch b/target/linux/ipq40xx/patches-4.14/050-0006-mtd-nand-qcom-Add-a-NULL-check-for-devm_kasprintf.patch
new file mode 100644 (file)
index 0000000..4ddc014
--- /dev/null
@@ -0,0 +1,26 @@
+From 069f05346d01e7298939f16533953cdf52370be3 Mon Sep 17 00:00:00 2001
+From: Fabio Estevam <fabio.estevam@nxp.com>
+Date: Fri, 5 Jan 2018 18:02:55 -0200
+Subject: [PATCH 6/7] mtd: nand: qcom: Add a NULL check for devm_kasprintf()
+
+devm_kasprintf() may fail, so we should better add a NULL check
+and propagate an error on failure.
+
+Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
+Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
+---
+ drivers/mtd/nand/qcom_nandc.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/mtd/nand/qcom_nandc.c
++++ b/drivers/mtd/nand/qcom_nandc.c
+@@ -2639,6 +2639,9 @@ static int qcom_nand_host_init(struct qc
+       nand_set_flash_node(chip, dn);
+       mtd->name = devm_kasprintf(dev, GFP_KERNEL, "qcom_nand.%d", host->cs);
++      if (!mtd->name)
++              return -ENOMEM;
++
+       mtd->owner = THIS_MODULE;
+       mtd->dev.parent = dev;
diff --git a/target/linux/ipq40xx/patches-4.14/059-ARM-cpuidle-Add-cpuidle-support-for-QCOM-cpus.patch b/target/linux/ipq40xx/patches-4.14/059-ARM-cpuidle-Add-cpuidle-support-for-QCOM-cpus.patch
new file mode 100644 (file)
index 0000000..5bd58c8
--- /dev/null
@@ -0,0 +1,29 @@
+From 04ca10340f1b4d92e849724d322a7ca225d11539 Mon Sep 17 00:00:00 2001
+From: Lina Iyer <lina.iyer@linaro.org>
+Date: Wed, 25 Mar 2015 14:25:29 -0600
+Subject: [PATCH 59/69] ARM: cpuidle: Add cpuidle support for QCOM cpus
+
+Define ARM_QCOM_CPUIDLE config item to enable cpuidle support.
+
+Cc: Stephen Boyd <sboyd@codeaurora.org>
+Cc: Arnd Bergmann <arnd@arndb.de>
+Cc: Kevin Hilman <khilman@linaro.org>
+Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
+Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
+---
+ drivers/cpuidle/Kconfig.arm | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/drivers/cpuidle/Kconfig.arm
++++ b/drivers/cpuidle/Kconfig.arm
+@@ -75,3 +75,10 @@ config ARM_MVEBU_V7_CPUIDLE
+       depends on ARCH_MVEBU && !ARM64
+       help
+         Select this to enable cpuidle on Armada 370, 38x and XP processors.
++
++config ARM_QCOM_CPUIDLE
++      bool "CPU Idle Driver for QCOM processors"
++      depends on ARCH_QCOM
++      select ARM_CPUIDLE
++      help
++        Select this to enable cpuidle on QCOM processors.
diff --git a/target/linux/ipq40xx/patches-4.14/069-arm-boot-add-dts-files.patch b/target/linux/ipq40xx/patches-4.14/069-arm-boot-add-dts-files.patch
new file mode 100644 (file)
index 0000000..e830565
--- /dev/null
@@ -0,0 +1,24 @@
+From 8f68331e14dff9a101f2d0e1d6bec84a031f27ee Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Thu, 9 Mar 2017 11:03:18 +0100
+Subject: [PATCH 69/69] arm: boot: add dts files
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/arm/boot/dts/Makefile | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -697,7 +697,11 @@ dtb-$(CONFIG_ARCH_QCOM) += \
+       qcom-apq8074-dragonboard.dtb \
+       qcom-apq8084-ifc6540.dtb \
+       qcom-apq8084-mtp.dtb \
++      qcom-ipq4019-a42.dtb \
+       qcom-ipq4019-ap.dk01.1-c1.dtb \
++      qcom-ipq4019-ap.dk04.1-c1.dtb \
++      qcom-ipq4019-fritz4040.dtb \
++      qcom-ipq4019-gl-b1300.dtb \
+       qcom-ipq8064-ap148.dtb \
+       qcom-msm8660-surf.dtb \
+       qcom-msm8960-cdp.dtb \
diff --git a/target/linux/ipq40xx/patches-4.14/070-qcom-spm-fix-probe-order.patch b/target/linux/ipq40xx/patches-4.14/070-qcom-spm-fix-probe-order.patch
new file mode 100644 (file)
index 0000000..b7e375d
--- /dev/null
@@ -0,0 +1,16 @@
+Check for SCM availability before attempting to use SPM
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+
+--- a/drivers/soc/qcom/spm.c
++++ b/drivers/soc/qcom/spm.c
+@@ -219,6 +219,9 @@ static int __init qcom_cpuidle_init(stru
+       cpumask_t mask;
+       bool use_scm_power_down = false;
++      if (!qcom_scm_is_available())
++              return -EPROBE_DEFER;
++
+       for (i = 0; ; i++) {
+               state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
+               if (!state_node)
diff --git a/target/linux/ipq40xx/patches-4.14/101-ARM-dts-ipq4019-Add-a-few-peripheral-nodes.patch b/target/linux/ipq40xx/patches-4.14/101-ARM-dts-ipq4019-Add-a-few-peripheral-nodes.patch
new file mode 100644 (file)
index 0000000..0f039f2
--- /dev/null
@@ -0,0 +1,188 @@
+From patchwork Mon Jan 29 05:11:16 2018
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+Subject: [02/15] ARM: dts: ipq4019: Add a few peripheral nodes
+From: Sricharan R <sricharan@codeaurora.org>
+X-Patchwork-Id: 10189263
+Message-Id: <1517202689-14212-3-git-send-email-sricharan@codeaurora.org>
+To: robh+dt@kernel.org, robh@kernel.org, mark.rutland@arm.com,
+ linux@armlinux.org.uk, andy.gross@linaro.org, david.brown@linaro.org, 
+ catalin.marinas@arm.com, will.deacon@arm.com, sboyd@codeaurora.org,
+ bjorn.andersson@linaro.org, devicetree@vger.kernel.org,
+ linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
+ linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org
+Cc: sricharan@codeaurora.org
+Date: Mon, 29 Jan 2018 10:41:16 +0530
+
+Now with the driver updates for some peripherals being there,
+add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
+peripheral support.
+
+Signed-off-by: Sricharan R <sricharan@codeaurora.org>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 134 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 134 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -25,7 +25,9 @@
+       aliases {
+               spi0 = &spi_0;
++              spi1 = &spi_1;
+               i2c0 = &i2c_0;
++              i2c1 = &i2c_1;
+       };
+       cpus {
+@@ -190,6 +192,22 @@
+                       clock-names = "core", "iface";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
++                      dmas = <&blsp_dma 5>, <&blsp_dma 4>;
++                      dma-names = "rx", "tx";
++                      status = "disabled";
++              };
++
++              spi_1: spi@78b6000 { /* BLSP1 QUP2 */
++                      compatible = "qcom,spi-qup-v2.2.1";
++                      reg = <0x78b6000 0x600>;
++                      interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
++                              <&gcc GCC_BLSP1_AHB_CLK>;
++                      clock-names = "core", "iface";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      dmas = <&blsp_dma 7>, <&blsp_dma 6>;
++                      dma-names = "rx", "tx";
+                       status = "disabled";
+               };
+@@ -202,9 +220,24 @@
+                       clock-names = "iface", "core";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
++                      dmas = <&blsp_dma 9>, <&blsp_dma 8>;
++                      dma-names = "rx", "tx";
+                       status = "disabled";
+               };
++              i2c_1: i2c@78b8000 { /* BLSP1 QUP4 */
++                      compatible = "qcom,i2c-qup-v2.2.1";
++                      reg = <0x78b8000 0x600>;
++                      interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&gcc GCC_BLSP1_AHB_CLK>,
++                               <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
++                      clock-names = "iface", "core";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      dmas = <&blsp_dma 11>, <&blsp_dma 10>;
++                      dma-names = "rx", "tx";
++                      status = "disabled";
++              };
+               cryptobam: dma@8e04000 {
+                       compatible = "qcom,bam-v1.7.0";
+@@ -311,6 +344,101 @@
+                       reg = <0x4ab000 0x4>;
+               };
++              pcie0: pci@40000000 {
++                      compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
++                      reg =  <0x40000000 0xf1d
++                              0x40000f20 0xa8
++                              0x80000 0x2000
++                              0x40100000 0x1000>;
++                      reg-names = "dbi", "elbi", "parf", "config";
++                      device_type = "pci";
++                      linux,pci-domain = <0>;
++                      bus-range = <0x00 0xff>;
++                      num-lanes = <1>;
++                      #address-cells = <3>;
++                      #size-cells = <2>;
++
++                      ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
++                                0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
++
++                      interrupts = <GIC_SPI 141 IRQ_TYPE_NONE>;
++                      interrupt-names = "msi";
++                      #interrupt-cells = <1>;
++                      interrupt-map-mask = <0 0 0 0x7>;
++                      interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
++                                      <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
++                                      <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
++                                      <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
++                      clocks = <&gcc GCC_PCIE_AHB_CLK>,
++                               <&gcc GCC_PCIE_AXI_M_CLK>,
++                               <&gcc GCC_PCIE_AXI_S_CLK>;
++                      clock-names = "aux",
++                                    "master_bus",
++                                    "slave_bus";
++
++                      resets = <&gcc PCIE_AXI_M_ARES>,
++                               <&gcc PCIE_AXI_S_ARES>,
++                               <&gcc PCIE_PIPE_ARES>,
++                               <&gcc PCIE_AXI_M_VMIDMT_ARES>,
++                               <&gcc PCIE_AXI_S_XPU_ARES>,
++                               <&gcc PCIE_PARF_XPU_ARES>,
++                               <&gcc PCIE_PHY_ARES>,
++                               <&gcc PCIE_AXI_M_STICKY_ARES>,
++                               <&gcc PCIE_PIPE_STICKY_ARES>,
++                               <&gcc PCIE_PWR_ARES>,
++                               <&gcc PCIE_AHB_ARES>,
++                               <&gcc PCIE_PHY_AHB_ARES>;
++                      reset-names = "axi_m",
++                                    "axi_s",
++                                    "pipe",
++                                    "axi_m_vmid",
++                                    "axi_s_xpu",
++                                    "parf",
++                                    "phy",
++                                    "axi_m_sticky",
++                                    "pipe_sticky",
++                                    "pwr",
++                                    "ahb",
++                                    "phy_ahb";
++
++                      status = "disabled";
++              };
++
++              qpic_bam: dma@7984000 {
++                      compatible = "qcom,bam-v1.7.0";
++                      reg = <0x7984000 0x1a000>;
++                      interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&gcc GCC_QPIC_CLK>;
++                      clock-names = "bam_clk";
++                      #dma-cells = <1>;
++                      qcom,ee = <0>;
++                      status = "disabled";
++              };
++
++              nand: qpic-nand@79b0000 {
++                      compatible = "qcom,ipq4019-nand";
++                      reg = <0x79b0000 0x1000>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      clocks = <&gcc GCC_QPIC_CLK>,
++                               <&gcc GCC_QPIC_AHB_CLK>;
++                      clock-names = "core", "aon";
++
++                      dmas = <&qpic_bam 0>,
++                             <&qpic_bam 1>,
++                             <&qpic_bam 2>;
++                      dma-names = "tx", "rx", "cmd";
++                      status = "disabled";
++
++                      nand@0 {
++                              reg = <0>;
++
++                              nand-ecc-strength = <4>;
++                              nand-ecc-step-size = <512>;
++                              nand-bus-width = <8>;
++                      };
++              };
++
+               wifi0: wifi@a000000 {
+                       compatible = "qcom,ipq4019-wifi";
+                       reg = <0xa000000 0x200000>;
diff --git a/target/linux/ipq40xx/patches-4.14/102-ARM-dts-ipq4019-fix-PCI-range.patch b/target/linux/ipq40xx/patches-4.14/102-ARM-dts-ipq4019-fix-PCI-range.patch
new file mode 100644 (file)
index 0000000..eaccb00
--- /dev/null
@@ -0,0 +1,23 @@
+From 561a7e69d2811f236266ff9222a1e683ebf8b9e0 Mon Sep 17 00:00:00 2001
+From: Mathias Kresin <dev@kresin.me>
+Date: Thu, 1 Mar 2018 20:50:29 +0100
+Subject: [PATCH] ARM: dts: ipq4019: fix PCI range
+
+The PCI range is invalid and PCI attached devices doen't work.
+
+Signed-off-by: Mathias Kresin <dev@kresin.me>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -359,7 +359,7 @@
+                       #size-cells = <2>;
+                       ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
+-                                0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
++                                0x82000000 0 0x40300000 0x40300000 0 0x400000>;
+                       interrupts = <GIC_SPI 141 IRQ_TYPE_NONE>;
+                       interrupt-names = "msi";
diff --git a/target/linux/ipq40xx/patches-4.14/104-mtd-nand-add-Winbond-manufacturer-and-chip.patch b/target/linux/ipq40xx/patches-4.14/104-mtd-nand-add-Winbond-manufacturer-and-chip.patch
new file mode 100644 (file)
index 0000000..295bc16
--- /dev/null
@@ -0,0 +1,38 @@
+From 07b6d0cdbbda8c917480eceaec668f09e4cf24a5 Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Mon, 14 Nov 2016 23:49:22 +0100
+Subject: [PATCH] mtd: nand: add Winbond manufacturer and chip
+
+This patch adds the W25N01GV NAND to the table of
+known devices. Without this patch the device gets detected:
+
+nand: device found, Manufacturer ID: 0xef, Chip ID: 0xaa
+nand: Unknown NAND 256MiB 1,8V 8-bit
+nand: 256 MiB, SLC, erase size: 64 KiB, page size: 1024, OOB size : 16
+
+Whereas the u-boot identifies it as:
+spi_nand: spi_nand_flash_probe SF NAND ID 00:ef:aa:21
+SF: Detected W25N01GV with page size 2 KiB, total 128 MiB
+
+Due to the page size discrepancy, it's impossible to attach
+ubi volumes on the device.
+
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+---
+ drivers/mtd/nand/nand_ids.c | 4 ++++
+ include/linux/mtd/nand.h    | 1 +
+ 2 files changed, 5 insertions(+)
+
+--- a/drivers/mtd/nand/nand_ids.c
++++ b/drivers/mtd/nand/nand_ids.c
+@@ -54,6 +54,10 @@ struct nand_flash_dev nand_flash_ids[] =
+               { .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
+                 SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
+                 NAND_ECC_INFO(40, SZ_1K), 4 },
++      {"W25N01GV 1G 3.3V 8-bit",
++              { .id = {0xef, 0xaa} },
++                SZ_2K, SZ_128, SZ_128K, NAND_NO_SUBPAGE_WRITE,
++                2, 64, NAND_ECC_INFO(1, SZ_512) },
+       LEGACY_ID_NAND("NAND 4MiB 5V 8-bit",   0x6B, 4, SZ_8K, SP_OPTIONS),
+       LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
diff --git a/target/linux/ipq40xx/patches-4.14/105-mtd-nor-add-mx25l25635f.patch b/target/linux/ipq40xx/patches-4.14/105-mtd-nor-add-mx25l25635f.patch
new file mode 100644 (file)
index 0000000..ea9d911
--- /dev/null
@@ -0,0 +1,22 @@
+Subject: mtd: spi-nor: add mx25l25635f with SECT_4K
+
+This patch fixes an issue with the creation of the
+ubi volume on the AVM FRITZ!Box 4040. The mx25l25635f
+and mx25l25635e support SECT_4K which will set the
+erase size to 4K. This is used by ubi to calculate
+VID header offsets. Without this, uboot and linux
+disagrees about the layout and refuse to attach
+the ubi volume created by the other.
+
+---
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -1023,7 +1023,7 @@ static const struct flash_info spi_nor_i
+       { "mx25u6435f",  INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
+       { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
+       { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
+-      { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
++      { "mx25l25635f", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SECT_4K) },
+       { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
+       { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
+       { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
diff --git a/target/linux/ipq40xx/patches-4.14/305-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch b/target/linux/ipq40xx/patches-4.14/305-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch
new file mode 100644 (file)
index 0000000..1d08b9d
--- /dev/null
@@ -0,0 +1,109 @@
+From 6a6c067b7ce2b3de4efbafddc134afbea3ddc1a3 Mon Sep 17 00:00:00 2001
+From: Matthew McClintock <mmcclint@codeaurora.org>
+Date: Fri, 8 Apr 2016 15:26:10 -0500
+Subject: [PATCH] qcom: ipq4019: use v2 of the kpss bringup mechanism
+
+v1 was the incorrect choice here and sometimes the board
+would not come up properly.
+
+Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+---
+Changes:
+       - moved L2-Cache to be a subnode of cpu0
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 32 ++++++++++++++++++++++++--------
+ 1 file changed, 24 insertions(+), 8 deletions(-)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -36,19 +36,27 @@
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+-                      enable-method = "qcom,kpss-acc-v1";
++                      enable-method = "qcom,kpss-acc-v2";
++                      next-level-cache = <&L2>;
+                       qcom,acc = <&acc0>;
+                       qcom,saw = <&saw0>;
+                       reg = <0x0>;
+                       clocks = <&gcc GCC_APPS_CLK_SRC>;
+                       clock-frequency = <0>;
+                       operating-points-v2 = <&cpu0_opp_table>;
++
++                      L2: l2-cache {
++                              compatible = "qcom,arch-cache";
++                              cache-level = <2>;
++                              qcom,saw = <&saw_l2>;
++                      };
+               };
+               cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+-                      enable-method = "qcom,kpss-acc-v1";
++                      enable-method = "qcom,kpss-acc-v2";
++                      next-level-cache = <&L2>;
+                       qcom,acc = <&acc1>;
+                       qcom,saw = <&saw1>;
+                       reg = <0x1>;
+@@ -60,7 +68,8 @@
+               cpu@2 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+-                      enable-method = "qcom,kpss-acc-v1";
++                      enable-method = "qcom,kpss-acc-v2";
++                      next-level-cache = <&L2>;
+                       qcom,acc = <&acc2>;
+                       qcom,saw = <&saw2>;
+                       reg = <0x2>;
+@@ -72,7 +81,8 @@
+               cpu@3 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+-                      enable-method = "qcom,kpss-acc-v1";
++                      enable-method = "qcom,kpss-acc-v2";
++                      next-level-cache = <&L2>;
+                       qcom,acc = <&acc3>;
+                       qcom,saw = <&saw3>;
+                       reg = <0x3>;
+@@ -264,22 +274,22 @@
+               };
+                 acc0: clock-controller@b088000 {
+-                        compatible = "qcom,kpss-acc-v1";
++                        compatible = "qcom,kpss-acc-v2";
+                         reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
+                 };
+                 acc1: clock-controller@b098000 {
+-                        compatible = "qcom,kpss-acc-v1";
++                        compatible = "qcom,kpss-acc-v2";
+                         reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
+                 };
+                 acc2: clock-controller@b0a8000 {
+-                        compatible = "qcom,kpss-acc-v1";
++                        compatible = "qcom,kpss-acc-v2";
+                         reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
+                 };
+                 acc3: clock-controller@b0b8000 {
+-                        compatible = "qcom,kpss-acc-v1";
++                        compatible = "qcom,kpss-acc-v2";
+                         reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
+                 };
+@@ -307,6 +317,12 @@
+                         regulator;
+                 };
++              saw_l2: regulator@b012000 {
++                      compatible = "qcom,saw2";
++                      reg = <0xb012000 0x1000>;
++                      regulator;
++              };
++
+               serial@78af000 {
+                       compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+                       reg = <0x78af000 0x200>;
diff --git a/target/linux/ipq40xx/patches-4.14/306-qcom-ipq4019-add-USB-nodes-to-ipq4019-SoC-device-tre.patch b/target/linux/ipq40xx/patches-4.14/306-qcom-ipq4019-add-USB-nodes-to-ipq4019-SoC-device-tre.patch
new file mode 100644 (file)
index 0000000..cd0f14e
--- /dev/null
@@ -0,0 +1,130 @@
+From ea5f4d6f4716f3a0bb4fc3614b7a0e8c0df1cb81 Mon Sep 17 00:00:00 2001
+From: Matthew McClintock <mmcclint@codeaurora.org>
+Date: Thu, 17 Mar 2016 16:22:28 -0500
+Subject: [PATCH] qcom: ipq4019: add USB nodes to ipq4019 SoC device tree
+
+This adds the SoC nodes to the ipq4019 device tree and
+enable it for the DK01.1 board.
+
+Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+---
+Changes:
+       - replaced space with tab
+       - added sleep and mock_utmi clocks
+       - added registers for usb2 and usb3 parent node
+       - changed compatible to qca,ipa4019-dwc3
+       - updated usb2 and usb3 names
+         (included the reg - in case they become necessary later)
+---
+ arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++
+ arch/arm/boot/dts/qcom-ipq4019.dtsi           | 71 +++++++++++++++++++++++++++
+ 2 files changed, 91 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+@@ -101,5 +101,25 @@
+               wifi@a800000 {
+                       status = "ok";
+               };
++
++              usb3_ss_phy: ssphy@9a000 {
++                      status = "ok";
++              };
++
++              usb3_hs_phy: hsphy@a6000 {
++                      status = "ok";
++              };
++
++              usb3: usb3@8af8800 {
++                      status = "ok";
++              };
++
++              usb2_hs_phy: hsphy@a8000 {
++                      status = "ok";
++              };
++
++              usb2: usb2@60f8800 {
++                      status = "ok";
++              };
+       };
+ };
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -538,5 +538,76 @@
+                                         "legacy";
+                       status = "disabled";
+               };
++
++              usb3_ss_phy: ssphy@9a000 {
++                      compatible = "qca,uni-ssphy";
++                      reg = <0x9a000 0x800>;
++                      reg-names = "phy_base";
++                      resets = <&gcc USB3_UNIPHY_PHY_ARES>;
++                      reset-names = "por_rst";
++                      status = "disabled";
++              };
++
++              usb3_hs_phy: hsphy@a6000 {
++                      compatible = "qca,baldur-usb3-hsphy";
++                      reg = <0xa6000 0x40>;
++                      reg-names = "phy_base";
++                      resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
++                      reset-names = "por_rst", "srif_rst";
++                      status = "disabled";
++              };
++
++              usb3@8af8800 {
++                      compatible = "qca,ipq4019-dwc3";
++                      reg = <0x8af8800 0x100>;
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      clocks = <&gcc GCC_USB3_MASTER_CLK>,
++                               <&gcc GCC_USB3_SLEEP_CLK>,
++                               <&gcc GCC_USB3_MOCK_UTMI_CLK>;
++                      clock-names = "master", "sleep", "mock_utmi";
++                      ranges;
++                      status = "disabled";
++
++                      dwc3@8a00000 {
++                              compatible = "snps,dwc3";
++                              reg = <0x8a00000 0xf8000>;
++                              interrupts = <0 132 0>;
++                              usb-phy = <&usb3_hs_phy>, <&usb3_ss_phy>;
++                              phy-names = "usb2-phy", "usb3-phy";
++                              dr_mode = "host";
++                      };
++              };
++
++              usb2_hs_phy: hsphy@a8000 {
++                      compatible = "qca,baldur-usb2-hsphy";
++                      reg = <0xa8000 0x40>;
++                      reg-names = "phy_base";
++                      resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
++                      reset-names = "por_rst", "srif_rst";
++                      status = "disabled";
++              };
++
++              usb2@60f8800 {
++                      compatible = "qca,ipq4019-dwc3";
++                      reg = <0x60f8800 0x100>;
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      clocks = <&gcc GCC_USB2_MASTER_CLK>,
++                               <&gcc GCC_USB2_SLEEP_CLK>,
++                               <&gcc GCC_USB2_MOCK_UTMI_CLK>;
++                      clock-names = "master", "sleep", "mock_utmi";
++                      ranges;
++                      status = "disabled";
++
++                      dwc3@6000000 {
++                              compatible = "snps,dwc3";
++                              reg = <0x6000000 0xf8000>;
++                              interrupts = <0 136 0>;
++                              usb-phy = <&usb2_hs_phy>;
++                              phy-names = "usb2-phy";
++                              dr_mode = "host";
++                      };
++              };
+       };
+ };
diff --git a/target/linux/ipq40xx/patches-4.14/307-ARM-qcom-Add-IPQ4019-SoC-support.patch b/target/linux/ipq40xx/patches-4.14/307-ARM-qcom-Add-IPQ4019-SoC-support.patch
new file mode 100644 (file)
index 0000000..1dc1c97
--- /dev/null
@@ -0,0 +1,35 @@
+From e7748d641ae37081e2034869491f1629461ae13c Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Sat, 19 Nov 2016 00:58:18 +0100
+Subject: [PATCH] ARM: qcom: Add IPQ4019 SoC support
+
+Add support for the Qualcomm Atheros IPQ4019 SoC.
+
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+---
+ arch/arm/Makefile          | 1 +
+ arch/arm/mach-qcom/Kconfig | 5 +++++
+ 2 files changed, 6 insertions(+)
+
+--- a/arch/arm/Makefile
++++ b/arch/arm/Makefile
+@@ -149,6 +149,7 @@ textofs-$(CONFIG_SA1111) := 0x00208000
+ endif
+ textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
+ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
++textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000
+ textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
+ # Machine directory name.  This list is sorted alphanumerically
+--- a/arch/arm/mach-qcom/Kconfig
++++ b/arch/arm/mach-qcom/Kconfig
+@@ -27,4 +27,9 @@ config ARCH_MDM9615
+       bool "Enable support for MDM9615"
+       select CLKSRC_QCOM
++config ARCH_IPQ40XX
++      bool "Enable support for IPQ40XX"
++      select CLKSRC_QCOM
++      select HAVE_ARM_ARCH_TIMER
++
+ endif
diff --git a/target/linux/ipq40xx/patches-4.14/310-msm-adhoc-bus-support.patch b/target/linux/ipq40xx/patches-4.14/310-msm-adhoc-bus-support.patch
new file mode 100644 (file)
index 0000000..cd9fd89
--- /dev/null
@@ -0,0 +1,11026 @@
+From: Christian Lamparter <chunkeey@googlemail.com>
+Subject: BUS: add MSM_BUS
+--- a/drivers/bus/Makefile
++++ b/drivers/bus/Makefile
+@@ -11,6 +11,7 @@ obj-$(CONFIG_BRCMSTB_GISB_ARB)       += brcmst
+ obj-$(CONFIG_IMX_WEIM)                += imx-weim.o
+ obj-$(CONFIG_MIPS_CDMM)               += mips_cdmm.o
+ obj-$(CONFIG_MVEBU_MBUS)      += mvebu-mbus.o
++obj-$(CONFIG_BUS_TOPOLOGY_ADHOC)+= msm_bus/
+ # Interconnect bus driver for OMAP SoCs.
+ obj-$(CONFIG_OMAP_INTERCONNECT)       += omap_l3_smx.o omap_l3_noc.o
+--- a/drivers/bus/Kconfig
++++ b/drivers/bus/Kconfig
+@@ -93,6 +93,8 @@ config MVEBU_MBUS
+         Driver needed for the MBus configuration on Marvell EBU SoCs
+         (Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP).
++source "drivers/bus/msm_bus/Kconfig"
++
+ config OMAP_INTERCONNECT
+       tristate "OMAP INTERCONNECT DRIVER"
+       depends on ARCH_OMAP2PLUS
+--- /dev/null
++++ b/include/dt-bindings/msm/msm-bus-ids.h
+@@ -0,0 +1,869 @@
++/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 and
++ * only version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef __MSM_BUS_IDS_H
++#define __MSM_BUS_IDS_H
++
++/* Topology related enums */
++#define       MSM_BUS_FAB_DEFAULT 0
++#define       MSM_BUS_FAB_APPSS 0
++#define       MSM_BUS_FAB_SYSTEM 1024
++#define       MSM_BUS_FAB_MMSS 2048
++#define       MSM_BUS_FAB_SYSTEM_FPB 3072
++#define       MSM_BUS_FAB_CPSS_FPB 4096
++
++#define       MSM_BUS_FAB_BIMC 0
++#define       MSM_BUS_FAB_SYS_NOC 1024
++#define       MSM_BUS_FAB_MMSS_NOC 2048
++#define       MSM_BUS_FAB_OCMEM_NOC 3072
++#define       MSM_BUS_FAB_PERIPH_NOC 4096
++#define       MSM_BUS_FAB_CONFIG_NOC 5120
++#define       MSM_BUS_FAB_OCMEM_VNOC 6144
++#define       MSM_BUS_FAB_MMSS_AHB 2049
++#define       MSM_BUS_FAB_A0_NOC 6145
++#define       MSM_BUS_FAB_A1_NOC 6146
++#define       MSM_BUS_FAB_A2_NOC 6147
++
++#define       MSM_BUS_MASTER_FIRST 1
++#define       MSM_BUS_MASTER_AMPSS_M0 1
++#define       MSM_BUS_MASTER_AMPSS_M1 2
++#define       MSM_BUS_APPSS_MASTER_FAB_MMSS 3
++#define       MSM_BUS_APPSS_MASTER_FAB_SYSTEM 4
++#define       MSM_BUS_SYSTEM_MASTER_FAB_APPSS 5
++#define       MSM_BUS_MASTER_SPS 6
++#define       MSM_BUS_MASTER_ADM_PORT0 7
++#define       MSM_BUS_MASTER_ADM_PORT1 8
++#define       MSM_BUS_SYSTEM_MASTER_ADM1_PORT0 9
++#define       MSM_BUS_MASTER_ADM1_PORT1 10
++#define       MSM_BUS_MASTER_LPASS_PROC 11
++#define       MSM_BUS_MASTER_MSS_PROCI 12
++#define       MSM_BUS_MASTER_MSS_PROCD 13
++#define       MSM_BUS_MASTER_MSS_MDM_PORT0 14
++#define       MSM_BUS_MASTER_LPASS 15
++#define       MSM_BUS_SYSTEM_MASTER_CPSS_FPB 16
++#define       MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB 17
++#define       MSM_BUS_SYSTEM_MASTER_MMSS_FPB 18
++#define       MSM_BUS_MASTER_ADM1_CI 19
++#define       MSM_BUS_MASTER_ADM0_CI 20
++#define       MSM_BUS_MASTER_MSS_MDM_PORT1 21
++#define       MSM_BUS_MASTER_MDP_PORT0 22
++#define       MSM_BUS_MASTER_MDP_PORT1 23
++#define       MSM_BUS_MMSS_MASTER_ADM1_PORT0 24
++#define       MSM_BUS_MASTER_ROTATOR 25
++#define       MSM_BUS_MASTER_GRAPHICS_3D 26
++#define       MSM_BUS_MASTER_JPEG_DEC 27
++#define       MSM_BUS_MASTER_GRAPHICS_2D_CORE0 28
++#define       MSM_BUS_MASTER_VFE 29
++#define       MSM_BUS_MASTER_VPE 30
++#define       MSM_BUS_MASTER_JPEG_ENC 31
++#define       MSM_BUS_MASTER_GRAPHICS_2D_CORE1 32
++#define       MSM_BUS_MMSS_MASTER_APPS_FAB 33
++#define       MSM_BUS_MASTER_HD_CODEC_PORT0 34
++#define       MSM_BUS_MASTER_HD_CODEC_PORT1 35
++#define       MSM_BUS_MASTER_SPDM 36
++#define       MSM_BUS_MASTER_RPM 37
++#define       MSM_BUS_MASTER_MSS 38
++#define       MSM_BUS_MASTER_RIVA 39
++#define       MSM_BUS_MASTER_SNOC_VMEM 40
++#define       MSM_BUS_MASTER_MSS_SW_PROC 41
++#define       MSM_BUS_MASTER_MSS_FW_PROC 42
++#define       MSM_BUS_MASTER_HMSS 43
++#define       MSM_BUS_MASTER_GSS_NAV 44
++#define       MSM_BUS_MASTER_PCIE 45
++#define       MSM_BUS_MASTER_SATA 46
++#define       MSM_BUS_MASTER_CRYPTO 47
++#define       MSM_BUS_MASTER_VIDEO_CAP 48
++#define       MSM_BUS_MASTER_GRAPHICS_3D_PORT1 49
++#define       MSM_BUS_MASTER_VIDEO_ENC 50
++#define       MSM_BUS_MASTER_VIDEO_DEC 51
++#define       MSM_BUS_MASTER_LPASS_AHB 52
++#define       MSM_BUS_MASTER_QDSS_BAM 53
++#define       MSM_BUS_MASTER_SNOC_CFG 54
++#define       MSM_BUS_MASTER_CRYPTO_CORE0 55
++#define       MSM_BUS_MASTER_CRYPTO_CORE1 56
++#define       MSM_BUS_MASTER_MSS_NAV 57
++#define       MSM_BUS_MASTER_OCMEM_DMA 58
++#define       MSM_BUS_MASTER_WCSS 59
++#define       MSM_BUS_MASTER_QDSS_ETR 60
++#define       MSM_BUS_MASTER_USB3 61
++#define       MSM_BUS_MASTER_JPEG 62
++#define       MSM_BUS_MASTER_VIDEO_P0 63
++#define       MSM_BUS_MASTER_VIDEO_P1 64
++#define       MSM_BUS_MASTER_MSS_PROC 65
++#define       MSM_BUS_MASTER_JPEG_OCMEM 66
++#define       MSM_BUS_MASTER_MDP_OCMEM 67
++#define       MSM_BUS_MASTER_VIDEO_P0_OCMEM 68
++#define       MSM_BUS_MASTER_VIDEO_P1_OCMEM 69
++#define       MSM_BUS_MASTER_VFE_OCMEM 70
++#define       MSM_BUS_MASTER_CNOC_ONOC_CFG 71
++#define       MSM_BUS_MASTER_RPM_INST 72
++#define       MSM_BUS_MASTER_RPM_DATA 73
++#define       MSM_BUS_MASTER_RPM_SYS 74
++#define       MSM_BUS_MASTER_DEHR 75
++#define       MSM_BUS_MASTER_QDSS_DAP 76
++#define       MSM_BUS_MASTER_TIC 77
++#define       MSM_BUS_MASTER_SDCC_1 78
++#define       MSM_BUS_MASTER_SDCC_3 79
++#define       MSM_BUS_MASTER_SDCC_4 80
++#define       MSM_BUS_MASTER_SDCC_2 81
++#define       MSM_BUS_MASTER_TSIF 82
++#define       MSM_BUS_MASTER_BAM_DMA 83
++#define       MSM_BUS_MASTER_BLSP_2 84
++#define       MSM_BUS_MASTER_USB_HSIC 85
++#define       MSM_BUS_MASTER_BLSP_1 86
++#define       MSM_BUS_MASTER_USB_HS 87
++#define       MSM_BUS_MASTER_PNOC_CFG 88
++#define       MSM_BUS_MASTER_V_OCMEM_GFX3D 89
++#define       MSM_BUS_MASTER_IPA 90
++#define       MSM_BUS_MASTER_QPIC 91
++#define       MSM_BUS_MASTER_MDPE 92
++#define       MSM_BUS_MASTER_USB_HS2 93
++#define       MSM_BUS_MASTER_VPU 94
++#define       MSM_BUS_MASTER_UFS 95
++#define       MSM_BUS_MASTER_BCAST 96
++#define       MSM_BUS_MASTER_CRYPTO_CORE2 97
++#define       MSM_BUS_MASTER_EMAC 98
++#define       MSM_BUS_MASTER_VPU_1 99
++#define       MSM_BUS_MASTER_PCIE_1 100
++#define       MSM_BUS_MASTER_USB3_1 101
++#define       MSM_BUS_MASTER_CNOC_MNOC_MMSS_CFG 102
++#define       MSM_BUS_MASTER_CNOC_MNOC_CFG 103
++#define       MSM_BUS_MASTER_TCU_0 104
++#define       MSM_BUS_MASTER_TCU_1 105
++#define       MSM_BUS_MASTER_CPP 106
++#define       MSM_BUS_MASTER_AUDIO 107
++#define       MSM_BUS_MASTER_PCIE_2 108
++#define       MSM_BUS_MASTER_BLSP_BAM 109
++#define       MSM_BUS_MASTER_USB2_BAM 110
++#define       MSM_BUS_MASTER_ADDS_DMA0 111
++#define       MSM_BUS_MASTER_ADDS_DMA1 112
++#define       MSM_BUS_MASTER_ADDS_DMA2 113
++#define       MSM_BUS_MASTER_ADDS_DMA3 114
++#define       MSM_BUS_MASTER_QPIC_BAM 115
++#define       MSM_BUS_MASTER_SDCC_BAM 116
++#define       MSM_BUS_MASTER_DDRC_SNOC 117
++#define       MSM_BUS_MASTER_WSS_0  118
++#define       MSM_BUS_MASTER_WSS_1  119
++#define       MSM_BUS_MASTER_ESS 120
++#define       MSM_BUS_MASTER_QDSS_BAMNDP 121
++#define       MSM_BUS_MASTER_QDSS_SNOC_CFG 122
++#define       MSM_BUS_MASTER_LAST 130
++
++#define       MSM_BUS_SYSTEM_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB
++#define       MSM_BUS_CPSS_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_CPSS_FPB
++
++#define       MSM_BUS_SNOC_MM_INT_0 10000
++#define       MSM_BUS_SNOC_MM_INT_1 10001
++#define       MSM_BUS_SNOC_MM_INT_2 10002
++#define       MSM_BUS_SNOC_MM_INT_BIMC 10003
++#define       MSM_BUS_SNOC_INT_0 10004
++#define       MSM_BUS_SNOC_INT_1 10005
++#define       MSM_BUS_SNOC_INT_BIMC 10006
++#define       MSM_BUS_SNOC_BIMC_0_MAS 10007
++#define       MSM_BUS_SNOC_BIMC_1_MAS 10008
++#define       MSM_BUS_SNOC_QDSS_INT 10009
++#define       MSM_BUS_PNOC_SNOC_MAS 10010
++#define       MSM_BUS_PNOC_SNOC_SLV 10011
++#define       MSM_BUS_PNOC_INT_0 10012
++#define       MSM_BUS_PNOC_INT_1 10013
++#define       MSM_BUS_PNOC_M_0 10014
++#define       MSM_BUS_PNOC_M_1 10015
++#define       MSM_BUS_BIMC_SNOC_MAS 10016
++#define       MSM_BUS_BIMC_SNOC_SLV 10017
++#define       MSM_BUS_PNOC_SLV_0 10018
++#define       MSM_BUS_PNOC_SLV_1 10019
++#define       MSM_BUS_PNOC_SLV_2 10020
++#define       MSM_BUS_PNOC_SLV_3 10021
++#define       MSM_BUS_PNOC_SLV_4 10022
++#define       MSM_BUS_PNOC_SLV_8 10023
++#define       MSM_BUS_PNOC_SLV_9 10024
++#define       MSM_BUS_SNOC_BIMC_0_SLV 10025
++#define       MSM_BUS_SNOC_BIMC_1_SLV 10026
++#define       MSM_BUS_MNOC_BIMC_MAS 10027
++#define       MSM_BUS_MNOC_BIMC_SLV 10028
++#define       MSM_BUS_BIMC_MNOC_MAS 10029
++#define       MSM_BUS_BIMC_MNOC_SLV 10030
++#define       MSM_BUS_SNOC_BIMC_MAS 10031
++#define       MSM_BUS_SNOC_BIMC_SLV 10032
++#define       MSM_BUS_CNOC_SNOC_MAS 10033
++#define       MSM_BUS_CNOC_SNOC_SLV 10034
++#define       MSM_BUS_SNOC_CNOC_MAS 10035
++#define       MSM_BUS_SNOC_CNOC_SLV 10036
++#define       MSM_BUS_OVNOC_SNOC_MAS 10037
++#define       MSM_BUS_OVNOC_SNOC_SLV 10038
++#define       MSM_BUS_SNOC_OVNOC_MAS 10039
++#define       MSM_BUS_SNOC_OVNOC_SLV 10040
++#define       MSM_BUS_SNOC_PNOC_MAS 10041
++#define       MSM_BUS_SNOC_PNOC_SLV 10042
++#define       MSM_BUS_BIMC_INT_APPS_EBI 10043
++#define       MSM_BUS_BIMC_INT_APPS_SNOC 10044
++#define       MSM_BUS_SNOC_BIMC_2_MAS 10045
++#define       MSM_BUS_SNOC_BIMC_2_SLV 10046
++#define       MSM_BUS_PNOC_SLV_5 10047
++#define       MSM_BUS_PNOC_SLV_6 10048
++#define       MSM_BUS_PNOC_INT_2 10049
++#define       MSM_BUS_PNOC_INT_3 10050
++#define       MSM_BUS_PNOC_INT_4 10051
++#define       MSM_BUS_PNOC_INT_5 10052
++#define       MSM_BUS_PNOC_INT_6 10053
++#define       MSM_BUS_PNOC_INT_7 10054
++#define       MSM_BUS_BIMC_SNOC_1_MAS 10055
++#define       MSM_BUS_BIMC_SNOC_1_SLV 10056
++#define       MSM_BUS_PNOC_A1NOC_MAS 10057
++#define       MSM_BUS_PNOC_A1NOC_SLV 10058
++#define       MSM_BUS_CNOC_A1NOC_MAS 10059
++#define       MSM_BUS_A0NOC_SNOC_MAS 10060
++#define       MSM_BUS_A0NOC_SNOC_SLV 10061
++#define       MSM_BUS_A1NOC_SNOC_SLV 10062
++#define       MSM_BUS_A1NOC_SNOC_MAS 10063
++#define       MSM_BUS_A2NOC_SNOC_MAS 10064
++#define       MSM_BUS_A2NOC_SNOC_SLV 10065
++#define       MSM_BUS_PNOC_SLV_7 10066
++#define       MSM_BUS_INT_LAST 10067
++
++#define       MSM_BUS_SLAVE_FIRST 512
++#define       MSM_BUS_SLAVE_EBI_CH0 512
++#define       MSM_BUS_SLAVE_EBI_CH1 513
++#define       MSM_BUS_SLAVE_AMPSS_L2 514
++#define       MSM_BUS_APPSS_SLAVE_FAB_MMSS 515
++#define       MSM_BUS_APPSS_SLAVE_FAB_SYSTEM 516
++#define       MSM_BUS_SYSTEM_SLAVE_FAB_APPS 517
++#define       MSM_BUS_SLAVE_SPS 518
++#define       MSM_BUS_SLAVE_SYSTEM_IMEM 519
++#define       MSM_BUS_SLAVE_AMPSS 520
++#define       MSM_BUS_SLAVE_MSS 521
++#define       MSM_BUS_SLAVE_LPASS 522
++#define       MSM_BUS_SYSTEM_SLAVE_CPSS_FPB 523
++#define       MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB 524
++#define       MSM_BUS_SYSTEM_SLAVE_MMSS_FPB 525
++#define       MSM_BUS_SLAVE_CORESIGHT 526
++#define       MSM_BUS_SLAVE_RIVA 527
++#define       MSM_BUS_SLAVE_SMI 528
++#define       MSM_BUS_MMSS_SLAVE_FAB_APPS 529
++#define       MSM_BUS_MMSS_SLAVE_FAB_APPS_1 530
++#define       MSM_BUS_SLAVE_MM_IMEM 531
++#define       MSM_BUS_SLAVE_CRYPTO 532
++#define       MSM_BUS_SLAVE_SPDM 533
++#define       MSM_BUS_SLAVE_RPM 534
++#define       MSM_BUS_SLAVE_RPM_MSG_RAM 535
++#define       MSM_BUS_SLAVE_MPM 536
++#define       MSM_BUS_SLAVE_PMIC1_SSBI1_A 537
++#define       MSM_BUS_SLAVE_PMIC1_SSBI1_B 538
++#define       MSM_BUS_SLAVE_PMIC1_SSBI1_C 539
++#define       MSM_BUS_SLAVE_PMIC2_SSBI2_A 540
++#define       MSM_BUS_SLAVE_PMIC2_SSBI2_B 541
++#define       MSM_BUS_SLAVE_GSBI1_UART 542
++#define       MSM_BUS_SLAVE_GSBI2_UART 543
++#define       MSM_BUS_SLAVE_GSBI3_UART 544
++#define       MSM_BUS_SLAVE_GSBI4_UART 545
++#define       MSM_BUS_SLAVE_GSBI5_UART 546
++#define       MSM_BUS_SLAVE_GSBI6_UART 547
++#define       MSM_BUS_SLAVE_GSBI7_UART 548
++#define       MSM_BUS_SLAVE_GSBI8_UART 549
++#define       MSM_BUS_SLAVE_GSBI9_UART 550
++#define       MSM_BUS_SLAVE_GSBI10_UART 551
++#define       MSM_BUS_SLAVE_GSBI11_UART 552
++#define       MSM_BUS_SLAVE_GSBI12_UART 553
++#define       MSM_BUS_SLAVE_GSBI1_QUP 554
++#define       MSM_BUS_SLAVE_GSBI2_QUP 555
++#define       MSM_BUS_SLAVE_GSBI3_QUP 556
++#define       MSM_BUS_SLAVE_GSBI4_QUP 557
++#define       MSM_BUS_SLAVE_GSBI5_QUP 558
++#define       MSM_BUS_SLAVE_GSBI6_QUP 559
++#define       MSM_BUS_SLAVE_GSBI7_QUP 560
++#define       MSM_BUS_SLAVE_GSBI8_QUP 561
++#define       MSM_BUS_SLAVE_GSBI9_QUP 562
++#define       MSM_BUS_SLAVE_GSBI10_QUP 563
++#define       MSM_BUS_SLAVE_GSBI11_QUP 564
++#define       MSM_BUS_SLAVE_GSBI12_QUP 565
++#define       MSM_BUS_SLAVE_EBI2_NAND 566
++#define       MSM_BUS_SLAVE_EBI2_CS0 567
++#define       MSM_BUS_SLAVE_EBI2_CS1 568
++#define       MSM_BUS_SLAVE_EBI2_CS2 569
++#define       MSM_BUS_SLAVE_EBI2_CS3 570
++#define       MSM_BUS_SLAVE_EBI2_CS4 571
++#define       MSM_BUS_SLAVE_EBI2_CS5 572
++#define       MSM_BUS_SLAVE_USB_FS1 573
++#define       MSM_BUS_SLAVE_USB_FS2 574
++#define       MSM_BUS_SLAVE_TSIF 575
++#define       MSM_BUS_SLAVE_MSM_TSSC 576
++#define       MSM_BUS_SLAVE_MSM_PDM 577
++#define       MSM_BUS_SLAVE_MSM_DIMEM 578
++#define       MSM_BUS_SLAVE_MSM_TCSR 579
++#define       MSM_BUS_SLAVE_MSM_PRNG 580
++#define       MSM_BUS_SLAVE_GSS 581
++#define       MSM_BUS_SLAVE_SATA 582
++#define       MSM_BUS_SLAVE_USB3 583
++#define       MSM_BUS_SLAVE_WCSS 584
++#define       MSM_BUS_SLAVE_OCIMEM 585
++#define       MSM_BUS_SLAVE_SNOC_OCMEM 586
++#define       MSM_BUS_SLAVE_SERVICE_SNOC 587
++#define       MSM_BUS_SLAVE_QDSS_STM 588
++#define       MSM_BUS_SLAVE_CAMERA_CFG 589
++#define       MSM_BUS_SLAVE_DISPLAY_CFG 590
++#define       MSM_BUS_SLAVE_OCMEM_CFG 591
++#define       MSM_BUS_SLAVE_CPR_CFG 592
++#define       MSM_BUS_SLAVE_CPR_XPU_CFG 593
++#define       MSM_BUS_SLAVE_MISC_CFG 594
++#define       MSM_BUS_SLAVE_MISC_XPU_CFG 595
++#define       MSM_BUS_SLAVE_VENUS_CFG 596
++#define       MSM_BUS_SLAVE_MISC_VENUS_CFG 597
++#define       MSM_BUS_SLAVE_GRAPHICS_3D_CFG 598
++#define       MSM_BUS_SLAVE_MMSS_CLK_CFG 599
++#define       MSM_BUS_SLAVE_MMSS_CLK_XPU_CFG 600
++#define       MSM_BUS_SLAVE_MNOC_MPU_CFG 601
++#define       MSM_BUS_SLAVE_ONOC_MPU_CFG 602
++#define       MSM_BUS_SLAVE_SERVICE_MNOC 603
++#define       MSM_BUS_SLAVE_OCMEM 604
++#define       MSM_BUS_SLAVE_SERVICE_ONOC 605
++#define       MSM_BUS_SLAVE_SDCC_1 606
++#define       MSM_BUS_SLAVE_SDCC_3 607
++#define       MSM_BUS_SLAVE_SDCC_2 608
++#define       MSM_BUS_SLAVE_SDCC_4 609
++#define       MSM_BUS_SLAVE_BAM_DMA 610
++#define       MSM_BUS_SLAVE_BLSP_2 611
++#define       MSM_BUS_SLAVE_USB_HSIC 612
++#define       MSM_BUS_SLAVE_BLSP_1 613
++#define       MSM_BUS_SLAVE_USB_HS 614
++#define       MSM_BUS_SLAVE_PDM 615
++#define       MSM_BUS_SLAVE_PERIPH_APU_CFG 616
++#define       MSM_BUS_SLAVE_PNOC_MPU_CFG 617
++#define       MSM_BUS_SLAVE_PRNG 618
++#define       MSM_BUS_SLAVE_SERVICE_PNOC 619
++#define       MSM_BUS_SLAVE_CLK_CTL 620
++#define       MSM_BUS_SLAVE_CNOC_MSS 621
++#define       MSM_BUS_SLAVE_SECURITY 622
++#define       MSM_BUS_SLAVE_TCSR 623
++#define       MSM_BUS_SLAVE_TLMM 624
++#define       MSM_BUS_SLAVE_CRYPTO_0_CFG 625
++#define       MSM_BUS_SLAVE_CRYPTO_1_CFG 626
++#define       MSM_BUS_SLAVE_IMEM_CFG 627
++#define       MSM_BUS_SLAVE_MESSAGE_RAM 628
++#define       MSM_BUS_SLAVE_BIMC_CFG 629
++#define       MSM_BUS_SLAVE_BOOT_ROM 630
++#define       MSM_BUS_SLAVE_CNOC_MNOC_MMSS_CFG 631
++#define       MSM_BUS_SLAVE_PMIC_ARB 632
++#define       MSM_BUS_SLAVE_SPDM_WRAPPER 633
++#define       MSM_BUS_SLAVE_DEHR_CFG 634
++#define       MSM_BUS_SLAVE_QDSS_CFG 635
++#define       MSM_BUS_SLAVE_RBCPR_CFG 636
++#define       MSM_BUS_SLAVE_RBCPR_QDSS_APU_CFG 637
++#define       MSM_BUS_SLAVE_SNOC_MPU_CFG 638
++#define       MSM_BUS_SLAVE_CNOC_ONOC_CFG 639
++#define       MSM_BUS_SLAVE_CNOC_MNOC_CFG 640
++#define       MSM_BUS_SLAVE_PNOC_CFG 641
++#define       MSM_BUS_SLAVE_SNOC_CFG 642
++#define       MSM_BUS_SLAVE_EBI1_DLL_CFG 643
++#define       MSM_BUS_SLAVE_PHY_APU_CFG 644
++#define       MSM_BUS_SLAVE_EBI1_PHY_CFG 645
++#define       MSM_BUS_SLAVE_SERVICE_CNOC 646
++#define       MSM_BUS_SLAVE_IPS_CFG 647
++#define       MSM_BUS_SLAVE_QPIC 648
++#define       MSM_BUS_SLAVE_DSI_CFG 649
++#define       MSM_BUS_SLAVE_UFS_CFG 650
++#define       MSM_BUS_SLAVE_RBCPR_CX_CFG 651
++#define       MSM_BUS_SLAVE_RBCPR_MX_CFG 652
++#define       MSM_BUS_SLAVE_PCIE_CFG 653
++#define       MSM_BUS_SLAVE_USB_PHYS_CFG 654
++#define       MSM_BUS_SLAVE_VIDEO_CAP_CFG 655
++#define       MSM_BUS_SLAVE_AVSYNC_CFG 656
++#define       MSM_BUS_SLAVE_CRYPTO_2_CFG 657
++#define       MSM_BUS_SLAVE_VPU_CFG 658
++#define       MSM_BUS_SLAVE_BCAST_CFG 659
++#define       MSM_BUS_SLAVE_KLM_CFG 660
++#define       MSM_BUS_SLAVE_GENI_IR_CFG 661
++#define       MSM_BUS_SLAVE_OCMEM_GFX 662
++#define       MSM_BUS_SLAVE_CATS_128 663
++#define       MSM_BUS_SLAVE_OCMEM_64 664
++#define MSM_BUS_SLAVE_PCIE_0 665
++#define MSM_BUS_SLAVE_PCIE_1 666
++#define       MSM_BUS_SLAVE_PCIE_0_CFG 667
++#define       MSM_BUS_SLAVE_PCIE_1_CFG 668
++#define       MSM_BUS_SLAVE_SRVC_MNOC 669
++#define       MSM_BUS_SLAVE_USB_HS2 670
++#define       MSM_BUS_SLAVE_AUDIO     671
++#define       MSM_BUS_SLAVE_TCU       672
++#define       MSM_BUS_SLAVE_APPSS     673
++#define       MSM_BUS_SLAVE_PCIE_PARF 674
++#define       MSM_BUS_SLAVE_USB3_PHY_CFG      675
++#define       MSM_BUS_SLAVE_IPA_CFG   676
++#define       MSM_BUS_SLAVE_A0NOC_SNOC 677
++#define       MSM_BUS_SLAVE_A1NOC_SNOC 678
++#define       MSM_BUS_SLAVE_A2NOC_SNOC 679
++#define       MSM_BUS_SLAVE_HMSS_L3 680
++#define       MSM_BUS_SLAVE_PIMEM_CFG 681
++#define       MSM_BUS_SLAVE_DCC_CFG 682
++#define       MSM_BUS_SLAVE_QDSS_RBCPR_APU_CFG 683
++#define       MSM_BUS_SLAVE_PCIE_2_CFG 684
++#define       MSM_BUS_SLAVE_PCIE20_AHB2PHY 685
++#define       MSM_BUS_SLAVE_A0NOC_CFG 686
++#define       MSM_BUS_SLAVE_A1NOC_CFG 687
++#define       MSM_BUS_SLAVE_A2NOC_CFG 688
++#define       MSM_BUS_SLAVE_A1NOC_MPU_CFG 689
++#define       MSM_BUS_SLAVE_A2NOC_MPU_CFG 690
++#define       MSM_BUS_SLAVE_A0NOC_SMMU_CFG 691
++#define       MSM_BUS_SLAVE_A1NOC_SMMU_CFG 692
++#define       MSM_BUS_SLAVE_A2NOC_SMMU_CFG 693
++#define       MSM_BUS_SLAVE_LPASS_SMMU_CFG 694
++#define       MSM_BUS_SLAVE_MMAGIC_CFG 695
++#define       MSM_BUS_SLAVE_VENUS_THROTTLE_CFG 696
++#define       MSM_BUS_SLAVE_SSC_CFG 697
++#define       MSM_BUS_SLAVE_DSA_CFG 698
++#define       MSM_BUS_SLAVE_DSA_MPU_CFG 699
++#define       MSM_BUS_SLAVE_DISPLAY_THROTTLE_CFG 700
++#define       MSM_BUS_SLAVE_SMMU_CPP_CFG 701
++#define       MSM_BUS_SLAVE_SMMU_JPEG_CFG 702
++#define       MSM_BUS_SLAVE_SMMU_MDP_CFG 703
++#define       MSM_BUS_SLAVE_SMMU_ROTATOR_CFG 704
++#define       MSM_BUS_SLAVE_SMMU_VENUS_CFG 705
++#define       MSM_BUS_SLAVE_SMMU_VFE_CFG 706
++#define       MSM_BUS_SLAVE_A0NOC_MPU_CFG 707
++#define       MSM_BUS_SLAVE_VMEM_CFG 708
++#define       MSM_BUS_SLAVE_CAMERA_THROTTLE_CFG 700
++#define       MSM_BUS_SLAVE_VMEM 709
++#define       MSM_BUS_SLAVE_AHB2PHY 710
++#define       MSM_BUS_SLAVE_PIMEM 711
++#define       MSM_BUS_SLAVE_SNOC_VMEM 712
++#define       MSM_BUS_SLAVE_PCIE_2 713
++#define       MSM_BUS_SLAVE_RBCPR_MX 714
++#define       MSM_BUS_SLAVE_RBCPR_CX 715
++#define       MSM_BUS_SLAVE_PRNG_APU_CFG 716
++#define       MSM_BUS_SLAVE_PERIPH_MPU_CFG 717
++#define       MSM_BUS_SLAVE_GCNT 718
++#define       MSM_BUS_SLAVE_ADSS_CFG 719
++#define       MSM_BUS_SLAVE_ADSS_VMIDMT_CFG 720
++#define       MSM_BUS_SLAVE_QHSS_APU_CFG 721
++#define       MSM_BUS_SLAVE_MDIO 722
++#define       MSM_BUS_SLAVE_FEPHY_CFG 723
++#define       MSM_BUS_SLAVE_SRIF 724
++#define       MSM_BUS_SLAVE_LAST 730
++#define       MSM_BUS_SLAVE_DDRC_CFG 731
++#define       MSM_BUS_SLAVE_DDRC_APU_CFG 732
++#define       MSM_BUS_SLAVE_MPU0_CFG 733
++#define       MSM_BUS_SLAVE_MPU1_CFG 734
++#define       MSM_BUS_SLAVE_MPU2_CFG 734
++#define       MSM_BUS_SLAVE_ESS_VMIDMT_CFG 735
++#define       MSM_BUS_SLAVE_ESS_APU_CFG 736
++#define       MSM_BUS_SLAVE_USB2_CFG 737
++#define       MSM_BUS_SLAVE_BLSP_CFG 738
++#define       MSM_BUS_SLAVE_QPIC_CFG 739
++#define       MSM_BUS_SLAVE_SDCC_CFG 740
++#define       MSM_BUS_SLAVE_WSS0_VMIDMT_CFG 741
++#define       MSM_BUS_SLAVE_WSS0_APU_CFG 742
++#define       MSM_BUS_SLAVE_WSS1_VMIDMT_CFG 743
++#define       MSM_BUS_SLAVE_WSS1_APU_CFG 744
++#define       MSM_BUS_SLAVE_SRVC_PCNOC 745
++#define       MSM_BUS_SLAVE_SNOC_DDRC 746
++#define       MSM_BUS_SLAVE_A7SS 747
++#define       MSM_BUS_SLAVE_WSS0_CFG 748
++#define       MSM_BUS_SLAVE_WSS1_CFG 749
++#define       MSM_BUS_SLAVE_PCIE 750
++#define       MSM_BUS_SLAVE_USB3_CFG 751
++#define       MSM_BUS_SLAVE_CRYPTO_CFG 752
++#define       MSM_BUS_SLAVE_ESS_CFG 753
++#define       MSM_BUS_SLAVE_SRVC_SNOC 754
++
++#define       MSM_BUS_SYSTEM_FPB_SLAVE_SYSTEM  MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB
++#define MSM_BUS_CPSS_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_CPSS_FPB
++
++/*
++ * ID's used in RPM messages
++ */
++#define ICBID_MASTER_APPSS_PROC 0
++#define ICBID_MASTER_MSS_PROC 1
++#define ICBID_MASTER_MNOC_BIMC 2
++#define ICBID_MASTER_SNOC_BIMC 3
++#define ICBID_MASTER_SNOC_BIMC_0 ICBID_MASTER_SNOC_BIMC
++#define ICBID_MASTER_CNOC_MNOC_MMSS_CFG 4
++#define ICBID_MASTER_CNOC_MNOC_CFG 5
++#define ICBID_MASTER_GFX3D 6
++#define ICBID_MASTER_JPEG 7
++#define ICBID_MASTER_MDP 8
++#define ICBID_MASTER_MDP0 ICBID_MASTER_MDP
++#define ICBID_MASTER_MDPS ICBID_MASTER_MDP
++#define ICBID_MASTER_VIDEO 9
++#define ICBID_MASTER_VIDEO_P0 ICBID_MASTER_VIDEO
++#define ICBID_MASTER_VIDEO_P1 10
++#define ICBID_MASTER_VFE 11
++#define ICBID_MASTER_CNOC_ONOC_CFG 12
++#define ICBID_MASTER_JPEG_OCMEM 13
++#define ICBID_MASTER_MDP_OCMEM 14
++#define ICBID_MASTER_VIDEO_P0_OCMEM 15
++#define ICBID_MASTER_VIDEO_P1_OCMEM 16
++#define ICBID_MASTER_VFE_OCMEM 17
++#define ICBID_MASTER_LPASS_AHB 18
++#define ICBID_MASTER_QDSS_BAM 19
++#define ICBID_MASTER_SNOC_CFG 20
++#define ICBID_MASTER_BIMC_SNOC 21
++#define ICBID_MASTER_CNOC_SNOC 22
++#define ICBID_MASTER_CRYPTO 23
++#define ICBID_MASTER_CRYPTO_CORE0 ICBID_MASTER_CRYPTO
++#define ICBID_MASTER_CRYPTO_CORE1 24
++#define ICBID_MASTER_LPASS_PROC 25
++#define ICBID_MASTER_MSS 26
++#define ICBID_MASTER_MSS_NAV 27
++#define ICBID_MASTER_OCMEM_DMA 28
++#define ICBID_MASTER_PNOC_SNOC 29
++#define ICBID_MASTER_WCSS 30
++#define ICBID_MASTER_QDSS_ETR 31
++#define ICBID_MASTER_USB3 32
++#define ICBID_MASTER_USB3_0 ICBID_MASTER_USB3
++#define ICBID_MASTER_SDCC_1 33
++#define ICBID_MASTER_SDCC_3 34
++#define ICBID_MASTER_SDCC_2 35
++#define ICBID_MASTER_SDCC_4 36
++#define ICBID_MASTER_TSIF 37
++#define ICBID_MASTER_BAM_DMA 38
++#define ICBID_MASTER_BLSP_2 39
++#define ICBID_MASTER_USB_HSIC 40
++#define ICBID_MASTER_BLSP_1 41
++#define ICBID_MASTER_USB_HS 42
++#define ICBID_MASTER_USB_HS1 ICBID_MASTER_USB_HS
++#define ICBID_MASTER_PNOC_CFG 43
++#define ICBID_MASTER_SNOC_PNOC 44
++#define ICBID_MASTER_RPM_INST 45
++#define ICBID_MASTER_RPM_DATA 46
++#define ICBID_MASTER_RPM_SYS 47
++#define ICBID_MASTER_DEHR 48
++#define ICBID_MASTER_QDSS_DAP 49
++#define ICBID_MASTER_SPDM 50
++#define ICBID_MASTER_TIC 51
++#define ICBID_MASTER_SNOC_CNOC 52
++#define ICBID_MASTER_GFX3D_OCMEM 53
++#define ICBID_MASTER_GFX3D_GMEM ICBID_MASTER_GFX3D_OCMEM
++#define ICBID_MASTER_OVIRT_SNOC 54
++#define ICBID_MASTER_SNOC_OVIRT 55
++#define ICBID_MASTER_SNOC_GVIRT ICBID_MASTER_SNOC_OVIRT
++#define ICBID_MASTER_ONOC_OVIRT 56
++#define ICBID_MASTER_USB_HS2 57
++#define ICBID_MASTER_QPIC 58
++#define ICBID_MASTER_IPA 59
++#define ICBID_MASTER_DSI 60
++#define ICBID_MASTER_MDP1 61
++#define ICBID_MASTER_MDPE ICBID_MASTER_MDP1
++#define ICBID_MASTER_VPU_PROC 62
++#define ICBID_MASTER_VPU 63
++#define ICBID_MASTER_VPU0 ICBID_MASTER_VPU
++#define ICBID_MASTER_CRYPTO_CORE2 64
++#define ICBID_MASTER_PCIE_0 65
++#define ICBID_MASTER_PCIE_1 66
++#define ICBID_MASTER_SATA 67
++#define ICBID_MASTER_UFS 68
++#define ICBID_MASTER_USB3_1 69
++#define ICBID_MASTER_VIDEO_OCMEM 70
++#define ICBID_MASTER_VPU1 71
++#define ICBID_MASTER_VCAP 72
++#define ICBID_MASTER_EMAC 73
++#define ICBID_MASTER_BCAST 74
++#define ICBID_MASTER_MMSS_PROC 75
++#define ICBID_MASTER_SNOC_BIMC_1 76
++#define ICBID_MASTER_SNOC_PCNOC 77
++#define ICBID_MASTER_AUDIO 78
++#define ICBID_MASTER_MM_INT_0 79
++#define ICBID_MASTER_MM_INT_1 80
++#define ICBID_MASTER_MM_INT_2 81
++#define ICBID_MASTER_MM_INT_BIMC 82
++#define ICBID_MASTER_MSS_INT 83
++#define ICBID_MASTER_PCNOC_CFG 84
++#define ICBID_MASTER_PCNOC_INT_0 85
++#define ICBID_MASTER_PCNOC_INT_1 86
++#define ICBID_MASTER_PCNOC_M_0 87
++#define ICBID_MASTER_PCNOC_M_1 88
++#define ICBID_MASTER_PCNOC_S_0 89
++#define ICBID_MASTER_PCNOC_S_1 90
++#define ICBID_MASTER_PCNOC_S_2 91
++#define ICBID_MASTER_PCNOC_S_3 92
++#define ICBID_MASTER_PCNOC_S_4 93
++#define ICBID_MASTER_PCNOC_S_6 94
++#define ICBID_MASTER_PCNOC_S_7 95
++#define ICBID_MASTER_PCNOC_S_8 96
++#define ICBID_MASTER_PCNOC_S_9 97
++#define ICBID_MASTER_QDSS_INT 98
++#define ICBID_MASTER_SNOC_INT_0 99
++#define ICBID_MASTER_SNOC_INT_1 100
++#define ICBID_MASTER_SNOC_INT_BIMC 101
++#define ICBID_MASTER_TCU_0 102
++#define ICBID_MASTER_TCU_1 103
++#define ICBID_MASTER_BIMC_INT_0 104
++#define ICBID_MASTER_BIMC_INT_1 105
++#define ICBID_MASTER_CAMERA 106
++#define ICBID_MASTER_RICA 107
++#define ICBID_MASTER_PCNOC_S_5        129
++#define ICBID_MASTER_PCNOC_INT_2      124
++#define ICBID_MASTER_PCNOC_INT_3      125
++#define ICBID_MASTER_PCNOC_INT_4      126
++#define ICBID_MASTER_PCNOC_INT_5