mediatek: bump to v4.14
authorJohn Crispin <john@phrozen.org>
Mon, 8 Jan 2018 14:06:24 +0000 (15:06 +0100)
committerJohn Crispin <john@phrozen.org>
Wed, 14 Feb 2018 10:27:50 +0000 (11:27 +0100)
This drops support for all the !emmc EVB and adds banannaPi-R2
Also drop mtkhnat until the nftables offoad driver is ready

Signed-off-by: John Crispin <john@phrozen.org>
104 files changed:
target/linux/mediatek/Makefile
target/linux/mediatek/base-files/etc/board.d/02_network
target/linux/mediatek/base-files/etc/config/mtkhnat [deleted file]
target/linux/mediatek/base-files/etc/init.d/mtkhnat [deleted file]
target/linux/mediatek/base-files/etc/uci-defaults/99-firewall [deleted file]
target/linux/mediatek/base-files/lib/upgrade/platform.sh
target/linux/mediatek/base-files/sbin/mtkhnat [deleted file]
target/linux/mediatek/config-4.14 [new file with mode: 0644]
target/linux/mediatek/files/arch/arm/boot/dts/_mt7623.dtsi [deleted file]
target/linux/mediatek/files/arch/arm/boot/dts/mt6323.dtsi [deleted file]
target/linux/mediatek/files/arch/arm/boot/dts/mt7623-NAND-ePHY.dts [deleted file]
target/linux/mediatek/files/arch/arm/boot/dts/mt7623-NAND.dts [deleted file]
target/linux/mediatek/files/arch/arm/boot/dts/mt7623-eMMC.dts [deleted file]
target/linux/mediatek/files/arch/arm/boot/dts/mt7623-evb.dts [deleted file]
target/linux/mediatek/files/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts [deleted file]
target/linux/mediatek/files/drivers/char/hw_random/mtk-rng.c [deleted file]
target/linux/mediatek/files/drivers/crypto/mediatek/Makefile [deleted file]
target/linux/mediatek/files/drivers/crypto/mediatek/mtk-aes.c [deleted file]
target/linux/mediatek/files/drivers/crypto/mediatek/mtk-platform.c [deleted file]
target/linux/mediatek/files/drivers/crypto/mediatek/mtk-platform.h [deleted file]
target/linux/mediatek/files/drivers/crypto/mediatek/mtk-regs.h [deleted file]
target/linux/mediatek/files/drivers/crypto/mediatek/mtk-sha.c [deleted file]
target/linux/mediatek/image/32.mk
target/linux/mediatek/modules.mk [deleted file]
target/linux/mediatek/patches-4.14/0006-reset-mediatek-mt2701-reset-driver.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0012-clk-dont-disable-unused-clocks.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0027-net-next-mediatek-fix-DQL-support.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0032-net-dsa-mediatek-add-support-for-GMAC2-wired-to-ext-.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0033-dsa-multi-cpu.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0035-net-mediatek-disable-RX-VLan-offloading.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0042-net-next-mediatek-honour-special-tag-bit-inside-RX-D.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0043-net-next-mediatek-enable-special-tag-indication-for-.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0044-net-next-dsa-mediatek-tell-GDMA-when-we-are-turning-.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0045-net-dsa-mediatek-turn-into-platform-driver.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0046-net-mediatek-add-irq-delay.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0048-net-core-add-RPS-balancer.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0051-net-mediatek-increase-tx_timeout.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0052-net-phy-add-FC.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0062-mdio-atomic.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0063-atomic-sleep.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0064-dts.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.9/0001-arch-arm-add-dts-build-code.patch [deleted file]
target/linux/mediatek/patches-4.9/0002-dt-bindings-add-MediaTek-PCIe-binding-documentation.patch [deleted file]
target/linux/mediatek/patches-4.9/0003-PCI-mediatek-add-support-for-PCIe-found-on-MT7623-MT.patch [deleted file]
target/linux/mediatek/patches-4.9/0004-soc-mediatek-Add-MT2701-power-dt-bindings.patch [deleted file]
target/linux/mediatek/patches-4.9/0005-clk-mediatek-Add-MT2701-clock-support.patch [deleted file]
target/linux/mediatek/patches-4.9/0006-reset-mediatek-mt2701-reset-driver.patch [deleted file]
target/linux/mediatek/patches-4.9/0007-ARM-mediatek-Add-MT2701-config-options-for-mediatek-.patch [deleted file]
target/linux/mediatek/patches-4.9/0008-soc-mediatek-Refine-scpsys-to-support-multiple-platf.patch [deleted file]
target/linux/mediatek/patches-4.9/0009-soc-mediatek-Add-MT2701-scpsys-driver.patch [deleted file]
target/linux/mediatek/patches-4.9/0010-clk-add-hifsys-reset.patch [deleted file]
target/linux/mediatek/patches-4.9/0011-scpsys-various-fixes.patch [deleted file]
target/linux/mediatek/patches-4.9/0012-clk-dont-disable-unused-clocks.patch [deleted file]
target/linux/mediatek/patches-4.9/0013-clk-mediatek-enable-critical-clocks.patch [deleted file]
target/linux/mediatek/patches-4.9/0014-clk-mediatek-Export-CPU-mux-clocks-for-CPU-frequency.patch [deleted file]
target/linux/mediatek/patches-4.9/0015-cpufreq-mediatek-add-driver.patch [deleted file]
target/linux/mediatek/patches-4.9/0016-pwm-add-pwm-mediatek.patch [deleted file]
target/linux/mediatek/patches-4.9/0017-mfd-mt6397-Add-MT6323-LED-support-into-MT6397-driver.patch [deleted file]
target/linux/mediatek/patches-4.9/0018-dt-bindings-leds-Add-document-bindings-for-leds-mt63.patch [deleted file]
target/linux/mediatek/patches-4.9/0019-dt-bindings-mfd-Add-the-description-for-LED-as-the-s.patch [deleted file]
target/linux/mediatek/patches-4.9/0020-leds-Add-LED-support-for-MT6323-PMIC.patch [deleted file]
target/linux/mediatek/patches-4.9/0021-mfd-mt6397-Align-the-placement-at-which-the-mfd_cell.patch [deleted file]
target/linux/mediatek/patches-4.9/0022-nand-make-bootrom-work-with-upstream-driver.patch [deleted file]
target/linux/mediatek/patches-4.9/0023-rng-add-mediatek-hw-rng.patch [deleted file]
target/linux/mediatek/patches-4.9/0024-media-rc-add-driver-for-IR-remote-receiver-on-MT7623.patch [deleted file]
target/linux/mediatek/patches-4.9/0025-dt-bindings-net-dsa-add-Mediatek-MT7530-binding.patch [deleted file]
target/linux/mediatek/patches-4.9/0026-net-mediatek-backport-v4.10-driver.patch [deleted file]
target/linux/mediatek/patches-4.9/0027-net-next-mediatek-fix-DQL-support.patch [deleted file]
target/linux/mediatek/patches-4.9/0028-net-next-dsa-add-Mediatek-tag-RX-TX-handler.patch [deleted file]
target/linux/mediatek/patches-4.9/0029-net-next-ethernet-mediatek-add-CDM-able-to-recognize.patch [deleted file]
target/linux/mediatek/patches-4.9/0030-net-next-dsa-add-dsa-support-for-Mediatek-MT7530-swi.patch [deleted file]
target/linux/mediatek/patches-4.9/0031-net-dsa-dsa-api-compat.patch [deleted file]
target/linux/mediatek/patches-4.9/0032-net-dsa-mediatek-add-support-for-GMAC2-wired-to-ext-.patch [deleted file]
target/linux/mediatek/patches-4.9/0033-net-dsa-add-multi-gmac-support.patch [deleted file]
target/linux/mediatek/patches-4.9/0034-net-dsa-mediatek-add-dual-gmac-support.patch [deleted file]
target/linux/mediatek/patches-4.9/0035-net-mediatek-disable-RX-VLan-offloading.patch [deleted file]
target/linux/mediatek/patches-4.9/0036-net-next-mediatek-fix-typos-inside-the-header-file.patch [deleted file]
target/linux/mediatek/patches-4.9/0037-net-next-mediatek-bring-up-QDMA-RX-ring-0.patch [deleted file]
target/linux/mediatek/patches-4.9/0038-net-next-dsa-move-struct-dsa_device_ops-to-the-globa.patch [deleted file]
target/linux/mediatek/patches-4.9/0039-net-next-dsa-add-flow_dissect-callback-to-struct-dsa.patch [deleted file]
target/linux/mediatek/patches-4.9/0040-net-next-tag_mtk-add-flow_dissect-callback-to-the-op.patch [deleted file]
target/linux/mediatek/patches-4.9/0041-net-next-dsa-fix-flow-dissection.patch [deleted file]
target/linux/mediatek/patches-4.9/0042-net-next-mediatek-honour-special-tag-bit-inside-RX-D.patch [deleted file]
target/linux/mediatek/patches-4.9/0043-net-next-mediatek-enable-special-tag-indication-for-.patch [deleted file]
target/linux/mediatek/patches-4.9/0044-net-next-dsa-mediatek-tell-GDMA-when-we-are-turning-.patch [deleted file]
target/linux/mediatek/patches-4.9/0045-net-dsa-mediatek-turn-into-platform-driver.patch [deleted file]
target/linux/mediatek/patches-4.9/0046-net-mediatek-add-irq-delay.patch [deleted file]
target/linux/mediatek/patches-4.9/0047-net-next-mediatek-split-IRQ-register-locking-into-TX.patch [deleted file]
target/linux/mediatek/patches-4.9/0048-net-core-add-RPS-balancer.patch [deleted file]
target/linux/mediatek/patches-4.9/0049-net-mediatek-add-rx-queue.patch [deleted file]
target/linux/mediatek/patches-4.9/0050-net-mediatek-add-trgmii-clock.patch [deleted file]
target/linux/mediatek/patches-4.9/0051-net-mediatek-increase-tx_timeout.patch [deleted file]
target/linux/mediatek/patches-4.9/0052-net-phy-add-FC.patch [deleted file]
target/linux/mediatek/patches-4.9/0053-net-dsa-mediatek-add-software-phy-polling.patch [deleted file]
target/linux/mediatek/patches-4.9/0054-net-ethernet-mediatek-fixed-deadlock-captured-by-loc.patch [deleted file]
target/linux/mediatek/patches-4.9/0055-net-ethernet-mediatek-avoid-potential-invalid-memory.patch [deleted file]
target/linux/mediatek/patches-4.9/0056-net-mediatek-add-hw-nat-support.patch [deleted file]
target/linux/mediatek/patches-4.9/0057-net-mediatek-add-HW-QoS-support.patch [deleted file]
target/linux/mediatek/patches-4.9/0058-pinctrl-update.patch [deleted file]
target/linux/mediatek/patches-4.9/0059-eth-fixes.patch [deleted file]
target/linux/mediatek/patches-4.9/0060-eth-debug.patch [deleted file]
target/linux/mediatek/patches-4.9/0061-eth-up_down_lock.patch [deleted file]
target/linux/mediatek/patches-4.9/0062-mdio-atomic.patch [deleted file]
target/linux/mediatek/patches-4.9/0063-atomic-sleep.patch [deleted file]

index 4ebac09..fb294ad 100644 (file)
@@ -9,7 +9,7 @@ SUBTARGETS:=32
 FEATURES:=squashfs nand ubifs
 MAINTAINER:=John Crispin <john@phrozen.org>
 
-KERNEL_PATCHVER:=4.9
+KERNEL_PATCHVER:=4.14
 
 KERNELNAME:=Image dtbs zImage
 
index e071ab2..8015cf3 100755 (executable)
@@ -9,13 +9,11 @@ mediatek_setup_interfaces()
        local board="$1"
 
        case $board in
-       'bananapi,bpi-r2' | \
-       'mediatek,mt7623-rfb-emmc' | \
-       'mediatek,mt7623-rfb-nand-ephy')
+       'mediatek,mt7623a-rfb-emmc')
                ucidef_set_interface_lan "lan0 lan1 lan2 lan3"
                ucidef_set_interface_wan eth1
                ;;
-       'mediatek,mt7623-rfb-nand')
+       'bananapi,bpi-r2') 
                ucidef_set_interface_lan "lan0 lan1 lan2 lan3"
                ucidef_set_interface_wan wan
                ;;
diff --git a/target/linux/mediatek/base-files/etc/config/mtkhnat b/target/linux/mediatek/base-files/etc/config/mtkhnat
deleted file mode 100644 (file)
index a23bd1c..0000000
+++ /dev/null
@@ -1,60 +0,0 @@
-config global global
-       option enable 0
-       option upstream 1000000
-       option downstream 1000000
-
-config queue
-       option id 0
-       option minrate 10
-       option maxrate 50
-       option weight 7
-       option resv 32
-
-config queue
-       option id 1
-       option minrate 30
-       option maxrate 100
-       option weight 7
-       option resv 32
-
-config queue
-       option id 2
-       option minrate 30
-       option maxrate 100
-       option weight 7
-       option resv 32
-
-config queue
-       option id 3
-       option minrate 30
-       option maxrate 100
-       option weight 7
-       option resv 32
-
-config queue
-       option id 4
-       option minrate 25
-       option maxrate 100
-       option weight 7
-       option resv 32
-
-config queue
-       option id 5
-       option minrate 25
-       option maxrate 100
-       option weight 7
-       option resv 32
-
-config queue
-       option id 6
-       option minrate 25
-       option maxrate 100
-       option weight 7
-       option resv 32
-
-config queue
-       option id 7
-       option minrate 25
-       option maxrate 100
-       option weight 7
-       option resv 32
diff --git a/target/linux/mediatek/base-files/etc/init.d/mtkhnat b/target/linux/mediatek/base-files/etc/init.d/mtkhnat
deleted file mode 100755 (executable)
index 32011e7..0000000
+++ /dev/null
@@ -1,13 +0,0 @@
-#!/bin/sh /etc/rc.common
-
-START=90
-
-USE_PROCD=1
-NAME=mtkhnat
-PROG=/sbin/mtkhnat
-
-start_service() {
-       procd_open_instance
-       procd_set_param command "${PROG}"
-       procd_close_instance
-}
diff --git a/target/linux/mediatek/base-files/etc/uci-defaults/99-firewall b/target/linux/mediatek/base-files/etc/uci-defaults/99-firewall
deleted file mode 100755 (executable)
index 9a0dd9b..0000000
+++ /dev/null
@@ -1,9 +0,0 @@
-echo "iptables -t mangle -A FORWARD -i br-lan -o eth1 -p tcp -m mark --mark 0/0x7 -j MARK --set-mark 4/0x7" >> /etc/firewall.user
-echo "iptables -t mangle -A FORWARD -i br-lan -o eth1 -p udp -m mark --mark 0/0x7 -j MARK --set-mark 5/0x7" >> /etc/firewall.user
-echo "iptables -t mangle -A FORWARD -i eth1 -o br-lan -p tcp -m mark --mark 0/0x7 -j MARK --set-mark 4/0x7" >> /etc/firewall.user
-echo "iptables -t mangle -A FORWARD -i eth1 -o br-lan -p udp -m mark --mark 0/0x7 -j MARK --set-mark 5/0x7" >> /etc/firewall.user
-
-echo "iptables -t mangle -A FORWARD -p udp -m mark --mark 0/0xf8 -j MARK --or-mark 0x60" >> /etc/firewall.user
-echo "iptables -t mangle -A FORWARD -p tcp -m mark --mark 0/0xf8 -j MARK --or-mark 0xc0" >> /etc/firewall.user
-
-exit 0
index 7161a4b..3f3c5a0 100755 (executable)
@@ -20,13 +20,8 @@ platform_check_image() {
        local board=$(board_name)
 
        case "$board" in
-       mediatek,mt7623-rfb-nand-ephy |\
-       mediatek,mt7623-rfb-nand)
-               nand_do_platform_check $board $1
-               return $?
-               ;;
        bananapi,bpi-r2 |\
-       mediatek,mt7623-rfb-emmc)
+       mediatek,mt7623a-rfb-emmc)
                local kernel_length=`(tar xf $tar_file sysupgrade-$board/kernel -O | wc -c) 2> /dev/null`
                local rootfs_length=`(tar xf $tar_file sysupgrade-$board/root -O | wc -c) 2> /dev/null`
                ;;
@@ -44,12 +39,3 @@ platform_check_image() {
 
        return 0
 }
-
-platform_pre_upgrade() {
-       case "$(board_name)" in
-       mediatek,mt7623-rfb-nand-ephy |\
-       mediatek,mt7623-rfb-nand)
-               nand_do_upgrade $1
-               ;;
-       esac
-}
diff --git a/target/linux/mediatek/base-files/sbin/mtkhnat b/target/linux/mediatek/base-files/sbin/mtkhnat
deleted file mode 100755 (executable)
index fdfc842..0000000
+++ /dev/null
@@ -1,64 +0,0 @@
-#!/bin/sh
-
-. /lib/functions.sh
-
-config_load mtkhnat
-config_get enable global enable 0
-
-[ "${enable}" -eq 1 ] || {
-       echo 0 ${sch_upstream} > /sys/kernel/debug/hnat/scheduler0
-       echo 0 ${sch_downstream} > /sys/kernel/debug/hnat/scheduler1
-
-       rmmod mtkhnat
-       exit 0
-}
-
-insmod mtkhnat
-
-sleep 1
-
-config_get sch_upstream global upstream 100000
-config_get sch_downstream global downstream 100000
-
-echo 1 ${sch_upstream} > /sys/kernel/debug/hnat/scheduler0
-echo 1 ${sch_downstream} > /sys/kernel/debug/hnat/scheduler1
-
-setup_queue() {
-       local queue_id queue_scheduler queue_minebl queue_maxebl queue_minrate queue_maxrate queue_resv minrate maxrate queue_weight
-
-       config_get queue_id $1 id 0
-       config_get queue_minrate $1 minrate 0
-       config_get queue_maxrate $1 maxrate 0
-       config_get queue_resv $1 resv 22
-       config_get queue_weight $1 weight 7
-
-       [ "${queue_id}" -gt 7 ] && return 0
-
-       queue_minebl=1
-       queue_maxebl=1
-       queue_scheduler=0
-
-       [ "${queue_minrate}" -eq 0 ] && queue_minebl=0
-       [ "${queue_maxrate}" -eq 0 ] && queue_maxebl=0
-
-       minrate=$((sch_upstream * $queue_minrate))
-       minrate=$((minrate / 100))
-
-       maxrate=$((sch_upstream * $queue_maxrate))
-       maxrate=$((maxrate / 100))
-
-       echo 0 ${queue_minebl} ${minrate} ${queue_maxebl} ${maxrate} ${queue_weight} ${queue_resv} > /sys/kernel/debug/hnat/queue${queue_id} 
-
-       queue_id=$((queue_id + 8))
-
-       minrate=$((sch_downstream * $queue_minrate))
-       minrate=$((minrate / 100))
-
-       maxrate=$((sch_downstream * $queue_maxrate))
-       maxrate=$((maxrate / 100))
-
-       echo 1 ${queue_minebl} ${minrate} ${queue_maxebl} ${maxrate} ${queue_weight} ${queue_resv} > /sys/kernel/debug/hnat/queue${queue_id} 
-}
-
-config_foreach setup_scheduler scheduler
-config_foreach setup_queue queue
diff --git a/target/linux/mediatek/config-4.14 b/target/linux/mediatek/config-4.14
new file mode 100644 (file)
index 0000000..af22186
--- /dev/null
@@ -0,0 +1,496 @@
+# CONFIG_AIO is not set
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_ARCH_HAS_SET_MEMORY=y
+CONFIG_ARCH_HAS_SG_CHAIN=y
+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
+CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+# CONFIG_ARCH_MULTI_CPU_AUTO is not set
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+# CONFIG_ARCH_WANTS_THP_SWAP is not set
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ARM=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+# CONFIG_ARM_ATAG_DTB_COMPAT is not set
+CONFIG_ARM_CPU_SUSPEND=y
+# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+# CONFIG_ARM_LPAE is not set
+CONFIG_ARM_MEDIATEK_CPUFREQ=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+# CONFIG_ARM_SMMU is not set
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ATAGS=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BOUNCE=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_CC_STACKPROTECTOR=y
+# CONFIG_CC_STACKPROTECTOR_NONE is not set
+CONFIG_CC_STACKPROTECTOR_REGULAR=y
+CONFIG_CLEANCACHE=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_FORCE=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_MEDIATEK=y
+CONFIG_COMMON_CLK_MT2701=y
+CONFIG_COMMON_CLK_MT2701_BDPSYS=y
+CONFIG_COMMON_CLK_MT2701_ETHSYS=y
+CONFIG_COMMON_CLK_MT2701_HIFSYS=y
+CONFIG_COMMON_CLK_MT2701_IMGSYS=y
+CONFIG_COMMON_CLK_MT2701_MMSYS=y
+CONFIG_COMMON_CLK_MT2701_VDECSYS=y
+# CONFIG_COMMON_CLK_MT8135 is not set
+# CONFIG_COMMON_CLK_MT8173 is not set
+CONFIG_COMPACTION=y
+CONFIG_COREDUMP=y
+# CONFIG_CPUFREQ_DT is not set
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+# CONFIG_CPU_THERMAL is not set
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_ACOMP2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DEV_MEDIATEK=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_NULL2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_ALIGN_RODATA=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
+CONFIG_DEBUG_MT6589_UART0=y
+# CONFIG_DEBUG_MT8127_UART0 is not set
+# CONFIG_DEBUG_MT8135_UART3 is not set
+CONFIG_DEBUG_PREEMPT=y
+CONFIG_DEBUG_UART_8250=y
+# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set
+CONFIG_DEBUG_UART_8250_SHIFT=2
+# CONFIG_DEBUG_UART_8250_WORD is not set
+CONFIG_DEBUG_UART_PHYS=0x11004000
+CONFIG_DEBUG_UART_VIRT=0xf1004000
+CONFIG_DEBUG_UNCOMPRESS=y
+# CONFIG_DEBUG_USER is not set
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+# CONFIG_DMA_NOOP_OPS is not set
+CONFIG_DMA_OF=y
+# CONFIG_DMA_VIRT_OPS is not set
+# CONFIG_DRM_LIB_RANDOM is not set
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_ELF_CORE=y
+CONFIG_EXPORTFS=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FREEZER=y
+CONFIG_FUTEX_PI=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_GRO_CELLS is not set
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_HAVE_ARCH_BITREVERSE=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+CONFIG_HAVE_ARM_SMCCC=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_HAVE_EBPF_JIT=y
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_OPTPROBES=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SMP=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_UID16=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HIGHMEM=y
+# CONFIG_HIGHPTE is not set
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HWMON=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_MTK=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MT65XX=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_IIO=y
+# CONFIG_IIO_BUFFER is not set
+# CONFIG_IIO_TRIGGER is not set
+CONFIG_INITRAMFS_COMPRESSION=""
+# CONFIG_INITRAMFS_FORCE is not set
+CONFIG_INITRAMFS_ROOT_GID=1000
+CONFIG_INITRAMFS_ROOT_UID=1000
+CONFIG_INITRAMFS_SOURCE="/openwrt/trunk/build_dir/target-arm_cortex-a7_musl-1.1.14_eabi/root-mediatek /openwrt/trunk/target/linux/generic/image/initramfs-base-files.txt"
+CONFIG_IOMMU_HELPER=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_KALLSYMS=y
+CONFIG_LEDS_MT6323=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MACH_MT2701=y
+# CONFIG_MACH_MT6589 is not set
+# CONFIG_MACH_MT6592 is not set
+CONFIG_MACH_MT7623=y
+CONFIG_MACH_MT8127=y
+# CONFIG_MACH_MT8135 is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_GPIO=y
+CONFIG_MEDIATEK_MT6577_AUXADC=y
+CONFIG_MEDIATEK_WATCHDOG=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_MT6397=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGHT_HAVE_PCI=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_MTK=y
+CONFIG_MMC_SDHCI=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_BLOCK2MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_MT81xx_NOR=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_MTK=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+# CONFIG_MTD_UBI_FASTMAP is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTK_EFUSE=y
+CONFIG_MTK_INFRACFG=y
+# CONFIG_MTK_IOMMU is not set
+# CONFIG_MTK_IOMMU_V1 is not set
+CONFIG_MTK_PMIC_WRAP=y
+CONFIG_MTK_SCPSYS=y
+CONFIG_MTK_THERMAL=y
+CONFIG_MTK_TIMER=y
+CONFIG_MULTI_IRQ_HANDLER=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+# CONFIG_NEON is not set
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_MT7530=y
+# CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set
+CONFIG_NET_DSA_TAG_MTK=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_MEDIATEK_SOC=y
+CONFIG_NET_SWITCHDEV=y
+# CONFIG_NET_VENDOR_AURORA is not set
+CONFIG_NET_VENDOR_MEDIATEK=y
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_NLS=y
+CONFIG_NO_BOOTMEM=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=4
+CONFIG_NVMEM=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_MEDIATEK=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHY_MTK_TPHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MT2701=y
+CONFIG_PINCTRL_MT6397=y
+CONFIG_PINCTRL_MT8127=y
+CONFIG_PINCTRL_MTK=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
+CONFIG_PM_OPP=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PREEMPT=y
+CONFIG_PREEMPT_COUNT=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_RCU=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PWM=y
+CONFIG_PWM_MEDIATEK=y
+# CONFIG_PWM_MTK_DISP is not set
+CONFIG_PWM_SYSFS=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+# CONFIG_RCU_EXPERT is not set
+CONFIG_RCU_NEED_SEGCBLIST=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_MT6323=y
+# CONFIG_REGULATOR_MT6380 is not set
+# CONFIG_REGULATOR_MT6397 is not set
+# CONFIG_REGULATOR_QCOM_SPMI is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_MT6397 is not set
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+# CONFIG_SCHED_INFO is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SERIAL_8250_DMA is not set
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_MT6577=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SMP=y
+# CONFIG_SMP_ON_UP is not set
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MT65XX=y
+CONFIG_SPMI=y
+CONFIG_SRCU=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWCONFIG=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_TASKS_RCU=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_OF=y
+CONFIG_THIN_ARCHIVES=y
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+# CONFIG_USB_EHCI_HCD is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USE_OF=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
diff --git a/target/linux/mediatek/files/arch/arm/boot/dts/_mt7623.dtsi b/target/linux/mediatek/files/arch/arm/boot/dts/_mt7623.dtsi
deleted file mode 100644 (file)
index 620ad95..0000000
+++ /dev/null
@@ -1,804 +0,0 @@
-/*
- * Copyright (c) 2016 MediaTek Inc.
- * Author: John Crispin <blogic@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/mt2701-clk.h>
-#include <dt-bindings/power/mt2701-power.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/reset/mt2701-resets.h>
-#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
-#include <dt-bindings/gpio/gpio.h>
-#include "skeleton64.dtsi"
-
-
-/ {
-       compatible = "mediatek,mt7623";
-       interrupt-parent = <&sysirq>;
-
-       cpus {
-               #address-cells = <1>;
-               #size-cells = <0>;
-               enable-method = "mediatek,mt6589-smp";
-
-               cpu0: cpu@0 {
-                       device_type = "cpu";
-                       compatible = "arm,cortex-a7";
-                       reg = <0x0>;
-                       clocks = <&infracfg CLK_INFRA_CPUSEL>,
-                                <&apmixedsys CLK_APMIXED_MAINPLL>;
-                       clock-names = "cpu", "intermediate";
-                       operating-points = <
-                               598000 1150000
-                               747500 1150000
-                               1040000 1150000
-                               1196000 1200000
-                               1300000 1300000
-                       >;
-               };
-               cpu1: cpu@1 {
-                       device_type = "cpu";
-                       compatible = "arm,cortex-a7";
-                       reg = <0x1>;
-                       clocks = <&infracfg CLK_INFRA_CPUSEL>,
-                                <&apmixedsys CLK_APMIXED_MAINPLL>;
-                       clock-names = "cpu", "intermediate";
-                       operating-points = <
-                               598000 1150000
-                               747500 1150000
-                               1040000 1150000
-                               1196000 1200000
-                               1300000 1300000
-                       >;
-               };
-               cpu2: cpu@2 {
-                       device_type = "cpu";
-                       compatible = "arm,cortex-a7";
-                       reg = <0x2>;
-                       clocks = <&infracfg CLK_INFRA_CPUSEL>,
-                                <&apmixedsys CLK_APMIXED_MAINPLL>;
-                       clock-names = "cpu", "intermediate";
-                       operating-points = <
-                               598000 1150000
-                               747500 1150000
-                               1040000 1150000
-                               1196000 1200000
-                               1300000 1300000
-                       >;
-               };
-               cpu3: cpu@3 {
-                       device_type = "cpu";
-                       compatible = "arm,cortex-a7";
-                       reg = <0x3>;
-                       clocks = <&infracfg CLK_INFRA_CPUSEL>,
-                                <&apmixedsys CLK_APMIXED_MAINPLL>;
-                       clock-names = "cpu", "intermediate";
-                       operating-points = <
-                               598000 1150000
-                               747500 1150000
-                               1040000 1150000
-                               1196000 1200000
-                               1300000 1300000
-                       >;
-               };
-       };
-
-       system_clk: dummy13m {
-               compatible = "fixed-clock";
-               clock-frequency = <13000000>;
-               #clock-cells = <0>;
-       };
-
-       rtc_clk: dummy32k {
-               compatible = "fixed-clock";
-               clock-frequency = <32000>;
-               #clock-cells = <0>;
-               clock-output-names = "clk32k";
-       };
-
-       clk26m: dummy26m {
-               compatible = "fixed-clock";
-               clock-frequency = <26000000>;
-               #clock-cells = <0>;
-               clock-output-names = "clk26m";
-       };
-
-       timer {
-               compatible = "arm,armv7-timer";
-               interrupt-parent = <&gic>;
-               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-               clock-frequency = <13000000>;
-               arm,cpu-registers-not-fw-configured;
-       };
-
-       topckgen: power-controller@10000000 {
-               compatible = "mediatek,mt7623-topckgen",
-                            "mediatek,mt2701-topckgen",
-                            "syscon";
-               reg = <0 0x10000000 0 0x1000>;
-               #clock-cells = <1>;
-       };
-
-       infracfg: power-controller@10001000 {
-               compatible = "mediatek,mt7623-infracfg",
-                            "mediatek,mt2701-infracfg",
-                            "syscon";
-               reg = <0 0x10001000 0 0x1000>;
-               #clock-cells = <1>;
-               #reset-cells = <1>;
-       };
-
-       pericfg: pericfg@10003000 {
-               compatible = "mediatek,mt7623-pericfg",
-                            "mediatek,mt2701-pericfg",
-                            "syscon";
-               reg = <0 0x10003000 0 0x1000>;
-               #clock-cells = <1>;
-               #reset-cells = <1>;
-       };
-
-       pio: pinctrl@10005000 {
-               compatible = "mediatek,mt7623-pinctrl";
-               reg = <0 0x1000b000 0 0x1000>;
-               mediatek,pctl-regmap = <&syscfg_pctl_a>;
-               pins-are-numbered;
-               gpio-controller;
-               #gpio-cells = <2>;
-               interrupt-controller;
-               interrupt-parent = <&gic>;
-               #interrupt-cells = <2>;
-               interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
-                            <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
-       };
-
-       syscfg_pctl_a: syscfg@10005000 {
-               compatible = "mediatek,mt7623-pctl-a-syscfg",
-                            "mediatek,mt2701-pctl-a-syscfg",
-                            "syscon";
-               reg = <0 0x10005000 0 0x1000>;
-       };
-
-       scpsys: scpsys@10006000 {
-               #power-domain-cells = <1>;
-               compatible = "mediatek,mt7623-scpsys",
-                            "mediatek,mt2701-scpsys";
-               reg = <0 0x10006000 0 0x1000>;
-               infracfg = <&infracfg>;
-               clocks = <&clk26m>,
-                        <&topckgen CLK_TOP_MM_SEL>,
-                        <&topckgen CLK_TOP_ETHIF_SEL>;
-               clock-names = "mfg", "mm", "ethif";
-       };
-
-       watchdog: watchdog@10007000 {
-               compatible = "mediatek,mt7623-wdt",
-                            "mediatek,mt6589-wdt";
-               reg = <0 0x10007000 0 0x100>;
-       };
-
-       timer: timer@10008000 {
-               compatible = "mediatek,mt7623-timer",
-                            "mediatek,mt6577-timer";
-               reg = <0 0x10008000 0 0x80>;
-               interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
-               clocks = <&system_clk>, <&rtc_clk>;
-               clock-names = "system-clk", "rtc-clk";
-       };
-
-       pwrap: pwrap@1000d000 {
-               compatible = "mediatek,mt7623-pwrap",
-                            "mediatek,mt2701-pwrap";
-               reg = <0 0x1000d000 0 0x1000>;
-               reg-names = "pwrap";
-               interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-               resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
-               reset-names = "pwrap";
-               clocks = <&infracfg CLK_INFRA_PMICSPI>,
-                        <&infracfg CLK_INFRA_PMICWRAP>;
-               clock-names = "spi", "wrap";
-       };
-
-       cir: cir@10013000 {
-               compatible = "mediatek,mt7623-cir";
-               reg = <0 0x10013000 0 0x1000>;
-               interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
-               clocks = <&infracfg CLK_INFRA_IRRX>;
-               clock-names = "clk";
-               status = "disabled";
-       };
-
-       sysirq: interrupt-controller@10200100 {
-               compatible = "mediatek,mt7623-sysirq",
-                            "mediatek,mt6577-sysirq";
-               interrupt-controller;
-               #interrupt-cells = <3>;
-               interrupt-parent = <&gic>;
-               reg = <0 0x10200100 0 0x1c>;
-       };
-
-       efuse: efuse@10206000 {
-               compatible = "mediatek,mt7623-efuse",
-                            "mediatek,efuse";
-               reg        = <0 0x10206000 0 0x1000>;
-               #address-cells = <1>;
-               #size-cells = <1>;
-
-               /* Data cells */
-               thermal_calibration: calib@424 {
-                       reg = <0x424 0xc>;
-               };
-       };
-
-       apmixedsys: apmixedsys@10209000 {
-               compatible = "mediatek,mt7623-apmixedsys",
-                            "mediatek,mt2701-apmixedsys";
-               reg = <0 0x10209000 0 0x1000>;
-               #clock-cells = <1>;
-       };
-
-       rng: rng@1020f000 {
-               compatible = "mediatek,mt7623-rng";
-               reg = <0 0x1020f000 0 0x1000>;
-               clocks = <&infracfg CLK_INFRA_TRNG>;
-               clock-names = "rng";
-       };
-
-       gic: interrupt-controller@10211000 {
-               compatible = "arm,cortex-a7-gic";
-               interrupt-controller;
-               #interrupt-cells = <3>;
-               interrupt-parent = <&gic>;
-               reg = <0 0x10211000 0 0x1000>,
-                     <0 0x10212000 0 0x1000>,
-                     <0 0x10214000 0 0x2000>,
-                     <0 0x10216000 0 0x2000>;
-       };
-
-       auxadc: adc@11001000 {
-               compatible = "mediatek,mt7623-auxadc",
-                            "mediatek,mt2701-auxadc";
-               reg = <0 0x11001000 0 0x1000>;
-               clocks = <&pericfg CLK_PERI_AUXADC>;
-               clock-names = "main";
-               #io-channel-cells = <1>;
-       };
-
-       uart0: serial@11002000 {
-               compatible = "mediatek,mt7623-uart",
-                            "mediatek,mt6577-uart";
-               reg = <0 0x11002000 0 0x400>;
-               interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
-               clocks = <&pericfg CLK_PERI_UART0_SEL>,
-                        <&pericfg CLK_PERI_UART0>;
-               clock-names = "baud", "bus";
-               status = "disabled";
-       };
-
-       uart1: serial@11003000 {
-               compatible = "mediatek,mt7623-uart",
-                            "mediatek,mt6577-uart";
-               reg = <0 0x11003000 0 0x400>;
-               interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
-               clocks = <&pericfg CLK_PERI_UART1_SEL>,
-                        <&pericfg CLK_PERI_UART1>;
-               clock-names = "baud", "bus";
-               status = "disabled";
-       };
-
-       uart2: serial@11004000 {
-               compatible = "mediatek,mt7623-uart",
-                            "mediatek,mt6577-uart";
-               reg = <0 0x11004000 0 0x400>;
-               interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
-               clocks = <&pericfg CLK_PERI_UART2_SEL>,
-                        <&pericfg CLK_PERI_UART2>;
-               clock-names = "baud", "bus";
-               status = "disabled";
-       };
-
-       uart3: serial@11005000 {
-               compatible = "mediatek,mt7623-uart",
-                            "mediatek,mt6577-uart";
-               reg = <0 0x11005000 0 0x400>;
-               interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
-               clocks = <&pericfg CLK_PERI_UART3_SEL>,
-                        <&pericfg CLK_PERI_UART3>;
-               clock-names = "baud", "bus";
-               status = "disabled";
-       };
-
-       pwm: pwm@11006000 {
-               compatible = "mediatek,mt7623-pwm";
-
-               reg = <0 0x11006000 0 0x1000>;
-               resets = <&pericfg MT2701_PERI_PWM_SW_RST>;
-               reset-names = "pwm";
-
-               #pwm-cells = <2>;
-               clocks = <&topckgen CLK_TOP_PWM_SEL>,
-                        <&pericfg CLK_PERI_PWM>,
-                        <&pericfg CLK_PERI_PWM1>,
-                        <&pericfg CLK_PERI_PWM2>,
-                        <&pericfg CLK_PERI_PWM3>,
-                        <&pericfg CLK_PERI_PWM4>,
-                        <&pericfg CLK_PERI_PWM5>;
-               clock-names = "top", "main", "pwm1", "pwm2",
-                             "pwm3", "pwm4", "pwm5";
-
-               status = "disabled";
-       };
-
-       i2c0: i2c@11007000 {
-               compatible = "mediatek,mt7623-i2c",
-                            "mediatek,mt6577-i2c";
-               reg = <0 0x11007000 0 0x70>,
-                     <0 0x11000200 0 0x80>;
-               interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
-               clock-div = <16>;
-               clocks = <&pericfg CLK_PERI_I2C0>,
-                        <&pericfg CLK_PERI_AP_DMA>;
-               clock-names = "main", "dma";
-               #address-cells = <1>;
-               #size-cells = <0>;
-               status = "disabled";
-       };
-
-       i2c1: i2c@11008000 {
-               compatible = "mediatek,mt7623-i2c",
-                            "mediatek,mt6577-i2c";
-               reg = <0 0x11008000 0 0x70>,
-                     <0 0x11000280 0 0x80>;
-               interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
-               clock-div = <16>;
-               clocks = <&pericfg CLK_PERI_I2C1>,
-                        <&pericfg CLK_PERI_AP_DMA>;
-               clock-names = "main", "dma";
-               #address-cells = <1>;
-               #size-cells = <0>;
-               status = "disabled";
-       };
-
-       i2c2: i2c@11009000 {
-               compatible = "mediatek,mt7623-i2c",
-                            "mediatek,mt6577-i2c";
-               reg = <0 0x11009000 0 0x70>,
-                     <0 0x11000300 0 0x80>;
-               interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
-               clock-div = <16>;
-               clocks = <&pericfg CLK_PERI_I2C2>,
-                        <&pericfg CLK_PERI_AP_DMA>;
-               clock-names = "main", "dma";
-               #address-cells = <1>;
-               #size-cells = <0>;
-               status = "disabled";
-       };
-
-       spi0: spi@1100a000 {
-               compatible = "mediatek,mt7623-spi",
-                            "mediatek,mt6589-spi";
-               reg = <0 0x1100a000 0 0x1000>;
-               interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
-               clocks = <&pericfg CLK_PERI_SPI0>;
-               clock-names = "main";
-
-               status = "disabled";
-       };
-
-       thermal: thermal@1100b000 {
-               #thermal-sensor-cells = <1>;
-               compatible = "mediatek,mt2701-thermal",
-                            "mediatek,mt2701-thermal";
-               reg = <0 0x1100b000 0 0x1000>;
-               interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
-               clocks = <&pericfg CLK_PERI_THERM>,
-                        <&pericfg CLK_PERI_AUXADC>;
-               clock-names = "therm", "auxadc";
-               resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
-               reset-names = "therm";
-               mediatek,auxadc = <&auxadc>;
-               mediatek,apmixedsys = <&apmixedsys>;
-
-               nvmem-cells = <&thermal_calibration>;
-               nvmem-cell-names = "calibration-data";
-       };
-
-       spi1: spi@11016000 {
-               compatible = "mediatek,mt7623-spi",
-                            "mediatek,mt2701-spi";
-               #address-cells = <1>;
-               #size-cells = <0>;
-               reg = <0 0x11016000 0 0x100>;
-               interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
-               clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
-                        <&topckgen CLK_TOP_SPI1_SEL>,
-                        <&pericfg CLK_PERI_SPI1>;
-               clock-names = "parent-clk", "sel-clk", "spi-clk";
-               status = "disabled";
-       };
-
-       spi2: spi@11017000 {
-               compatible = "mediatek,mt7623-spi",
-                       "mediatek,mt2701-spi";
-               #address-cells = <1>;
-               #size-cells = <0>;
-               reg = <0 0x11017000 0 0x1000>;
-               interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
-               clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
-                        <&topckgen CLK_TOP_SPI2_SEL>,
-                        <&pericfg CLK_PERI_SPI2>;
-               clock-names = "parent-clk", "sel-clk", "spi-clk";
-               status = "disabled";
-       };
-
-       nandc: nfi@1100d000 {
-               compatible = "mediatek,mt7623-nfc",
-                            "mediatek,mt2701-nfc";
-               reg = <0 0x1100d000 0 0x1000>;
-               power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
-               interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
-               clocks = <&pericfg CLK_PERI_NFI>,
-                        <&pericfg CLK_PERI_NFI_PAD>;
-               clock-names = "nfi_clk", "pad_clk";
-               status = "disabled";
-               ecc-engine = <&bch>;
-               #address-cells = <1>;
-               #size-cells = <0>;
-       };
-
-       bch: ecc@1100e000 {
-               compatible = "mediatek,mt7623-ecc",
-                            "mediatek,mt2701-ecc";
-               reg = <0 0x1100e000 0 0x1000>;
-               interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
-               clocks = <&pericfg CLK_PERI_NFI_ECC>;
-               clock-names = "nfiecc_clk";
-               status = "disabled";
-       };
-
-       afe: audio-controller@11220000 {
-       compatible = "mediatek,mt7623-audio",
-                    "mediatek,mt2701-audio";
-       reg = <0 0x11220000 0 0x2000>,
-             <0 0x112a0000 0 0x20000>;
-       interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
-       power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
-       
-       clocks = <&infracfg CLK_INFRA_AUDIO>,
-                <&topckgen CLK_TOP_AUD_MUX1_SEL>,
-                <&topckgen CLK_TOP_AUD_MUX2_SEL>,
-                <&topckgen CLK_TOP_AUD_MUX1_DIV>,
-                <&topckgen CLK_TOP_AUD_MUX2_DIV>,
-                <&topckgen CLK_TOP_AUD_48K_TIMING>,
-                <&topckgen CLK_TOP_AUD_44K_TIMING>,
-                <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
-                <&topckgen CLK_TOP_APLL_SEL>,
-                <&topckgen CLK_TOP_AUD1PLL_98M>,
-                <&topckgen CLK_TOP_AUD2PLL_90M>,
-                <&topckgen CLK_TOP_HADDS2PLL_98M>,
-                <&topckgen CLK_TOP_HADDS2PLL_294M>,
-                <&topckgen CLK_TOP_AUDPLL>,
-                <&topckgen CLK_TOP_AUDPLL_D4>,
-                <&topckgen CLK_TOP_AUDPLL_D8>,
-                <&topckgen CLK_TOP_AUDPLL_D16>,
-                <&topckgen CLK_TOP_AUDPLL_D24>,
-                <&topckgen CLK_TOP_AUDINTBUS_SEL>,
-                <&clk26m>,
-                <&topckgen CLK_TOP_SYSPLL1_D4>,
-                <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
-                <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
-                <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
-                <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
-                <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
-                <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
-                <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
-                <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
-                <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
-                <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
-                <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
-                <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
-                <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
-                <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
-                <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
-                <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
-                <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
-                <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
-                <&topckgen CLK_TOP_ASM_M_SEL>,
-                <&topckgen CLK_TOP_ASM_H_SEL>,
-                <&topckgen CLK_TOP_UNIVPLL2_D4>,
-                <&topckgen CLK_TOP_UNIVPLL2_D2>,
-                <&topckgen CLK_TOP_SYSPLL_D5>;
-       clock-names = "infra_sys_audio_clk",
-               "top_audio_mux1_sel",
-               "top_audio_mux2_sel",
-               "top_audio_mux1_div",
-               "top_audio_mux2_div",
-               "top_audio_48k_timing",
-               "top_audio_44k_timing",
-               "top_audpll_mux_sel",
-               "top_apll_sel",
-               "top_aud1_pll_98M",
-               "top_aud2_pll_90M",
-               "top_hadds2_pll_98M",
-               "top_hadds2_pll_294M",
-               "top_audpll",
-               "top_audpll_d4",
-               "top_audpll_d8",
-               "top_audpll_d16",
-               "top_audpll_d24",
-               "top_audintbus_sel",
-               "clk_26m",
-               "top_syspll1_d4",
-               "top_aud_k1_src_sel",
-               "top_aud_k2_src_sel",
-               "top_aud_k3_src_sel",
-               "top_aud_k4_src_sel",
-               "top_aud_k5_src_sel",
-               "top_aud_k6_src_sel",
-               "top_aud_k1_src_div",
-               "top_aud_k2_src_div",
-               "top_aud_k3_src_div",
-               "top_aud_k4_src_div",
-               "top_aud_k5_src_div",
-               "top_aud_k6_src_div",
-               "top_aud_i2s1_mclk",
-               "top_aud_i2s2_mclk",
-               "top_aud_i2s3_mclk",
-               "top_aud_i2s4_mclk",
-               "top_aud_i2s5_mclk",
-               "top_aud_i2s6_mclk",
-               "top_asm_m_sel",
-               "top_asm_h_sel",
-               "top_univpll2_d4",
-               "top_univpll2_d2",
-               "top_syspll_d5";
-       };
-
-       mmc0: mmc@11230000 {
-               compatible = "mediatek,mt7623-mmc",
-                            "mediatek,mt8135-mmc";
-               reg = <0 0x11230000 0 0x1000>;
-               interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
-               clocks = <&pericfg CLK_PERI_MSDC30_0>,
-                        <&topckgen CLK_TOP_MSDC30_0_SEL>;
-               clock-names = "source", "hclk";
-               status = "disabled";
-       };
-
-       mmc1: mmc@11240000 {
-               compatible = "mediatek,mt7623-mmc",
-                            "mediatek,mt8135-mmc";
-               reg = <0 0x11240000 0 0x1000>;
-               interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
-               clocks = <&pericfg CLK_PERI_MSDC30_1>,
-                        <&topckgen CLK_TOP_MSDC30_1_SEL>;
-               clock-names = "source", "hclk";
-               status = "disabled";
-       };
-
-       usb1: usb@1a1c0000 {
-               compatible = "mediatek,mt7623-xhci",
-                            "mediatek,mt8173-xhci";
-               reg = <0 0x1a1c0000 0 0x1000>,
-                     <0 0x1a1c4700 0 0x0100>;
-               interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
-               clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
-                        <&topckgen CLK_TOP_ETHIF_SEL>;
-               clock-names = "sys_ck", "ethif";
-               power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
-               phys = <&phy_port0 PHY_TYPE_USB3>;
-               status = "disabled";
-       };
-
-       u3phy1: usb-phy@1a1c4000 {
-               compatible = "mediatek,mt2701-u3phy",
-                            "mediatek,mt8173-u3phy";
-               reg = <0 0x1a1c4000 0 0x0700>;
-               clocks = <&clk26m>;
-               clock-names = "u3phya_ref";
-               #phy-cells = <1>;
-               #address-cells = <2>;
-               #size-cells = <2>;
-               ranges;
-               status = "disabled";
-
-               phy_port0: phy_port0: port@1a1c4800 {
-                       reg = <0 0x1a1c4800 0 0x800>;
-                       #phy-cells = <1>;
-                       status = "okay";
-               };
-       };
-
-       usb2: usb@1a240000 {
-               compatible = "mediatek,mt2701-xhci",
-                            "mediatek,mt8173-xhci";
-               reg = <0 0x1a240000 0 0x1000>,
-                     <0 0x1a244700 0 0x0100>;
-               interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
-               clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
-                        <&topckgen CLK_TOP_ETHIF_SEL>;
-               clock-names = "sys_ck", "ethif";
-               power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
-               phys = <&u3phy2 0>;
-               status = "disabled";
-       };
-
-       u3phy2: usb-phy@1a244000 {
-               compatible = "mediatek,mt2701-u3phy",
-                            "mediatek,mt8173-u3phy";
-               reg = <0 0x1a244000 0 0x0700>,
-                     <0 0x1a244800 0 0x0800>;
-               clocks = <&clk26m>;
-               clock-names = "u3phya_ref";
-               #phy-cells = <1>;
-               status = "disabled";
-       };
-
-       hifsys: clock-controller@1a000000 {
-               compatible = "mediatek,mt7623-hifsys",
-                            "mediatek,mt2701-hifsys",
-                            "syscon";
-               reg = <0 0x1a000000 0 0x1000>;
-               #clock-cells = <1>;
-               #reset-cells = <1>;
-       };
-
-       pcie: pcie@1a140000 {
-               compatible = "mediatek,mt7623-pcie";
-               device_type = "pci";
-               reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
-                     <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
-                     <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
-                     <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
-               reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
-               interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
-                            <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
-                            <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
-               interrupt-names = "pcie0", "pcie1", "pcie2";
-               clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
-               clock-names = "pcie";
-               power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
-               resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
-                        <&hifsys MT2701_HIFSYS_PCIE1_RST>,
-                        <&hifsys MT2701_HIFSYS_PCIE2_RST>;
-               reset-names = "pcie0", "pcie1", "pcie2";
-
-               mediatek,hifsys = <&hifsys>;
-
-               bus-range = <0x00 0xff>;
-               #address-cells = <3>;
-               #size-cells = <2>;
-
-               ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
-                         0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
-
-               status = "disabled";
-
-               pcie@1,0 {
-                       device_type = "pci";
-                       reg = <0x0800 0 0 0 0>;
-
-                       #address-cells = <3>;
-                       #size-cells = <2>;
-                       ranges;
-               };
-
-               pcie@2,0{
-                       device_type = "pci";
-                       reg = <0x1000 0 0 0 0>;
-
-                       #address-cells = <3>;
-                       #size-cells = <2>;
-                       ranges;
-               };
-
-               pcie@3,0{
-                       device_type = "pci";
-                       reg = <0x1800 0 0 0 0>;
-
-                       #address-cells = <3>;
-                       #size-cells = <2>;
-                       ranges;
-               };
-       };
-
-       ethsys: syscon@1b000000 {
-               compatible = "mediatek,mt7623-ethsys",
-                            "mediatek,mt2701-ethsys",
-                            "syscon";
-               reg = <0 0x1b000000 0 0x1000>;
-               #reset-cells = <1>;
-               #clock-cells = <1>;
-       };
-
-       eth: ethernet@1b100000 {
-               compatible = "mediatek,mt7623-eth",
-                            "mediatek,mt2701-eth",
-                            "syscon";
-               reg = <0 0x1b100000 0 0x20000>;
-
-               clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
-                        <&ethsys CLK_ETHSYS_ESW>,
-                        <&ethsys CLK_ETHSYS_GP2>,
-                        <&ethsys CLK_ETHSYS_GP1>,
-                        <&apmixedsys CLK_APMIXED_TRGPLL>;
-               clock-names = "ethif", "esw", "gp2", "gp1", "trgpll";
-               interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
-                             GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
-                             GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
-               power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
-
-               resets = <&ethsys 6>;
-               reset-names = "eth";
-
-               mediatek,ethsys = <&ethsys>;
-               mediatek,pctl = <&syscfg_pctl_a>;
-
-               #address-cells = <1>;
-               #size-cells = <0>;
-
-               status = "disabled";
-
-               gmac1: mac@0 {
-                       compatible = "mediatek,eth-mac";
-                       reg = <0>;
-
-                       status = "disabled";
-
-                       phy-mode = "trgmii";
-
-                       fixed-link {
-                               speed = <1000>;
-                               full-duplex;
-                               pause;
-                       };
-               };
-
-               gmac2: mac@1 {
-                       compatible = "mediatek,eth-mac";
-                       reg = <1>;
-
-                       status = "disabled";
-               };
-
-               mdio0: mdio-bus {
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-               };
-       };
-
-       hnat: hnat@1b000000 {
-               compatible = "mediatek,mt7623-hnat";
-               reg = <0 0x1b100000 0 0x3000>;
-               mtketh-wan = "eth1";
-               resets = <&ethsys 0>;
-               reset-names = "mtketh";
-       };
-
-       crypto: crypto@1b240000 {
-               compatible = "mediatek,mt7623-crypto", "mediatek,eip97-crypto";
-               reg = <0 0x1b240000 0 0x20000>;
-               interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
-                            <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
-                            <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
-                            <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
-                            <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
-               clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
-                        <&ethsys CLK_ETHSYS_CRYPTO>;
-               clock-names = "ethif","cryp";
-               power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
-       };
-};
diff --git a/target/linux/mediatek/files/arch/arm/boot/dts/mt6323.dtsi b/target/linux/mediatek/files/arch/arm/boot/dts/mt6323.dtsi
deleted file mode 100644 (file)
index 7c783d6..0000000
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * Copyright (c) 2017 MediaTek Inc.
- * Author: John Crispin <john@phrozen.org>
- *        Sean Wang <sean.wang@mediatek.com>
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-&pwrap {
-       pmic: mt6323 {
-               compatible = "mediatek,mt6323";
-               interrupt-parent = <&pio>;
-               interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
-               interrupt-controller;
-               #interrupt-cells = <2>;
-
-               mt6323regulator: mt6323regulator{
-                       compatible = "mediatek,mt6323-regulator";
-
-                       mt6323_vproc_reg: buck_vproc{
-                               regulator-name = "vproc";
-                               regulator-min-microvolt = < 700000>;
-                               regulator-max-microvolt = <1350000>;
-                               regulator-ramp-delay = <12500>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vsys_reg: buck_vsys{
-                               regulator-name = "vsys";
-                               regulator-min-microvolt = <1400000>;
-                               regulator-max-microvolt = <2987500>;
-                               regulator-ramp-delay = <25000>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vpa_reg: buck_vpa{
-                               regulator-name = "vpa";
-                               regulator-min-microvolt = < 500000>;
-                               regulator-max-microvolt = <3650000>;
-                       };
-
-                       mt6323_vtcxo_reg: ldo_vtcxo{
-                               regulator-name = "vtcxo";
-                               regulator-min-microvolt = <2800000>;
-                               regulator-max-microvolt = <2800000>;
-                               regulator-enable-ramp-delay = <90>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vcn28_reg: ldo_vcn28{
-                               regulator-name = "vcn28";
-                               regulator-min-microvolt = <2800000>;
-                               regulator-max-microvolt = <2800000>;
-                               regulator-enable-ramp-delay = <185>;
-                       };
-
-                       mt6323_vcn33_bt_reg: ldo_vcn33_bt{
-                               regulator-name = "vcn33_bt";
-                               regulator-min-microvolt = <3300000>;
-                               regulator-max-microvolt = <3600000>;
-                               regulator-enable-ramp-delay = <185>;
-                       };
-
-                       mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{
-                               regulator-name = "vcn33_wifi";
-                               regulator-min-microvolt = <3300000>;
-                               regulator-max-microvolt = <3600000>;
-                               regulator-enable-ramp-delay = <185>;
-                       };
-
-                       mt6323_va_reg: ldo_va{
-                               regulator-name = "va";
-                               regulator-min-microvolt = <2800000>;
-                               regulator-max-microvolt = <2800000>;
-                               regulator-enable-ramp-delay = <216>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vcama_reg: ldo_vcama{
-                               regulator-name = "vcama";
-                               regulator-min-microvolt = <1500000>;
-                               regulator-max-microvolt = <2800000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vio28_reg: ldo_vio28{
-                               regulator-name = "vio28";
-                               regulator-min-microvolt = <2800000>;
-                               regulator-max-microvolt = <2800000>;
-                               regulator-enable-ramp-delay = <216>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vusb_reg: ldo_vusb{
-                               regulator-name = "vusb";
-                               regulator-min-microvolt = <3300000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <216>;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vmc_reg: ldo_vmc{
-                               regulator-name = "vmc";
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <36>;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vmch_reg: ldo_vmch{
-                               regulator-name = "vmch";
-                               regulator-min-microvolt = <3000000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <36>;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vemc3v3_reg: ldo_vemc3v3{
-                               regulator-name = "vemc3v3";
-                               regulator-min-microvolt = <3000000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <36>;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vgp1_reg: ldo_vgp1{
-                               regulator-name = "vgp1";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vgp2_reg: ldo_vgp2{
-                               regulator-name = "vgp2";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <3000000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vgp3_reg: ldo_vgp3{
-                               regulator-name = "vgp3";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vcn18_reg: ldo_vcn18{
-                               regulator-name = "vcn18";
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vsim1_reg: ldo_vsim1{
-                               regulator-name = "vsim1";
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3000000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vsim2_reg: ldo_vsim2{
-                               regulator-name = "vsim2";
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3000000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vrtc_reg: ldo_vrtc{
-                               regulator-name = "vrtc";
-                               regulator-min-microvolt = <2800000>;
-                               regulator-max-microvolt = <2800000>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vcamaf_reg: ldo_vcamaf{
-                               regulator-name = "vcamaf";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vibr_reg: ldo_vibr{
-                               regulator-name = "vibr";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <36>;
-                       };
-
-                       mt6323_vrf18_reg: ldo_vrf18{
-                               regulator-name = "vrf18";
-                               regulator-min-microvolt = <1825000>;
-                               regulator-max-microvolt = <1825000>;
-                               regulator-enable-ramp-delay = <187>;
-                       };
-
-                       mt6323_vm_reg: ldo_vm{
-                               regulator-name = "vm";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-enable-ramp-delay = <216>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vio18_reg: ldo_vio18{
-                               regulator-name = "vio18";
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-enable-ramp-delay = <216>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vcamd_reg: ldo_vcamd{
-                               regulator-name = "vcamd";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vcamio_reg: ldo_vcamio{
-                               regulator-name = "vcamio";
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-               };
-       };
-};
diff --git a/target/linux/mediatek/files/arch/arm/boot/dts/mt7623-NAND-ePHY.dts b/target/linux/mediatek/files/arch/arm/boot/dts/mt7623-NAND-ePHY.dts
deleted file mode 100644 (file)
index bcd2df2..0000000
+++ /dev/null
@@ -1,523 +0,0 @@
-/*
- * Copyright (c) 2016 MediaTek Inc.
- * Author: John Crispin <blogic@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/dts-v1/;
-
-#include "_mt7623.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-       model = "MediaTek MT7623 NAND reference board";
-       compatible = "mediatek,mt7623-rfb-nand-ephy", "mediatek,mt7623";
-
-       chosen {
-               stdout-path = &uart2;
-       };
-
-       memory {
-               reg = <0 0x80000000 0 0x20000000>;
-       };
-
-       usb_p1_vbus: regulator@0 {
-               compatible = "regulator-fixed";
-               regulator-name = "usb_vbus";
-               regulator-min-microvolt = <5000000>;
-               regulator-max-microvolt = <5000000>;
-               gpio = <&pio 135 GPIO_ACTIVE_HIGH>;
-               enable-active-high;
-       };
-};
-
-&cpu0 {
-       proc-supply = <&mt6323_vproc_reg>;
-};
-
-&cpu1 {
-       proc-supply = <&mt6323_vproc_reg>;
-};
-
-&cpu2 {
-       proc-supply = <&mt6323_vproc_reg>;
-};
-
-&cpu3 {
-       proc-supply = <&mt6323_vproc_reg>;
-};
-
-&pwrap {
-       pmic: mt6323 {
-               compatible = "mediatek,mt6323";
-               interrupt-parent = <&pio>;
-               interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
-               interrupt-controller;
-               #interrupt-cells = <2>;
-
-               mt6323regulator: mt6323regulator{
-                       compatible = "mediatek,mt6323-regulator";
-
-                       mt6323_vproc_reg: buck_vproc{
-                               regulator-name = "vproc";
-                               regulator-min-microvolt = < 700000>;
-                               regulator-max-microvolt = <1350000>;
-                               regulator-ramp-delay = <12500>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vsys_reg: buck_vsys{
-                               regulator-name = "vsys";
-                               regulator-min-microvolt = <1400000>;
-                               regulator-max-microvolt = <2987500>;
-                               regulator-ramp-delay = <25000>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vpa_reg: buck_vpa{
-                               regulator-name = "vpa";
-                               regulator-min-microvolt = < 500000>;
-                               regulator-max-microvolt = <3650000>;
-                       };
-
-                       mt6323_vtcxo_reg: ldo_vtcxo{
-                               regulator-name = "vtcxo";
-                               regulator-min-microvolt = <2800000>;
-                               regulator-max-microvolt = <2800000>;
-                               regulator-enable-ramp-delay = <90>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vcn28_reg: ldo_vcn28{
-                               regulator-name = "vcn28";
-                               regulator-min-microvolt = <2800000>;
-                               regulator-max-microvolt = <2800000>;
-                               regulator-enable-ramp-delay = <185>;
-                       };
-
-                       mt6323_vcn33_bt_reg: ldo_vcn33_bt{
-                               regulator-name = "vcn33_bt";
-                               regulator-min-microvolt = <3300000>;
-                               regulator-max-microvolt = <3600000>;
-                               regulator-enable-ramp-delay = <185>;
-                       };
-
-                       mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{
-                               regulator-name = "vcn33_wifi";
-                               regulator-min-microvolt = <3300000>;
-                               regulator-max-microvolt = <3600000>;
-                               regulator-enable-ramp-delay = <185>;
-                       };
-
-                       mt6323_va_reg: ldo_va{
-                               regulator-name = "va";
-                               regulator-min-microvolt = <2800000>;
-                               regulator-max-microvolt = <2800000>;
-                               regulator-enable-ramp-delay = <216>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vcama_reg: ldo_vcama{
-                               regulator-name = "vcama";
-                               regulator-min-microvolt = <1500000>;
-                               regulator-max-microvolt = <2800000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vio28_reg: ldo_vio28{
-                               regulator-name = "vio28";
-                               regulator-min-microvolt = <2800000>;
-                               regulator-max-microvolt = <2800000>;
-                               regulator-enable-ramp-delay = <216>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vusb_reg: ldo_vusb{
-                               regulator-name = "vusb";
-                               regulator-min-microvolt = <3300000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <216>;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vmc_reg: ldo_vmc{
-                               regulator-name = "vmc";
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <36>;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vmch_reg: ldo_vmch{
-                               regulator-name = "vmch";
-                               regulator-min-microvolt = <3000000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <36>;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vemc3v3_reg: ldo_vemc3v3{
-                               regulator-name = "vemc3v3";
-                               regulator-min-microvolt = <3000000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <36>;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vgp1_reg: ldo_vgp1{
-                               regulator-name = "vgp1";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vgp2_reg: ldo_vgp2{
-                               regulator-name = "vgp2";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <3000000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vgp3_reg: ldo_vgp3{
-                               regulator-name = "vgp3";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vcn18_reg: ldo_vcn18{
-                               regulator-name = "vcn18";
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vsim1_reg: ldo_vsim1{
-                               regulator-name = "vsim1";
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3000000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vsim2_reg: ldo_vsim2{
-                               regulator-name = "vsim2";
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3000000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vrtc_reg: ldo_vrtc{
-                               regulator-name = "vrtc";
-                               regulator-min-microvolt = <2800000>;
-                               regulator-max-microvolt = <2800000>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vcamaf_reg: ldo_vcamaf{
-                               regulator-name = "vcamaf";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vibr_reg: ldo_vibr{
-                               regulator-name = "vibr";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <36>;
-                       };
-
-                       mt6323_vrf18_reg: ldo_vrf18{
-                               regulator-name = "vrf18";
-                               regulator-min-microvolt = <1825000>;
-                               regulator-max-microvolt = <1825000>;
-                               regulator-enable-ramp-delay = <187>;
-                       };
-
-                       mt6323_vm_reg: ldo_vm{
-                               regulator-name = "vm";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-enable-ramp-delay = <216>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vio18_reg: ldo_vio18{
-                               regulator-name = "vio18";
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-enable-ramp-delay = <216>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vcamd_reg: ldo_vcamd{
-                               regulator-name = "vcamd";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vcamio_reg: ldo_vcamio{
-                               regulator-name = "vcamio";
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-               };
-
-               mt6323led: leds {
-                       compatible = "mediatek,mt6323-led";
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-
-                       led@0 {
-                               reg = <0>;
-                               label = "LED0";
-                               linux,default-trigger = "timer";
-                               default-state = "on";
-                       };
-                       led@1 {
-                               reg = <1>;
-                               label = "LED1";
-                               default-state = "off";
-                       };
-                       led@2 {
-                               reg = <2>;
-                               label = "LED2";
-                               default-state = "on";
-                       };
-                       led@3 {
-                               reg = <3>;
-                               label = "LED3";
-                               default-state = "on";
-                       };
-               };
-       };
-};
-
-&uart2 {
-       status = "okay";
-};
-
-&pio {
-       nand_pins_default: nanddefault {
-               pins_dat {
-                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
-                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
-                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
-                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>,
-                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>,
-                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>,
-                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>,
-                                <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
-                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
-                               input-enable;
-                               drive-strength = <MTK_DRIVE_8mA>;
-                               bias-pull-up;
-               };
-
-               pins_we {
-                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
-                       drive-strength = <MTK_DRIVE_8mA>;
-                       bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
-               };
-
-               pins_ale {
-                       pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
-                       drive-strength = <MTK_DRIVE_8mA>;
-                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
-               };
-       };
-
-       eth_default: eth {
-               pins_eth {
-                       pinmux = <MT7623_PIN_275_G2_MDC_FUNC_MDC>,
-                                <MT7623_PIN_276_G2_MDIO_FUNC_MDIO>,
-                                <MT7623_PIN_262_G2_TXEN_FUNC_G2_TXEN>,
-                                <MT7623_PIN_263_G2_TXD3_FUNC_G2_TXD3>,
-                                <MT7623_PIN_264_G2_TXD2_FUNC_G2_TXD2>,
-                                <MT7623_PIN_265_G2_TXD1_FUNC_G2_TXD1>,
-                                <MT7623_PIN_266_G2_TXD0_FUNC_G2_TXD0>,
-                                <MT7623_PIN_267_G2_TXCLK_FUNC_G2_TXC>,
-                                <MT7623_PIN_268_G2_RXCLK_FUNC_G2_RXC>,
-                                <MT7623_PIN_269_G2_RXD0_FUNC_G2_RXD0>,
-                                <MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1>,
-                                <MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2>,
-                                <MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3>,
-                                <MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV>;
-               };
-
-               pins_eth_rst {
-                       pinmux = <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
-                       output-low;
-               };
-       };
-
-       pwm_pins: pwm {
-               pins_pwm1 {
-                       pinmux = <MT7623_PIN_204_PWM1_FUNC_PWM1>;
-               };
-
-               pins_pwm2 {
-                       pinmux = <MT7623_PIN_205_PWM2_FUNC_PWM2>;
-               };
-       };
-};
-
-&nandc {
-       status = "okay";
-       pinctrl-names = "default";
-       pinctrl-0 = <&nand_pins_default>;
-       nand@0 {
-               reg = <0>;
-               spare_per_sector = <64>;
-               nand-ecc-mode = "hw";
-               nand-ecc-strength = <12>;
-               nand-ecc-step-size = <1024>;
-               partitions {
-                       compatible = "fixed-partitions";
-                       #address-cells = <1>;
-                       #size-cells = <1>;
-
-                       partition@C0000 {
-                               label = "uboot-env";
-                               reg = <0xC0000 0x40000>;
-                       };
-
-                       partition@100000 {
-                               label = "factory";
-                               reg = <0x100000 0x40000>;
-                       };
-
-                       partition@140000 {
-                               label = "kernel";
-                               reg = <0x140000 0x2000000>;
-                       };
-
-                       partition@2140000 {
-                               label = "recovery";
-                               reg = <0x2140000 0x2000000>;
-                       };
-
-                       partition@4140000 {
-                               label = "ubi";
-                               reg = <0x4140000 0x1000000>;
-                       };
-               };
-       };
-};
-&bch {
-       status = "okay";
-};
-
-&usb1 {
-       vusb33-supply = <&mt6323_vusb_reg>;
-       vbus-supply = <&usb_p1_vbus>;
-       status = "okay";
-};
-
-&u3phy1 {
-       status = "okay";
-};
-
-&pcie {
-       status = "okay";
-};
-
-&eth {
-       status = "okay";
-};
-
-&gmac1 {
-       mac-address = [00 11 22 33 44 56];
-       status = "okay";
-};
-
-&gmac2 {
-       mac-address = [00 11 22 33 44 55];
-       status = "okay";
-
-       phy-handle = <&phy5>;
-};
-
-&mdio0 {
-       switch@0 {
-               compatible = "mediatek,mt7530";
-               #address-cells = <1>;
-               #size-cells = <0>;
-               reg = <0>;
-
-               pinctrl-names = "default";
-               pinctrl-0 = <&eth_default>;
-
-               core-supply = <&mt6323_vpa_reg>;
-               io-supply = <&mt6323_vemc3v3_reg>;
-
-               mediatek,mcm;
-               resets = <&ethsys 2>;
-               reset-names = "mcm";
-
-               ports {
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-                       reg = <0>;
-                       port@0 {
-                               reg = <0>;
-                               label = "lan0";
-                       };
-
-                       port@1 {
-                               reg = <1>;
-                               label = "lan1";
-                       };
-
-                       port@2 {
-                               reg = <2>;
-                               label = "lan2";
-                       };
-
-                       port@3 {
-                               reg = <3>;
-                               label = "lan3";
-                       };
-
-                       port@6 {
-                               reg = <6>;
-                               label = "cpu";
-                               ethernet = <&gmac1>;
-                               phy-mode = "trgmii";
-                               fixed-link {
-                                       speed = <1000>;
-                                       full-duplex;
-                               };
-                       };
-               };
-       };
-
-       phy5: ethernet-phy@5 {
-               reg = <5>;
-               phy-mode = "rgmii-rxid";
-       };
-};
-
-&pwm {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pwm_pins>;
-       status = "okay";
-};
diff --git a/target/linux/mediatek/files/arch/arm/boot/dts/mt7623-NAND.dts b/target/linux/mediatek/files/arch/arm/boot/dts/mt7623-NAND.dts
deleted file mode 100644 (file)
index d9f08d0..0000000
+++ /dev/null
@@ -1,553 +0,0 @@
-/*
- * Copyright (c) 2016 MediaTek Inc.
- * Author: John Crispin <blogic@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/dts-v1/;
-
-#include "_mt7623.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-       model = "MediaTek MT7623 NAND reference board";
-       compatible = "mediatek,mt7623-rfb-nand", "mediatek,mt7623";
-
-       chosen {
-               stdout-path = &uart2;
-       };
-
-       memory {
-               reg = <0 0x80000000 0 0x20000000>;
-       };
-
-       usb_p1_vbus: regulator@0 {
-               compatible = "regulator-fixed";
-               regulator-name = "usb_vbus";
-               regulator-min-microvolt = <5000000>;
-               regulator-max-microvolt = <5000000>;
-               gpio = <&pio 135 GPIO_ACTIVE_HIGH>;
-               enable-active-high;
-       };
-};
-
-&cpu0 {
-       proc-supply = <&mt6323_vproc_reg>;
-};
-
-&cpu1 {
-       proc-supply = <&mt6323_vproc_reg>;
-};
-
-&cpu2 {
-       proc-supply = <&mt6323_vproc_reg>;
-};
-
-&cpu3 {
-       proc-supply = <&mt6323_vproc_reg>;
-};
-
-&pwrap {
-       pmic: mt6323 {
-               compatible = "mediatek,mt6323";
-               interrupt-parent = <&pio>;
-               interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
-               interrupt-controller;
-               #interrupt-cells = <2>;
-
-               mt6323regulator: mt6323regulator{
-                       compatible = "mediatek,mt6323-regulator";
-
-                       mt6323_vproc_reg: buck_vproc{
-                               regulator-name = "vproc";
-                               regulator-min-microvolt = < 700000>;
-                               regulator-max-microvolt = <1350000>;
-                               regulator-ramp-delay = <12500>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vsys_reg: buck_vsys{
-                               regulator-name = "vsys";
-                               regulator-min-microvolt = <1400000>;
-                               regulator-max-microvolt = <2987500>;
-                               regulator-ramp-delay = <25000>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vpa_reg: buck_vpa{
-                               regulator-name = "vpa";
-                               regulator-min-microvolt = < 500000>;
-                               regulator-max-microvolt = <3650000>;
-                       };
-
-                       mt6323_vtcxo_reg: ldo_vtcxo{
-                               regulator-name = "vtcxo";
-                               regulator-min-microvolt = <2800000>;
-                               regulator-max-microvolt = <2800000>;
-                               regulator-enable-ramp-delay = <90>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vcn28_reg: ldo_vcn28{
-                               regulator-name = "vcn28";
-                               regulator-min-microvolt = <2800000>;
-                               regulator-max-microvolt = <2800000>;
-                               regulator-enable-ramp-delay = <185>;
-                       };
-
-                       mt6323_vcn33_bt_reg: ldo_vcn33_bt{
-                               regulator-name = "vcn33_bt";
-                               regulator-min-microvolt = <3300000>;
-                               regulator-max-microvolt = <3600000>;
-                               regulator-enable-ramp-delay = <185>;
-                       };
-
-                       mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{
-                               regulator-name = "vcn33_wifi";
-                               regulator-min-microvolt = <3300000>;
-                               regulator-max-microvolt = <3600000>;
-                               regulator-enable-ramp-delay = <185>;
-                       };
-
-                       mt6323_va_reg: ldo_va{
-                               regulator-name = "va";
-                               regulator-min-microvolt = <2800000>;
-                               regulator-max-microvolt = <2800000>;
-                               regulator-enable-ramp-delay = <216>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vcama_reg: ldo_vcama{
-                               regulator-name = "vcama";
-                               regulator-min-microvolt = <1500000>;
-                               regulator-max-microvolt = <2800000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vio28_reg: ldo_vio28{
-                               regulator-name = "vio28";
-                               regulator-min-microvolt = <2800000>;
-                               regulator-max-microvolt = <2800000>;
-                               regulator-enable-ramp-delay = <216>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vusb_reg: ldo_vusb{
-                               regulator-name = "vusb";
-                               regulator-min-microvolt = <3300000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <216>;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vmc_reg: ldo_vmc{
-                               regulator-name = "vmc";
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <36>;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vmch_reg: ldo_vmch{
-                               regulator-name = "vmch";
-                               regulator-min-microvolt = <3000000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <36>;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vemc3v3_reg: ldo_vemc3v3{
-                               regulator-name = "vemc3v3";
-                               regulator-min-microvolt = <3000000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <36>;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vgp1_reg: ldo_vgp1{
-                               regulator-name = "vgp1";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vgp2_reg: ldo_vgp2{
-                               regulator-name = "vgp2";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <3000000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vgp3_reg: ldo_vgp3{
-                               regulator-name = "vgp3";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vcn18_reg: ldo_vcn18{
-                               regulator-name = "vcn18";
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vsim1_reg: ldo_vsim1{
-                               regulator-name = "vsim1";
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3000000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vsim2_reg: ldo_vsim2{
-                               regulator-name = "vsim2";
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3000000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vrtc_reg: ldo_vrtc{
-                               regulator-name = "vrtc";
-                               regulator-min-microvolt = <2800000>;
-                               regulator-max-microvolt = <2800000>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vcamaf_reg: ldo_vcamaf{
-                               regulator-name = "vcamaf";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vibr_reg: ldo_vibr{
-                               regulator-name = "vibr";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <36>;
-                       };
-
-                       mt6323_vrf18_reg: ldo_vrf18{
-                               regulator-name = "vrf18";
-                               regulator-min-microvolt = <1825000>;
-                               regulator-max-microvolt = <1825000>;
-                               regulator-enable-ramp-delay = <187>;
-                       };
-
-                       mt6323_vm_reg: ldo_vm{
-                               regulator-name = "vm";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-enable-ramp-delay = <216>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vio18_reg: ldo_vio18{
-                               regulator-name = "vio18";
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-enable-ramp-delay = <216>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vcamd_reg: ldo_vcamd{
-                               regulator-name = "vcamd";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vcamio_reg: ldo_vcamio{
-                               regulator-name = "vcamio";
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-               };
-
-               mt6323led: leds {
-                       compatible = "mediatek,mt6323-led";
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-
-                       led@0 {
-                               reg = <0>;
-                               label = "LED0";
-                               linux,default-trigger = "timer";
-                               default-state = "on";
-                       };
-                       led@1 {
-                               reg = <1>;
-                               label = "LED1";
-                               default-state = "off";
-                       };
-                       led@2 {
-                               reg = <2>;
-                               label = "LED2";
-                               default-state = "on";
-                       };
-                       led@3 {
-                               reg = <3>;
-                               label = "LED3";
-                               default-state = "on";
-                       };
-               };
-       };
-};
-
-&uart2 {
-       status = "okay";
-};
-
-&pio {
-       nand_pins_default: nanddefault {
-               pins_dat {
-                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
-                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
-                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
-                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>,
-                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>,
-                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>,
-                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>,
-                                <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
-                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
-                               input-enable;
-                               drive-strength = <MTK_DRIVE_8mA>;
-                               bias-pull-up;
-               };
-
-               pins_we {
-                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
-                       drive-strength = <MTK_DRIVE_8mA>;
-                       bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
-               };
-
-               pins_ale {
-                       pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
-                       drive-strength = <MTK_DRIVE_8mA>;
-                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
-               };
-       };
-
-       eth_default: eth {
-               pins_eth {
-                       pinmux = <MT7623_PIN_275_G2_MDC_FUNC_MDC>,
-                                <MT7623_PIN_276_G2_MDIO_FUNC_MDIO>,
-                                <MT7623_PIN_262_G2_TXEN_FUNC_G2_TXEN>,
-                                <MT7623_PIN_263_G2_TXD3_FUNC_G2_TXD3>,
-                                <MT7623_PIN_264_G2_TXD2_FUNC_G2_TXD2>,
-                                <MT7623_PIN_265_G2_TXD1_FUNC_G2_TXD1>,
-                                <MT7623_PIN_266_G2_TXD0_FUNC_G2_TXD0>,
-                                <MT7623_PIN_267_G2_TXCLK_FUNC_G2_TXC>,
-                                <MT7623_PIN_268_G2_RXCLK_FUNC_G2_RXC>,
-                                <MT7623_PIN_269_G2_RXD0_FUNC_G2_RXD0>,
-                                <MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1>,
-                                <MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2>,
-                                <MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3>,
-                                <MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV>;
-               };
-
-               pins_eth_rst {
-                       pinmux = <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
-                       output-low;
-               };
-       };
-
-       pwm_pins: pwm {
-               pins_pwm1 {
-                       pinmux = <MT7623_PIN_204_PWM1_FUNC_PWM1>;
-               };
-
-               pins_pwm2 {
-                       pinmux = <MT7623_PIN_205_PWM2_FUNC_PWM2>;
-               };
-       };
-};
-
-&nandc {
-       status = "okay";
-       pinctrl-names = "default";
-       pinctrl-0 = <&nand_pins_default>;
-       nand@0 {
-               reg = <0>;
-               spare_per_sector = <64>;
-               nand-ecc-mode = "hw";
-               nand-ecc-strength = <12>;
-               nand-ecc-step-size = <1024>;
-               partitions {
-                       compatible = "fixed-partitions";
-                       #address-cells = <1>;
-                       #size-cells = <1>;
-
-                       partition@C0000 {
-                               label = "uboot-env";
-                               reg = <0xC0000 0x40000>;
-                       };
-
-                       partition@100000 {
-                               label = "factory";
-                               reg = <0x100000 0x40000>;
-                       };
-
-                       partition@140000 {
-                               label = "kernel";
-                               reg = <0x140000 0x2000000>;
-                       };
-
-                       partition@2140000 {
-                               label = "recovery";
-                               reg = <0x2140000 0x2000000>;
-                       };
-
-                       partition@4140000 {
-                               label = "ubi";
-                               reg = <0x4140000 0x1000000>;
-                       };
-               };
-       };
-};
-&bch {
-       status = "okay";
-};
-
-&usb1 {
-       vusb33-supply = <&mt6323_vusb_reg>;
-       vbus-supply = <&usb_p1_vbus>;
-       status = "okay";
-};
-
-&u3phy1 {
-       status = "okay";
-};
-
-&pcie {
-       status = "okay";
-};
-
-&eth {
-       status = "okay";
-};
-
-&gmac1 {
-       mac-address = [00 11 22 33 44 56];
-       status = "okay";
-
-       phy-mode = "trgmii";
-
-       fixed-link {
-               speed = <1000>;
-               full-duplex;
-               pause;
-       };
-};
-
-&gmac2 {
-       mac-address = [00 11 22 33 44 55];
-       status = "okay";
-
-       phy-mode = "trgmii";
-
-       fixed-link {
-               speed = <1000>;
-               full-duplex;
-               pause;
-       };
-};
-
-&mdio0 {
-       switch@0 {
-               compatible = "mediatek,mt7530";
-               #address-cells = <1>;
-               #size-cells = <0>;
-               reg = <0>;
-
-               pinctrl-names = "default";
-               pinctrl-0 = <&eth_default>;
-
-               core-supply = <&mt6323_vpa_reg>;
-               io-supply = <&mt6323_vemc3v3_reg>;
-
-               mediatek,mcm;
-               resets = <&ethsys 2>;
-               reset-names = "mcm";
-
-               ports {
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-                       reg = <0>;
-                       port@0 {
-                               reg = <0>;
-                               label = "lan0";
-                               cpu = <&cpu_port0>;
-                       };
-
-                       port@1 {
-                               reg = <1>;
-                               label = "lan1";
-                               cpu = <&cpu_port0>;
-                       };
-
-                       port@2 {
-                               reg = <2>;
-                               label = "lan2";
-                               cpu = <&cpu_port0>;
-                       };
-
-                       port@3 {
-                               reg = <3>;
-                               label = "lan3";
-                               cpu = <&cpu_port0>;
-                       };
-
-                       port@4 {
-                               reg = <4>;
-                               label = "wan";
-                               cpu = <&cpu_port1>;
-                       };
-
-                       cpu_port1: port@5 {
-                               reg = <5>;
-                               label = "cpu";
-                               ethernet = <&gmac2>;
-                               phy-mode = "trgmii";
-                               fixed-link {
-                                       speed = <1000>;
-                                       full-duplex;
-                               };
-                       };
-
-                       cpu_port0: port@6 {
-                               reg = <6>;
-                               label = "cpu";
-                               ethernet = <&gmac1>;
-                               phy-mode = "trgmii";
-                               fixed-link {
-                                       speed = <1000>;
-                                       full-duplex;
-                               };
-                       };
-               };
-       };
-};
-
-&pwm {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pwm_pins>;
-       status = "okay";
-};
diff --git a/target/linux/mediatek/files/arch/arm/boot/dts/mt7623-eMMC.dts b/target/linux/mediatek/files/arch/arm/boot/dts/mt7623-eMMC.dts
deleted file mode 100644 (file)
index 6f45ff6..0000000
+++ /dev/null
@@ -1,547 +0,0 @@
-/*
- * Copyright (c) 2016 MediaTek Inc.
- * Author: John Crispin <blogic@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/dts-v1/;
-
-#include "_mt7623.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-       model = "MediaTek MT7623 eMMC reference board";
-       compatible = "mediatek,mt7623-rfb-emmc", "mediatek,mt7623";
-
-       chosen {
-               stdout-path = &uart2;
-               bootargs = "earlyprintk block2mtd.block2mtd=/dev/mmcblk0,65536,eMMC,5 mtdparts=eMMC:256k(mbr)ro,512k(uboot)ro,256k(config)ro,256k(factory)ro,32M(kernel),32M(recovery),1024M(rootfs),2048M(usrdata),-(bmtpool) rootfstype=squashfs,jffs2";
-       };
-
-       memory {
-               reg = <0 0x80000000 0 0x20000000>;
-       };
-
-       usb_p1_vbus: regulator@0 {
-               compatible = "regulator-fixed";
-               regulator-name = "usb_vbus";
-               regulator-min-microvolt = <5000000>;
-               regulator-max-microvolt = <5000000>;
-               gpio = <&pio 135 GPIO_ACTIVE_HIGH>;
-               enable-active-high;
-       };
-
-       switch {
-               compatible = "mediatek,mt7530";
-               #address-cells = <1>;
-               #size-cells = <0>;
-               reg = <0>;
-
-               dsa,mii-bus = <&mdio0>;
-
-               pinctrl-names = "default";
-               pinctrl-0 = <&eth_default>;
-
-               core-supply = <&mt6323_vpa_reg>;
-               io-supply = <&mt6323_vemc3v3_reg>;
-
-               mediatek,mcm;
-               resets = <&ethsys 2>;
-               reset-names = "mcm";
-
-               ports {
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-                       reg = <0>;
-                       port@0 {
-                               reg = <0>;
-                               label = "lan0";
-                       };
-
-                       port@1 {
-                               reg = <1>;
-                               label = "lan1";
-                       };
-
-                       port@2 {
-                               reg = <2>;
-                               label = "lan2";
-                       };
-
-                       port@3 {
-                               reg = <3>;
-                               label = "lan3";
-                       };
-
-                       port@6 {
-                               reg = <6>;
-                               label = "cpu";
-                               ethernet = <&gmac1>;
-                               phy-mode = "trgmii";
-                               fixed-link {
-                                       speed = <1000>;
-                                       full-duplex;
-                               };
-                       };
-               };
-       };
-};
-
-&cpu0 {
-       proc-supply = <&mt6323_vproc_reg>;
-};
-
-&cpu1 {
-       proc-supply = <&mt6323_vproc_reg>;
-};
-
-&cpu2 {
-       proc-supply = <&mt6323_vproc_reg>;
-};
-
-&cpu3 {
-       proc-supply = <&mt6323_vproc_reg>;
-};
-
-&pwrap {
-       pmic: mt6323 {
-               compatible = "mediatek,mt6323";
-               interrupt-parent = <&pio>;
-               interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
-               interrupt-controller;
-               #interrupt-cells = <2>;
-
-               mt6323regulator: mt6323regulator{
-                       compatible = "mediatek,mt6323-regulator";
-
-                       mt6323_vproc_reg: buck_vproc{
-                               regulator-name = "vproc";
-                               regulator-min-microvolt = < 700000>;
-                               regulator-max-microvolt = <1350000>;
-                               regulator-ramp-delay = <12500>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vsys_reg: buck_vsys{
-                               regulator-name = "vsys";
-                               regulator-min-microvolt = <1400000>;
-                               regulator-max-microvolt = <2987500>;
-                               regulator-ramp-delay = <25000>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vpa_reg: buck_vpa{
-                               regulator-name = "vpa";
-                               regulator-min-microvolt = < 500000>;
-                               regulator-max-microvolt = <3650000>;
-                       };
-
-                       mt6323_vtcxo_reg: ldo_vtcxo{
-                               regulator-name = "vtcxo";
-                               regulator-min-microvolt = <2800000>;
-                               regulator-max-microvolt = <2800000>;
-                               regulator-enable-ramp-delay = <90>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vcn28_reg: ldo_vcn28{
-                               regulator-name = "vcn28";
-                               regulator-min-microvolt = <2800000>;
-                               regulator-max-microvolt = <2800000>;
-                               regulator-enable-ramp-delay = <185>;
-                       };
-
-                       mt6323_vcn33_bt_reg: ldo_vcn33_bt{
-                               regulator-name = "vcn33_bt";
-                               regulator-min-microvolt = <3300000>;
-                               regulator-max-microvolt = <3600000>;
-                               regulator-enable-ramp-delay = <185>;
-                       };
-
-                       mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{
-                               regulator-name = "vcn33_wifi";
-                               regulator-min-microvolt = <3300000>;
-                               regulator-max-microvolt = <3600000>;
-                               regulator-enable-ramp-delay = <185>;
-                       };
-
-                       mt6323_va_reg: ldo_va{
-                               regulator-name = "va";
-                               regulator-min-microvolt = <2800000>;
-                               regulator-max-microvolt = <2800000>;
-                               regulator-enable-ramp-delay = <216>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vcama_reg: ldo_vcama{
-                               regulator-name = "vcama";
-                               regulator-min-microvolt = <1500000>;
-                               regulator-max-microvolt = <2800000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vio28_reg: ldo_vio28{
-                               regulator-name = "vio28";
-                               regulator-min-microvolt = <2800000>;
-                               regulator-max-microvolt = <2800000>;
-                               regulator-enable-ramp-delay = <216>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vusb_reg: ldo_vusb{
-                               regulator-name = "vusb";
-                               regulator-min-microvolt = <3300000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <216>;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vmc_reg: ldo_vmc{
-                               regulator-name = "vmc";
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <36>;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vmch_reg: ldo_vmch{
-                               regulator-name = "vmch";
-                               regulator-min-microvolt = <3000000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <36>;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vemc3v3_reg: ldo_vemc3v3{
-                               regulator-name = "vemc3v3";
-                               regulator-min-microvolt = <3000000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <36>;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vgp1_reg: ldo_vgp1{
-                               regulator-name = "vgp1";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vgp2_reg: ldo_vgp2{
-                               regulator-name = "vgp2";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <3000000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vgp3_reg: ldo_vgp3{
-                               regulator-name = "vgp3";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vcn18_reg: ldo_vcn18{
-                               regulator-name = "vcn18";
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vsim1_reg: ldo_vsim1{
-                               regulator-name = "vsim1";
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3000000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vsim2_reg: ldo_vsim2{
-                               regulator-name = "vsim2";
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3000000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vrtc_reg: ldo_vrtc{
-                               regulator-name = "vrtc";
-                               regulator-min-microvolt = <2800000>;
-                               regulator-max-microvolt = <2800000>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vcamaf_reg: ldo_vcamaf{
-                               regulator-name = "vcamaf";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vibr_reg: ldo_vibr{
-                               regulator-name = "vibr";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-enable-ramp-delay = <36>;
-                       };
-
-                       mt6323_vrf18_reg: ldo_vrf18{
-                               regulator-name = "vrf18";
-                               regulator-min-microvolt = <1825000>;
-                               regulator-max-microvolt = <1825000>;
-                               regulator-enable-ramp-delay = <187>;
-                       };
-
-                       mt6323_vm_reg: ldo_vm{
-                               regulator-name = "vm";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-enable-ramp-delay = <216>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vio18_reg: ldo_vio18{
-                               regulator-name = "vio18";
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-enable-ramp-delay = <216>;
-                               regulator-always-on;
-                               regulator-boot-on;
-                       };
-
-                       mt6323_vcamd_reg: ldo_vcamd{
-                               regulator-name = "vcamd";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-
-                       mt6323_vcamio_reg: ldo_vcamio{
-                               regulator-name = "vcamio";
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-enable-ramp-delay = <216>;
-                       };
-               };
-       };
-};
-
-&uart2 {
-       status = "okay";
-};
-
-&mmc0 {
-       status = "okay";
-       pinctrl-names = "default", "state_uhs";
-       pinctrl-0 = <&mmc0_pins_default>;
-       pinctrl-1 = <&mmc0_pins_uhs>;
-       bus-width = <8>;
-       max-frequency = <50000000>;
-       cap-mmc-highspeed;
-       vmmc-supply = <&mt6323_vemc3v3_reg>;
-       vqmmc-supply = <&mt6323_vio18_reg>;
-       non-removable;
-};
-
-&mmc1 {
-       status = "okay";
-       pinctrl-names = "default", "state_uhs";
-       pinctrl-0 = <&mmc1_pins_default>;
-       pinctrl-1 = <&mmc1_pins_uhs>;
-       bus-width = <4>;
-       max-frequency = <50000000>;
-       cap-sd-highspeed;
-       sd-uhs-sdr25;
-//     cd-gpios = <&pio 132 0>;
-       vmmc-supply = <&mt6323_vmch_reg>;
-       vqmmc-supply = <&mt6323_vmc_reg>;
-};
-
-&pio {
-       mmc0_pins_default: mmc0default {
-               pins_cmd_dat {
-                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
-                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
-                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
-                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
-                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
-                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
-                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
-                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
-                                <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
-                       input-enable;
-                       bias-pull-up;
-               };
-
-               pins_clk {
-                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
-                       bias-pull-down;
-               };
-
-               pins_rst {
-                       pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
-                       bias-pull-up;
-               };
-       };
-
-       mmc0_pins_uhs: mmc0 {
-               pins_cmd_dat {
-                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
-                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
-                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
-                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
-                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
-                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
-                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
-                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
-                                <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
-                       input-enable;
-                       drive-strength = <MTK_DRIVE_2mA>;
-                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
-               };
-
-               pins_clk {
-                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
-                       drive-strength = <MTK_DRIVE_2mA>;
-                       bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
-               };
-
-               pins_rst {
-                       pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
-                       bias-pull-up;
-               };
-       };
-
-       mmc1_pins_default: mmc1default {
-               pins_cmd_dat {
-                       pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
-                                <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
-                                <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
-                                <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
-                                <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
-                       input-enable;
-                       drive-strength = <MTK_DRIVE_4mA>;
-                       bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
-               };
-
-               pins_clk {
-                       pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
-                       bias-pull-down;
-                       drive-strength = <MTK_DRIVE_4mA>;
-               };
-
-//             pins_insert {
-//                     pinmux = <MT8173_PIN_132_I2S0_DATA1_FUNC_GPIO132>;
-//                     bias-pull-up;
-//             };
-       };
-
-       mmc1_pins_uhs: mmc1 {
-               pins_cmd_dat {
-                       pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
-                                <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
-                                <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
-                                <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
-                                <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
-                       input-enable;
-                       drive-strength = <MTK_DRIVE_4mA>;
-                       bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
-               };
-
-               pins_clk {
-                       pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
-                       drive-strength = <MTK_DRIVE_4mA>;
-                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
-               };
-       };
-
-       eth_default: eth {
-               pins_eth {
-                       pinmux = <MT7623_PIN_275_G2_MDC_FUNC_MDC>,
-                                <MT7623_PIN_276_G2_MDIO_FUNC_MDIO>,
-                                <MT7623_PIN_262_G2_TXEN_FUNC_G2_TXEN>,
-                                <MT7623_PIN_263_G2_TXD3_FUNC_G2_TXD3>,
-                                <MT7623_PIN_264_G2_TXD2_FUNC_G2_TXD2>,
-                                <MT7623_PIN_265_G2_TXD1_FUNC_G2_TXD1>,
-                                <MT7623_PIN_266_G2_TXD0_FUNC_G2_TXD0>,
-                                <MT7623_PIN_267_G2_TXCLK_FUNC_G2_TXC>,
-                                <MT7623_PIN_268_G2_RXCLK_FUNC_G2_RXC>,
-                                <MT7623_PIN_269_G2_RXD0_FUNC_G2_RXD0>,
-                                <MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1>,
-                                <MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2>,
-                                <MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3>,
-                                <MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV>;
-               };
-
-               pins_eth_rst {
-                       pinmux = <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
-                       output-low;
-               };
-       };
-
-       pwm_pins: pwm {
-               pins_pwm1 {
-                       pinmux = <MT7623_PIN_204_PWM1_FUNC_PWM1>;
-               };
-
-               pins_pwm2 {
-                       pinmux = <MT7623_PIN_205_PWM2_FUNC_PWM2>;
-               };
-       };
-};
-
-&usb1 {
-       vusb33-supply = <&mt6323_vusb_reg>;
-       vbus-supply = <&usb_p1_vbus>;
-       status = "okay";
-};
-
-&u3phy1 {
-       status = "okay";
-};
-
-&pcie {
-       status = "okay";
-};
-
-&eth {
-       status = "okay";
-};
-
-&gmac1 {
-       mac-address = [00 11 22 33 44 56];
-       status = "okay";
-};
-
-&gmac2 {
-       mac-address = [00 11 22 33 44 55];
-       status = "okay";
-
-       phy-handle = <&phy5>;
-};
-
-&mdio0 {
-       phy5: ethernet-phy@5 {
-               reg = <5>;
-               phy-mode = "rgmii-rxid";
-       };
-};
-
-&pwm {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pwm_pins>;
-       status = "okay";
-};
diff --git a/target/linux/mediatek/files/arch/arm/boot/dts/mt7623-evb.dts b/target/linux/mediatek/files/arch/arm/boot/dts/mt7623-evb.dts
deleted file mode 100644 (file)
index ad2a38b..0000000
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright (c) 2016 MediaTek Inc.
- * Author: John Crispin <blogic@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/dts-v1/;
-#include "mt7623.dtsi"
-
-/ {
-       model = "MediaTek MT7623 evaluation board";
-       compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
-
-       chosen {
-               stdout-path = &uart2;
-       };
-
-       memory {
-               reg = <0 0x80000000 0 0x40000000>;
-       };
-/*
-       pwm_pins: pwm {
-               pins_pwm1 {
-                       pinmux = <MT7623_PIN_204_PWM1_FUNC_PWM1>;
-               };
-
-               pins_pwm2 {
-                       pinmux = <MT7623_PIN_205_PWM2_FUNC_PWM2>;
-               };
-       };*/
-
-};
-
-&uart2 {
-       status = "okay";
-};
-
-/*&pwm {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pwm_pins>;
-       status = "okay";
-};*/
diff --git a/target/linux/mediatek/files/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/target/linux/mediatek/files/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
deleted file mode 100644 (file)
index a66956e..0000000
+++ /dev/null
@@ -1,443 +0,0 @@
-/*
- * Copyright 2017 Sean Wang <sean.wang@mediatek.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
-
-/dts-v1/;
-#include <dt-bindings/input/input.h>
-#include "_mt7623.dtsi"
-#include "mt6323.dtsi"
-
-/ {
-       model = "Bananapi BPI-R2";
-       compatible = "bananapi,bpi-r2", "mediatek,mt7623";
-
-       aliases {
-               serial2 = &uart2;
-       };
-
-       chosen {
-               stdout-path = "serial2:115200n8";
-       };
-
-       cpus {
-               cpu@0 {
-                       proc-supply = <&mt6323_vproc_reg>;
-               };
-
-               cpu@1 {
-                       proc-supply = <&mt6323_vproc_reg>;
-               };
-
-               cpu@2 {
-                       proc-supply = <&mt6323_vproc_reg>;
-               };
-
-               cpu@3 {
-                       proc-supply = <&mt6323_vproc_reg>;
-               };
-       };
-
-       gpio_keys {
-               compatible = "gpio-keys";
-               pinctrl-names = "default";
-               pinctrl-0 = <&key_pins_a>;
-
-               factory {
-                       label = "factory";
-                       linux,code = <BTN_0>;
-                       gpios = <&pio 256 GPIO_ACTIVE_LOW>;
-               };
-
-               wps {
-                       label = "wps";
-                       linux,code = <KEY_WPS_BUTTON>;
-                       gpios = <&pio 257 GPIO_ACTIVE_HIGH>;
-               };
-       };
-
-       leds {
-               compatible = "gpio-leds";
-               pinctrl-names = "default";
-               pinctrl-0 = <&led_pins_a>;
-
-               red {
-                       label = "bpi-r2:pio:red";
-                       gpios = <&pio 239 GPIO_ACTIVE_HIGH>;
-                       default-state = "off";
-               };
-
-               green {
-                       label = "bpi-r2:pio:green";
-                       gpios = <&pio 240 GPIO_ACTIVE_HIGH>;
-                       default-state = "off";
-               };
-
-               blue {
-                       label = "bpi-r2:pio:blue";
-                       gpios = <&pio 241 GPIO_ACTIVE_HIGH>;
-                       default-state = "off";
-               };
-       };
-
-       memory@80000000 {
-               reg = <0 0x80000000 0 0x40000000>;
-       };
-};
-
-&cir {
-       pinctrl-names = "default";
-       pinctrl-0 = <&cir_pins_a>;
-       status = "okay";
-};
-
-&crypto {
-       status = "okay";
-};
-
-&eth {
-       status = "okay";
-       gmac0: mac@0 {
-               compatible = "mediatek,eth-mac";
-               reg = <0>;
-               phy-mode = "trgmii";
-               fixed-link {
-                       speed = <1000>;
-                       full-duplex;
-                       pause;
-               };
-       };
-
-       mdio: mdio-bus {
-               #address-cells = <1>;
-               #size-cells = <0>;
-               switch@0 {
-                       compatible = "mediatek,mt7530";
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-                       reg = <0>;
-
-                       pinctrl-names = "default";
-                       reset-gpios = <&pio 33 0>;
-                       core-supply = <&mt6323_vpa_reg>;
-                       io-supply = <&mt6323_vemc3v3_reg>;
-
-                       ports {
-                               #address-cells = <1>;
-                               #size-cells = <0>;
-                               reg = <0>;
-                               port@0 {
-                                       reg = <0>;
-                                       label = "wan";
-                               };
-
-                               port@1 {
-                                       reg = <1>;
-                                       label = "lan0";
-                               };
-
-                               port@2 {
-                                       reg = <2>;
-                                       label = "lan1";
-                               };
-
-                               port@3 {
-                                       reg = <3>;
-                                       label = "lan2";
-                               };
-
-                               port@4 {
-                                       reg = <4>;
-                                       label = "lan3";
-                               };
-
-                               port@6 {
-                                       reg = <6>;
-                                       label = "cpu";
-                                       ethernet = <&gmac0>;
-                                       phy-mode = "trgmii";
-                                       fixed-link {
-                                               speed = <1000>;
-                                               full-duplex;
-                                       };
-                               };
-                       };
-               };
-       };
-};
-
-&i2c0 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&i2c0_pins_a>;
-       status = "okay";
-};
-
-&i2c1 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&i2c1_pins_a>;
-       status = "okay";
-};
-
-&pio {
-       cir_pins_a:cir@0 {
-               pins_cir {
-                       pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
-                       bias-disable;
-               };
-       };
-
-       i2c0_pins_a: i2c@0 {
-               pins_i2c0 {
-                       pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
-                                <MT7623_PIN_76_SCL0_FUNC_SCL0>;
-                       bias-disable;
-               };
-       };
-
-       i2c1_pins_a: i2c@1 {
-               pin_i2c1 {
-                       pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
-                                <MT7623_PIN_58_SCL1_FUNC_SCL1>;
-                       bias-disable;
-               };
-       };
-
-       i2s0_pins_a: i2s@0 {
-               pin_i2s0 {
-                       pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
-                                <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
-                                <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
-                                <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
-                                <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
-                       drive-strength = <MTK_DRIVE_12mA>;
-                       bias-pull-down;
-               };
-       };
-
-       i2s1_pins_a: i2s@1 {
-               pin_i2s1 {
-                       pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
-                                <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
-                                <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
-                                <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
-                                <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
-                       drive-strength = <MTK_DRIVE_12mA>;
-                       bias-pull-down;
-               };
-       };
-
-       key_pins_a: keys@0 {
-               pins_keys {
-                       pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
-                                <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;
-                       input-enable;
-               };
-       };
-
-       led_pins_a: leds@0 {
-               pins_leds {
-                       pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,
-                                <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,
-                                <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
-               };
-       };
-
-       mmc0_pins_default: mmc0default {
-               pins_cmd_dat {
-                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
-                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
-                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
-                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
-                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
-                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
-                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
-                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
-                                <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
-                       input-enable;
-                       bias-pull-up;
-               };
-
-               pins_clk {
-                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
-                       bias-pull-down;
-               };
-
-               pins_rst {
-                       pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
-                       bias-pull-up;
-               };
-       };
-
-       mmc0_pins_uhs: mmc0 {
-               pins_cmd_dat {
-                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
-                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
-                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
-                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
-                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
-                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
-                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
-                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
-                                <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
-                       input-enable;
-                       drive-strength = <MTK_DRIVE_2mA>;
-                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
-               };
-
-               pins_clk {
-                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
-                       drive-strength = <MTK_DRIVE_2mA>;
-                       bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
-               };
-
-               pins_rst {
-                       pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
-                       bias-pull-up;
-               };
-       };
-
-       mmc1_pins_default: mmc1default {
-               pins_cmd_dat {
-                       pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
-                                <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
-                                <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
-                                <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
-                                <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
-                       input-enable;
-                       drive-strength = <MTK_DRIVE_4mA>;
-                       bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
-               };
-
-               pins_clk {
-                       pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
-                       bias-pull-down;
-                       drive-strength = <MTK_DRIVE_4mA>;
-               };
-       };
-
-       mmc1_pins_uhs: mmc1 {
-               pins_cmd_dat {
-                       pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
-                                <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
-                                <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
-                                <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
-                                <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
-                       input-enable;
-                       drive-strength = <MTK_DRIVE_4mA>;
-                       bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
-               };
-
-               pins_clk {
-                       pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
-                       drive-strength = <MTK_DRIVE_4mA>;
-                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
-               };
-       };
-
-       spi0_pins_a: spi@0 {
-               pins_spi {
-                       pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
-                               <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
-                               <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
-                               <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
-                       bias-disable;
-               };
-       };
-
-       pwm_pins_a: pwm@0 {
-               pins_pwm {
-                       pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
-                                <MT7623_PIN_204_PWM1_FUNC_PWM1>,
-                                <MT7623_PIN_205_PWM2_FUNC_PWM2>,
-                                <MT7623_PIN_206_PWM3_FUNC_PWM3>,
-                                <MT7623_PIN_207_PWM4_FUNC_PWM4>;
-               };
-       };
-
-       uart0_pins_a: uart@0 {
-               pins_dat {
-                       pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
-                                <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
-               };
-       };
-
-       uart1_pins_a: uart@1 {
-               pins_dat {
-                       pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
-                                <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
-               };
-       };
-};
-
-&pwm {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pwm_pins_a>;
-       status = "okay";
-};
-
-&pwrap {
-       mt6323 {
-               mt6323led: led {
-                       compatible = "mediatek,mt6323-led";
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-
-                       led@0 {
-                               reg = <0>;
-                               label = "bpi-r2:isink:green";
-                               default-state = "off";
-                       };
-                       led@1 {
-                               reg = <1>;
-                               label = "bpi-r2:isink:red";
-                               default-state = "off";
-                       };
-                       led@2 {
-                               reg = <2>;
-                               label = "bpi-r2:isink:blue";
-                               default-state = "off";
-                       };
-               };
-       };
-};
-
-&spi0 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&spi0_pins_a>;
-       status = "okay";
-};
-
-&uart0 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&uart0_pins_a>;
-       status = "disabled";
-};
-
-&u3phy1 {
-       status = "okay";
-};
-
-&u3phy2 {
-       status = "okay";
-};
-
-&uart1 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&uart1_pins_a>;
-       status = "disabled";
-};
-
-&uart2 {
-       status = "okay";
-};
-
-&usb1 {
-       vusb33-supply = <&mt6323_vusb_reg>;
-       status = "okay";
-};
-
-&usb2 {
-       vusb33-supply = <&mt6323_vusb_reg>;
-       status = "okay";
-};
diff --git a/target/linux/mediatek/files/drivers/char/hw_random/mtk-rng.c b/target/linux/mediatek/files/drivers/char/hw_random/mtk-rng.c
deleted file mode 100644 (file)
index df8eb54..0000000
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Driver for Mediatek Hardware Random Number Generator
- *
- * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#define MTK_RNG_DEV KBUILD_MODNAME
-
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/hw_random.h>
-#include <linux/io.h>
-#include <linux/iopoll.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-
-#define USEC_POLL                      2
-#define TIMEOUT_POLL                   20
-
-#define RNG_CTRL                       0x00
-#define RNG_EN                         BIT(0)
-#define RNG_READY                      BIT(31)
-
-#define RNG_DATA                       0x08
-
-#define to_mtk_rng(p)  container_of(p, struct mtk_rng, rng)
-
-struct mtk_rng {
-       void __iomem *base;
-       struct clk *clk;
-       struct hwrng rng;
-};
-
-static int mtk_rng_init(struct hwrng *rng)
-{
-       struct mtk_rng *priv = to_mtk_rng(rng);
-       u32 val;
-       int err;
-
-       err = clk_prepare_enable(priv->clk);
-       if (err)
-               return err;
-
-       val = readl(priv->base + RNG_CTRL);
-       val |= RNG_EN;
-       writel(val, priv->base + RNG_CTRL);
-
-       return 0;
-}
-
-static void mtk_rng_cleanup(struct hwrng *rng)
-{
-       struct mtk_rng *priv = to_mtk_rng(rng);
-       u32 val;
-
-       val = readl(priv->base + RNG_CTRL);
-       val &= ~RNG_EN;
-       writel(val, priv->base + RNG_CTRL);
-
-       clk_disable_unprepare(priv->clk);
-}
-
-static bool mtk_rng_wait_ready(struct hwrng *rng, bool wait)
-{
-       struct mtk_rng *priv = to_mtk_rng(rng);
-       int ready;
-
-       ready = readl(priv->base + RNG_CTRL) & RNG_READY;
-       if (!ready && wait)
-               readl_poll_timeout_atomic(priv->base + RNG_CTRL, ready,
-                                         ready & RNG_READY, USEC_POLL,
-                                         TIMEOUT_POLL);
-       return !!ready;
-}
-
-static int mtk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
-{
-       struct mtk_rng *priv = to_mtk_rng(rng);
-       int retval = 0;
-
-       while (max >= sizeof(u32)) {
-               if (!mtk_rng_wait_ready(rng, wait))
-                       break;
-
-               *(u32 *)buf = readl(priv->base + RNG_DATA);
-               retval += sizeof(u32);
-               buf += sizeof(u32);
-               max -= sizeof(u32);
-       }
-
-       return retval || !wait ? retval : -EIO;
-}
-
-static int mtk_rng_probe(struct platform_device *pdev)
-{
-       struct resource *res;
-       int ret;
-       struct mtk_rng *priv;
-
-       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-       if (!res) {
-               dev_err(&pdev->dev, "no iomem resource\n");
-               return -ENXIO;
-       }
-
-       priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
-       if (!priv)
-               return -ENOMEM;
-
-       priv->rng.name = pdev->name;
-       priv->rng.init = mtk_rng_init;
-       priv->rng.cleanup = mtk_rng_cleanup;
-       priv->rng.read = mtk_rng_read;
-
-       priv->clk = devm_clk_get(&pdev->dev, "rng");
-       if (IS_ERR(priv->clk)) {
-               ret = PTR_ERR(priv->clk);
-               dev_err(&pdev->dev, "no clock for device: %d\n", ret);
-               return ret;
-       }
-
-       priv->base = devm_ioremap_resource(&pdev->dev, res);
-       if (IS_ERR(priv->base))
-               return PTR_ERR(priv->base);
-
-       ret = devm_hwrng_register(&pdev->dev, &priv->rng);
-       if (ret) {
-               dev_err(&pdev->dev, "failed to register rng device: %d\n",
-                       ret);
-               return ret;
-       }
-
-       dev_info(&pdev->dev, "registered RNG driver\n");
-
-       return 0;
-}
-
-static const struct of_device_id mtk_rng_match[] = {
-       { .compatible = "mediatek,mt7623-rng" },
-       {},
-};
-MODULE_DEVICE_TABLE(of, mtk_rng_match);
-
-static struct platform_driver mtk_rng_driver = {
-       .probe          = mtk_rng_probe,
-       .driver = {
-               .name = MTK_RNG_DEV,
-               .of_match_table = mtk_rng_match,
-       },
-};
-
-module_platform_driver(mtk_rng_driver);
-
-MODULE_DESCRIPTION("Mediatek Random Number Generator Driver");
-MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
-MODULE_LICENSE("GPL");
diff --git a/target/linux/mediatek/files/drivers/crypto/mediatek/Makefile b/target/linux/mediatek/files/drivers/crypto/mediatek/Makefile
deleted file mode 100644 (file)
index 187be79..0000000
+++ /dev/null
@@ -1,2 +0,0 @@
-obj-$(CONFIG_CRYPTO_DEV_MEDIATEK) += mtk-crypto.o
-mtk-crypto-objs:= mtk-platform.o mtk-aes.o mtk-sha.o
diff --git a/target/linux/mediatek/files/drivers/crypto/mediatek/mtk-aes.c b/target/linux/mediatek/files/drivers/crypto/mediatek/mtk-aes.c
deleted file mode 100644 (file)
index 9e845e8..0000000
+++ /dev/null
@@ -1,1304 +0,0 @@
-/*
- * Cryptographic API.
- *
- * Driver for EIP97 AES acceleration.
- *
- * Copyright (c) 2016 Ryder Lee <ryder.lee@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Some ideas are from atmel-aes.c drivers.
- */
-
-#include <crypto/aes.h>
-#include "mtk-platform.h"
-
-#define AES_QUEUE_SIZE         512
-#define AES_BUF_ORDER          2
-#define AES_BUF_SIZE           ((PAGE_SIZE << AES_BUF_ORDER) \
-                               & ~(AES_BLOCK_SIZE - 1))
-#define AES_MAX_STATE_BUF_SIZE SIZE_IN_WORDS(AES_KEYSIZE_256 + \
-                               AES_BLOCK_SIZE * 2)
-#define AES_MAX_CT_SIZE                6
-
-#define AES_CT_CTRL_HDR                cpu_to_le32(0x00220000)
-
-/* AES-CBC/ECB/CTR command token */
-#define AES_CMD0               cpu_to_le32(0x05000000)
-#define AES_CMD1               cpu_to_le32(0x2d060000)
-#define AES_CMD2               cpu_to_le32(0xe4a63806)
-/* AES-GCM command token */
-#define AES_GCM_CMD0           cpu_to_le32(0x0b000000)
-#define AES_GCM_CMD1           cpu_to_le32(0xa0800000)
-#define AES_GCM_CMD2           cpu_to_le32(0x25000010)
-#define AES_GCM_CMD3           cpu_to_le32(0x0f020000)
-#define AES_GCM_CMD4           cpu_to_le32(0x21e60000)
-#define AES_GCM_CMD5           cpu_to_le32(0x40e60000)
-#define AES_GCM_CMD6           cpu_to_le32(0xd0070000)
-
-/* AES transform information word 0 fields */
-#define AES_TFM_BASIC_OUT      cpu_to_le32(0x4 << 0)
-#define AES_TFM_BASIC_IN       cpu_to_le32(0x5 << 0)
-#define AES_TFM_GCM_OUT                cpu_to_le32(0x6 << 0)
-#define AES_TFM_GCM_IN         cpu_to_le32(0xf << 0)
-#define AES_TFM_SIZE(x)                cpu_to_le32((x) << 8)
-#define AES_TFM_128BITS                cpu_to_le32(0xb << 16)
-#define AES_TFM_192BITS                cpu_to_le32(0xd << 16)
-#define AES_TFM_256BITS                cpu_to_le32(0xf << 16)
-#define AES_TFM_GHASH_DIGEST   cpu_to_le32(0x2 << 21)
-#define AES_TFM_GHASH          cpu_to_le32(0x4 << 23)
-/* AES transform information word 1 fields */
-#define AES_TFM_ECB            cpu_to_le32(0x0 << 0)
-#define AES_TFM_CBC            cpu_to_le32(0x1 << 0)
-#define AES_TFM_CTR_INIT       cpu_to_le32(0x2 << 0)   /* init counter to 1 */
-#define AES_TFM_CTR_LOAD       cpu_to_le32(0x6 << 0)   /* load/reuse counter */
-#define AES_TFM_3IV            cpu_to_le32(0x7 << 5)   /* using IV 0-2 */
-#define AES_TFM_FULL_IV                cpu_to_le32(0xf << 5)   /* using IV 0-3 */
-#define AES_TFM_IV_CTR_MODE    cpu_to_le32(0x1 << 10)
-#define AES_TFM_ENC_HASH       cpu_to_le32(0x1 << 17)
-
-/* AES flags */
-#define AES_FLAGS_CIPHER_MSK   GENMASK(2, 0)
-#define AES_FLAGS_ECB          BIT(0)
-#define AES_FLAGS_CBC          BIT(1)
-#define AES_FLAGS_CTR          BIT(2)
-#define AES_FLAGS_GCM          BIT(3)
-#define AES_FLAGS_ENCRYPT      BIT(4)
-#define AES_FLAGS_BUSY         BIT(5)
-
-#define AES_AUTH_TAG_ERR       cpu_to_le32(BIT(26))
-
-/**
- * mtk_aes_info - hardware information of AES
- * @cmd:       command token, hardware instruction
- * @tfm:       transform state of cipher algorithm.
- * @state:     contains keys and initial vectors.
- *
- * Memory layout of GCM buffer:
- * /-----------\
- * |  AES KEY  | 128/196/256 bits
- * |-----------|
- * |  HASH KEY | a string 128 zero bits encrypted using the block cipher
- * |-----------|
- * |    IVs    | 4 * 4 bytes
- * \-----------/
- *
- * The engine requires all these info to do:
- * - Commands decoding and control of the engine's data path.
- * - Coordinating hardware data fetch and store operations.
- * - Result token construction and output.
- */
-struct mtk_aes_info {
-       __le32 cmd[AES_MAX_CT_SIZE];
-       __le32 tfm[2];
-       __le32 state[AES_MAX_STATE_BUF_SIZE];
-};
-
-struct mtk_aes_reqctx {
-       u64 mode;
-};
-
-struct mtk_aes_base_ctx {
-       struct mtk_cryp *cryp;
-       u32 keylen;
-       __le32 keymode;
-
-       mtk_aes_fn start;
-
-       struct mtk_aes_info info;
-       dma_addr_t ct_dma;
-       dma_addr_t tfm_dma;
-
-       __le32 ct_hdr;
-       u32 ct_size;
-};
-
-struct mtk_aes_ctx {
-       struct mtk_aes_base_ctx base;
-};
-
-struct mtk_aes_ctr_ctx {
-       struct mtk_aes_base_ctx base;
-
-       u32     iv[AES_BLOCK_SIZE / sizeof(u32)];
-       size_t offset;
-       struct scatterlist src[2];
-       struct scatterlist dst[2];
-};
-
-struct mtk_aes_gcm_ctx {
-       struct mtk_aes_base_ctx base;
-
-       u32 authsize;
-       size_t textlen;
-
-       struct crypto_skcipher *ctr;
-};
-
-struct mtk_aes_gcm_setkey_result {
-       int err;
-       struct completion completion;
-};
-
-struct mtk_aes_drv {
-       struct list_head dev_list;
-       /* Device list lock */
-       spinlock_t lock;
-};
-
-static struct mtk_aes_drv mtk_aes = {
-       .dev_list = LIST_HEAD_INIT(mtk_aes.dev_list),
-       .lock = __SPIN_LOCK_UNLOCKED(mtk_aes.lock),
-};
-
-static inline u32 mtk_aes_read(struct mtk_cryp *cryp, u32 offset)
-{
-       return readl_relaxed(cryp->base + offset);
-}
-
-static inline void mtk_aes_write(struct mtk_cryp *cryp,
-                                u32 offset, u32 value)
-{
-       writel_relaxed(value, cryp->base + offset);
-}
-
-static struct mtk_cryp *mtk_aes_find_dev(struct mtk_aes_base_ctx *ctx)
-{
-       struct mtk_cryp *cryp = NULL;
-       struct mtk_cryp *tmp;
-
-       spin_lock_bh(&mtk_aes.lock);
-       if (!ctx->cryp) {
-               list_for_each_entry(tmp, &mtk_aes.dev_list, aes_list) {
-                       cryp = tmp;
-                       break;
-               }
-               ctx->cryp = cryp;
-       } else {
-               cryp = ctx->cryp;
-       }
-       spin_unlock_bh(&mtk_aes.lock);
-
-       return cryp;
-}
-
-static inline size_t mtk_aes_padlen(size_t len)
-{
-       len &= AES_BLOCK_SIZE - 1;
-       return len ? AES_BLOCK_SIZE - len : 0;
-}
-
-static bool mtk_aes_check_aligned(struct scatterlist *sg, size_t len,
-                                 struct mtk_aes_dma *dma)
-{
-       int nents;
-
-       if (!IS_ALIGNED(len, AES_BLOCK_SIZE))
-               return false;
-
-       for (nents = 0; sg; sg = sg_next(sg), ++nents) {
-               if (!IS_ALIGNED(sg->offset, sizeof(u32)))
-                       return false;
-
-               if (len <= sg->length) {
-                       if (!IS_ALIGNED(len, AES_BLOCK_SIZE))
-                               return false;
-
-                       dma->nents = nents + 1;
-                       dma->remainder = sg->length - len;
-                       sg->length = len;
-                       return true;
-               }
-
-               if (!IS_ALIGNED(sg->length, AES_BLOCK_SIZE))
-                       return false;
-
-               len -= sg->length;
-       }
-
-       return false;
-}
-
-static inline void mtk_aes_set_mode(struct mtk_aes_rec *aes,
-                                   const struct mtk_aes_reqctx *rctx)
-{
-       /* Clear all but persistent flags and set request flags. */
-       aes->flags = (aes->flags & AES_FLAGS_BUSY) | rctx->mode;
-}
-
-static inline void mtk_aes_restore_sg(const struct mtk_aes_dma *dma)
-{
-       struct scatterlist *sg = dma->sg;
-       int nents = dma->nents;
-
-       if (!dma->remainder)
-               return;
-
-       while (--nents > 0 && sg)
-               sg = sg_next(sg);
-
-       if (!sg)
-               return;
-
-       sg->length += dma->remainder;
-}
-
-static inline void mtk_aes_write_state_le(__le32 *dst, const u32 *src, u32 size)
-{
-       int i;
-
-       for (i = 0; i < SIZE_IN_WORDS(size); i++)
-               dst[i] = cpu_to_le32(src[i]);
-}
-
-static inline void mtk_aes_write_state_be(__be32 *dst, const u32 *src, u32 size)
-{
-       int i;
-
-       for (i = 0; i < SIZE_IN_WORDS(size); i++)
-               dst[i] = cpu_to_be32(src[i]);
-}
-
-static inline int mtk_aes_complete(struct mtk_cryp *cryp,
-                                  struct mtk_aes_rec *aes,
-                                  int err)
-{
-       aes->flags &= ~AES_FLAGS_BUSY;
-       aes->areq->complete(aes->areq, err);
-       /* Handle new request */
-       tasklet_schedule(&aes->queue_task);
-       return err;
-}
-
-/*
- * Write descriptors for processing. This will configure the engine, load
- * the transform information and then start the packet processing.
- */
-static int mtk_aes_xmit(struct mtk_cryp *cryp, struct mtk_aes_rec *aes)
-{
-       struct mtk_ring *ring = cryp->ring[aes->id];
-       struct mtk_desc *cmd = NULL, *res = NULL;
-       struct scatterlist *ssg = aes->src.sg, *dsg = aes->dst.sg;
-       u32 slen = aes->src.sg_len, dlen = aes->dst.sg_len;
-       int nents;
-
-       /* Write command descriptors */
-       for (nents = 0; nents < slen; ++nents, ssg = sg_next(ssg)) {
-               cmd = ring->cmd_next;
-               cmd->hdr = MTK_DESC_BUF_LEN(ssg->length);
-               cmd->buf = cpu_to_le32(sg_dma_address(ssg));
-
-               if (nents == 0) {
-                       cmd->hdr |= MTK_DESC_FIRST |
-                                   MTK_DESC_CT_LEN(aes->ctx->ct_size);
-                       cmd->ct = cpu_to_le32(aes->ctx->ct_dma);
-                       cmd->ct_hdr = aes->ctx->ct_hdr;
-                       cmd->tfm = cpu_to_le32(aes->ctx->tfm_dma);
-               }
-
-               /* Shift ring buffer and check boundary */
-               if (++ring->cmd_next == ring->cmd_base + MTK_DESC_NUM)
-                       ring->cmd_next = ring->cmd_base;
-       }
-       cmd->hdr |= MTK_DESC_LAST;
-
-       /* Prepare result descriptors */
-       for (nents = 0; nents < dlen; ++nents, dsg = sg_next(dsg)) {
-               res = ring->res_next;
-               res->hdr = MTK_DESC_BUF_LEN(dsg->length);
-               res->buf = cpu_to_le32(sg_dma_address(dsg));
-
-               if (nents == 0)
-                       res->hdr |= MTK_DESC_FIRST;
-
-               /* Shift ring buffer and check boundary */
-               if (++ring->res_next == ring->res_base + MTK_DESC_NUM)
-                       ring->res_next = ring->res_base;
-       }
-       res->hdr |= MTK_DESC_LAST;
-
-       /* Pointer to current result descriptor */
-       ring->res_prev = res;
-
-       /* Prepare enough space for authenticated tag */
-       if (aes->flags & AES_FLAGS_GCM)
-               res->hdr += AES_BLOCK_SIZE;
-
-       /*
-        * Make sure that all changes to the DMA ring are done before we
-        * start engine.
-        */
-       wmb();
-       /* Start DMA transfer */
-       mtk_aes_write(cryp, RDR_PREP_COUNT(aes->id), MTK_DESC_CNT(dlen));
-       mtk_aes_write(cryp, CDR_PREP_COUNT(aes->id), MTK_DESC_CNT(slen));
-
-       return -EINPROGRESS;
-}
-
-static void mtk_aes_unmap(struct mtk_cryp *cryp, struct mtk_aes_rec *aes)
-{
-       struct mtk_aes_base_ctx *ctx = aes->ctx;
-
-       dma_unmap_single(cryp->dev, ctx->ct_dma, sizeof(ctx->info),
-                        DMA_TO_DEVICE);
-
-       if (aes->src.sg == aes->dst.sg) {
-               dma_unmap_sg(cryp->dev, aes->src.sg, aes->src.nents,
-                            DMA_BIDIRECTIONAL);
-
-               if (aes->src.sg != &aes->aligned_sg)
-                       mtk_aes_restore_sg(&aes->src);
-       } else {
-               dma_unmap_sg(cryp->dev, aes->dst.sg, aes->dst.nents,
-                            DMA_FROM_DEVICE);
-
-               if (aes->dst.sg != &aes->aligned_sg)
-                       mtk_aes_restore_sg(&aes->dst);
-
-               dma_unmap_sg(cryp->dev, aes->src.sg, aes->src.nents,
-                            DMA_TO_DEVICE);
-
-               if (aes->src.sg != &aes->aligned_sg)
-                       mtk_aes_restore_sg(&aes->src);
-       }
-
-       if (aes->dst.sg == &aes->aligned_sg)
-               sg_copy_from_buffer(aes->real_dst, sg_nents(aes->real_dst),
-                                   aes->buf, aes->total);
-}
-
-static int mtk_aes_map(struct mtk_cryp *cryp, struct mtk_aes_rec *aes)
-{
-       struct mtk_aes_base_ctx *ctx = aes->ctx;
-       struct mtk_aes_info *info = &ctx->info;
-
-       ctx->ct_dma = dma_map_single(cryp->dev, info, sizeof(*info),
-                                    DMA_TO_DEVICE);
-       if (unlikely(dma_mapping_error(cryp->dev, ctx->ct_dma)))
-               goto exit;
-
-       ctx->tfm_dma = ctx->ct_dma + sizeof(info->cmd);
-
-       if (aes->src.sg == aes->dst.sg) {
-               aes->src.sg_len = dma_map_sg(cryp->dev, aes->src.sg,
-                                            aes->src.nents,
-                                            DMA_BIDIRECTIONAL);
-               aes->dst.sg_len = aes->src.sg_len;
-               if (unlikely(!aes->src.sg_len))
-                       goto sg_map_err;
-       } else {
-               aes->src.sg_len = dma_map_sg(cryp->dev, aes->src.sg,
-                                            aes->src.nents, DMA_TO_DEVICE);
-               if (unlikely(!aes->src.sg_len))
-                       goto sg_map_err;
-
-               aes->dst.sg_len = dma_map_sg(cryp->dev, aes->dst.sg,
-                                            aes->dst.nents, DMA_FROM_DEVICE);
-               if (unlikely(!aes->dst.sg_len)) {
-                       dma_unmap_sg(cryp->dev, aes->src.sg, aes->src.nents,
-                                    DMA_TO_DEVICE);
-                       goto sg_map_err;
-               }
-       }
-
-       return mtk_aes_xmit(cryp, aes);
-
-sg_map_err:
-       dma_unmap_single(cryp->dev, ctx->ct_dma, sizeof(*info), DMA_TO_DEVICE);
-exit:
-       return mtk_aes_complete(cryp, aes, -EINVAL);
-}
-
-/* Initialize transform information of CBC/ECB/CTR mode */
-static void mtk_aes_info_init(struct mtk_cryp *cryp, struct mtk_aes_rec *aes,
-                             size_t len)
-{
-       struct ablkcipher_request *req = ablkcipher_request_cast(aes->areq);
-       struct mtk_aes_base_ctx *ctx = aes->ctx;
-       struct mtk_aes_info *info = &ctx->info;
-       u32 cnt = 0;
-
-       ctx->ct_hdr = AES_CT_CTRL_HDR | cpu_to_le32(len);
-       info->cmd[cnt++] = AES_CMD0 | cpu_to_le32(len);
-       info->cmd[cnt++] = AES_CMD1;
-
-       info->tfm[0] = AES_TFM_SIZE(ctx->keylen) | ctx->keymode;
-       if (aes->flags & AES_FLAGS_ENCRYPT)
-               info->tfm[0] |= AES_TFM_BASIC_OUT;
-       else
-               info->tfm[0] |= AES_TFM_BASIC_IN;
-
-       switch (aes->flags & AES_FLAGS_CIPHER_MSK) {
-       case AES_FLAGS_CBC:
-               info->tfm[1] = AES_TFM_CBC;
-               break;
-       case AES_FLAGS_ECB:
-               info->tfm[1] = AES_TFM_ECB;
-               goto ecb;
-       case AES_FLAGS_CTR:
-               info->tfm[1] = AES_TFM_CTR_LOAD;
-               goto ctr;
-
-       default:
-               /* Should not happen... */
-               return;
-       }
-
-       mtk_aes_write_state_le(info->state + ctx->keylen, req->info,
-                              AES_BLOCK_SIZE);
-ctr:
-       info->tfm[0] += AES_TFM_SIZE(SIZE_IN_WORDS(AES_BLOCK_SIZE));
-       info->tfm[1] |= AES_TFM_FULL_IV;
-       info->cmd[cnt++] = AES_CMD2;
-ecb:
-       ctx->ct_size = cnt;
-}
-
-static int mtk_aes_dma(struct mtk_cryp *cryp, struct mtk_aes_rec *aes,
-                      struct scatterlist *src, struct scatterlist *dst,
-                      size_t len)
-{
-       size_t padlen = 0;
-       bool src_aligned, dst_aligned;
-
-       aes->total = len;
-       aes->src.sg = src;
-       aes->dst.sg = dst;
-       aes->real_dst = dst;
-
-       src_aligned = mtk_aes_check_aligned(src, len, &aes->src);
-       if (src == dst)
-               dst_aligned = src_aligned;
-       else
-               dst_aligned = mtk_aes_check_aligned(dst, len, &aes->dst);
-
-       if (!src_aligned || !dst_aligned) {
-               padlen = mtk_aes_padlen(len);
-
-               if (len + padlen > AES_BUF_SIZE)
-                       return mtk_aes_complete(cryp, aes, -ENOMEM);
-
-               if (!src_aligned) {
-                       sg_copy_to_buffer(src, sg_nents(src), aes->buf, len);
-                       aes->src.sg = &aes->aligned_sg;
-                       aes->src.nents = 1;
-                       aes->src.remainder = 0;
-               }
-
-               if (!dst_aligned) {
-                       aes->dst.sg = &aes->aligned_sg;
-                       aes->dst.nents = 1;
-                       aes->dst.remainder = 0;
-               }
-
-               sg_init_table(&aes->aligned_sg, 1);
-               sg_set_buf(&aes->aligned_sg, aes->buf, len + padlen);
-       }
-
-       mtk_aes_info_init(cryp, aes, len + padlen);
-
-       return mtk_aes_map(cryp, aes);
-}
-
-static int mtk_aes_handle_queue(struct mtk_cryp *cryp, u8 id,
-                               struct crypto_async_request *new_areq)
-{
-       struct mtk_aes_rec *aes = cryp->aes[id];
-       struct crypto_async_request *areq, *backlog;
-       struct mtk_aes_base_ctx *ctx;
-       unsigned long flags;
-       int ret = 0;
-
-       spin_lock_irqsave(&aes->lock, flags);
-       if (new_areq)
-               ret = crypto_enqueue_request(&aes->queue, new_areq);
-       if (aes->flags & AES_FLAGS_BUSY) {
-               spin_unlock_irqrestore(&aes->lock, flags);
-               return ret;
-       }
-       backlog = crypto_get_backlog(&aes->queue);
-       areq = crypto_dequeue_request(&aes->queue);
-       if (areq)
-               aes->flags |= AES_FLAGS_BUSY;
-       spin_unlock_irqrestore(&aes->lock, flags);
-
-       if (!areq)
-               return ret;
-
-       if (backlog)
-               backlog->complete(backlog, -EINPROGRESS);
-
-       ctx = crypto_tfm_ctx(areq->tfm);
-
-       aes->areq = areq;
-       aes->ctx = ctx;
-
-       return ctx->start(cryp, aes);
-}
-
-static int mtk_aes_transfer_complete(struct mtk_cryp *cryp,
-                                    struct mtk_aes_rec *aes)
-{
-       return mtk_aes_complete(cryp, aes, 0);
-}
-
-static int mtk_aes_start(struct mtk_cryp *cryp, struct mtk_aes_rec *aes)
-{
-       struct ablkcipher_request *req = ablkcipher_request_cast(aes->areq);
-       struct mtk_aes_reqctx *rctx = ablkcipher_request_ctx(req);
-
-       mtk_aes_set_mode(aes, rctx);
-       aes->resume = mtk_aes_transfer_complete;
-
-       return mtk_aes_dma(cryp, aes, req->src, req->dst, req->nbytes);
-}
-
-static inline struct mtk_aes_ctr_ctx *
-mtk_aes_ctr_ctx_cast(struct mtk_aes_base_ctx *ctx)
-{
-       return container_of(ctx, struct mtk_aes_ctr_ctx, base);
-}
-
-static int mtk_aes_ctr_transfer(struct mtk_cryp *cryp, struct mtk_aes_rec *aes)
-{
-       struct mtk_aes_base_ctx *ctx = aes->ctx;
-       struct mtk_aes_ctr_ctx *cctx = mtk_aes_ctr_ctx_cast(ctx);
-       struct ablkcipher_request *req = ablkcipher_request_cast(aes->areq);
-       struct scatterlist *src, *dst;
-       u32 start, end, ctr, blocks;
-       size_t datalen;
-       bool fragmented = false;
-
-       /* Check for transfer completion. */
-       cctx->offset += aes->total;
-       if (cctx->offset >= req->nbytes)
-               return mtk_aes_transfer_complete(cryp, aes);
-
-       /* Compute data length. */
-       datalen = req->nbytes - cctx->offset;
-       blocks = DIV_ROUND_UP(datalen, AES_BLOCK_SIZE);
-       ctr = be32_to_cpu(cctx->iv[3]);
-
-       /* Check 32bit counter overflow. */
-       start = ctr;
-       end = start + blocks - 1;
-       if (end < start) {
-               ctr |= 0xffffffff;
-               datalen = AES_BLOCK_SIZE * -start;
-               fragmented = true;
-       }
-
-       /* Jump to offset. */
-       src = scatterwalk_ffwd(cctx->src, req->src, cctx->offset);
-       dst = ((req->src == req->dst) ? src :
-              scatterwalk_ffwd(cctx->dst, req->dst, cctx->offset));
-
-       /* Write IVs into transform state buffer. */
-       mtk_aes_write_state_le(ctx->info.state + ctx->keylen, cctx->iv,
-                              AES_BLOCK_SIZE);
-
-       if (unlikely(fragmented)) {
-       /*
-        * Increment the counter manually to cope with the hardware
-        * counter overflow.
-        */
-               cctx->iv[3] = cpu_to_be32(ctr);
-               crypto_inc((u8 *)cctx->iv, AES_BLOCK_SIZE);
-       }
-
-       return mtk_aes_dma(cryp, aes, src, dst, datalen);
-}
-
-static int mtk_aes_ctr_start(struct mtk_cryp *cryp, struct mtk_aes_rec *aes)
-{
-       struct mtk_aes_ctr_ctx *cctx = mtk_aes_ctr_ctx_cast(aes->ctx);
-       struct ablkcipher_request *req = ablkcipher_request_cast(aes->areq);
-       struct mtk_aes_reqctx *rctx = ablkcipher_request_ctx(req);
-
-       mtk_aes_set_mode(aes, rctx);
-
-       memcpy(cctx->iv, req->info, AES_BLOCK_SIZE);
-       cctx->offset = 0;
-       aes->total = 0;
-       aes->resume = mtk_aes_ctr_transfer;
-
-       return mtk_aes_ctr_transfer(cryp, aes);
-}
-
-/* Check and set the AES key to transform state buffer */
-static int mtk_aes_setkey(struct crypto_ablkcipher *tfm,
-                         const u8 *key, u32 keylen)
-{
-       struct mtk_aes_base_ctx *ctx = crypto_ablkcipher_ctx(tfm);
-
-       switch (keylen) {
-       case AES_KEYSIZE_128:
-               ctx->keymode = AES_TFM_128BITS;
-               break;
-       case AES_KEYSIZE_192:
-               ctx->keymode = AES_TFM_192BITS;
-               break;
-       case AES_KEYSIZE_256:
-               ctx->keymode = AES_TFM_256BITS;
-               break;
-
-       default:
-               crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
-               return -EINVAL;
-       }
-
-       ctx->keylen = SIZE_IN_WORDS(keylen);
-       mtk_aes_write_state_le(ctx->info.state, (const u32 *)key, keylen);
-
-       return 0;
-}
-
-static int mtk_aes_crypt(struct ablkcipher_request *req, u64 mode)
-{
-       struct mtk_aes_base_ctx *ctx;
-       struct mtk_aes_reqctx *rctx;
-
-       ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
-       rctx = ablkcipher_request_ctx(req);
-       rctx->mode = mode;
-
-       return mtk_aes_handle_queue(ctx->cryp, !(mode & AES_FLAGS_ENCRYPT),
-                                   &req->base);
-}
-
-static int mtk_aes_ecb_encrypt(struct ablkcipher_request *req)
-{
-       return mtk_aes_crypt(req, AES_FLAGS_ENCRYPT | AES_FLAGS_ECB);
-}
-
-static int mtk_aes_ecb_decrypt(struct ablkcipher_request *req)
-{
-       return mtk_aes_crypt(req, AES_FLAGS_ECB);
-}
-
-static int mtk_aes_cbc_encrypt(struct ablkcipher_request *req)
-{
-       return mtk_aes_crypt(req, AES_FLAGS_ENCRYPT | AES_FLAGS_CBC);
-}
-
-static int mtk_aes_cbc_decrypt(struct ablkcipher_request *req)
-{
-       return mtk_aes_crypt(req, AES_FLAGS_CBC);
-}
-
-static int mtk_aes_ctr_encrypt(struct ablkcipher_request *req)
-{
-       return mtk_aes_crypt(req, AES_FLAGS_ENCRYPT | AES_FLAGS_CTR);
-}
-
-static int mtk_aes_ctr_decrypt(struct ablkcipher_request *req)
-{
-       return mtk_aes_crypt(req, AES_FLAGS_CTR);
-}
-
-static int mtk_aes_cra_init(struct crypto_tfm *tfm)
-{
-       struct mtk_aes_ctx *ctx = crypto_tfm_ctx(tfm);
-       struct mtk_cryp *cryp = NULL;
-
-       cryp = mtk_aes_find_dev(&ctx->base);
-       if (!cryp) {
-               pr_err("can't find crypto device\n");
-               return -ENODEV;
-       }
-
-       tfm->crt_ablkcipher.reqsize = sizeof(struct mtk_aes_reqctx);
-       ctx->base.start = mtk_aes_start;
-       return 0;
-}
-
-static int mtk_aes_ctr_cra_init(struct crypto_tfm *tfm)
-{
-       struct mtk_aes_ctx *ctx = crypto_tfm_ctx(tfm);
-       struct mtk_cryp *cryp = NULL;
-
-       cryp = mtk_aes_find_dev(&ctx->base);
-       if (!cryp) {
-               pr_err("can't find crypto device\n");
-               return -ENODEV;
-       }
-
-       tfm->crt_ablkcipher.reqsize = sizeof(struct mtk_aes_reqctx);
-       ctx->base.start = mtk_aes_ctr_start;
-       return 0;
-}
-
-static struct crypto_alg aes_algs[] = {
-{
-       .cra_name               = "cbc(aes)",
-       .cra_driver_name        = "cbc-aes-mtk",
-       .cra_priority           = 400,
-       .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
-                                 CRYPTO_ALG_ASYNC,
-       .cra_init               = mtk_aes_cra_init,
-       .cra_blocksize          = AES_BLOCK_SIZE,
-       .cra_ctxsize            = sizeof(struct mtk_aes_ctx),
-       .cra_alignmask          = 0xf,
-       .cra_type               = &crypto_ablkcipher_type,
-       .cra_module             = THIS_MODULE,
-       .cra_u.ablkcipher = {
-               .min_keysize    = AES_MIN_KEY_SIZE,
-               .max_keysize    = AES_MAX_KEY_SIZE,
-               .setkey         = mtk_aes_setkey,
-               .encrypt        = mtk_aes_cbc_encrypt,
-               .decrypt        = mtk_aes_cbc_decrypt,
-               .ivsize         = AES_BLOCK_SIZE,
-       }
-},
-{
-       .cra_name               = "ecb(aes)",
-       .cra_driver_name        = "ecb-aes-mtk",
-       .cra_priority           = 400,
-       .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
-                                 CRYPTO_ALG_ASYNC,
-       .cra_init               = mtk_aes_cra_init,
-       .cra_blocksize          = AES_BLOCK_SIZE,
-       .cra_ctxsize            = sizeof(struct mtk_aes_ctx),
-       .cra_alignmask          = 0xf,
-       .cra_type               = &crypto_ablkcipher_type,
-       .cra_module             = THIS_MODULE,
-       .cra_u.ablkcipher = {
-               .min_keysize    = AES_MIN_KEY_SIZE,
-               .max_keysize    = AES_MAX_KEY_SIZE,
-               .setkey         = mtk_aes_setkey,
-               .encrypt        = mtk_aes_ecb_encrypt,
-               .decrypt        = mtk_aes_ecb_decrypt,
-       }
-},
-{
-       .cra_name               = "ctr(aes)",
-       .cra_driver_name        = "ctr-aes-mtk",
-       .cra_priority           = 400,
-       .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
-                                 CRYPTO_ALG_ASYNC,
-       .cra_init               = mtk_aes_ctr_cra_init,
-       .cra_blocksize          = 1,
-       .cra_ctxsize            = sizeof(struct mtk_aes_ctr_ctx),
-       .cra_alignmask          = 0xf,
-       .cra_type               = &crypto_ablkcipher_type,
-       .cra_module             = THIS_MODULE,
-       .cra_u.ablkcipher = {
-               .min_keysize    = AES_MIN_KEY_SIZE,
-               .max_keysize    = AES_MAX_KEY_SIZE,
-               .ivsize         = AES_BLOCK_SIZE,
-               .setkey         = mtk_aes_setkey,
-               .encrypt        = mtk_aes_ctr_encrypt,
-               .decrypt        = mtk_aes_ctr_decrypt,
-       }
-},
-};
-
-static inline struct mtk_aes_gcm_ctx *
-mtk_aes_gcm_ctx_cast(struct mtk_aes_base_ctx *ctx)
-{
-       return container_of(ctx, struct mtk_aes_gcm_ctx, base);
-}
-
-/*
- * Engine will verify and compare tag automatically, so we just need
- * to check returned status which stored in the result descriptor.
- */
-static int mtk_aes_gcm_tag_verify(struct mtk_cryp *cryp,
-                                 struct mtk_aes_rec *aes)
-{
-       u32 status = cryp->ring[aes->id]->res_prev->ct;
-
-       return mtk_aes_complete(cryp, aes, (status & AES_AUTH_TAG_ERR) ?
-                               -EBADMSG : 0);
-}
-
-/* Initialize transform information of GCM mode */
-static void mtk_aes_gcm_info_init(struct mtk_cryp *cryp,
-                                 struct mtk_aes_rec *aes,
-                                 size_t len)
-{
-       struct aead_request *req = aead_request_cast(aes->areq);
-       struct mtk_aes_base_ctx *ctx = aes->ctx;
-       struct mtk_aes_gcm_ctx *gctx = mtk_aes_gcm_ctx_cast(ctx);
-       struct mtk_aes_info *info = &ctx->info;
-       u32 ivsize = crypto_aead_ivsize(crypto_aead_reqtfm(req));
-       u32 cnt = 0;
-
-       ctx->ct_hdr = AES_CT_CTRL_HDR | len;
-
-       info->cmd[cnt++] = AES_GCM_CMD0 | cpu_to_le32(req->assoclen);
-       info->cmd[cnt++] = AES_GCM_CMD1 | cpu_to_le32(req->assoclen);
-       info->cmd[cnt++] = AES_GCM_CMD2;
-       info->cmd[cnt++] = AES_GCM_CMD3 | cpu_to_le32(gctx->textlen);
-
-       if (aes->flags & AES_FLAGS_ENCRYPT) {
-               info->cmd[cnt++] = AES_GCM_CMD4 | cpu_to_le32(gctx->authsize);
-               info->tfm[0] = AES_TFM_GCM_OUT;
-       } else {
-               info->cmd[cnt++] = AES_GCM_CMD5 | cpu_to_le32(gctx->authsize);
-               info->cmd[cnt++] = AES_GCM_CMD6 | cpu_to_le32(gctx->authsize);
-               info->tfm[0] = AES_TFM_GCM_IN;
-       }
-       ctx->ct_size = cnt;
-
-       info->tfm[0] |= AES_TFM_GHASH_DIGEST | AES_TFM_GHASH | AES_TFM_SIZE(
-                       ctx->keylen + SIZE_IN_WORDS(AES_BLOCK_SIZE + ivsize)) |
-                       ctx->keymode;
-       info->tfm[1] = AES_TFM_CTR_INIT | AES_TFM_IV_CTR_MODE | AES_TFM_3IV |
-                      AES_TFM_ENC_HASH;
-
-       mtk_aes_write_state_le(info->state + ctx->keylen + SIZE_IN_WORDS(
-                              AES_BLOCK_SIZE), (const u32 *)req->iv, ivsize);
-}
-
-static int mtk_aes_gcm_dma(struct mtk_cryp *cryp, struct mtk_aes_rec *aes,
-                          struct scatterlist *src, struct scatterlist *dst,
-                          size_t len)
-{
-       bool src_aligned, dst_aligned;
-
-       aes->src.sg = src;
-       aes->dst.sg = dst;
-       aes->real_dst = dst;
-
-       src_aligned = mtk_aes_check_aligned(src, len, &aes->src);
-       if (src == dst)
-               dst_aligned = src_aligned;
-       else
-               dst_aligned = mtk_aes_check_aligned(dst, len, &aes->dst);
-
-       if (!src_aligned || !dst_aligned) {
-               if (aes->total > AES_BUF_SIZE)
-                       return mtk_aes_complete(cryp, aes, -ENOMEM);
-
-               if (!src_aligned) {
-                       sg_copy_to_buffer(src, sg_nents(src), aes->buf, len);
-                       aes->src.sg = &aes->aligned_sg;
-                       aes->src.nents = 1;
-                       aes->src.remainder = 0;
-               }
-
-               if (!dst_aligned) {
-                       aes->dst.sg = &aes->aligned_sg;
-                       aes->dst.nents = 1;
-                       aes->dst.remainder = 0;
-               }
-
-               sg_init_table(&aes->aligned_sg, 1);
-               sg_set_buf(&aes->aligned_sg, aes->buf, aes->total);
-       }
-
-       mtk_aes_gcm_info_init(cryp, aes, len);
-
-       return mtk_aes_map(cryp, aes);
-}
-
-/* Todo: GMAC */
-static int mtk_aes_gcm_start(struct mtk_cryp *cryp, struct mtk_aes_rec *aes)
-{
-       struct mtk_aes_gcm_ctx *gctx = mtk_aes_gcm_ctx_cast(aes->ctx);
-       struct aead_request *req = aead_request_cast(aes->areq);
-       struct mtk_aes_reqctx *rctx = aead_request_ctx(req);
-       u32 len = req->assoclen + req->cryptlen;
-
-       mtk_aes_set_mode(aes, rctx);
-
-       if (aes->flags & AES_FLAGS_ENCRYPT) {
-               u32 tag[4];
-
-               aes->resume = mtk_aes_transfer_complete;
-               /* Compute total process length. */
-               aes->total = len + gctx->authsize;
-               /* Compute text length. */
-               gctx->textlen = req->cryptlen;
-               /* Hardware will append authenticated tag to output buffer */
-               scatterwalk_map_and_copy(tag, req->dst, len, gctx->authsize, 1);
-       } else {
-               aes->resume = mtk_aes_gcm_tag_verify;
-               aes->total = len;
-               gctx->textlen = req->cryptlen - gctx->authsize;
-       }
-
-       return mtk_aes_gcm_dma(cryp, aes, req->src, req->dst, len);
-}
-
-static int mtk_aes_gcm_crypt(struct aead_request *req, u64 mode)
-{
-       struct mtk_aes_base_ctx *ctx = crypto_aead_ctx(crypto_aead_reqtfm(req));
-       struct mtk_aes_reqctx *rctx = aead_request_ctx(req);
-
-       rctx->mode = AES_FLAGS_GCM | mode;
-
-       return mtk_aes_handle_queue(ctx->cryp, !!(mode & AES_FLAGS_ENCRYPT),
-                                   &req->base);
-}
-
-static void mtk_gcm_setkey_done(struct crypto_async_request *req, int err)
-{
-       struct mtk_aes_gcm_setkey_result *result = req->data;
-
-       if (err == -EINPROGRESS)
-               return;
-
-       result->err = err;
-       complete(&result->completion);
-}
-
-/*
- * Because of the hardware limitation, we need to pre-calculate key(H)
- * for the GHASH operation. The result of the encryption operation
- * need to be stored in the transform state buffer.
- */
-static int mtk_aes_gcm_setkey(struct crypto_aead *aead, const u8 *key,
-                             u32 keylen)
-{
-       struct mtk_aes_base_ctx *ctx = crypto_aead_ctx(aead);
-       struct mtk_aes_gcm_ctx *gctx = mtk_aes_gcm_ctx_cast(ctx);
-       struct crypto_skcipher *ctr = gctx->ctr;
-       struct {
-               u32 hash[4];
-               u8 iv[8];
-
-               struct mtk_aes_gcm_setkey_result result;
-
-               struct scatterlist sg[1];
-               struct skcipher_request req;
-       } *data;
-       int err;
-
-       switch (keylen) {
-       case AES_KEYSIZE_128:
-               ctx->keymode = AES_TFM_128BITS;
-               break;
-       case AES_KEYSIZE_192:
-               ctx->keymode = AES_TFM_192BITS;
-               break;
-       case AES_KEYSIZE_256:
-               ctx->keymode = AES_TFM_256BITS;
-               break;
-
-       default:
-               crypto_aead_set_flags(aead, CRYPTO_TFM_RES_BAD_KEY_LEN);
-               return -EINVAL;
-       }
-
-       ctx->keylen = SIZE_IN_WORDS(keylen);
-
-       /* Same as crypto_gcm_setkey() from crypto/gcm.c */
-       crypto_skcipher_clear_flags(ctr, CRYPTO_TFM_REQ_MASK);
-       crypto_skcipher_set_flags(ctr, crypto_aead_get_flags(aead) &
-                                 CRYPTO_TFM_REQ_MASK);
-       err = crypto_skcipher_setkey(ctr, key, keylen);
-       crypto_aead_set_flags(aead, crypto_skcipher_get_flags(ctr) &
-                             CRYPTO_TFM_RES_MASK);
-       if (err)
-               return err;
-
-       data = kzalloc(sizeof(*data) + crypto_skcipher_reqsize(ctr),
-                      GFP_KERNEL);
-       if (!data)
-               return -ENOMEM;
-
-       init_completion(&data->result.completion);
-       sg_init_one(data->sg, &data->hash, AES_BLOCK_SIZE);
-       skcipher_request_set_tfm(&data->req, ctr);
-       skcipher_request_set_callback(&data->req, CRYPTO_TFM_REQ_MAY_SLEEP |
-                                     CRYPTO_TFM_REQ_MAY_BACKLOG,
-                                     mtk_gcm_setkey_done, &data->result);
-       skcipher_request_set_crypt(&data->req, data->sg, data->sg,
-                                  AES_BLOCK_SIZE, data->iv);
-
-       err = crypto_skcipher_encrypt(&data->req);
-       if (err == -EINPROGRESS || err == -EBUSY) {
-               err = wait_for_completion_interruptible(
-                       &data->result.completion);
-               if (!err)
-                       err = data->result.err;
-       }
-       if (err)
-               goto out;
-
-       /* Write key into state buffer */
-       mtk_aes_write_state_le(ctx->info.state, (const u32 *)key, keylen);
-       /* Write key(H) into state buffer */
-       mtk_aes_write_state_be(ctx->info.state + ctx->keylen, data->hash,
-                              AES_BLOCK_SIZE);
-out:
-       kzfree(data);
-       return err;
-}
-
-static int mtk_aes_gcm_setauthsize(struct crypto_aead *aead,
-                                  u32 authsize)
-{
-       struct mtk_aes_base_ctx *ctx = crypto_aead_ctx(aead);
-       struct mtk_aes_gcm_ctx *gctx = mtk_aes_gcm_ctx_cast(ctx);
-
-       /* Same as crypto_gcm_authsize() from crypto/gcm.c */
-       switch (authsize) {
-       case 8:
-       case 12:
-       case 16:
-               break;
-       default:
-               return -EINVAL;
-       }
-
-       gctx->authsize = authsize;
-       return 0;
-}
-
-static int mtk_aes_gcm_encrypt(struct aead_request *req)
-{
-       return mtk_aes_gcm_crypt(req, AES_FLAGS_ENCRYPT);
-}
-
-static int mtk_aes_gcm_decrypt(struct aead_request *req)
-{
-       return mtk_aes_gcm_crypt(req, 0);
-}
-
-static int mtk_aes_gcm_init(struct crypto_aead *aead)
-{
-       struct mtk_aes_gcm_ctx *ctx = crypto_aead_ctx(aead);
-       struct mtk_cryp *cryp = NULL;
-
-       cryp = mtk_aes_find_dev(&ctx->base);
-       if (!cryp) {
-               pr_err("can't find crypto device\n");
-               return -ENODEV;
-       }
-
-       ctx->ctr = crypto_alloc_skcipher("ctr(aes)", 0,
-                                        CRYPTO_ALG_ASYNC);
-       if (IS_ERR(ctx->ctr)) {
-               pr_err("Error allocating ctr(aes)\n");
-               return PTR_ERR(ctx->ctr);
-       }
-
-       crypto_aead_set_reqsize(aead, sizeof(struct mtk_aes_reqctx));
-       ctx->base.start = mtk_aes_gcm_start;
-       return 0;
-}
-
-static void mtk_aes_gcm_exit(struct crypto_aead *aead)
-{
-       struct mtk_aes_gcm_ctx *ctx = crypto_aead_ctx(aead);
-
-       crypto_free_skcipher(ctx->ctr);
-}
-
-static struct aead_alg aes_gcm_alg = {
-       .setkey         = mtk_aes_gcm_setkey,
-       .setauthsize    = mtk_aes_gcm_setauthsize,
-       .encrypt        = mtk_aes_gcm_encrypt,
-       .decrypt        = mtk_aes_gcm_decrypt,
-       .init           = mtk_aes_gcm_init,
-       .exit           = mtk_aes_gcm_exit,
-       .ivsize         = 12,
-       .maxauthsize    = AES_BLOCK_SIZE,
-
-       .base = {
-               .cra_name               = "gcm(aes)",
-               .cra_driver_name        = "gcm-aes-mtk",
-               .cra_priority           = 400,
-               .cra_flags              = CRYPTO_ALG_ASYNC,
-               .cra_blocksize          = 1,
-               .cra_ctxsize            = sizeof(struct mtk_aes_gcm_ctx),
-               .cra_alignmask          = 0xf,
-               .cra_module             = THIS_MODULE,
-       },
-};
-
-static void mtk_aes_queue_task(unsigned long data)
-{
-       struct mtk_aes_rec *aes = (struct mtk_aes_rec *)data;
-
-       mtk_aes_handle_queue(aes->cryp, aes->id, NULL);
-}
-
-static void mtk_aes_done_task(unsigned long data)
-{
-       struct mtk_aes_rec *aes = (struct mtk_aes_rec *)data;
-       struct mtk_cryp *cryp = aes->cryp;
-
-       mtk_aes_unmap(cryp, aes);
-       aes->resume(cryp, aes);
-}
-
-static irqreturn_t mtk_aes_irq(int irq, void *dev_id)
-{
-       struct mtk_aes_rec *aes  = (struct mtk_aes_rec *)dev_id;
-       struct mtk_cryp *cryp = aes->cryp;
-       u32 val = mtk_aes_read(cryp, RDR_STAT(aes->id));
-
-       mtk_aes_write(cryp, RDR_STAT(aes->id), val);
-
-       if (likely(AES_FLAGS_BUSY & aes->flags)) {
-               mtk_aes_write(cryp, RDR_PROC_COUNT(aes->id), MTK_CNT_RST);
-               mtk_aes_write(cryp, RDR_THRESH(aes->id),
-                             MTK_RDR_PROC_THRESH | MTK_RDR_PROC_MODE);
-
-               tasklet_schedule(&aes->done_task);
-       } else {
-               dev_warn(cryp->dev, "AES interrupt when no active requests.\n");
-       }
-       return IRQ_HANDLED;
-}
-
-/*
- * The purpose of creating encryption and decryption records is
- * to process outbound/inbound data in parallel, it can improve
- * performance in most use cases, such as IPSec VPN, especially
- * under heavy network traffic.
- */
-static int mtk_aes_record_init(struct mtk_cryp *cryp)
-{
-       struct mtk_aes_rec **aes = cryp->aes;
-       int i, err = -ENOMEM;
-
-       for (i = 0; i < MTK_REC_NUM; i++) {
-               aes[i] = kzalloc(sizeof(**aes), GFP_KERNEL);
-               if (!aes[i])
-                       goto err_cleanup;
-
-               aes[i]->buf = (void *)__get_free_pages(GFP_KERNEL,
-                                               AES_BUF_ORDER);
-               if (!aes[i]->buf)
-                       goto err_cleanup;
-
-               aes[i]->cryp = cryp;
-
-               spin_lock_init(&aes[i]->lock);
-               crypto_init_queue(&aes[i]->queue, AES_QUEUE_SIZE);
-
-               tasklet_init(&aes[i]->queue_task, mtk_aes_queue_task,
-                            (unsigned long)aes[i]);
-               tasklet_init(&aes[i]->done_task, mtk_aes_done_task,
-                            (unsigned long)aes[i]);
-       }
-
-       /* Link to ring0 and ring1 respectively */
-       aes[0]->id = MTK_RING0;
-       aes[1]->id = MTK_RING1;
-
-       return 0;
-
-err_cleanup:
-       for (; i--; ) {
-               free_page((unsigned long)aes[i]->buf);
-               kfree(aes[i]);
-       }
-
-       return err;
-}
-
-static void mtk_aes_record_free(struct mtk_cryp *cryp)
-{
-       int i;
-
-       for (i = 0; i < MTK_REC_NUM; i++) {
-               tasklet_kill(&cryp->aes[i]->done_task);
-               tasklet_kill(&cryp->aes[i]->queue_task);
-
-               free_page((unsigned long)cryp->aes[i]->buf);
-               kfree(cryp->aes[i]);
-       }
-}
-
-static void mtk_aes_unregister_algs(void)
-{
-       int i;
-
-       crypto_unregister_aead(&aes_gcm_alg);
-
-       for (i = 0; i < ARRAY_SIZE(aes_algs); i++)
-               crypto_unregister_alg(&aes_algs[i]);
-}
-
-static int mtk_aes_register_algs(void)
-{
-       int err, i;
-
-       for (i = 0; i < ARRAY_SIZE(aes_algs); i++) {
-               err = crypto_register_alg(&aes_algs[i]);
-               if (err)
-                       goto err_aes_algs;
-       }
-
-       err = crypto_register_aead(&aes_gcm_alg);
-       if (err)
-               goto err_aes_algs;
-
-       return 0;
-
-err_aes_algs:
-       for (; i--; )
-               crypto_unregister_alg(&aes_algs[i]);
-
-       return err;
-}
-
-int mtk_cipher_alg_register(struct mtk_cryp *cryp)
-{
-       int ret;
-
-       INIT_LIST_HEAD(&cryp->aes_list);
-
-       /* Initialize two cipher records */
-       ret = mtk_aes_record_init(cryp);
-       if (ret)
-               goto err_record;
-
-       ret = devm_request_irq(cryp->dev, cryp->irq[MTK_RING0], mtk_aes_irq,
-                              0, "mtk-aes", cryp->aes[0]);
-       if (ret) {
-               dev_err(cryp->dev, "unable to request AES irq.\n");
-               goto err_res;
-       }
-
-       ret = devm_request_irq(cryp->dev, cryp->irq[MTK_RING1], mtk_aes_irq,
-                              0, "mtk-aes", cryp->aes[1]);
-       if (ret) {
-               dev_err(cryp->dev, "unable to request AES irq.\n");
-               goto err_res;
-       }
-
-       /* Enable ring0 and ring1 interrupt */
-       mtk_aes_write(cryp, AIC_ENABLE_SET(MTK_RING0), MTK_IRQ_RDR0);
-       mtk_aes_write(cryp, AIC_ENABLE_SET(MTK_RING1), MTK_IRQ_RDR1);
-
-       spin_lock(&mtk_aes.lock);
-       list_add_tail(&cryp->aes_list, &mtk_aes.dev_list);
-       spin_unlock(&mtk_aes.lock);
-
-       ret = mtk_aes_register_algs();
-       if (ret)
-               goto err_algs;
-
-       return 0;
-
-err_algs:
-       spin_lock(&mtk_aes.lock);
-       list_del(&cryp->aes_list);
-       spin_unlock(&mtk_aes.lock);
-err_res:
-       mtk_aes_record_free(cryp);
-err_record:
-
-       dev_err(cryp->dev, "mtk-aes initialization failed.\n");
-       return ret;
-}
-
-void mtk_cipher_alg_release(struct mtk_cryp *cryp)
-{
-       spin_lock(&mtk_aes.lock);
-       list_del(&cryp->aes_list);
-       spin_unlock(&mtk_aes.lock);
-
-       mtk_aes_unregister_algs();
-       mtk_aes_record_free(cryp);
-}
diff --git a/target/linux/mediatek/files/drivers/crypto/mediatek/mtk-platform.c b/target/linux/mediatek/files/drivers/crypto/mediatek/mtk-platform.c
deleted file mode 100644 (file)
index b6ecc28..0000000
+++ /dev/null
@@ -1,607 +0,0 @@
-/*
- * Driver for EIP97 cryptographic accelerator.
- *
- * Copyright (c) 2016 Ryder Lee <ryder.lee@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/clk.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/pm_runtime.h>
-#include "mtk-platform.h"
-
-#define MTK_BURST_SIZE_MSK             GENMASK(7, 4)
-#define MTK_BURST_SIZE(x)              ((x) << 4)
-#define MTK_DESC_SIZE(x)               ((x) << 0)
-#define MTK_DESC_OFFSET(x)             ((x) << 16)
-#define MTK_DESC_FETCH_SIZE(x)         ((x) << 0)
-#define MTK_DESC_FETCH_THRESH(x)       ((x) << 16)
-#define MTK_DESC_OVL_IRQ_EN            BIT(25)
-#define MTK_DESC_ATP_PRESENT           BIT(30)
-
-#define MTK_DFSE_IDLE                  GENMASK(3, 0)
-#define MTK_DFSE_THR_CTRL_EN           BIT(30)
-#define MTK_DFSE_THR_CTRL_RESET                BIT(31)
-#define MTK_DFSE_RING_ID(x)            (((x) >> 12) & GENMASK(3, 0))
-#define MTK_DFSE_MIN_DATA(x)           ((x) << 0)
-#define MTK_DFSE_MAX_DATA(x)           ((x) << 8)
-#define MTK_DFE_MIN_CTRL(x)            ((x) << 16)
-#define MTK_DFE_MAX_CTRL(x)            ((x) << 24)
-
-#define MTK_IN_BUF_MIN_THRESH(x)       ((x) << 8)
-#define MTK_IN_BUF_MAX_THRESH(x)       ((x) << 12)
-#define MTK_OUT_BUF_MIN_THRESH(x)      ((x) << 0)
-#define MTK_OUT_BUF_MAX_THRESH(x)      ((x) << 4)
-#define MTK_IN_TBUF_SIZE(x)            (((x) >> 4) & GENMASK(3, 0))
-#define MTK_IN_DBUF_SIZE(x)            (((x) >> 8) & GENMASK(3, 0))
-#define MTK_OUT_DBUF_SIZE(x)           (((x) >> 16) & GENMASK(3, 0))
-#define MTK_CMD_FIFO_SIZE(x)           (((x) >> 8) & GENMASK(3, 0))
-#define MTK_RES_FIFO_SIZE(x)           (((x) >> 12) & GENMASK(3, 0))
-
-#define MTK_PE_TK_LOC_AVL              BIT(2)
-#define MTK_PE_PROC_HELD               BIT(14)
-#define MTK_PE_TK_TIMEOUT_EN           BIT(22)
-#define MTK_PE_INPUT_DMA_ERR           BIT(0)
-#define MTK_PE_OUTPUT_DMA_ERR          BIT(1)
-#define MTK_PE_PKT_PORC_ERR            BIT(2)
-#define MTK_PE_PKT_TIMEOUT             BIT(3)
-#define MTK_PE_FATAL_ERR               BIT(14)
-#define MTK_PE_INPUT_DMA_ERR_EN                BIT(16)
-#define MTK_PE_OUTPUT_DMA_ERR_EN       BIT(17)
-#define MTK_PE_PKT_PORC_ERR_EN         BIT(18)
-#define MTK_PE_PKT_TIMEOUT_EN          BIT(19)
-#define MTK_PE_FATAL_ERR_EN            BIT(30)
-#define MTK_PE_INT_OUT_EN              BIT(31)
-
-#define MTK_HIA_SIGNATURE              ((u16)0x35ca)
-#define MTK_HIA_DATA_WIDTH(x)          (((x) >> 25) & GENMASK(1, 0))
-#define MTK_HIA_DMA_LENGTH(x)          (((x) >> 20) & GENMASK(4, 0))
-#define MTK_CDR_STAT_CLR               GENMASK(4, 0)
-#define MTK_RDR_STAT_CLR               GENMASK(7, 0)
-
-#define MTK_AIC_INT_MSK                        GENMASK(5, 0)
-#define MTK_AIC_VER_MSK                        (GENMASK(15, 0) | GENMASK(27, 20))
-#define MTK_AIC_VER11                  0x011036c9
-#define MTK_AIC_VER12                  0x012036c9
-#define MTK_AIC_G_CLR                  GENMASK(30, 20)
-
-/**
- * EIP97 is an integrated security subsystem to accelerate cryptographic
- * functions and protocols to offload the host processor.
- * Some important hardware modules are briefly introduced below:
- *
- * Host Interface Adapter(HIA) - the main interface between the host
- * system and the hardware subsystem. It is responsible for attaching
- * processing engine to the specific host bus interface and provides a
- * standardized software view for off loading tasks to the engine.
- *
- * Command Descriptor Ring Manager(CDR Manager) - keeps track of how many
- * CD the host has prepared in the CDR. It monitors the fill level of its
- * CD-FIFO and if there's sufficient space for the next block of descriptors,
- * then it fires off a DMA request to fetch a block of CDs.
- *
- * Data fetch engine(DFE) - It is responsible for parsing the CD and
- * setting up the required control and packet data DMA transfers from
- * system memory to the processing engine.
- *
- * Result Descriptor Ring Manager(RDR Manager) - same as CDR Manager,
- * but target is result descriptors, Moreover, it also handles the RD
- * updates under control of the DSE. For each packet data segment
- * processed, the DSE triggers the RDR Manager to write the updated RD.
- * If triggered to update, the RDR Manager sets up a DMA operation to
- * copy the RD from the DSE to the correct location in the RDR.
- *
- * Data Store Engine(DSE) - It is responsible for parsing the prepared RD
- * and setting up the required control and packet data DMA transfers from
- * the processing engine to system memory.
- *
- * Advanced Interrupt Controllers(AICs) - receive interrupt request signals
- * from various sources and combine them into one interrupt output.
- * The AICs are used by:
- * - One for the HIA global and processing engine interrupts.
- * - The others for the descriptor ring interrupts.
- */
-
-/* Cryptographic engine capabilities */
-struct mtk_sys_cap {
-       /* host interface adapter */
-       u32 hia_ver;
-       u32 hia_opt;
-       /* packet engine */
-       u32 pkt_eng_opt;
-       /* global hardware */
-       u32 hw_opt;
-};
-
-static void mtk_desc_ring_link(struct mtk_cryp *cryp, u32 mask)
-{
-       /* Assign rings to DFE/DSE thread and enable it */
-       writel(MTK_DFSE_THR_CTRL_EN | mask, cryp->base + DFE_THR_CTRL);
-       writel(MTK_DFSE_THR_CTRL_EN | mask, cryp->base + DSE_THR_CTRL);
-}
-
-static void mtk_dfe_dse_buf_setup(struct mtk_cryp *cryp,
-                                 struct mtk_sys_cap *cap)
-{
-       u32 width = MTK_HIA_DATA_WIDTH(cap->hia_opt) + 2;
-       u32 len = MTK_HIA_DMA_LENGTH(cap->hia_opt) - 1;
-       u32 ipbuf = min((u32)MTK_IN_DBUF_SIZE(cap->hw_opt) + width, len);
-       u32 opbuf = min((u32)MTK_OUT_DBUF_SIZE(cap->hw_opt) + width, len);
-       u32 itbuf = min((u32)MTK_IN_TBUF_SIZE(cap->hw_opt) + width, len);
-
-       writel(MTK_DFSE_MIN_DATA(ipbuf - 1) |
-              MTK_DFSE_MAX_DATA(ipbuf) |
-              MTK_DFE_MIN_CTRL(itbuf - 1) |
-              MTK_DFE_MAX_CTRL(itbuf),
-              cryp->base + DFE_CFG);
-
-       writel(MTK_DFSE_MIN_DATA(opbuf - 1) |
-              MTK_DFSE_MAX_DATA(opbuf),
-              cryp->base + DSE_CFG);
-
-       writel(MTK_IN_BUF_MIN_THRESH(ipbuf - 1) |
-              MTK_IN_BUF_MAX_THRESH(ipbuf),
-              cryp->base + PE_IN_DBUF_THRESH);
-
-       writel(MTK_IN_BUF_MIN_THRESH(itbuf - 1) |
-              MTK_IN_BUF_MAX_THRESH(itbuf),
-              cryp->base + PE_IN_TBUF_THRESH);
-
-       writel(MTK_OUT_BUF_MIN_THRESH(opbuf - 1) |
-              MTK_OUT_BUF_MAX_THRESH(opbuf),
-              cryp->base + PE_OUT_DBUF_THRESH);
-
-       writel(0, cryp->base + PE_OUT_TBUF_THRESH);
-       writel(0, cryp->base + PE_OUT_BUF_CTRL);
-}
-
-static int mtk_dfe_dse_state_check(struct mtk_cryp *cryp)
-{
-       int ret = -EINVAL;
-       u32 val;
-
-       /* Check for completion of all DMA transfers */
-       val = readl(cryp->base + DFE_THR_STAT);
-       if (MTK_DFSE_RING_ID(val) == MTK_DFSE_IDLE) {
-               val = readl(cryp->base + DSE_THR_STAT);
-               if (MTK_DFSE_RING_ID(val) == MTK_DFSE_IDLE)
-                       ret = 0;
-       }
-
-       if (!ret) {
-               /* Take DFE/DSE thread out of reset */
-               writel(0, cryp->base + DFE_THR_CTRL);
-               writel(0, cryp->base + DSE_THR_CTRL);
-       } else {
-               return -EBUSY;
-       }
-
-       return 0;
-}
-
-static int mtk_dfe_dse_reset(struct mtk_cryp *cryp)
-{
-       int err;
-
-       /* Reset DSE/DFE and correct system priorities for all rings. */
-       writel(MTK_DFSE_THR_CTRL_RESET, cryp->base + DFE_THR_CTRL);
-       writel(0, cryp->base + DFE_PRIO_0);
-       writel(0, cryp->base + DFE_PRIO_1);
-       writel(0, cryp->base + DFE_PRIO_2);
-       writel(0, cryp->base + DFE_PRIO_3);
-
-       writel(MTK_DFSE_THR_CTRL_RESET, cryp->base + DSE_THR_CTRL);
-       writel(0, cryp->base + DSE_PRIO_0);
-       writel(0, cryp->base + DSE_PRIO_1);
-       writel(0, cryp->base + DSE_PRIO_2);
-       writel(0, cryp->base + DSE_PRIO_3);
-
-       err = mtk_dfe_dse_state_check(cryp);
-       if (err)
-               return err;
-
-       return 0;
-}
-
-static void mtk_cmd_desc_ring_setup(struct mtk_cryp *cryp,
-                                   int i, struct mtk_sys_cap *cap)
-{
-       /* Full descriptor that fits FIFO minus one */
-       u32 count =
-               ((1 << MTK_CMD_FIFO_SIZE(cap->hia_opt)) / MTK_DESC_SZ) - 1;
-
-       /* Temporarily disable external triggering */
-       writel(0, cryp->base + CDR_CFG(i));
-
-       /* Clear CDR count */
-       writel(MTK_CNT_RST, cryp->base + CDR_PREP_COUNT(i));
-       writel(MTK_CNT_RST, cryp->base + CDR_PROC_COUNT(i));
-
-       writel(0, cryp->base + CDR_PREP_PNTR(i));
-       writel(0, cryp->base + CDR_PROC_PNTR(i));
-       writel(0, cryp->base + CDR_DMA_CFG(i));
-
-       /* Configure CDR host address space */
-       writel(0, cryp->base + CDR_BASE_ADDR_HI(i));
-       writel(cryp->ring[i]->cmd_dma, cryp->base + CDR_BASE_ADDR_LO(i));
-
-       writel(MTK_DESC_RING_SZ, cryp->base + CDR_RING_SIZE(i));
-
-       /* Clear and disable all CDR interrupts */
-       writel(MTK_CDR_STAT_CLR, cryp->base + CDR_STAT(i));
-
-       /*
-        * Set command descriptor offset and enable additional
-        * token present in descriptor.
-        */
-       writel(MTK_DESC_SIZE(MTK_DESC_SZ) |
-                  MTK_DESC_OFFSET(MTK_DESC_OFF) |
-              MTK_DESC_ATP_PRESENT,
-              cryp->base + CDR_DESC_SIZE(i));
-
-       writel(MTK_DESC_FETCH_SIZE(count * MTK_DESC_OFF) |
-                  MTK_DESC_FETCH_THRESH(count * MTK_DESC_SZ),
-                  cryp->base + CDR_CFG(i));
-}
-
-static void mtk_res_desc_ring_setup(struct mtk_cryp *cryp,
-                                   int i, struct mtk_sys_cap *cap)
-{
-       u32 rndup = 2;
-       u32 count = ((1 << MTK_RES_FIFO_SIZE(cap->hia_opt)) / rndup) - 1;
-
-       /* Temporarily disable external triggering */
-       writel(0, cryp->base + RDR_CFG(i));
-
-       /* Clear RDR count */
-       writel(MTK_CNT_RST, cryp->base + RDR_PREP_COUNT(i));
-       writel(MTK_CNT_RST, cryp->base + RDR_PROC_COUNT(i));
-
-       writel(0, cryp->base + RDR_PREP_PNTR(i));
-       writel(0, cryp->base + RDR_PROC_PNTR(i));
-       writel(0, cryp->base + RDR_DMA_CFG(i));
-
-       /* Configure RDR host address space */
-       writel(0, cryp->base + RDR_BASE_ADDR_HI(i));
-       writel(cryp->ring[i]->res_dma, cryp->base + RDR_BASE_ADDR_LO(i));
-
-       writel(MTK_DESC_RING_SZ, cryp->base + RDR_RING_SIZE(i));
-       writel(MTK_RDR_STAT_CLR, cryp->base + RDR_STAT(i));
-
-       /*
-        * RDR manager generates update interrupts on a per-completed-packet,
-        * and the rd_proc_thresh_irq interrupt is fired when proc_pkt_count
-        * for the RDR exceeds the number of packets.
-        */
-       writel(MTK_RDR_PROC_THRESH | MTK_RDR_PROC_MODE,
-              cryp->base + RDR_THRESH(i));
-
-       /*
-        * Configure a threshold and time-out value for the processed
-        * result descriptors (or complete packets) that are written to
-        * the RDR.
-        */
-       writel(MTK_DESC_SIZE(MTK_DESC_SZ) | MTK_DESC_OFFSET(MTK_DESC_OFF),
-              cryp->base + RDR_DESC_SIZE(i));
-
-       /*
-        * Configure HIA fetch size and fetch threshold that are used to
-        * fetch blocks of multiple descriptors.
-        */
-       writel(MTK_DESC_FETCH_SIZE(count * MTK_DESC_OFF) |
-              MTK_DESC_FETCH_THRESH(count * rndup) |
-              MTK_DESC_OVL_IRQ_EN,
-                  cryp->base + RDR_CFG(i));
-}
-
-static int mtk_packet_engine_setup(struct mtk_cryp *cryp)
-{
-       struct mtk_sys_cap cap;
-       int i, err;
-       u32 val;
-
-       cap.hia_ver = readl(cryp->base + HIA_VERSION);
-       cap.hia_opt = readl(cryp->base + HIA_OPTIONS);
-       cap.hw_opt = readl(cryp->base + EIP97_OPTIONS);
-
-       if (!(((u16)cap.hia_ver) == MTK_HIA_SIGNATURE))
-               return -EINVAL;
-
-       /* Configure endianness conversion method for master (DMA) interface */
-       writel(0, cryp->base + EIP97_MST_CTRL);
-
-       /* Set HIA burst size */
-       val = readl(cryp->base + HIA_MST_CTRL);
-       val &= ~MTK_BURST_SIZE_MSK;
-       val |= MTK_BURST_SIZE(5);
-       writel(val, cryp->base + HIA_MST_CTRL);
-
-       err = mtk_dfe_dse_reset(cryp);
-       if (err) {
-               dev_err(cryp->dev, "Failed to reset DFE and DSE.\n");
-               return err;
-       }
-
-       mtk_dfe_dse_buf_setup(cryp, &cap);
-
-       /* Enable the 4 rings for the packet engines. */
-       mtk_desc_ring_link(cryp, 0xf);
-
-       for (i = 0; i < MTK_RING_MAX; i++) {
-               mtk_cmd_desc_ring_setup(cryp, i, &cap);
-               mtk_res_desc_ring_setup(cryp, i, &cap);
-       }
-
-       writel(MTK_PE_TK_LOC_AVL | MTK_PE_PROC_HELD | MTK_PE_TK_TIMEOUT_EN,
-              cryp->base + PE_TOKEN_CTRL_STAT);
-
-       /* Clear all pending interrupts */
-       writel(MTK_AIC_G_CLR, cryp->base + AIC_G_ACK);
-       writel(MTK_PE_INPUT_DMA_ERR | MTK_PE_OUTPUT_DMA_ERR |
-              MTK_PE_PKT_PORC_ERR | MTK_PE_PKT_TIMEOUT |
-              MTK_PE_FATAL_ERR | MTK_PE_INPUT_DMA_ERR_EN |
-              MTK_PE_OUTPUT_DMA_ERR_EN | MTK_PE_PKT_PORC_ERR_EN |
-              MTK_PE_PKT_TIMEOUT_EN | MTK_PE_FATAL_ERR_EN |
-              MTK_PE_INT_OUT_EN,
-              cryp->base + PE_INTERRUPT_CTRL_STAT);
-
-       return 0;
-}
-
-static int mtk_aic_cap_check(struct mtk_cryp *cryp, int hw)
-{
-       u32 val;
-
-       if (hw == MTK_RING_MAX)
-               val = readl(cryp->base + AIC_G_VERSION);
-       else
-               val = readl(cryp->base + AIC_VERSION(hw));
-
-       val &= MTK_AIC_VER_MSK;
-       if (val != MTK_AIC_VER11 && val != MTK_AIC_VER12)
-               return -ENXIO;
-
-       if (hw == MTK_RING_MAX)
-               val = readl(cryp->base + AIC_G_OPTIONS);
-       else
-               val = readl(cryp->base + AIC_OPTIONS(hw));
-
-       val &= MTK_AIC_INT_MSK;
-       if (!val || val > 32)
-               return -ENXIO;
-
-       return 0;
-}
-
-static int mtk_aic_init(struct mtk_cryp *cryp, int hw)
-{
-       int err;
-
-       err = mtk_aic_cap_check(cryp, hw);
-       if (err)
-               return err;
-
-       /* Disable all interrupts and set initial configuration */
-       if (hw == MTK_RING_MAX) {
-               writel(0, cryp->base + AIC_G_ENABLE_CTRL);
-               writel(0, cryp->base + AIC_G_POL_CTRL);
-               writel(0, cryp->base + AIC_G_TYPE_CTRL);
-               writel(0, cryp->base + AIC_G_ENABLE_SET);
-       } else {
-               writel(0, cryp->base + AIC_ENABLE_CTRL(hw));
-               writel(0, cryp->base + AIC_POL_CTRL(hw));
-               writel(0, cryp->base + AIC_TYPE_CTRL(hw));
-               writel(0, cryp->base + AIC_ENABLE_SET(hw));
-       }
-
-       return 0;
-}
-
-static int mtk_accelerator_init(struct mtk_cryp *cryp)
-{
-       int i, err;
-
-       /* Initialize advanced interrupt controller(AIC) */
-       for (i = 0; i < MTK_IRQ_NUM; i++) {
-               err = mtk_aic_init(cryp, i);
-               if (err) {
-                       dev_err(cryp->dev, "Failed to initialize AIC.\n");
-                       return err;
-               }
-       }
-
-       /* Initialize packet engine */
-       err = mtk_packet_engine_setup(cryp);
-       if (err) {
-               dev_err(cryp->dev, "Failed to configure packet engine.\n");
-               return err;
-       }
-
-       return 0;
-}
-
-static void mtk_desc_dma_free(struct mtk_cryp *cryp)
-{
-       int i;
-
-       for (i = 0; i < MTK_RING_MAX; i++) {
-               dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
-                                 cryp->ring[i]->res_base,
-                                 cryp->ring[i]->res_dma);
-               dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
-                                 cryp->ring[i]->cmd_base,
-                                 cryp->ring[i]->cmd_dma);
-               kfree(cryp->ring[i]);
-       }
-}
-
-static int mtk_desc_ring_alloc(struct mtk_cryp *cryp)
-{
-       struct mtk_ring **ring = cryp->ring;
-       int i, err = ENOMEM;
-
-       for (i = 0; i < MTK_RING_MAX; i++) {
-               ring[i] = kzalloc(sizeof(**ring), GFP_KERNEL);
-               if (!ring[i])
-                       goto err_cleanup;
-
-               ring[i]->cmd_base = dma_zalloc_coherent(cryp->dev,
-                                          MTK_DESC_RING_SZ,
-                                          &ring[i]->cmd_dma,
-                                          GFP_KERNEL);
-               if (!ring[i]->cmd_base)
-                       goto err_cleanup;
-
-               ring[i]->res_base = dma_zalloc_coherent(cryp->dev,
-                                          MTK_DESC_RING_SZ,
-                                          &ring[i]->res_dma,
-                                          GFP_KERNEL);
-               if (!ring[i]->res_base)
-                       goto err_cleanup;
-
-               ring[i]->cmd_next = ring[i]->cmd_base;
-               ring[i]->res_next = ring[i]->res_base;
-       }
-       return 0;
-
-err_cleanup:
-       for (; i--; ) {
-               dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
-                                 ring[i]->res_base, ring[i]->res_dma);
-               dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
-                                 ring[i]->cmd_base, ring[i]->cmd_dma);
-               kfree(ring[i]);
-       }
-       return err;
-}
-
-static int mtk_crypto_probe(struct platform_device *pdev)
-{
-       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-       struct mtk_cryp *cryp;
-       int i, err;
-
-       cryp = devm_kzalloc(&pdev->dev, sizeof(*cryp), GFP_KERNEL);
-       if (!cryp)
-               return -ENOMEM;
-
-       cryp->base = devm_ioremap_resource(&pdev->dev, res);
-       if (IS_ERR(cryp->base))
-               return PTR_ERR(cryp->base);
-
-       for (i = 0; i < MTK_IRQ_NUM; i++) {
-               cryp->irq[i] = platform_get_irq(pdev, i);
-               if (cryp->irq[i] < 0) {
-                       dev_err(cryp->dev, "no IRQ:%d resource info\n", i);
-                       return -ENXIO;
-               }
-       }
-
-       cryp->clk_ethif = devm_clk_get(&pdev->dev, "ethif");
-       cryp->clk_cryp = devm_clk_get(&pdev->dev, "cryp");
-       if (IS_ERR(cryp->clk_ethif) || IS_ERR(cryp->clk_cryp))
-               return -EPROBE_DEFER;
-
-       cryp->dev = &pdev->dev;
-       pm_runtime_enable(cryp->dev);
-       pm_runtime_get_sync(cryp->dev);
-
-       err = clk_prepare_enable(cryp->clk_ethif);
-       if (err)
-               goto err_clk_ethif;
-
-       err = clk_prepare_enable(cryp->clk_cryp);
-       if (err)
-               goto err_clk_cryp;
-
-       /* Allocate four command/result descriptor rings */
-       err = mtk_desc_ring_alloc(cryp);
-       if (err) {
-               dev_err(cryp->dev, "Unable to allocate descriptor rings.\n");
-               goto err_resource;
-       }
-
-       /* Initialize hardware modules */
-       err = mtk_accelerator_init(cryp);
-       if (err) {
-               dev_err(cryp->dev, "Failed to initialize cryptographic engine.\n");
-               goto err_engine;
-       }
-
-       err = mtk_cipher_alg_register(cryp);
-       if (err) {
-               dev_err(cryp->dev, "Unable to register cipher algorithm.\n");
-               goto err_cipher;
-       }
-
-       err = mtk_hash_alg_register(cryp);
-       if (err) {
-               dev_err(cryp->dev, "Unable to register hash algorithm.\n");
-               goto err_hash;
-       }
-
-       platform_set_drvdata(pdev, cryp);
-       return 0;
-
-err_hash:
-       mtk_cipher_alg_release(cryp);
-err_cipher:
-       mtk_dfe_dse_reset(cryp);
-err_engine:
-       mtk_desc_dma_free(cryp);
-err_resource:
-       clk_disable_unprepare(cryp->clk_cryp);
-err_clk_cryp:
-       clk_disable_unprepare(cryp->clk_ethif);
-err_clk_ethif:
-       pm_runtime_put_sync(cryp->dev);
-       pm_runtime_disable(cryp->dev);
-
-       return err;
-}
-
-static int mtk_crypto_remove(struct platform_device *pdev)
-{
-       struct mtk_cryp *cryp = platform_get_drvdata(pdev);
-
-       mtk_hash_alg_release(cryp);
-       mtk_cipher_alg_release(cryp);
-       mtk_desc_dma_free(cryp);
-
-       clk_disable_unprepare(cryp->clk_cryp);
-       clk_disable_unprepare(cryp->clk_ethif);
-
-       pm_runtime_put_sync(cryp->dev);
-       pm_runtime_disable(cryp->dev);
-       platform_set_drvdata(pdev, NULL);
-
-       return 0;
-}
-
-static const struct of_device_id of_crypto_id[] = {
-       { .compatible = "mediatek,eip97-crypto" },
-       {},
-};
-MODULE_DEVICE_TABLE(of, of_crypto_id);
-
-static struct platform_driver mtk_crypto_driver = {
-       .probe = mtk_crypto_probe,
-       .remove = mtk_crypto_remove,
-       .driver = {
-                  .name = "mtk-crypto",
-                  .owner = THIS_MODULE,
-                  .of_match_table = of_crypto_id,
-       },
-};
-module_platform_driver(mtk_crypto_driver);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Ryder Lee <ryder.lee@mediatek.com>");
-MODULE_DESCRIPTION("Cryptographic accelerator driver for EIP97");
diff --git a/target/linux/mediatek/files/drivers/crypto/mediatek/mtk-platform.h b/target/linux/mediatek/files/drivers/crypto/mediatek/mtk-platform.h
deleted file mode 100644 (file)
index 303c152..0000000
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * Driver for EIP97 cryptographic accelerator.
- *
- * Copyright (c) 2016 Ryder Lee <ryder.lee@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __MTK_PLATFORM_H_
-#define __MTK_PLATFORM_H_
-
-#include <crypto/algapi.h>
-#include <crypto/internal/aead.h>
-#include <crypto/internal/hash.h>
-#include <crypto/scatterwalk.h>
-#include <crypto/skcipher.h>
-#include <linux/crypto.h>
-#include <linux/dma-mapping.h>
-#include <linux/interrupt.h>
-#include <linux/scatterlist.h>
-#include "mtk-regs.h"
-
-#define MTK_RDR_PROC_THRESH    BIT(0)
-#define MTK_RDR_PROC_MODE      BIT(23)
-#define MTK_CNT_RST            BIT(31)
-#define MTK_IRQ_RDR0           BIT(1)
-#define MTK_IRQ_RDR1           BIT(3)
-#define MTK_IRQ_RDR2           BIT(5)
-#define MTK_IRQ_RDR3           BIT(7)
-
-#define SIZE_IN_WORDS(x)       ((x) >> 2)
-
-/**
- * Ring 0/1 are used by AES encrypt and decrypt.
- * Ring 2/3 are used by SHA.
- */
-enum {
-       MTK_RING0,
-       MTK_RING1,
-       MTK_RING2,
-       MTK_RING3,
-       MTK_RING_MAX
-};
-
-#define MTK_REC_NUM            (MTK_RING_MAX / 2)
-#define MTK_IRQ_NUM            5
-
-/**
- * struct mtk_desc - DMA descriptor
- * @hdr:       the descriptor control header
- * @buf:       DMA address of input buffer segment
- * @ct:                DMA address of command token that control operation flow
- * @ct_hdr:    the command token control header
- * @tag:       the user-defined field
- * @tfm:       DMA address of transform state
- * @bound:     align descriptors offset boundary
- *
- * Structure passed to the crypto engine to describe where source
- * data needs to be fetched and how it needs to be processed.
- */
-struct mtk_desc {
-       __le32 hdr;
-       __le32 buf;
-       __le32 ct;
-       __le32 ct_hdr;
-       __le32 tag;
-       __le32 tfm;
-       __le32 bound[2];
-};
-
-#define MTK_DESC_NUM           512
-#define MTK_DESC_OFF           SIZE_IN_WORDS(sizeof(struct mtk_desc))
-#define MTK_DESC_SZ            (MTK_DESC_OFF - 2)
-#define MTK_DESC_RING_SZ       ((sizeof(struct mtk_desc) * MTK_DESC_NUM))
-#define MTK_DESC_CNT(x)                ((MTK_DESC_OFF * (x)) << 2)
-#define MTK_DESC_LAST          cpu_to_le32(BIT(22))
-#define MTK_DESC_FIRST         cpu_to_le32(BIT(23))
-#define MTK_DESC_BUF_LEN(x)    cpu_to_le32(x)
-#define MTK_DESC_CT_LEN(x)     cpu_to_le32((x) << 24)
-
-/**
- * struct mtk_ring - Descriptor ring
- * @cmd_base:  pointer to command descriptor ring base
- * @cmd_next:  pointer to the next command descriptor
- * @cmd_dma:   DMA address of command descriptor ring
- * @res_base:  pointer to result descriptor ring base
- * @res_next:  pointer to the next result descriptor
- * @res_prev:  pointer to the previous result descriptor
- * @res_dma:   DMA address of result descriptor ring
- *
- * A descriptor ring is a circular buffer that is used to manage
- * one or more descriptors. There are two type of descriptor rings;
- * the command descriptor ring and result descriptor ring.
- */
-struct mtk_ring {
-       struct mtk_desc *cmd_base;
-       struct mtk_desc *cmd_next;
-       dma_addr_t cmd_dma;
-       struct mtk_desc *res_base;
-       struct mtk_desc *res_next;
-       struct mtk_desc *res_prev;
-       dma_addr_t res_dma;
-};
-
-/**
- * struct mtk_aes_dma - Structure that holds sg list info
- * @sg:                pointer to scatter-gather list
- * @nents:     number of entries in the sg list
- * @remainder: remainder of sg list
- * @sg_len:    number of entries in the sg mapped list
- */
-struct mtk_aes_dma {
-       struct scatterlist *sg;
-       int nents;
-       u32 remainder;
-       u32 sg_len;
-};
-
-struct mtk_aes_base_ctx;
-struct mtk_aes_rec;
-struct mtk_cryp;
-
-typedef int (*mtk_aes_fn)(struct mtk_cryp *cryp, struct mtk_aes_rec *aes);
-
-/**
- * struct mtk_aes_rec - AES operation record
- * @cryp:      pointer to Cryptographic device
- * @queue:     crypto request queue
- * @areq:      pointer to async request
- * @done_task: the tasklet is use in AES interrupt
- * @queue_task:        the tasklet is used to dequeue request
- * @ctx:       pointer to current context
- * @src:       the structure that holds source sg list info
- * @dst:       the structure that holds destination sg list info
- * @aligned_sg:        the scatter list is use to alignment
- * @real_dst:  pointer to the destination sg list
- * @resume:    pointer to resume function
- * @total:     request buffer length
- * @buf:       pointer to page buffer
- * @id:                the current use of ring
- * @flags:     it's describing AES operation state
- * @lock:      the async queue lock
- *
- * Structure used to record AES execution state.
- */
-struct mtk_aes_rec {
-       struct mtk_cryp *cryp;
-       struct crypto_queue queue;
-       struct crypto_async_request *areq;
-       struct tasklet_struct done_task;
-       struct tasklet_struct queue_task;
-       struct mtk_aes_base_ctx *ctx;
-       struct mtk_aes_dma src;
-       struct mtk_aes_dma dst;
-
-       struct scatterlist aligned_sg;
-       struct scatterlist *real_dst;
-
-       mtk_aes_fn resume;
-
-       size_t total;
-       void *buf;
-
-       u8 id;
-       unsigned long flags;
-       /* queue lock */
-       spinlock_t lock;
-};
-
-/**
- * struct mtk_sha_rec - SHA operation record
- * @cryp:      pointer to Cryptographic device
- * @queue:     crypto request queue
- * @req:       pointer to ahash request
- * @done_task: the tasklet is use in SHA interrupt
- * @queue_task:        the tasklet is used to dequeue request
- * @id:                the current use of ring
- * @flags:     it's describing SHA operation state
- * @lock:      the async queue lock
- *
- * Structure used to record SHA execution state.
- */
-struct mtk_sha_rec {
-       struct mtk_cryp *cryp;
-       struct crypto_queue queue;
-       struct ahash_request *req;
-       struct tasklet_struct done_task;
-       struct tasklet_struct queue_task;
-
-       u8 id;
-       unsigned long flags;
-       /* queue lock */
-       spinlock_t lock;
-};
-
-/**
- * struct mtk_cryp - Cryptographic device
- * @base:      pointer to mapped register I/O base
- * @dev:       pointer to device
- * @clk_ethif: pointer to ethif clock
- * @clk_cryp:  pointer to crypto clock
- * @irq:       global system and rings IRQ
- * @ring:      pointer to descriptor rings
- * @aes:       pointer to operation record of AES
- * @sha:       pointer to operation record of SHA
- * @aes_list:  device list of AES
- * @sha_list:  device list of SHA
- * @rec:       it's used to select SHA record for tfm
- *
- * Structure storing cryptographic device information.
- */
-struct mtk_cryp {
-       void __iomem *base;
-       struct device *dev;
-       struct clk *clk_ethif;
-       struct clk *clk_cryp;
-       int irq[MTK_IRQ_NUM];
-
-       struct mtk_ring *ring[MTK_RING_MAX];
-       struct mtk_aes_rec *aes[MTK_REC_NUM];
-       struct mtk_sha_rec *sha[MTK_REC_NUM];
-
-       struct list_head aes_list;
-       struct list_head sha_list;
-
-       bool rec;
-};
-
-int mtk_cipher_alg_register(struct mtk_cryp *cryp);
-void mtk_cipher_alg_release(struct mtk_cryp *cryp);
-int mtk_hash_alg_register(struct mtk_cryp *cryp);
-void mtk_hash_alg_release(struct mtk_cryp *cryp);
-
-#endif /* __MTK_PLATFORM_H_ */
diff --git a/target/linux/mediatek/files/drivers/crypto/mediatek/mtk-regs.h b/target/linux/mediatek/files/drivers/crypto/mediatek/mtk-regs.h
deleted file mode 100644 (file)
index 94f4eb8..0000000
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
- * Support for MediaTek cryptographic accelerator.
- *
- * Copyright (c) 2016 MediaTek Inc.
- * Author: Ryder Lee <ryder.lee@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
- *
- */
-
-#ifndef __MTK_REGS_H__
-#define __MTK_REGS_H__
-
-/* HIA, Command Descriptor Ring Manager */
-#define CDR_BASE_ADDR_LO(x)            (0x0 + ((x) << 12))
-#define CDR_BASE_ADDR_HI(x)            (0x4 + ((x) << 12))
-#define CDR_DATA_BASE_ADDR_LO(x)       (0x8 + ((x) << 12))
-#define CDR_DATA_BASE_ADDR_HI(x)       (0xC + ((x) << 12))
-#define CDR_ACD_BASE_ADDR_LO(x)                (0x10 + ((x) << 12))
-#define CDR_ACD_BASE_ADDR_HI(x)                (0x14 + ((x) << 12))
-#define CDR_RING_SIZE(x)               (0x18 + ((x) << 12))
-#define CDR_DESC_SIZE(x)               (0x1C + ((x) << 12))
-#define CDR_CFG(x)                     (0x20 + ((x) << 12))
-#define CDR_DMA_CFG(x)                 (0x24 + ((x) << 12))
-#define CDR_THRESH(x)                  (0x28 + ((x) << 12))
-#define CDR_PREP_COUNT(x)              (0x2C + ((x) << 12))
-#define CDR_PROC_COUNT(x)              (0x30 + ((x) << 12))
-#define CDR_PREP_PNTR(x)               (0x34 + ((x) << 12))
-#define CDR_PROC_PNTR(x)               (0x38 + ((x) << 12))
-#define CDR_STAT(x)                    (0x3C + ((x) << 12))
-
-/* HIA, Result Descriptor Ring Manager */
-#define RDR_BASE_ADDR_LO(x)            (0x800 + ((x) << 12))
-#define RDR_BASE_ADDR_HI(x)            (0x804 + ((x) << 12))
-#define RDR_DATA_BASE_ADDR_LO(x)       (0x808 + ((x) << 12))
-#define RDR_DATA_BASE_ADDR_HI(x)       (0x80C + ((x) << 12))
-#define RDR_ACD_BASE_ADDR_LO(x)                (0x810 + ((x) << 12))
-#define RDR_ACD_BASE_ADDR_HI(x)                (0x814 + ((x) << 12))
-#define RDR_RING_SIZE(x)               (0x818 + ((x) << 12))
-#define RDR_DESC_SIZE(x)               (0x81C + ((x) << 12))
-#define RDR_CFG(x)                     (0x820 + ((x) << 12))
-#define RDR_DMA_CFG(x)                 (0x824 + ((x) << 12))
-#define RDR_THRESH(x)                  (0x828 + ((x) << 12))
-#define RDR_PREP_COUNT(x)              (0x82C + ((x) << 12))
-#define RDR_PROC_COUNT(x)              (0x830 + ((x) << 12))
-#define RDR_PREP_PNTR(x)               (0x834 + ((x) << 12))
-#define RDR_PROC_PNTR(x)               (0x838 + ((x) << 12))
-#define RDR_STAT(x)                    (0x83C + ((x) << 12))
-
-/* HIA, Ring AIC */
-#define AIC_POL_CTRL(x)                        (0xE000 - ((x) << 12))
-#define        AIC_TYPE_CTRL(x)                (0xE004 - ((x) << 12))
-#define        AIC_ENABLE_CTRL(x)              (0xE008 - ((x) << 12))
-#define        AIC_RAW_STAL(x)                 (0xE00C - ((x) << 12))
-#define        AIC_ENABLE_SET(x)               (0xE00C - ((x) << 12))
-#define        AIC_ENABLED_STAT(x)             (0xE010 - ((x) << 12))
-#define        AIC_ACK(x)                      (0xE010 - ((x) << 12))
-#define        AIC_ENABLE_CLR(x)               (0xE014 - ((x) << 12))
-#define        AIC_OPTIONS(x)                  (0xE018 - ((x) << 12))
-#define        AIC_VERSION(x)                  (0xE01C - ((x) << 12))
-
-/* HIA, Global AIC */
-#define AIC_G_POL_CTRL                 0xF800
-#define AIC_G_TYPE_CTRL                        0xF804
-#define AIC_G_ENABLE_CTRL              0xF808
-#define AIC_G_RAW_STAT                 0xF80C
-#define AIC_G_ENABLE_SET               0xF80C
-#define AIC_G_ENABLED_STAT             0xF810
-#define AIC_G_ACK                      0xF810
-#define AIC_G_ENABLE_CLR               0xF814
-#define AIC_G_OPTIONS                  0xF818
-#define AIC_G_VERSION                  0xF81C
-
-/* HIA, Data Fetch Engine */
-#define DFE_CFG                                0xF000
-#define DFE_PRIO_0                     0xF010
-#define DFE_PRIO_1                     0xF014
-#define DFE_PRIO_2                     0xF018
-#define DFE_PRIO_3                     0xF01C
-
-/* HIA, Data Fetch Engine access monitoring for CDR */
-#define DFE_RING_REGION_LO(x)          (0xF080 + ((x) << 3))
-#define DFE_RING_REGION_HI(x)          (0xF084 + ((x) << 3))
-
-/* HIA, Data Fetch Engine thread control and status for thread */
-#define DFE_THR_CTRL                   0xF200
-#define DFE_THR_STAT                   0xF204
-#define DFE_THR_DESC_CTRL              0xF208
-#define DFE_THR_DESC_DPTR_LO           0xF210
-#define DFE_THR_DESC_DPTR_HI           0xF214
-#define DFE_THR_DESC_ACDPTR_LO         0xF218
-#define DFE_THR_DESC_ACDPTR_HI         0xF21C
-
-/* HIA, Data Store Engine */
-#define DSE_CFG                                0xF400
-#define DSE_PRIO_0                     0xF410
-#define DSE_PRIO_1                     0xF414
-#define DSE_PRIO_2                     0xF418
-#define DSE_PRIO_3                     0xF41C
-
-/* HIA, Data Store Engine access monitoring for RDR */
-#define DSE_RING_REGION_LO(x)          (0xF480 + ((x) << 3))
-#define DSE_RING_REGION_HI(x)          (0xF484 + ((x) << 3))
-
-/* HIA, Data Store Engine thread control and status for thread */
-#define DSE_THR_CTRL                   0xF600
-#define DSE_THR_STAT                   0xF604
-#define DSE_THR_DESC_CTRL              0xF608
-#define DSE_THR_DESC_DPTR_LO           0xF610
-#define DSE_THR_DESC_DPTR_HI           0xF614
-#define DSE_THR_DESC_S_DPTR_LO         0xF618
-#define DSE_THR_DESC_S_DPTR_HI         0xF61C
-#define DSE_THR_ERROR_STAT             0xF620
-
-/* HIA Global */
-#define HIA_MST_CTRL                   0xFFF4
-#define HIA_OPTIONS                    0xFFF8
-#define HIA_VERSION                    0xFFFC
-
-/* Processing Engine Input Side, Processing Engine */
-#define PE_IN_DBUF_THRESH              0x10000
-#define PE_IN_TBUF_THRESH              0x10100
-
-/* Packet Engine Configuration / Status Registers */
-#define PE_TOKEN_CTRL_STAT             0x11000
-#define PE_FUNCTION_EN                 0x11004
-#define PE_CONTEXT_CTRL                        0x11008
-#define PE_INTERRUPT_CTRL_STAT         0x11010
-#define PE_CONTEXT_STAT                        0x1100C
-#define PE_OUT_TRANS_CTRL_STAT         0x11018
-#define PE_OUT_BUF_CTRL                        0x1101C
-
-/* Packet Engine PRNG Registers */
-#define PE_PRNG_STAT                   0x11040
-#define PE_PRNG_CTRL                   0x11044
-#define PE_PRNG_SEED_L                 0x11048
-#define PE_PRNG_SEED_H                 0x1104C
-#define PE_PRNG_KEY_0_L                        0x11050
-#define PE_PRNG_KEY_0_H                        0x11054
-#define PE_PRNG_KEY_1_L                        0x11058
-#define PE_PRNG_KEY_1_H                        0x1105C
-#define PE_PRNG_RES_0                  0x11060
-#define PE_PRNG_RES_1                  0x11064
-#define PE_PRNG_RES_2                  0x11068
-#define PE_PRNG_RES_3                  0x1106C
-#define PE_PRNG_LFSR_L                 0x11070
-#define PE_PRNG_LFSR_H                 0x11074
-
-/* Packet Engine AIC */
-#define PE_EIP96_AIC_POL_CTRL          0x113C0
-#define PE_EIP96_AIC_TYPE_CTRL         0x113C4
-#define PE_EIP96_AIC_ENABLE_CTRL       0x113C8
-#define PE_EIP96_AIC_RAW_STAT          0x113CC
-#define PE_EIP96_AIC_ENABLE_SET                0x113CC
-#define PE_EIP96_AIC_ENABLED_STAT      0x113D0
-#define PE_EIP96_AIC_ACK               0x113D0
-#define PE_EIP96_AIC_ENABLE_CLR                0x113D4
-#define PE_EIP96_AIC_OPTIONS           0x113D8
-#define PE_EIP96_AIC_VERSION           0x113DC
-
-/* Packet Engine Options & Version Registers */
-#define PE_EIP96_OPTIONS               0x113F8
-#define PE_EIP96_VERSION               0x113FC
-
-/* Processing Engine Output Side */
-#define PE_OUT_DBUF_THRESH             0x11C00
-#define PE_OUT_TBUF_THRESH             0x11D00
-
-/* Processing Engine Local AIC */
-#define PE_AIC_POL_CTRL                        0x11F00
-#define PE_AIC_TYPE_CTRL               0x11F04
-#define PE_AIC_ENABLE_CTRL             0x11F08
-#define PE_AIC_RAW_STAT                        0x11F0C
-#define PE_AIC_ENABLE_SET              0x11F0C
-#define PE_AIC_ENABLED_STAT            0x11F10
-#define PE_AIC_ENABLE_CLR              0x11F14
-#define PE_AIC_OPTIONS                 0x11F18
-#define PE_AIC_VERSION                 0x11F1C
-
-/* Processing Engine General Configuration and Version */
-#define PE_IN_FLIGHT                   0x11FF0
-#define PE_OPTIONS                     0x11FF8
-#define PE_VERSION                     0x11FFC
-
-/* EIP-97 - Global */
-#define EIP97_CLOCK_STATE              0x1FFE4
-#define EIP97_FORCE_CLOCK_ON           0x1FFE8
-#define EIP97_FORCE_CLOCK_OFF          0x1FFEC
-#define EIP97_MST_CTRL                 0x1FFF4
-#define EIP97_OPTIONS                  0x1FFF8
-#define EIP97_VERSION                  0x1FFFC
-#endif /* __MTK_REGS_H__ */
diff --git a/target/linux/mediatek/files/drivers/crypto/mediatek/mtk-sha.c b/target/linux/mediatek/files/drivers/crypto/mediatek/mtk-sha.c
deleted file mode 100644 (file)
index 2226f12..0000000
+++ /dev/null
@@ -1,1358 +0,0 @@
-/*
- * Cryptographic API.
- *
- * Driver for EIP97 SHA1/SHA2(HMAC) acceleration.
- *
- * Copyright (c) 2016 Ryder Lee <ryder.lee@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Some ideas are from atmel-sha.c and omap-sham.c drivers.
- */
-
-#include <crypto/sha.h>
-#include "mtk-platform.h"
-
-#define SHA_ALIGN_MSK          (sizeof(u32) - 1)
-#define SHA_QUEUE_SIZE         512
-#define SHA_BUF_SIZE           ((u32)PAGE_SIZE)
-
-#define SHA_OP_UPDATE          1
-#define SHA_OP_FINAL           2
-
-#define SHA_DATA_LEN_MSK       cpu_to_le32(GENMASK(16, 0))
-#define SHA_MAX_DIGEST_BUF_SIZE        32
-
-/* SHA command token */
-#define SHA_CT_SIZE            5
-#define SHA_CT_CTRL_HDR                cpu_to_le32(0x02220000)
-#define SHA_CMD0               cpu_to_le32(0x03020000)
-#define SHA_CMD1               cpu_to_le32(0x21060000)
-#define SHA_CMD2               cpu_to_le32(0xe0e63802)
-
-/* SHA transform information */
-#define SHA_TFM_HASH           cpu_to_le32(0x2 << 0)
-#define SHA_TFM_SIZE(x)                cpu_to_le32((x) << 8)
-#define SHA_TFM_START          cpu_to_le32(0x1 << 4)
-#define SHA_TFM_CONTINUE       cpu_to_le32(0x1 << 5)
-#define SHA_TFM_HASH_STORE     cpu_to_le32(0x1 << 19)
-#define SHA_TFM_SHA1           cpu_to_le32(0x2 << 23)
-#define SHA_TFM_SHA256         cpu_to_le32(0x3 << 23)
-#define SHA_TFM_SHA224         cpu_to_le32(0x4 << 23)
-#define SHA_TFM_SHA512         cpu_to_le32(0x5 << 23)
-#define SHA_TFM_SHA384         cpu_to_le32(0x6 << 23)
-#define SHA_TFM_DIGEST(x)      cpu_to_le32(((x) & GENMASK(3, 0)) << 24)
-
-/* SHA flags */
-#define SHA_FLAGS_BUSY         BIT(0)
-#define        SHA_FLAGS_FINAL         BIT(1)
-#define SHA_FLAGS_FINUP                BIT(2)
-#define SHA_FLAGS_SG           BIT(3)
-#define SHA_FLAGS_ALGO_MSK     GENMASK(8, 4)
-#define SHA_FLAGS_SHA1         BIT(4)
-#define SHA_FLAGS_SHA224       BIT(5)
-#define SHA_FLAGS_SHA256       BIT(6)
-#define SHA_FLAGS_SHA384       BIT(7)
-#define SHA_FLAGS_SHA512       BIT(8)
-#define SHA_FLAGS_HMAC         BIT(9)
-#define SHA_FLAGS_PAD          BIT(10)
-
-/**
- * mtk_sha_info - hardware information of AES
- * @cmd:       command token, hardware instruction
- * @tfm:       transform state of cipher algorithm.
- * @state:     contains keys and initial vectors.
- *
- */
-struct mtk_sha_info {
-       __le32 ctrl[2];
-       __le32 cmd[3];
-       __le32 tfm[2];
-       __le32 digest[SHA_MAX_DIGEST_BUF_SIZE];
-};
-
-struct mtk_sha_reqctx {
-       struct mtk_sha_info info;
-       unsigned long flags;
-       unsigned long op;
-
-       u64 digcnt;
-       size_t bufcnt;
-       dma_addr_t dma_addr;
-
-       __le32 ct_hdr;
-       u32 ct_size;
-       dma_addr_t ct_dma;
-       dma_addr_t tfm_dma;
-
-       /* Walk state */
-       struct scatterlist *sg;
-       u32 offset;     /* Offset in current sg */
-       u32 total;      /* Total request */
-       size_t ds;
-       size_t bs;
-
-       u8 *buffer;
-};
-
-struct mtk_sha_hmac_ctx {
-       struct crypto_shash     *shash;
-       u8 ipad[SHA512_BLOCK_SIZE] __aligned(sizeof(u32));
-       u8 opad[SHA512_BLOCK_SIZE] __aligned(sizeof(u32));
-};
-
-struct mtk_sha_ctx {
-       struct mtk_cryp *cryp;
-       unsigned long flags;
-       u8 id;
-       u8 buf[SHA_BUF_SIZE] __aligned(sizeof(u32));
-
-       struct mtk_sha_hmac_ctx base[0];
-};
-
-struct mtk_sha_drv {
-       struct list_head dev_list;
-       /* Device list lock */
-       spinlock_t lock;
-};
-
-static struct mtk_sha_drv mtk_sha = {
-       .dev_list = LIST_HEAD_INIT(mtk_sha.dev_list),
-       .lock = __SPIN_LOCK_UNLOCKED(mtk_sha.lock),
-};
-
-static int mtk_sha_handle_queue(struct mtk_cryp *cryp, u8 id,
-                               struct ahash_request *req);
-
-static inline u32 mtk_sha_read(struct mtk_cryp *cryp, u32 offset)
-{
-       return readl_relaxed(cryp->base + offset);
-}
-
-static inline void mtk_sha_write(struct mtk_cryp *cryp,
-                                u32 offset, u32 value)
-{
-       writel_relaxed(value, cryp->base + offset);
-}
-
-static inline void mtk_sha_ring_shift(struct mtk_ring *ring,
-                                     struct mtk_desc **cmd_curr,
-                                     struct mtk_desc **res_curr,
-                                     int *count)
-{
-       *cmd_curr = ring->cmd_next++;
-       *res_curr = ring->res_next++;
-       (*count)++;
-
-       if (ring->cmd_next == ring->cmd_base + MTK_DESC_NUM) {
-               ring->cmd_next = ring->cmd_base;
-               ring->res_next = ring->res_base;
-       }
-}
-
-static struct mtk_cryp *mtk_sha_find_dev(struct mtk_sha_ctx *tctx)
-{
-       struct mtk_cryp *cryp = NULL;
-       struct mtk_cryp *tmp;
-
-       spin_lock_bh(&mtk_sha.lock);
-       if (!tctx->cryp) {
-               list_for_each_entry(tmp, &mtk_sha.dev_list, sha_list) {
-                       cryp = tmp;
-                       break;
-               }
-               tctx->cryp = cryp;
-       } else {
-               cryp = tctx->cryp;
-       }
-
-       /*
-        * Assign record id to tfm in round-robin fashion, and this
-        * will help tfm to bind  to corresponding descriptor rings.
-        */
-       tctx->id = cryp->rec;
-       cryp->rec = !cryp->rec;
-
-       spin_unlock_bh(&mtk_sha.lock);
-
-       return cryp;
-}
-
-static int mtk_sha_append_sg(struct mtk_sha_reqctx *ctx)
-{
-       size_t count;
-
-       while ((ctx->bufcnt < SHA_BUF_SIZE) && ctx->total) {
-               count = min(ctx->sg->length - ctx->offset, ctx->total);
-               count = min(count, SHA_BUF_SIZE - ctx->bufcnt);
-
-               if (count <= 0) {
-                       /*
-                        * Check if count <= 0 because the buffer is full or
-                        * because the sg length is 0. In the latest case,
-                        * check if there is another sg in the list, a 0 length
-                        * sg doesn't necessarily mean the end of the sg list.
-                        */
-                       if ((ctx->sg->length == 0) && !sg_is_last(ctx->sg)) {
-                               ctx->sg = sg_next(ctx->sg);
-                               continue;
-                       } else {
-                               break;
-                       }
-               }
-
-               scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, ctx->sg,
-                                        ctx->offset, count, 0);
-
-               ctx->bufcnt += count;
-               ctx->offset += count;
-               ctx->total -= count;
-
-               if (ctx->offset == ctx->sg->length) {
-                       ctx->sg = sg_next(ctx->sg);
-                       if (ctx->sg)
-                               ctx->offset = 0;
-                       else
-                               ctx->total = 0;
-               }
-       }
-
-       return 0;
-}
-
-/*
- * The purpose of this padding is to ensure that the padded message is a
- * multiple of 512 bits (SHA1/SHA224/SHA256) or 1024 bits (SHA384/SHA512).
- * The bit "1" is appended at the end of the message followed by
- * "padlen-1" zero bits. Then a 64 bits block (SHA1/SHA224/SHA256) or
- * 128 bits block (SHA384/SHA512) equals to the message length in bits
- * is appended.
- *
- * For SHA1/SHA224/SHA256, padlen is calculated as followed:
- *  - if message length < 56 bytes then padlen = 56 - message length
- *  - else padlen = 64 + 56 - message length
- *
- * For SHA384/SHA512, padlen is calculated as followed:
- *  - if message length < 112 bytes then padlen = 112 - message length
- *  - else padlen = 128 + 112 - message length
- */
-static void mtk_sha_fill_padding(struct mtk_sha_reqctx *ctx, u32 len)
-{
-       u32 index, padlen;
-       u64 bits[2];
-       u64 size = ctx->digcnt;
-
-       size += ctx->bufcnt;
-       size += len;
-
-       bits[1] = cpu_to_be64(size << 3);
-       bits[0] = cpu_to_be64(size >> 61);
-
-       switch (ctx->flags & SHA_FLAGS_ALGO_MSK) {
-       case SHA_FLAGS_SHA384:
-       case SHA_FLAGS_SHA512:
-               index = ctx->bufcnt & 0x7f;
-               padlen = (index < 112) ? (112 - index) : ((128 + 112) - index);
-               *(ctx->buffer + ctx->bufcnt) = 0x80;
-               memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen - 1);
-               memcpy(ctx->buffer + ctx->bufcnt + padlen, bits, 16);
-               ctx->bufcnt += padlen + 16;
-               ctx->flags |= SHA_FLAGS_PAD;
-               break;
-
-       default:
-               index = ctx->bufcnt & 0x3f;
-               padlen = (index < 56) ? (56 - index) : ((64 + 56) - index);
-               *(ctx->buffer + ctx->bufcnt) = 0x80;
-               memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen - 1);
-               memcpy(ctx->buffer + ctx->bufcnt + padlen, &bits[1], 8);
-               ctx->bufcnt += padlen + 8;
-               ctx->flags |= SHA_FLAGS_PAD;
-               break;
-       }
-}
-
-/* Initialize basic transform information of SHA */
-static void mtk_sha_info_init(struct mtk_sha_reqctx *ctx)
-{
-       struct mtk_sha_info *info = &ctx->info;
-
-       ctx->ct_hdr = SHA_CT_CTRL_HDR;
-       ctx->ct_size = SHA_CT_SIZE;
-
-       info->tfm[0] = SHA_TFM_HASH | SHA_TFM_SIZE(SIZE_IN_WORDS(ctx->ds));
-
-       switch (ctx->flags & SHA_FLAGS_ALGO_MSK) {
-       case SHA_FLAGS_SHA1:
-               info->tfm[0] |= SHA_TFM_SHA1;
-               break;
-       case SHA_FLAGS_SHA224:
-               info->tfm[0] |= SHA_TFM_SHA224;
-               break;
-       case SHA_FLAGS_SHA256:
-               info->tfm[0] |= SHA_TFM_SHA256;
-               break;
-       case SHA_FLAGS_SHA384:
-               info->tfm[0] |= SHA_TFM_SHA384;
-               break;
-       case SHA_FLAGS_SHA512:
-               info->tfm[0] |= SHA_TFM_SHA512;
-               break;
-
-       default:
-               /* Should not happen... */
-               return;
-       }
-
-       info->tfm[1] = SHA_TFM_HASH_STORE;
-       info->ctrl[0] = info->tfm[0] | SHA_TFM_CONTINUE | SHA_TFM_START;
-       info->ctrl[1] = info->tfm[1];
-
-       info->cmd[0] = SHA_CMD0;
-       info->cmd[1] = SHA_CMD1;
-       info->cmd[2] = SHA_CMD2 | SHA_TFM_DIGEST(SIZE_IN_WORDS(ctx->ds));
-}
-
-/*
- * Update input data length field of transform information and
- * map it to DMA region.
- */
-static int mtk_sha_info_update(struct mtk_cryp *cryp,
-                              struct mtk_sha_rec *sha,
-                              size_t len1, size_t len2)
-{
-       struct mtk_sha_reqctx *ctx = ahash_request_ctx(sha->req);
-       struct mtk_sha_info *info = &ctx->info;
-
-       ctx->ct_hdr &= ~SHA_DATA_LEN_MSK;
-       ctx->ct_hdr |= cpu_to_le32(len1 + len2);
-       info->cmd[0] &= ~SHA_DATA_LEN_MSK;
-       info->cmd[0] |= cpu_to_le32(len1 + len2);
-
-       /* Setting SHA_TFM_START only for the first iteration */
-       if (ctx->digcnt)
-               info->ctrl[0] &= ~SHA_TFM_START;
-
-       ctx->digcnt += len1;
-
-       ctx->ct_dma = dma_map_single(cryp->dev, info, sizeof(*info),
-                                    DMA_BIDIRECTIONAL);
-       if (unlikely(dma_mapping_error(cryp->dev, ctx->ct_dma))) {
-               dev_err(cryp->dev, "dma %zu bytes error\n", sizeof(*info));
-               return -EINVAL;
-       }
-
-       ctx->tfm_dma = ctx->ct_dma + sizeof(info->ctrl) + sizeof(info->cmd);
-
-       return 0;
-}
-
-/*
- * Because of hardware limitation, we must pre-calculate the inner
- * and outer digest that need to be processed firstly by engine, then
- * apply the result digest to the input message. These complex hashing
- * procedures limits HMAC performance, so we use fallback SW encoding.
- */
-static int mtk_sha_finish_hmac(struct ahash_request *req)
-{
-       struct mtk_sha_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
-       struct mtk_sha_hmac_ctx *bctx = tctx->base;
-       struct mtk_sha_reqctx *ctx = ahash_request_ctx(req);
-
-       SHASH_DESC_ON_STACK(shash, bctx->shash);
-
-       shash->tfm = bctx->shash;
-       shash->flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
-
-       return crypto_shash_init(shash) ?:
-              crypto_shash_update(shash, bctx->opad, ctx->bs) ?:
-              crypto_shash_finup(shash, req->result, ctx->ds, req->result);
-}
-
-/* Initialize request context */
-static int mtk_sha_init(struct ahash_request *req)
-{
-       struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
-       struct mtk_sha_ctx *tctx = crypto_ahash_ctx(tfm);
-       struct mtk_sha_reqctx *ctx = ahash_request_ctx(req);
-
-       ctx->flags = 0;
-       ctx->ds = crypto_ahash_digestsize(tfm);
-
-       switch (ctx->ds) {
-       case SHA1_DIGEST_SIZE:
-               ctx->flags |= SHA_FLAGS_SHA1;
-               ctx->bs = SHA1_BLOCK_SIZE;
-               break;
-       case SHA224_DIGEST_SIZE:
-               ctx->flags |= SHA_FLAGS_SHA224;
-               ctx->bs = SHA224_BLOCK_SIZE;
-               break;
-       case SHA256_DIGEST_SIZE:
-               ctx->flags |= SHA_FLAGS_SHA256;
-               ctx->bs = SHA256_BLOCK_SIZE;
-               break;
-       case SHA384_DIGEST_SIZE:
-               ctx->flags |= SHA_FLAGS_SHA384;
-               ctx->bs = SHA384_BLOCK_SIZE;
-               break;
-       case SHA512_DIGEST_SIZE:
-               ctx->flags |= SHA_FLAGS_SHA512;
-               ctx->bs = SHA512_BLOCK_SIZE;
-               break;
-       default:
-               return -EINVAL;
-       }
-
-       ctx->bufcnt = 0;
-       ctx->digcnt = 0;
-       ctx->buffer = tctx->buf;
-
-       if (tctx->flags & SHA_FLAGS_HMAC) {
-               struct mtk_sha_hmac_ctx *bctx = tctx->base;
-
-               memcpy(ctx->buffer, bctx->ipad, ctx->bs);
-               ctx->bufcnt = ctx->bs;
-               ctx->flags |= SHA_FLAGS_HMAC;
-       }
-
-       return 0;
-}
-
-static int mtk_sha_xmit(struct mtk_cryp *cryp, struct mtk_sha_rec *sha,
-                       dma_addr_t addr1, size_t len1,
-                       dma_addr_t addr2, size_t len2)
-{
-       struct mtk_sha_reqctx *ctx = ahash_request_ctx(sha->req);
-       struct mtk_ring *ring = cryp->ring[sha->id];
-       struct mtk_desc *cmd, *res;
-       int err, count = 0;
-
-       err = mtk_sha_info_update(cryp, sha, len1, len2);
-       if (err)
-               return err;
-
-       /* Fill in the command/result descriptors */
-       mtk_sha_ring_shift(ring, &cmd, &res, &count);
-
-       res->hdr = MTK_DESC_FIRST | MTK_DESC_BUF_LEN(len1);
-       cmd->hdr = MTK_DESC_FIRST | MTK_DESC_BUF_LEN(len1) |
-                  MTK_DESC_CT_LEN(ctx->ct_size);
-       cmd->buf = cpu_to_le32(addr1);
-       cmd->ct = cpu_to_le32(ctx->ct_dma);
-       cmd->ct_hdr = ctx->ct_hdr;
-       cmd->tfm = cpu_to_le32(ctx->tfm_dma);
-
-       if (len2) {
-               mtk_sha_ring_shift(ring, &cmd, &res, &count);
-
-               res->hdr = MTK_DESC_BUF_LEN(len2);
-               cmd->hdr = MTK_DESC_BUF_LEN(len2);
-               cmd->buf = cpu_to_le32(addr2);
-       }
-
-       cmd->hdr |= MTK_DESC_LAST;
-       res->hdr |= MTK_DESC_LAST;
-
-       /*
-        * Make sure that all changes to the DMA ring are done before we
-        * start engine.
-        */
-       wmb();
-       /* Start DMA transfer */
-       mtk_sha_write(cryp, RDR_PREP_COUNT(sha->id), MTK_DESC_CNT(count));
-       mtk_sha_write(cryp, CDR_PREP_COUNT(sha->id), MTK_DESC_CNT(count));
-
-       return -EINPROGRESS;
-}
-
-static int mtk_sha_dma_map(struct mtk_cryp *cryp,
-                          struct mtk_sha_rec *sha,
-                          struct mtk_sha_reqctx *ctx,
-                          size_t count)
-{
-       ctx->dma_addr = dma_map_single(cryp->dev, ctx->buffer,
-                                      SHA_BUF_SIZE, DMA_TO_DEVICE);
-       if (unlikely(dma_mapping_error(cryp->dev, ctx->dma_addr))) {
-               dev_err(cryp->dev, "dma map error\n");
-               return -EINVAL;
-       }
-
-       ctx->flags &= ~SHA_FLAGS_SG;
-
-       return mtk_sha_xmit(cryp, sha, ctx->dma_addr, count, 0, 0);
-}
-
-static int mtk_sha_update_slow(struct mtk_cryp *cryp,
-                              struct mtk_sha_rec *sha)
-{
-       struct mtk_sha_reqctx *ctx = ahash_request_ctx(sha->req);
-       size_t count;
-       u32 final;
-
-       mtk_sha_append_sg(ctx);
-
-       final = (ctx->flags & SHA_FLAGS_FINUP) && !ctx->total;
-
-       dev_dbg(cryp->dev, "slow: bufcnt: %zu\n", ctx->bufcnt);
-
-       if (final) {
-               sha->flags |= SHA_FLAGS_FINAL;
-               mtk_sha_fill_padding(ctx, 0);
-       }
-
-       if (final || (ctx->bufcnt == SHA_BUF_SIZE && ctx->total)) {
-               count = ctx->bufcnt;
-               ctx->bufcnt = 0;
-
-               return mtk_sha_dma_map(cryp, sha, ctx, count);
-       }
-       return 0;
-}
-
-static int mtk_sha_update_start(struct mtk_cryp *cryp,
-                               struct mtk_sha_rec *sha)
-{
-       struct mtk_sha_reqctx *ctx = ahash_request_ctx(sha->req);
-       u32 len, final, tail;
-       struct scatterlist *sg;
-
-       if (!ctx->total)
-               return 0;
-
-       if (ctx->bufcnt || ctx->offset)
-               return mtk_sha_update_slow(cryp, sha);
-
-       sg = ctx->sg;
-
-       if (!IS_ALIGNED(sg->offset, sizeof(u32)))
-               return mtk_sha_update_slow(cryp, sha);
-
-       if (!sg_is_last(sg) && !IS_ALIGNED(sg->length, ctx->bs))
-               /* size is not ctx->bs aligned */
-               return mtk_sha_update_slow(cryp, sha);
-
-       len = min(ctx->total, sg->length);
-
-       if (sg_is_last(sg)) {
-               if (!(ctx->flags & SHA_FLAGS_FINUP)) {
-                       /* not last sg must be ctx->bs aligned */
-                       tail = len & (ctx->bs - 1);
-                       len -= tail;
-               }
-       }
-
-       ctx->total -= len;
-       ctx->offset = len; /* offset where to start slow */
-
-       final = (ctx->flags & SHA_FLAGS_FINUP) && !ctx->total;
-
-       /* Add padding */
-       if (final) {
-               size_t count;
-
-               tail = len & (ctx->bs - 1);
-               len -= tail;
-               ctx->total += tail;
-               ctx->offset = len; /* offset where to start slow */
-
-               sg = ctx->sg;
-               mtk_sha_append_sg(ctx);
-               mtk_sha_fill_padding(ctx, len);
-
-               ctx->dma_addr = dma_map_single(cryp->dev, ctx->buffer,
-                                              SHA_BUF_SIZE, DMA_TO_DEVICE);
-               if (unlikely(dma_mapping_error(cryp->dev, ctx->dma_addr))) {
-                       dev_err(cryp->dev, "dma map bytes error\n");
-                       return -EINVAL;
-               }
-
-               sha->flags |= SHA_FLAGS_FINAL;
-               count = ctx->bufcnt;
-               ctx->bufcnt = 0;
-
-               if (len == 0) {
-                       ctx->flags &= ~SHA_FLAGS_SG;
-                       return mtk_sha_xmit(cryp, sha, ctx->dma_addr,
-                                           count, 0, 0);
-
-               } else {
-                       ctx->sg = sg;
-                       if (!dma_map_sg(cryp->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
-                               dev_err(cryp->dev, "dma_map_sg error\n");
-                               return -EINVAL;
-                       }
-
-                       ctx->flags |= SHA_FLAGS_SG;
-                       return mtk_sha_xmit(cryp, sha, sg_dma_address(ctx->sg),
-                                           len, ctx->dma_addr, count);
-               }
-       }
-
-       if (!dma_map_sg(cryp->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
-               dev_err(cryp->dev, "dma_map_sg  error\n");
-               return -EINVAL;
-       }
-
-       ctx->flags |= SHA_FLAGS_SG;
-
-       return mtk_sha_xmit(cryp, sha, sg_dma_address(ctx->sg),
-                           len, 0, 0);
-}
-
-static int mtk_sha_final_req(struct mtk_cryp *cryp,
-                            struct mtk_sha_rec *sha)
-{
-       struct mtk_sha_reqctx *ctx = ahash_request_ctx(sha->req);
-       size_t count;
-
-       mtk_sha_fill_padding(ctx, 0);
-
-       sha->flags |= SHA_FLAGS_FINAL;
-       count = ctx->bufcnt;
-       ctx->bufcnt = 0;
-
-       return mtk_sha_dma_map(cryp, sha, ctx, count);
-}
-
-/* Copy ready hash (+ finalize hmac) */
-static int mtk_sha_finish(struct ahash_request *req)
-{
-       struct mtk_sha_reqctx *ctx = ahash_request_ctx(req);
-       __le32 *digest = ctx->info.digest;
-       u32 *result = (u32 *)req->result;
-       int i;
-
-       /* Get the hash from the digest buffer */
-       for (i = 0; i < SIZE_IN_WORDS(ctx->ds); i++)
-               result[i] = le32_to_cpu(digest[i]);
-
-       if (ctx->flags & SHA_FLAGS_HMAC)
-               return mtk_sha_finish_hmac(req);
-
-       return 0;
-}
-
-static void mtk_sha_finish_req(struct mtk_cryp *cryp,
-                              struct mtk_sha_rec *sha,
-                              int err)
-{
-       if (likely(!err && (SHA_FLAGS_FINAL & sha->flags)))
-               err = mtk_sha_finish(sha->req);
-
-       sha->flags &= ~(SHA_FLAGS_BUSY | SHA_FLAGS_FINAL);
-
-       sha->req->base.complete(&sha->req->base, err);
-
-       /* Handle new request */
-       tasklet_schedule(&sha->queue_task);
-}
-
-static int mtk_sha_handle_queue(struct mtk_cryp *cryp, u8 id,
-                               struct ahash_request *req)
-{
-       struct mtk_sha_rec *sha = cryp->sha[id];
-       struct crypto_async_request *async_req, *backlog;
-       struct mtk_sha_reqctx *ctx;
-       unsigned long flags;
-       int err = 0, ret = 0;
-
-       spin_lock_irqsave(&sha->lock, flags);
-       if (req)
-               ret = ahash_enqueue_request(&sha->queue, req);
-
-       if (SHA_FLAGS_BUSY & sha->flags) {
-               spin_unlock_irqrestore(&sha->lock, flags);
-               return ret;
-       }
-
-       backlog = crypto_get_backlog(&sha->queue);
-       async_req = crypto_dequeue_request(&sha->queue);
-       if (async_req)
-               sha->flags |= SHA_FLAGS_BUSY;
-       spin_unlock_irqrestore(&sha->lock, flags);
-
-       if (!async_req)
-               return ret;
-
-       if (backlog)
-               backlog->complete(backlog, -EINPROGRESS);
-
-       req = ahash_request_cast(async_req);
-       ctx = ahash_request_ctx(req);
-
-       sha->req = req;
-
-       mtk_sha_info_init(ctx);
-
-       if (ctx->op == SHA_OP_UPDATE) {
-               err = mtk_sha_update_start(cryp, sha);
-               if (err != -EINPROGRESS && (ctx->flags & SHA_FLAGS_FINUP))
-                       /* No final() after finup() */
-                       err = mtk_sha_final_req(cryp, sha);
-       } else if (ctx->op == SHA_OP_FINAL) {
-               err = mtk_sha_final_req(cryp, sha);
-       }
-
-       if (unlikely(err != -EINPROGRESS))
-               /* Task will not finish it, so do it here */
-               mtk_sha_finish_req(cryp, sha, err);
-
-&nb