ipq806x: fix pci pins
authorPavel Kubelun <be.dissent@gmail.com>
Tue, 8 Nov 2016 12:52:46 +0000 (15:52 +0300)
committerJohn Crispin <john@phrozen.org>
Wed, 16 Nov 2016 09:59:30 +0000 (10:59 +0100)
Fix pci pins drive-strength according to oem sources.

Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065.dtsi
target/linux/ipq806x/patches-4.4/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch

index 0d54303..bff9979 100644 (file)
                                mux {
                                        pins = "gpio3";
                                        function = "pcie1_rst";
-                                       drive-strength = <12>;
+                                       drive-strength = <2>;
                                        bias-disable;
                                };
                        };
                                mux {
                                        pins = "gpio48";
                                        function = "pcie2_rst";
-                                       drive-strength = <12>;
+                                       drive-strength = <2>;
                                        bias-disable;
                                };
                        };
                                mux {
                                        pins = "gpio63";
                                        function = "pcie3_rst";
-                                       drive-strength = <12>;
+                                       drive-strength = <2>;
                                        bias-disable;
+                                       output-low;
                                };
                        };
                };
index 2394926..31a384f 100644 (file)
@@ -63,7 +63,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  
  / {
        model = "Qualcomm IPQ8064";
-@@ -99,6 +102,33 @@
+@@ -99,6 +102,34 @@
                        interrupt-controller;
                        #interrupt-cells = <2>;
                        interrupts = <0 16 0x4>;
@@ -72,7 +72,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +                              mux {
 +                                      pins = "gpio3";
 +                                      function = "pcie1_rst";
-+                                      drive-strength = <12>;
++                                      drive-strength = <2>;
 +                                      bias-disable;
 +                              };
 +                      };
@@ -81,7 +81,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +                              mux {
 +                                      pins = "gpio48";
 +                                      function = "pcie2_rst";
-+                                      drive-strength = <12>;
++                                      drive-strength = <2>;
 +                                      bias-disable;
 +                              };
 +                      };
@@ -90,8 +90,9 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +                              mux {
 +                                      pins = "gpio63";
 +                                      function = "pcie3_rst";
-+                                      drive-strength = <12>;
++                                      drive-strength = <2>;
 +                                      bias-disable;
++                                      output-low;
 +                              };
 +                      };
                };