realtek: add support for Panasonic Switch-M24eG PN28240K

Panasonic Switch-M24eG PN28240K is a 24 + 2 port gigabit switch, based on
RTL8382M.

Specification:

- SoC           : Realtek RTL8382M
- RAM           : DDR3 128 MiB (Winbond W631GG8KB-15)
- Flash         : SPI-NOR 32 MiB (Macronix MX25L25635FMI-10G)
- Ethernet      : 10/100/1000 Mbps x24 + 2
  - port  1-8   : TP, RTL8218B
  - port  9-16  : TP, RTL8218B (SoC)
  - port 17-24  : RTL8218FB
    - port 17-22: TP
    - port 23-24: TP/SFP (Combo)
- LEDs/Keys     : 7x / 1x
- UART          : RS-232 port on the front panel (connector: RJ-45)
  - 3:TX, 4:GND, 5:GND, 6:RX (pin number: RJ-45)
  - 9600n8
- Power         : 100-240 VAC, 50/60 Hz, 0.5 A
  - Plug        : IEC 60320-C13
- Stock OS      : VxWorks based

Flash instruction using initramfs image:

1.  Prepare the TFTP server with the IP address 192.168.1.111
2.  Rename the OpenWrt initramfs image to "0101A8C0.img" and place it to
    the TFTP directory
3.  Download the official upgrading firmware (ex: pn28240k_v30000.rom)
    and place it to the TFTP directory
4.  Boot M24eG and interrupt the U-Boot with Ctrl + C keys
5.  Execute the following commands and boot with the OpenWrt initramfs
    image

    rtk network on
    tftpboot 0x81000000
    bootm

6.  Backup mtdblock files to the computer by scp or anything and reboot
7.  Interrupt the U-Boot and execute the following commands to re-create
    filesystem in the flash

    ffsmount c:/
    ffsfmt c:/

    this step takes a long time, about ~ 4 mins

8.  Execute the following commands to put the official images to the
    filesystem

    updatert <official image>

    example:

      updatert pn28240k_v30000.rom

    this step takes about ~ 40 secs

9.  Set the environment variables of the U-Boot by the following commands

    setenv loadaddr 0xb4e00000
    setenv bootcmd bootm
    saveenv

10: Download the OpenWrt initramfs image and boot with it

    tftpboot 0x81000000 0101A8C0.img
    bootm

11: On the initramfs image, download the sysupgrade image and perform
    sysupgrade with it

    sysupgrade <imagename>

12: Wait ~ 120 seconds to complete flashing

Known Issues:

- 2x SFP ports are provided as combo ports by the RTL8218FB chip, but the
  phy driver has no support for it. Currently, only TP ports work by the
  RTL8218D support.

Note:

- "Switch-M24eG" is a model name, and "PN28240K" is a model number.
  Switch-M24eG has an another (old) model number ("PN28240"), it's not a
  Realtek based hardware.

- Switch-M24eG has a "POWER" LED (Green), but it's not connected to any
  GPIO pin.

- U-Boot checks the runtime images in the flash when booting and fails
  to execute "bootcmd" variable if the images are not existing.

- A filesystem is formed in the flash (0x100000-0x1DFFFFF) on the stock
  firmware and it includes the stock images, configuration files and
  checksum files. It's unknown format, can't be managed on the OpenWrt.
  To get the enough space for OpenWrt, move the filesystem to the head
  of "fs_reserved" partition by execution of "ffsfmt" and "updatert".

- A GPIO pin on PCA9539 is used for resetting external RTL8218B phy and
  RTL8218FB phy.
  This should be specified as "reset-gpios" property in MDIO node, but
  the current configuration of RTL8218B phy in the phy driver seems to
  be incomplete and RTL8218FB won't be configured on RTL8218D support.
  So, ethernet ports on these phys will be broken after hard-resetting.
  At the moment, configure this pin as gpio-hog to avoid breaking by
  resetting.

Back to the stock firmware:

1. Delete "loadaddr" variable and set "bootcmd" to the original value

   on U-Boot:

     setenv loadaddr
     setenv bootcmd 'bootm 0x81000000'

   on OpenWrt:

     fw_setenv loadaddr
     fw_setenv bootcmd 'bootm 0x81000000'

2. Perform reset or reboot

  on U-Boot:

    reset

  on OpenWrt:

    reboot

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>

diff --git a/target/linux/realtek/dts-5.10/rtl8382_panasonic_m24eg-pn28240k.dts b/target/linux/realtek/dts-5.10/rtl8382_panasonic_m24eg-pn28240k.dts
new file mode 100644 (file)
index 0000000..1fa9d2c
--- /dev/null
+++ b/target/linux/realtek/dts-5.10/rtl8382_panasonic_m24eg-pn28240k.dts
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl838x.dtsi"
+#include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi"
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+       compatible = "panasonic,m24eg-pn28240k", "realtek,rtl8382-soc";
+       model = "Panasonic Switch-M24eG PN28240K";
+
+       aliases {
+               led-boot = &led_status_eco_green;
+               led-failsafe = &led_status_eco_amber;
+               led-running = &led_status_eco_green;
+               led-upgrade = &led_status_eco_green;
+       };
+
+       /*
+        * sfp0/1 are "combo" port with each TP port (23/24), and they are
+        * connected to the RTL8218FB. Currently, there is no support for
+        * the chip and only TP ports work by the RTL8218D support.
+        */
+       sfp0: sfp-p23 {
+               compatible = "sff,sfp";
+               i2c-bus = <&i2c0>;
+               tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+               tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+               mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+               los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+       };
+
+       sfp1: sfp-p24 {
+               compatible = "sff,sfp";
+               i2c-bus = <&i2c1>;
+               tx-fault-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+               tx-disable-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+               mod-def0-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
+               los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+       };
+};
+
+&leds {
+       led_status_eco_amber: led-5 {
+               label = "amber:status_eco";
+               gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+               color = <LED_COLOR_ID_AMBER>;
+               function = LED_FUNCTION_STATUS;
+               function-enumerator = <1>;
+       };
+
+       led_status_eco_green: led-6 {
+               label = "green:status_eco";
+               gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+               color = <LED_COLOR_ID_GREEN>;
+               function = LED_FUNCTION_STATUS;
+               function-enumerator = <2>;
+       };
+};
+
+&i2c_gpio_0 {
+       scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+       sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+&i2c_gpio_1 {
+       scl-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+       sda-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+&gpio2 {
+       interrupt-controller;
+       #interrupt-cells = <2>;
+       interrupt-parent = <&gpio0>;
+       interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+
+       /*
+        * GPIO12 (IO1_4): RTL8218B + RTL8218FB
+        *
+        * This GPIO pin should be specified as "reset-gpio" in mdio node,
+        * but the current configuration of RTL8218B phy in the phy driver
+        * seems to be incomplete and RTL8218FB phy won't be configured on
+        * RTL8218D support. So, ethernet ports on these phys will be broken
+        * after hard-resetting.
+        * (RTL8218FB phy will be detected as RTL8218D by the phy driver)
+        * At the moment, configure this GPIO pin as gpio-hog to avoid breaking
+        * by resetting.
+        */
+       ext_switch_reset {
+               gpio-hog;
+               gpios = <12 GPIO_ACTIVE_HIGH>;
+               output-high;
+               line-name = "ext-switch-reset";
+       };
+};
+
+&i2c_switch {
+       i2c0: i2c@0 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <0>;
+       };
+
+       i2c1: i2c@1 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <1>;
+       };
+};
+
+&ethernet0 {
+       mdio-bus {
+               compatible = "realtek,rtl838x-mdio";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               EXTERNAL_PHY(0)
+               EXTERNAL_PHY(1)
+               EXTERNAL_PHY(2)
+               EXTERNAL_PHY(3)
+               EXTERNAL_PHY(4)
+               EXTERNAL_PHY(5)
+               EXTERNAL_PHY(6)
+               EXTERNAL_PHY(7)
+
+               INTERNAL_PHY(8)
+               INTERNAL_PHY(9)
+               INTERNAL_PHY(10)
+               INTERNAL_PHY(11)
+               INTERNAL_PHY(12)
+               INTERNAL_PHY(13)
+               INTERNAL_PHY(14)
+               INTERNAL_PHY(15)
+
+               /* RTL8218FB */
+               EXTERNAL_PHY(16)
+               EXTERNAL_PHY(17)
+               EXTERNAL_PHY(18)
+               EXTERNAL_PHY(19)
+               EXTERNAL_PHY(20)
+               EXTERNAL_PHY(21)
+               EXTERNAL_PHY(22)
+               EXTERNAL_PHY(23)
+       };
+};
+
+&switch0 {
+       ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               SWITCH_PORT(0, 1, qsgmii)
+               SWITCH_PORT(1, 2, qsgmii)
+               SWITCH_PORT(2, 3, qsgmii)
+               SWITCH_PORT(3, 4, qsgmii)
+               SWITCH_PORT(4, 5, qsgmii)
+               SWITCH_PORT(5, 6, qsgmii)
+               SWITCH_PORT(6, 7, qsgmii)
+               SWITCH_PORT(7, 8, qsgmii)
+
+               SWITCH_PORT(8, 9, internal)
+               SWITCH_PORT(9, 10, internal)
+               SWITCH_PORT(10, 11, internal)
+               SWITCH_PORT(11, 12, internal)
+               SWITCH_PORT(12, 13, internal)
+               SWITCH_PORT(13, 14, internal)
+               SWITCH_PORT(14, 15, internal)
+               SWITCH_PORT(15, 16, internal)
+
+               SWITCH_PORT(16, 17, qsgmii)
+               SWITCH_PORT(17, 18, qsgmii)
+               SWITCH_PORT(18, 19, qsgmii)
+               SWITCH_PORT(19, 20, qsgmii)
+               SWITCH_PORT(20, 21, qsgmii)
+               SWITCH_PORT(21, 22, qsgmii)
+               SWITCH_PORT(22, 23, qsgmii)
+               SWITCH_PORT(23, 24, qsgmii)
+
+               port@28 {
+                       ethernet = <&ethernet0>;
+                       reg = <28>;
+                       phy-mode = "internal";
+
+                       fixed-link {
+                               speed = <1000>;
+                               full-duplex;
+                       };
+               };
+       };
+};

diff --git a/target/linux/realtek/image/rtl838x.mk b/target/linux/realtek/image/rtl838x.mk
index cbd41ce841a71f32506fbeb11efa2681f2409a91..9e1dd0308df3c4c22e1fcb37b70588444f836711 100644 (file)
--- a/target/linux/realtek/image/rtl838x.mk
+++ b/target/linux/realtek/image/rtl838x.mk
@@ -148,6 +148,16 @@ define Device/panasonic_m16eg-pn28160k
 endef
 TARGET_DEVICES += panasonic_m16eg-pn28160k
 
 endef
 TARGET_DEVICES += panasonic_m16eg-pn28160k
 

+define Device/panasonic_m24eg-pn28240k
+  SOC := rtl8382
+  IMAGE_SIZE := 16384k
+  DEVICE_VENDOR := Panasonic
+  DEVICE_MODEL := Switch-M24eG
+  DEVICE_VARIANT := PN28240K
+  DEVICE_PACKAGES := kmod-i2c-mux-pca954x
+endef
+TARGET_DEVICES += panasonic_m24eg-pn28240k
+

 define Device/panasonic_m8eg-pn28080k
   SOC := rtl8380
   IMAGE_SIZE := 16384k
 define Device/panasonic_m8eg-pn28080k
   SOC := rtl8380
   IMAGE_SIZE := 16384k