ath79: update WA/XC devices UBNT_VERSION to 8.7.4
[openwrt/staging/wigyori.git] / target / linux / ath79 / dts / ar7242_engenius_ecb350-v1.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "ar7242.dtsi"
4 #include "ar724x_senao_loader-4k.dtsi"
5
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/leds/common.h>
9
10 / {
11 compatible = "engenius,ecb350-v1", "qca,ar7242";
12 model = "EnGenius ECB350 v1";
13
14 aliases {
15 label-mac-device = &ath9k;
16 led-boot = &led_power;
17 led-failsafe = &led_power;
18 led-running = &led_power;
19 led-upgrade = &led_power;
20 };
21
22 keys {
23 compatible = "gpio-keys";
24
25 reset {
26 label = "reset";
27 gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
28 debounce-interval = <60>;
29 linux,code = <KEY_RESTART>;
30 };
31 };
32
33 leds {
34 compatible = "gpio-leds";
35
36 led_power: power {
37 function = LED_FUNCTION_POWER;
38 color = <LED_COLOR_ID_GREEN>;
39 gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
40 default-state = "on";
41 };
42 };
43
44 ath9k-leds {
45 compatible = "gpio-leds";
46
47 wlan {
48 function = LED_FUNCTION_WLAN;
49 color = <LED_COLOR_ID_GREEN>;
50 gpios = <&ath9k 1 GPIO_ACTIVE_LOW>;
51 linux,default-trigger = "phy0tpt";
52 };
53 };
54 };
55
56 &mdio0 {
57 status = "okay";
58
59 phy4: ethernet-phy@4 {
60 reg = <4>;
61 eee-broken-100tx;
62 eee-broken-1000t;
63 };
64 };
65
66 &eth0 {
67 status = "okay";
68
69 nvmem-cells = <&macaddr_art_0 0>;
70 nvmem-cell-names = "mac-address";
71
72 phy-handle = <&phy4>;
73 phy-mode = "rgmii-id";
74
75 pll-data = <0x02000000 0x00000101 0x00001313>;
76 };
77
78 &pcie {
79 status = "okay";
80
81 ath9k: wifi@0,0 {
82 compatible = "pci168c,002a";
83 reg = <0x0 0 0 0 0>;
84 nvmem-cells = <&macaddr_art_0 (-1)>;
85 nvmem-cell-names = "mac-address";
86 qca,no-eeprom;
87 #gpio-cells = <2>;
88 gpio-controller;
89 };
90 };
91
92 &art {
93 nvmem-layout {
94 compatible = "fixed-layout";
95 #address-cells = <1>;
96 #size-cells = <1>;
97
98 macaddr_art_0: macaddr@0 {
99 compatible = "mac-base";
100 reg = <0x0 0x6>;
101 #nvmem-cell-cells = <1>;
102 };
103 };
104 };