ath79: update WA/XC devices UBNT_VERSION to 8.7.4
[openwrt/staging/wigyori.git] / target / linux / ath79 / dts / ar9344_devolo_dlan_wifi.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "ar9344.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/leds/common.h>
8
9 / {
10 aliases {
11 led-boot = &led_dlan_red;
12 led-failsafe = &led_dlan_red;
13 led-running = &led_dlan_white;
14 led-upgrade = &led_dlan_red;
15 };
16
17 leds {
18 compatible = "gpio-leds";
19
20 wlan {
21 function = LED_FUNCTION_WLAN;
22 color = <LED_COLOR_ID_WHITE>;
23 gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
24 linux,default-trigger = "phy1tpt";
25 };
26
27 led_dlan_white: dlan_white {
28 label = "white:dlan";
29 gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
30 };
31
32 led_dlan_red: dlan_red {
33 label = "red:dlan";
34 gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
35 panic-indicator;
36 };
37 };
38
39 keys {
40 compatible = "gpio-keys";
41
42 reset {
43 label = "Reset button";
44 linux,code = <KEY_RESTART>;
45 gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
46 debounce-interval = <60>;
47 };
48
49 wifi {
50 label = "WIFI button";
51 linux,code = <KEY_RFKILL>;
52 gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
53 debounce-interval = <60>;
54 };
55
56 dlan {
57 label = "DLAN button";
58 linux,code = <BTN_0>;
59 gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
60 debounce-interval = <60>;
61 };
62 };
63 };
64
65 &gpio {
66 wlan_power {
67 gpio-hog;
68 line-name = "WLAN power";
69 gpios = <&gpio 21 GPIO_ACTIVE_HIGH>;
70 output-high;
71 };
72 };
73
74 &spi {
75 status = "okay";
76
77 flash@0 {
78 compatible = "jedec,spi-nor";
79 reg = <0>;
80 spi-max-frequency = <25000000>;
81
82 partitions {
83 compatible = "fixed-partitions";
84 #address-cells = <1>;
85 #size-cells = <1>;
86
87 uboot: partition@0 {
88 label = "u-boot";
89 reg = <0x0 0x40000>;
90 read-only;
91 };
92
93 partition@40000 {
94 label = "u-boot-env";
95 reg = <0x40000 0x10000>;
96 read-only;
97 };
98
99 partition@50000 {
100 label = "Config1";
101 reg = <0x50000 0x10000>;
102 read-only;
103 };
104
105 partition@60000 {
106 label = "Config2";
107 reg = <0x60000 0x10000>;
108 read-only;
109 };
110
111 partition@70000 {
112 compatible = "denx,uimage";
113 label = "firmware";
114 reg = <0x70000 0xf80000>;
115 };
116
117 art: partition@ff0000 {
118 label = "art";
119 reg = <0xff0000 0x10000>;
120 read-only;
121
122 nvmem-layout {
123 compatible = "fixed-layout";
124 #address-cells = <1>;
125 #size-cells = <1>;
126
127 macaddr_art_1002: macaddr@1002 {
128 compatible = "mac-base";
129 reg = <0x1002 0x6>;
130 #nvmem-cell-cells = <1>;
131 };
132
133 cal_art_5000: calibration@5000 {
134 reg = <0x5000 0x844>;
135 };
136 };
137 };
138 };
139 };
140 };
141
142 &ref {
143 clock-frequency = <40000000>;
144 };
145
146 &eth0 {
147 status = "okay";
148
149 pll-data = <0x02000000 0x00000101 0x00001616>;
150
151 nvmem-cells = <&macaddr_art_1002 2>;
152 nvmem-cell-names = "mac-address";
153
154 phy-mode = "rgmii";
155 phy-handle = <&phy0>;
156 };
157
158 &wmac {
159 status = "okay";
160
161 mtd-cal-data = <&art 0x1000>;
162 };
163
164 &pcie {
165 status = "okay";
166
167 wifi@0,0 {
168 compatible = "qcom,ath10k";
169 reg = <0 0 0 0 0>;
170 nvmem-cells = <&cal_art_5000>;
171 nvmem-cell-names = "calibration";
172 };
173 };
174
175 &mdio0 {
176 status = "okay";
177
178 phy0: ethernet-phy@0 {
179 reg = <0>;
180 phy-mode = "rgmii";
181
182 qca,ar8327-initvals = <
183 /* PORT0: RGMII, MAC0/6 exchange, tx_delay 01, No rx_delay */
184 0x04 0x06400000
185 0x08 0x00000000 /* PORT5 PAD MODE CTRL */
186 0x0c 0x00000000 /* PORT6 PAD MODE CTRL */
187 0x7c 0x0000007e /* PORT0_STATUS */
188 >;
189 };
190 };