target/linux/ath79/dts/ar9344_engenius_eap600.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include <dt-bindings/leds/common.h>
   4
   5 #include "ar9344_senao_ap-dual.dtsi"
   6
   7 / {
   8         model = "EnGenius EAP600";
   9         compatible = "engenius,eap600", "qca,ar9344";
  10
  11         leds {
  12                 compatible = "gpio-leds";
  13
  14                 led_power: power {
  15                         function = LED_FUNCTION_POWER;
  16                         color = <LED_COLOR_ID_AMBER>;
  17                         gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
  18                         default-state = "on";
  19                 };
  20
  21                 wps {
  22                         function = LED_FUNCTION_WPS;
  23                         color = <LED_COLOR_ID_BLUE>;
  24                         gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
  25                 };
  26
  27                 wifi5g {
  28                         label = "green:wifi5g";
  29                         gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
  30                         linux,default-trigger = "phy0tpt";
  31                 };
  32         };
  33 };
  34
  35 &eth0 {
  36         nvmem-cells = <&macaddr_art_0 (-2)>;
  37         nvmem-cell-names = "mac-address";
  38 };
  39
  40 &pcie {
  41         wifi@0,0 {
  42                 nvmem-cells = <&macaddr_art_0 0>, <&calibration_art_5000>;
  43                 nvmem-cell-names = "mac-address", "calibration";
  44         };
  45 };
  46
  47 &wmac {
  48         nvmem-cells = <&macaddr_art_0 (-1)>, <&calibration_art_1000>;
  49         nvmem-cell-names = "mac-address", "calibration";
  50 };
  51
  52 &art {
  53         nvmem-layout {
  54                 compatible = "fixed-layout";
  55                 #address-cells = <1>;
  56                 #size-cells = <1>;
  57
  58                 macaddr_art_0: macaddr@0 {
  59                         compatible = "mac-base";
  60                         reg = <0x0 0x6>;
  61                         #nvmem-cell-cells = <1>;
  62                 };
  63
  64                 calibration_art_1000: calibration@1000 {
  65                         reg = <0x1000 0x440>;
  66                 };
  67
  68                 calibration_art_5000: calibration@5000 {
  69                         reg = <0x5000 0x440>;
  70                 };
  71         };
  72 };