ath79: update WA/XC devices UBNT_VERSION to 8.7.4
[openwrt/staging/wigyori.git] / target / linux / ath79 / dts / qca953x.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "ath79.dtsi"
4
5 / {
6 compatible = "qca,qca9530";
7
8 #address-cells = <1>;
9 #size-cells = <1>;
10
11 chosen {
12 bootargs = "console=ttyS0,115200n8";
13 };
14
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 device_type = "cpu";
21 compatible = "mips,mips24Kc";
22 clocks = <&pll ATH79_CLK_CPU>;
23 reg = <0>;
24 };
25 };
26
27 extosc: ref {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-output-names = "ref";
31 clock-frequency = <25000000>;
32 };
33
34 ahb {
35 apb {
36 ddr_ctrl: memory-controller@18000000 {
37 compatible = "qca,qca9530-ddr-controller",
38 "qca,ar7240-ddr-controller";
39 reg = <0x18000000 0x128>;
40
41 #qca,ddr-wb-channel-cells = <1>;
42 };
43
44 uart: uart@18020000 {
45 compatible = "ns16550a";
46 reg = <0x18020000 0x20>;
47
48 interrupts = <3>;
49
50 clocks = <&pll ATH79_CLK_REF>;
51 clock-names = "uart";
52
53 reg-io-width = <4>;
54 reg-shift = <2>;
55 no-loopback-test;
56 };
57
58 usb_phy: usb-phy@18030000 {
59 compatible = "qca,ar7200-usb-phy";
60 reg = <0x18030000 0x100>;
61 #phy-cells = <0>;
62
63 reset-names = "usb-phy-analog", "usb-phy", "usb-suspend-override";
64 resets = <&rst 11>, <&rst 4>, <&rst 3>;
65
66 status = "disabled";
67 };
68
69 gpio: gpio@18040000 {
70 compatible = "qca,qca9530-gpio",
71 "qca,ar9340-gpio";
72 reg = <0x18040000 0x28>;
73
74 interrupts = <2>;
75 ngpios = <20>;
76
77 gpio-controller;
78 #gpio-cells = <2>;
79
80 interrupt-controller;
81 #interrupt-cells = <2>;
82 };
83
84 pinmux: pinmux@1804002c {
85 compatible = "pinctrl-single";
86
87 reg = <0x1804002c 0x48>;
88
89 #size-cells = <0>;
90
91 pinctrl-single,bit-per-mux;
92 pinctrl-single,register-width = <32>;
93 pinctrl-single,function-mask = <0x1>;
94 #pinctrl-cells = <2>;
95
96 jtag_disable_pins: pinmux_jtag_disable_pins {
97 pinctrl-single,bits = <0x40 0x2 0x2>;
98 };
99 };
100
101 pll: pll-controller@18050000 {
102 compatible = "qca,qca9530-pll", "syscon";
103 reg = <0x18050000 0x48>;
104
105 #clock-cells = <1>;
106 clock-output-names = "cpu", "ddr", "ahb";
107
108 clocks = <&extosc>;
109 clock-names = "ref";
110 };
111
112 wdt: wdt@18060008 {
113 compatible = "qca,qca9530-wdt", "qca,ar7130-wdt";
114 reg = <0x18060008 0x8>;
115
116 interrupts = <4>;
117
118 clocks = <&pll ATH79_CLK_AHB>;
119 clock-names = "wdt";
120 };
121
122 rst: reset-controller@1806001c {
123 compatible = "qca,qca9530-reset",
124 "qca,ar7100-reset";
125 reg = <0x1806001c 0xac>;
126
127 #reset-cells = <1>;
128
129 intc2: interrupt-controller {
130 compatible = "qca,ar9340-intc";
131
132 interrupt-parent = <&cpuintc>;
133 interrupts = <2>;
134
135 interrupt-controller;
136 #interrupt-cells = <1>;
137
138 qca,int-status-addr = <0xac>;
139 qca,pending-bits = <0xf>, /* wmac */
140 <0x1f0>; /* pcie rc1 */
141
142 qca,ddr-wb-channel-interrupts = <0>, <1>;
143 qca,ddr-wb-channels = <&ddr_ctrl 4>, <&ddr_ctrl 3>;
144 };
145 };
146 };
147
148 gmac: gmac@18070000 {
149 compatible = "qca,ar9330-gmac";
150 reg = <0x18070000 0x4>;
151 };
152
153 pcie0: pcie@180c0000 {
154 compatible = "qcom,ar7240-pci";
155 #address-cells = <3>;
156 #size-cells = <2>;
157 bus-range = <0x0 0x0>;
158 reg = <0x180c0000 0x1000>, /* CRP */
159 <0x180f0000 0x100>, /* CTRL */
160 <0x14000000 0x1000>; /* CFG */
161 reg-names = "crp_base", "ctrl_base", "cfg_base";
162 ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 /* pci memory */
163 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
164 interrupt-parent = <&intc2>;
165 interrupts = <1>;
166
167 device_type = "pci";
168
169 resets = <&rst 6>, <&rst 7>;
170 reset-names = "hc", "phy";
171
172 interrupt-controller;
173 #interrupt-cells = <1>;
174
175 interrupt-map-mask = <0 0 0 1>;
176 interrupt-map = <0 0 0 0 &pcie0 0>;
177 status = "disabled";
178 };
179
180 wmac: wmac@18100000 {
181 compatible = "qca,qca9530-wmac";
182 reg = <0x18100000 0x20000>;
183
184 interrupt-parent = <&intc2>;
185 interrupts = <0>;
186
187 status = "disabled";
188 };
189
190 usb0: usb@1b000000 {
191 compatible = "generic-ehci";
192 reg = <0x1b000000 0x1000>;
193
194 interrupts = <3>;
195 resets = <&rst 5>;
196 reset-names = "usb-host";
197 dr_mode = "host";
198
199 has-transaction-translator;
200 caps-offset = <0x100>;
201
202 phy-names = "usb-phy";
203 phys = <&usb_phy>;
204
205 status = "disabled";
206
207 #address-cells = <1>;
208 #size-cells = <0>;
209
210 hub_port0: port@1 {
211 reg = <1>;
212 #trigger-source-cells = <0>;
213 };
214 };
215
216 spi: spi@1f000000 {
217 compatible = "qca,ar934x-spi";
218 reg = <0x1f000000 0x1c>;
219
220 clocks = <&pll ATH79_CLK_AHB>;
221
222 status = "disabled";
223
224 #address-cells = <1>;
225 #size-cells = <0>;
226 };
227 };
228 };
229
230 &cpuintc {
231 qca,ddr-wb-channel-interrupts = <3>, <4>, <5>;
232 qca,ddr-wb-channels = <&ddr_ctrl 2>, <&ddr_ctrl 0>,
233 <&ddr_ctrl 1>;
234 };
235
236 &eth0 {
237 compatible = "qca,qca9530-eth", "syscon";
238 pll-data = <0x82000101 0x80000101 0x80001313>;
239 reg = <0x19000000 0x200
240 0x18070000 0x4>;
241 pll-reg = <0x4 0x2c 17>;
242 pll-handle = <&pll>;
243
244 reset-names = "mac";
245 resets = <&rst 9>;
246 };
247
248 &mdio1 {
249 status = "okay";
250 resets = <&rst 23>;
251 reset-names = "mdio";
252 builtin-switch;
253
254 builtin_switch: switch0@1f {
255 compatible = "qca,ar8229";
256
257 reg = <0x1f>;
258 resets = <&rst 8>;
259 reset-names = "switch";
260 phy-mode = "gmii";
261 qca,phy4-mii-enable;
262 qca,mib-poll-interval = <500>;
263
264 mdio-bus {
265 #address-cells = <1>;
266 #size-cells = <0>;
267
268 swphy0: ethernet-phy@0 {
269 reg = <0>;
270 phy-mode = "mii";
271 };
272
273 swphy4: ethernet-phy@4 {
274 reg = <4>;
275 phy-mode = "mii";
276 };
277 };
278 };
279 };
280
281 &eth1 {
282 status = "okay";
283
284 compatible = "qca,qca9530-eth", "syscon";
285 resets = <&rst 13>;
286 reset-names = "mac";
287
288 phy-mode = "gmii";
289
290 fixed-link {
291 speed = <1000>;
292 full-duplex;
293 };
294 };