imx6: drop 3.10 support
authorLuka Perkov <luka@openwrt.org>
Fri, 8 Aug 2014 13:38:31 +0000 (13:38 +0000)
committerLuka Perkov <luka@openwrt.org>
Fri, 8 Aug 2014 13:38:31 +0000 (13:38 +0000)
Signed-off-by: Luka Perkov <luka@openwrt.org>
SVN-Revision: 42075

53 files changed:
target/linux/imx6/config-3.10 [deleted file]
target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6dl-gw51xx.dts [deleted file]
target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6dl-gw52xx.dts [deleted file]
target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6dl-gw53xx.dts [deleted file]
target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6dl-gw54xx.dts [deleted file]
target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6q-gw51xx.dts [deleted file]
target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6q-gw52xx.dts [deleted file]
target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6q-gw53xx.dts [deleted file]
target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6q-gw5400-a.dts [deleted file]
target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6q-gw54xx.dts [deleted file]
target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi [deleted file]
target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi [deleted file]
target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi [deleted file]
target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi [deleted file]
target/linux/imx6/files-3.10/drivers/pci/host/pcie-designware.c [deleted file]
target/linux/imx6/files-3.10/drivers/pci/host/pcie-designware.h [deleted file]
target/linux/imx6/patches-3.10/0001-usb-chipidea-improve-kconfig.patch [deleted file]
target/linux/imx6/patches-3.10/0002-usb-chipidea-fix-the-build-error-with-randconfig.patch [deleted file]
target/linux/imx6/patches-3.10/0003-usb-chipidea-improve-kconfig-2.0.patch [deleted file]
target/linux/imx6/patches-3.10/0005-ahci_imx-add-ahci-sata-support-on-imx-platforms.patch [deleted file]
target/linux/imx6/patches-3.10/0006-ARM-imx6q-update-the-sata-bits-definitions-of-gpr13.patch [deleted file]
target/linux/imx6/patches-3.10/0007-ARM-dtsi-enable-ahci-sata-on-imx6q-platforms.patch [deleted file]
target/linux/imx6/patches-3.10/0008-ahci_imx-depend-on-CONFIG_MFD_SYSCON.patch [deleted file]
target/linux/imx6/patches-3.10/0009-of-pci-Provide-support-for-parsing-PCI-DT-ranges-pro.patch [deleted file]
target/linux/imx6/patches-3.10/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch [deleted file]
target/linux/imx6/patches-3.10/0011-PCI-imx6-Add-support-for-i.MX6-PCIe-controller.patch [deleted file]
target/linux/imx6/patches-3.10/0012-ARM-imx-Add-LVDS-general-purpose-clocks-to-i.MX6Q.patch [deleted file]
target/linux/imx6/patches-3.10/0013-ARM-imx6q-clock-and-Kconfig-update-for-PCIe-support.patch [deleted file]
target/linux/imx6/patches-3.10/0014-ARM-dts-imx6qdl-add-pcie-device-node.patch [deleted file]
target/linux/imx6/patches-3.10/0015-thermal-add-imx-thermal-driver-support.patch [deleted file]
target/linux/imx6/patches-3.10/0019-regulator-pfuze100-add-pfuze100-regulator-driver.patch [deleted file]
target/linux/imx6/patches-3.10/0020-regulator-pfuze100-REGULATOR_PFUZE100-needs-to-selec.patch [deleted file]
target/linux/imx6/patches-3.10/0021-regulator-pfuze100-fix-build-warning-and-correct-the.patch [deleted file]
target/linux/imx6/patches-3.10/0022-regulator-pfuze100-add-MODULE_LICENSE-in-pfuze100-dr.patch [deleted file]
target/linux/imx6/patches-3.10/0023-regulator-pfuze100-Use-i2c_-set-get-_clientdata.patch [deleted file]
target/linux/imx6/patches-3.10/0024-regulator-pfuze100-Fix-module-alias-prefix.patch [deleted file]
target/linux/imx6/patches-3.10/0025-regulator-pfuze100-Use-regulator_map_voltage_ascend.patch [deleted file]
target/linux/imx6/patches-3.10/0026-regulator-pfuze100-Fix-n_voltages-setting-for-SW2-SW.patch [deleted file]
target/linux/imx6/patches-3.10/0027-regulator-pfuze100-Simplify-pfuze100_set_ramp_delay-.patch [deleted file]
target/linux/imx6/patches-3.10/0028-regulator-pfuze100-Fix-off-by-one-for-max_register-s.patch [deleted file]
target/linux/imx6/patches-3.10/0029-regulator-pfuze100-allow-misprogrammed-ID.patch [deleted file]
target/linux/imx6/patches-3.10/0030-pcie-designware-fix-io-transfers.patch [deleted file]
target/linux/imx6/patches-3.10/0031-PCI-imx6-init-must-be-early.patch [deleted file]
target/linux/imx6/patches-3.10/0032-PCI-imx6-fix-imprecise-abort-handler.patch [deleted file]
target/linux/imx6/patches-3.10/0033-PCI-imx6-increase-link-startup.patch [deleted file]
target/linux/imx6/patches-3.10/0034-PCI-imx6-add-support-for-legacy-irqs.patch [deleted file]
target/linux/imx6/patches-3.10/0050-sky2-allow-mac-to-come-from-dt.patch [deleted file]
target/linux/imx6/patches-3.10/0060-flexcan.patch [deleted file]
target/linux/imx6/patches-3.10/0061-can-flexcan-use-correct-clock-as-base-for-bit-rate-c.patch [deleted file]
target/linux/imx6/patches-3.10/010-pcie-backport-fixes.patch [deleted file]
target/linux/imx6/patches-3.10/100-bootargs.patch [deleted file]
target/linux/imx6/patches-3.10/110-gateworks-ventana.patch [deleted file]
target/linux/imx6/patches-3.10/120-ventana-init.ptach [deleted file]

diff --git a/target/linux/imx6/config-3.10 b/target/linux/imx6/config-3.10
deleted file mode 100644 (file)
index 21433fc..0000000
+++ /dev/null
@@ -1,366 +0,0 @@
-CONFIG_AHCI_IMX=y
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_ARCH_BCM is not set
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_CPUFREQ=y
-CONFIG_ARCH_HAS_OPP=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_MULTIPLATFORM=y
-# CONFIG_ARCH_MULTI_CPU_AUTO is not set
-# CONFIG_ARCH_MULTI_V6 is not set
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_MXC=y
-# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SUNXI is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_ARCH_VIRT is not set
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-# CONFIG_ARCH_WM8850 is not set
-CONFIG_ARM=y
-# CONFIG_ARM_APPENDED_DTB is not set
-# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set
-# CONFIG_ARM_CPU_SUSPEND is not set
-CONFIG_ARM_ERRATA_754322=y
-CONFIG_ARM_ERRATA_764369=y
-CONFIG_ARM_ERRATA_775420=y
-# CONFIG_ARM_EXYNOS4210_CPUFREQ is not set
-# CONFIG_ARM_EXYNOS4X12_CPUFREQ is not set
-# CONFIG_ARM_EXYNOS5250_CPUFREQ is not set
-# CONFIG_ARM_EXYNOS5440_CPUFREQ is not set
-CONFIG_ARM_GIC=y
-CONFIG_ARM_IMX6Q_CPUFREQ=y
-# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-# CONFIG_ARM_LPAE is not set
-CONFIG_ARM_NR_BANKS=8
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-# CONFIG_ARM_THUMBEE is not set
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ATA=y
-CONFIG_ATAGS=y
-# CONFIG_ATA_SFF is not set
-CONFIG_AUTO_ZRELADDR=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_OF=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_FREQ_STAT_DETAILS=y
-CONFIG_CPU_FREQ_TABLE=y
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_XZ=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_IMX_UART_PORT=1
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-# CONFIG_DEBUG_PINCTRL is not set
-# CONFIG_DEBUG_USER is not set
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_LZO=y
-CONFIG_DECOMPRESS_XZ=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DTC=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_EXT3_FS_XATTR=y
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-CONFIG_FEC=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CPUFREQ_CPU0=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_MXC=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HAMRADIO is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_ARM_SCU=y
-CONFIG_HAVE_ARM_TWD=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_HW_BREAKPOINT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IMX_ANATOP=y
-CONFIG_HAVE_IMX_GPC=y
-CONFIG_HAVE_IMX_MMDC=y
-CONFIG_HAVE_IMX_SRC=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SMP=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_IMX=y
-CONFIG_IMX2_WDT=y
-# CONFIG_IMX_DMA is not set
-# CONFIG_IMX_SDMA is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD=y
-CONFIG_JBD2=y
-CONFIG_KTIME_SCALAR=y
-# CONFIG_LEDS_REGULATOR is not set
-CONFIG_LOCAL_TIMERS=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_M25PXX_USE_FAST_READ=y
-# CONFIG_MACH_EUKREA_CPUIMX51SD is not set
-# CONFIG_MACH_IMX51_DT is not set
-# CONFIG_MACH_MX51_BABBAGE is not set
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_PCI=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-# CONFIG_MMC_MXC is not set
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ESDHC_IMX=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-# CONFIG_MMC_TIFM_SD is not set
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MPCORE_WATCHDOG is not set
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_GPMI_NAND=y
-CONFIG_MTD_OF_PARTS=y
-# CONFIG_MTD_PHYSMAP_OF is not set
-# CONFIG_MTD_SM_COMMON is not set
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-# CONFIG_MTD_UBI_BLOCK is not set
-# CONFIG_MTD_UBI_FASTMAP is not set
-# CONFIG_MTD_UBI_GLUEBI is not set
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-# CONFIG_MX3_IPU is not set
-# CONFIG_MXC_DEBUG_BOARD is not set
-# CONFIG_MXC_IRQ_PRIOR is not set
-CONFIG_MXS_DMA=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DEVICE=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_I2C=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0x80000000
-CONFIG_PCI=y
-CONFIG_PCIE_DW=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_IMX6=y
-CONFIG_PERF_EVENTS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_IMX=y
-CONFIG_PINCTRL_IMX6Q=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PINMUX=y
-CONFIG_PM_OPP=y
-CONFIG_PPS=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_PROC_DEVICETREE=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_RATIONAL=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_GZIP=y
-CONFIG_RD_LZO=y
-CONFIG_RD_XZ=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_SPI=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_ANATOP=y
-# CONFIG_REGULATOR_DEBUG is not set
-# CONFIG_REGULATOR_DUMMY is not set
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_PFUZE100=y
-# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-# CONFIG_RFKILL_REGULATOR is not set
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_IMXDI is not set
-# CONFIG_RTC_DRV_MXC is not set
-# CONFIG_SAMSUNG_USB2PHY is not set
-# CONFIG_SAMSUNG_USB3PHY is not set
-# CONFIG_SAMSUNG_USBPHY is not set
-CONFIG_SATA_AHCI_PLATFORM=y
-CONFIG_SCHED_HRTICK=y
-CONFIG_SCSI=y
-CONFIG_SERIAL_IMX=y
-CONFIG_SERIAL_IMX_CONSOLE=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-# CONFIG_SOC_IMX53 is not set
-CONFIG_SOC_IMX6Q=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_IMX=y
-CONFIG_SPI_MASTER=y
-CONFIG_STMP_DEVICE=y
-CONFIG_STOP_MACHINE=y
-# CONFIG_SWP_EMULATE is not set
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-# CONFIG_TEGRA_HOST1X is not set
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TREE_RCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-CONFIG_UBIFS_FS_LZO=y
-CONFIG_UBIFS_FS_XZ=y
-CONFIG_UBIFS_FS_ZLIB=y
-CONFIG_UID16=y
-CONFIG_UIDGID_CONVERTED=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_USB_ARCH_HAS_XHCI=y
-# CONFIG_USB_MXS_PHY is not set
-CONFIG_USB_PHY=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_GENERIC_SMP_HELPERS=y
-CONFIG_USE_OF=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VMSPLIT_2G=y
-# CONFIG_VMSPLIT_3G is not set
-# CONFIG_XEN is not set
-CONFIG_XPS=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA_FLAG=0
diff --git a/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6dl-gw51xx.dts b/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6dl-gw51xx.dts
deleted file mode 100644 (file)
index 113f1c6..0000000
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright 2013 Gateworks Corporation
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/dts-v1/;
-#include "imx6dl.dtsi"
-#include "imx6qdl-gw51xx.dtsi"
-
-/ {
-       model = "Gateworks Ventana i.MX6 DualLite/Solo GW51XX";
-       compatible = "gw,imx6dl-gw51xx", "gw,ventana", "fsl,imx6dl";
-};
-
-&iomuxc {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_hog>;
-
-       hog {
-               pinctrl_hog: hoggrp {
-                       fsl,pins = <
-                               MX6DL_PAD_EIM_A19__GPIO2_IO19   0x80000000 /* MEZZ_DIO0 */
-                               MX6DL_PAD_EIM_A20__GPIO2_IO18   0x80000000 /* MEZZ_DIO1 */
-                               MX6DL_PAD_EIM_D22__GPIO3_IO22   0x80000000 /* OTG_PWR_EN */
-                               MX6DL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */
-                               MX6DL_PAD_GPIO_0__GPIO1_IO00    0x80000000 /* PCIE_RST# */
-                               MX6DL_PAD_KEY_COL0__GPIO4_IO06  0x80000000 /* user1 led */
-                               MX6DL_PAD_KEY_ROW0__GPIO4_IO07  0x80000000 /* user2 led */
-                        >;
-               };
-       };
-};
diff --git a/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6dl-gw52xx.dts b/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6dl-gw52xx.dts
deleted file mode 100644 (file)
index 816a242..0000000
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright 2013 Gateworks Corporation
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/dts-v1/;
-#include "imx6dl.dtsi"
-#include "imx6qdl-gw52xx.dtsi"
-
-/ {
-       model = "Gateworks Ventana i.MX6 DualLite/Solo GW52XX";
-       compatible = "gw,imx6dl-gw52xx", "gw,ventana", "fsl,imx6dl";
-};
-
-&iomuxc {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_hog>;
-
-       hog {
-               pinctrl_hog: hoggrp {
-                       fsl,pins = <
-                               MX6DL_PAD_EIM_A19__GPIO2_IO19   0x80000000 /* MEZZ_DIO0 */
-                               MX6DL_PAD_EIM_A20__GPIO2_IO18   0x80000000 /* MEZZ_DIO1 */
-                               MX6DL_PAD_EIM_D22__GPIO3_IO22   0x80000000 /* OTG_PWR_EN */
-                               MX6DL_PAD_EIM_D31__GPIO3_IO31   0x80000000 /* VIDDEC_PDN# */
-                               MX6DL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */
-                               MX6DL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE_RST# */
-                               MX6DL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_PWDN */
-                               MX6DL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */
-                               MX6DL_PAD_GPIO_0__CCM_CLKO1     0x000130b0 /* AUD4_MCK */
-                               MX6DL_PAD_GPIO_2__GPIO1_IO02    0x80000000 /* USB_SEL_PCI */
-                               MX6DL_PAD_GPIO_17__GPIO7_IO12   0x80000000 /* TOUCH_IRQ# */
-                               MX6DL_PAD_KEY_COL0__GPIO4_IO06  0x80000000 /* user1 led */
-                               MX6DL_PAD_KEY_ROW0__GPIO4_IO07  0x80000000 /* user2 led */
-                               MX6DL_PAD_KEY_ROW4__GPIO4_IO15  0x80000000 /* user3 led */
-                               MX6DL_PAD_SD2_CMD__GPIO1_IO11   0x80000000 /* LVDS_TCH# */
-                               MX6DL_PAD_SD3_DAT5__GPIO7_IO00  0x80000000 /* SD3_CD# */
-                               MX6DL_PAD_SD4_DAT3__GPIO2_IO11  0x80000000 /* UART2_EN# */
-                        >;
-               };
-       };
-};
diff --git a/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6dl-gw53xx.dts b/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6dl-gw53xx.dts
deleted file mode 100644 (file)
index 9679257..0000000
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright 2013 Gateworks Corporation
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/dts-v1/;
-#include "imx6dl.dtsi"
-#include "imx6qdl-gw53xx.dtsi"
-
-/ {
-       model = "Gateworks Ventana i.MX6 DualLite/Solo GW53XX";
-       compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl";
-};
-
-&iomuxc {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_hog>;
-
-       hog {
-               pinctrl_hog: hoggrp {
-                       fsl,pins = <
-                               MX6DL_PAD_EIM_A19__GPIO2_IO19   0x80000000 /* MEZZ_DIO0 */
-                               MX6DL_PAD_EIM_A20__GPIO2_IO18   0x80000000 /* MEZZ_DIO1 */
-                               MX6DL_PAD_EIM_D22__GPIO3_IO22   0x80000000 /* OTG_PWR_EN */
-                               MX6DL_PAD_EIM_D31__GPIO3_IO31   0x80000000 /* VIDDEC_PDN# */
-                               MX6DL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */
-                               MX6DL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE_RST# */
-                               MX6DL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_PWDN */
-                               MX6DL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */
-                               MX6DL_PAD_GPIO_0__CCM_CLKO1     0x000130b0 /* AUD4_MCK */
-                               MX6DL_PAD_GPIO_17__GPIO7_IO12   0x80000000 /* TOUCH_IRQ# */
-                               MX6DL_PAD_KEY_COL0__GPIO4_IO06  0x80000000 /* user1 led */
-                               MX6DL_PAD_KEY_ROW0__GPIO4_IO07  0x80000000 /* user2 led */
-                               MX6DL_PAD_KEY_ROW4__GPIO4_IO15  0x80000000 /* user3 led */
-                               MX6DL_PAD_SD2_CMD__GPIO1_IO11   0x80000000 /* LVDS_TCH# */
-                               MX6DL_PAD_SD3_DAT5__GPIO7_IO00  0x80000000 /* SD3_CD# */
-                               MX6DL_PAD_SD4_DAT3__GPIO2_IO11  0x80000000 /* UART2_EN# */
-                        >;
-               };
-       };
-};
diff --git a/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6dl-gw54xx.dts b/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6dl-gw54xx.dts
deleted file mode 100644 (file)
index 76c760b..0000000
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright 2013 Gateworks Corporation
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/dts-v1/;
-#include "imx6dl.dtsi"
-#include "imx6qdl-gw54xx.dtsi"
-
-/ {
-       model = "Gateworks Ventana i.MX6 DualLite/Solo GW54XX";
-       compatible = "gw,imx6dl-gw54xx", "gw,ventana", "fsl,imx6dl";
-};
-
-&iomuxc {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_hog>;
-
-       hog {
-               pinctrl_hog: hoggrp {
-                       fsl,pins = <
-                               MX6DL_PAD_EIM_D22__GPIO3_IO22    0x80000000 /* OTG_PWR_EN */
-                               MX6DL_PAD_EIM_D19__GPIO3_IO19    0x80000000 /* SPINOR_CS0# */
-                               MX6DL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */
-                               MX6DL_PAD_ENET_TXD1__GPIO1_IO29  0x80000000 /* PCIE RST */
-                               MX6DL_PAD_GPIO_0__CCM_CLKO1      0x000130b0 /* AUD4_MCK */
-                               MX6DL_PAD_GPIO_2__GPIO1_IO02     0x80000000 /* CAN_STBY */
-                               MX6DL_PAD_GPIO_17__GPIO7_IO12    0x80000000 /* TOUCH_IRQ# */
-                               MX6DL_PAD_KEY_COL0__GPIO4_IO06   0x80000000 /* user1 led */
-                               MX6DL_PAD_KEY_ROW0__GPIO4_IO07   0x80000000 /* user2 led */
-                               MX6DL_PAD_KEY_ROW4__GPIO4_IO15   0x80000000 /* user3 led */
-                               MX6DL_PAD_SD1_DAT0__GPIO1_IO16   0x80000000 /* USBHUB_RST# */
-                               MX6DL_PAD_SD1_DAT3__GPIO1_IO21   0x80000000 /* MIPI_DIO */
-                        >;
-               };
-       };
-};
diff --git a/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6q-gw51xx.dts b/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6q-gw51xx.dts
deleted file mode 100644 (file)
index 84b08f9..0000000
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright 2013 Gateworks Corporation
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/dts-v1/;
-#include "imx6q.dtsi"
-#include "imx6qdl-gw51xx.dtsi"
-
-/ {
-       model = "Gateworks Ventana i.MX6 Dual/Quad GW51XX";
-       compatible = "gw,imx6q-gw51xx", "gw,ventana", "fsl,imx6q";
-};
-
-&iomuxc {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_hog>;
-
-       hog {
-               pinctrl_hog: hoggrp {
-                       fsl,pins = <
-                               MX6Q_PAD_EIM_A19__GPIO2_IO19   0x80000000 /* MEZZ_DIO0 */
-                               MX6Q_PAD_EIM_A20__GPIO2_IO18   0x80000000 /* MEZZ_DIO1 */
-                               MX6Q_PAD_EIM_D22__GPIO3_IO22   0x80000000 /* OTG_PWR_EN */
-                               MX6Q_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */
-                               MX6Q_PAD_GPIO_0__GPIO1_IO00    0x80000000 /* PCIE_RST# */
-                               MX6Q_PAD_KEY_COL0__GPIO4_IO06  0x80000000 /* user1 led */
-                               MX6Q_PAD_KEY_ROW0__GPIO4_IO07  0x80000000 /* user2 led */
-                        >;
-               };
-       };
-};
diff --git a/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6q-gw52xx.dts b/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6q-gw52xx.dts
deleted file mode 100644 (file)
index 6e0558e..0000000
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright 2013 Gateworks Corporation
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/dts-v1/;
-#include "imx6q.dtsi"
-#include "imx6qdl-gw52xx.dtsi"
-
-/ {
-       model = "Gateworks Ventana i.MX6 Dual/Quad GW52XX";
-       compatible = "gw,imx6q-gw52xx", "gw,ventana", "fsl,imx6q";
-};
-
-&iomuxc {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_hog>;
-
-       hog {
-               pinctrl_hog: hoggrp {
-                       fsl,pins = <
-                               MX6Q_PAD_EIM_A19__GPIO2_IO19   0x80000000 /* MEZZ_DIO0 */
-                               MX6Q_PAD_EIM_A20__GPIO2_IO18   0x80000000 /* MEZZ_DIO1 */
-                               MX6Q_PAD_EIM_D22__GPIO3_IO22   0x80000000 /* OTG_PWR_EN */
-                               MX6Q_PAD_EIM_D31__GPIO3_IO31   0x80000000 /* VIDDEC_PDN# */
-                               MX6Q_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */
-                               MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE_RST# */
-                               MX6Q_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_PWDN */
-                               MX6Q_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */
-                               MX6Q_PAD_GPIO_0__CCM_CLKO1     0x000130b0 /* AUD4_MCK */
-                               MX6Q_PAD_GPIO_2__GPIO1_IO02    0x80000000 /* USB_SEL_PCI */
-                               MX6Q_PAD_GPIO_17__GPIO7_IO12   0x80000000 /* TOUCH_IRQ# */
-                               MX6Q_PAD_KEY_COL0__GPIO4_IO06  0x80000000 /* user1 led */
-                               MX6Q_PAD_KEY_ROW0__GPIO4_IO07  0x80000000 /* user2 led */
-                               MX6Q_PAD_KEY_ROW4__GPIO4_IO15  0x80000000 /* user3 led */
-                               MX6Q_PAD_SD2_CMD__GPIO1_IO11   0x80000000 /* LVDS_TCH# */
-                               MX6Q_PAD_SD3_DAT5__GPIO7_IO00  0x80000000 /* SD3_CD# */
-                               MX6Q_PAD_SD4_DAT3__GPIO2_IO11  0x80000000 /* UART2_EN# */
-                        >;
-               };
-       };
-};
-
-&sata {
-        status = "okay";
-};
diff --git a/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6q-gw53xx.dts b/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6q-gw53xx.dts
deleted file mode 100644 (file)
index 4f9319a..0000000
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright 2013 Gateworks Corporation
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/dts-v1/;
-#include "imx6q.dtsi"
-#include "imx6qdl-gw53xx.dtsi"
-
-/ {
-       model = "Gateworks Ventana i.MX6 Dual/Quad GW53XX";
-       compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q";
-};
-
-&iomuxc {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_hog>;
-
-       hog {
-               pinctrl_hog: hoggrp {
-                       fsl,pins = <
-                               MX6Q_PAD_EIM_A19__GPIO2_IO19   0x80000000 /* MEZZ_DIO0 */
-                               MX6Q_PAD_EIM_A20__GPIO2_IO18   0x80000000 /* MEZZ_DIO1 */
-                               MX6Q_PAD_EIM_D22__GPIO3_IO22   0x80000000 /* OTG_PWR_EN */
-                               MX6Q_PAD_EIM_D31__GPIO3_IO31   0x80000000 /* VIDDEC_PDN# */
-                               MX6Q_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */
-                               MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE_RST# */
-                               MX6Q_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_PWDN */
-                               MX6Q_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */
-                               MX6Q_PAD_GPIO_0__CCM_CLKO1     0x000130b0 /* AUD4_MCK */
-                               MX6Q_PAD_GPIO_17__GPIO7_IO12   0x80000000 /* TOUCH_IRQ# */
-                               MX6Q_PAD_KEY_COL0__GPIO4_IO06  0x80000000 /* user1 led */
-                               MX6Q_PAD_KEY_ROW0__GPIO4_IO07  0x80000000 /* user2 led */
-                               MX6Q_PAD_KEY_ROW4__GPIO4_IO15  0x80000000 /* user3 led */
-                               MX6Q_PAD_SD2_CMD__GPIO1_IO11   0x80000000 /* LVDS_TCH# */
-                               MX6Q_PAD_SD3_DAT5__GPIO7_IO00  0x80000000 /* SD3_CD# */
-                               MX6Q_PAD_SD4_DAT3__GPIO2_IO11  0x80000000 /* UART2_EN# */
-                        >;
-               };
-       };
-};
-
-&sata {
-        status = "okay";
-};
diff --git a/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6q-gw5400-a.dts b/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6q-gw5400-a.dts
deleted file mode 100644 (file)
index 9677135..0000000
+++ /dev/null
@@ -1,438 +0,0 @@
-/*
- * Copyright 2013 Gateworks Corporation
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/dts-v1/;
-#include "imx6q.dtsi"
-
-/ {
-       model = "Gateworks Ventana GW5400-A";
-       compatible = "gw,imx6q-gw5400-a", "gw,ventana", "fsl,imx6q";
-
-       /* these are used by bootloader for disabling nodes */
-       aliases {
-               ethernet0 = &fec;
-               ethernet1 = &eth1;
-               i2c0 = &i2c1;
-               i2c1 = &i2c2;
-               i2c2 = &i2c3;
-               led0 = &led0;
-               led1 = &led1;
-               led2 = &led2;
-               sky2 = &eth1;
-               ssi0 = &ssi1;
-               spi0 = &ecspi1;
-               usb0 = &usbh1;
-               usb1 = &usbotg;
-               usdhc2 = &usdhc3;
-       };
-
-       chosen {
-               bootargs = "console=ttymxc1,115200";
-       };
-
-       leds {
-               compatible = "gpio-leds";
-
-               led0: user1 {
-                       label = "user1";
-                       gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
-                       default-state = "on";
-                       linux,default-trigger = "heartbeat";
-               };
-
-               led1: user2 {
-                       label = "user2";
-                       gpios = <&gpio4 10 0>; /* 106 -> MX6_PANLEDR */
-                       default-state = "off";
-               };
-
-               led2: user3 {
-                       label = "user3";
-                       gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */
-                       default-state = "off";
-               };
-       };
-
-       memory {
-               reg = <0x10000000 0x40000000>;
-       };
-
-       regulators {
-               compatible = "simple-bus";
-
-               reg_1p0v: 1p0v {
-                       compatible = "regulator-fixed";
-                       regulator-name = "1P0V";
-                       regulator-min-microvolt = <1000000>;
-                       regulator-max-microvolt = <1000000>;
-                       regulator-always-on;
-               };
-
-               reg_3p3v: 3p3v {
-                       compatible = "regulator-fixed";
-                       regulator-name = "3P3V";
-                       regulator-min-microvolt = <3300000>;
-                       regulator-max-microvolt = <3300000>;
-                       regulator-always-on;
-               };
-
-               reg_usb_h1_vbus: usb_h1_vbus {
-                       compatible = "regulator-fixed";
-                       regulator-name = "usb_h1_vbus";
-                       regulator-min-microvolt = <5000000>;
-                       regulator-max-microvolt = <5000000>;
-                       regulator-always-on;
-               };
-
-               reg_usb_otg_vbus: usb_otg_vbus {
-                       compatible = "regulator-fixed";
-                       regulator-name = "usb_otg_vbus";
-                       regulator-min-microvolt = <5000000>;
-                       regulator-max-microvolt = <5000000>;
-                       gpio = <&gpio3 22 0>;
-                       enable-active-high;
-               };
-       };
-
-       sound {
-               compatible = "fsl,imx6q-sabrelite-sgtl5000",
-                            "fsl,imx-audio-sgtl5000";
-               model = "imx6q-sabrelite-sgtl5000";
-               ssi-controller = <&ssi1>;
-               audio-codec = <&codec>;
-               audio-routing =
-                       "MIC_IN", "Mic Jack",
-                       "Mic Jack", "Mic Bias",
-                       "Headphone Jack", "HP_OUT";
-               mux-int-port = <1>;
-               mux-ext-port = <4>;
-       };
-};
-
-&audmux {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_audmux_1>;
-       status = "okay";
-};
-
-&ecspi1 {
-       fsl,spi-num-chipselects = <1>;
-       cs-gpios = <&gpio3 19 0>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_ecspi1_1>;
-       status = "okay";
-
-       flash: m25p80@0 {
-               compatible = "sst,w25q256";
-               spi-max-frequency = <30000000>;
-               reg = <0>;
-       };
-};
-
-&fec {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_enet_1>;
-       phy-mode = "rgmii";
-       phy-reset-gpios = <&gpio1 30 0>;
-       status = "okay";
-};
-
-&i2c1 {
-       clock-frequency = <100000>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_i2c1_1>;
-       status = "okay";
-
-       eeprom1: eeprom@50 {
-               compatible = "atmel,24c02";
-               reg = <0x50>;
-               pagesize = <16>;
-       };
-
-       eeprom2: eeprom@51 {
-               compatible = "atmel,24c02";
-               reg = <0x51>;
-               pagesize = <16>;
-       };
-
-       eeprom3: eeprom@52 {
-               compatible = "atmel,24c02";
-               reg = <0x52>;
-               pagesize = <16>;
-       };
-
-       eeprom4: eeprom@53 {
-               compatible = "atmel,24c02";
-               reg = <0x53>;
-               pagesize = <16>;
-       };
-
-       gpio: pca9555@23 {
-               compatible = "nxp,pca9555";
-               reg = <0x23>;
-               gpio-controller;
-               #gpio-cells = <2>;
-       };
-
-       hwmon: gsc@29 {
-               compatible = "gw,gsp";
-               reg = <0x29>;
-       };
-
-       rtc: ds1672@68 {
-               compatible = "dallas,ds1672";
-               reg = <0x68>;
-       };
-};
-
-&i2c2 {
-       clock-frequency = <100000>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_i2c2_2>;
-       status = "okay";
-
-       pmic: pfuze100@08 {
-               compatible = "fsl,pfuze100";
-               reg = <0x08>;
-
-               regulators {
-                       sw1a_reg: sw1ab {
-                               regulator-min-microvolt = <300000>;
-                               regulator-max-microvolt = <1875000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                               regulator-ramp-delay = <6250>;
-                       };
-
-                       sw1c_reg: sw1c {
-                               regulator-min-microvolt = <300000>;
-                               regulator-max-microvolt = <1875000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                               regulator-ramp-delay = <6250>;
-                       };
-
-                       sw2_reg: sw2 {
-                               regulator-min-microvolt = <800000>;
-                               regulator-max-microvolt = <3950000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       sw3a_reg: sw3a {
-                               regulator-min-microvolt = <400000>;
-                               regulator-max-microvolt = <1975000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       sw3b_reg: sw3b {
-                               regulator-min-microvolt = <400000>;
-                               regulator-max-microvolt = <1975000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       sw4_reg: sw4 {
-                               regulator-min-microvolt = <800000>;
-                               regulator-max-microvolt = <3300000>;
-                       };
-
-                       swbst_reg: swbst {
-                               regulator-min-microvolt = <5000000>;
-                               regulator-max-microvolt = <5150000>;
-                       };
-
-                       snvs_reg: vsnvs {
-                               regulator-min-microvolt = <1000000>;
-                               regulator-max-microvolt = <3000000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       vref_reg: vrefddr {
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       vgen1_reg: vgen1 {
-                               regulator-min-microvolt = <800000>;
-                               regulator-max-microvolt = <1550000>;
-                       };
-
-                       vgen2_reg: vgen2 {
-                               regulator-min-microvolt = <800000>;
-                               regulator-max-microvolt = <1550000>;
-                       };
-
-                       vgen3_reg: vgen3 {
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3300000>;
-                       };
-
-                       vgen4_reg: vgen4 {
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-always-on;
-                       };
-
-                       vgen5_reg: vgen5 {
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-always-on;
-                       };
-
-                       vgen6_reg: vgen6 {
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-always-on;
-                       };
-               };
-       };
-
-       pciswitch: pex8609@3f {
-               compatible = "plx,pex8609";
-               reg = <0x3f>;
-       };
-
-       pciclkgen: si52147@6b {
-               compatible = "sil,si52147";
-               reg = <0x6b>;
-       };
-};
-
-&i2c3 {
-       clock-frequency = <100000>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_i2c3_2>;
-       status = "okay";
-
-       accelerometer: mma8450@1c {
-               compatible = "fsl,mma8450";
-               reg = <0x1c>;
-       };
-
-       codec: sgtl5000@0a {
-               compatible = "fsl,sgtl5000";
-               reg = <0x0a>;
-               clocks = <&clks 169>;
-               VDDA-supply = <&sw4_reg>;
-               VDDIO-supply = <&reg_3p3v>;
-       };
-
-       hdmiin: adv7611@4c {
-               compatible = "adi,adv7611";
-               reg = <0x4c>;
-       };
-
-       touchscreen: egalax_ts@04 {
-               compatible = "eeti,egalax_ts";
-               reg = <0x04>;
-               interrupt-parent = <&gpio7>;
-               interrupts = <12 2>; /* gpio7_12 active low */
-               wakeup-gpios = <&gpio7 12 0>;
-       };
-
-       videoout: adv7393@2a {
-               compatible = "adi,adv7393";
-               reg = <0x2a>;
-       };
-
-       videoin: adv7180@20 {
-               compatible = "adi,adv7180";
-               reg = <0x20>;
-       };
-};
-
-&iomuxc {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_hog>;
-
-       hog {
-               pinctrl_hog: hoggrp {
-                       fsl,pins = <
-                               MX6Q_PAD_EIM_D22__GPIO3_IO22    0x80000000 /* OTG_PWR_EN */
-                               MX6Q_PAD_EIM_D19__GPIO3_IO19    0x80000000 /* SPINOR_CS0# */
-                               MX6Q_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */
-                               MX6Q_PAD_ENET_TXD1__GPIO1_IO29  0x80000000 /* PCIE RST */
-                               MX6Q_PAD_GPIO_0__CCM_CLKO1      0x000130b0 /* AUD4_MCK */
-                               MX6Q_PAD_GPIO_17__GPIO7_IO12    0x80000000 /* TOUCH_IRQ# */
-                               MX6Q_PAD_KEY_COL0__GPIO4_IO06   0x80000000 /* user1 led */
-                               MX6Q_PAD_KEY_COL2__GPIO4_IO10   0x80000000 /* user2 led */
-                               MX6Q_PAD_KEY_ROW4__GPIO4_IO15   0x80000000 /* user3 led */
-                               MX6Q_PAD_SD1_DAT0__GPIO1_IO16   0x80000000 /* USBHUB_RST# */
-                               MX6Q_PAD_SD1_DAT3__GPIO1_IO21   0x80000000 /* MIPI_DIO */
-                        >;
-               };
-       };
-};
-
-&ldb {
-       status = "okay";
-       lvds-channel@0 {
-               crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
-       };
-};
-
-&pcie {
-       reset-gpio = <&gpio1 29 0>;
-       status = "okay";
-
-       eth1: sky2@8 { /* MAC/PHY on bus 8 */
-               compatible = "marvell,sky2";
-               /* Filled in by U-Boot */
-               mac-address = [ 00 00 00 00 00 00 ];
-       };
-};
-
-&ssi1 {
-       fsl,mode = "i2s-slave";
-       status = "okay";
-};
-
-&uart1 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_uart1_2>;
-       status = "okay";
-};
-
-&uart2 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_uart2_3>;
-       status = "okay";
-};
-
-&uart5 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_uart5_1>;
-       status = "okay";
-};
-
-&usbotg {
-       vbus-supply = <&reg_usb_otg_vbus>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_usbotg_1>;
-       disable-over-current;
-       status = "okay";
-};
-
-&usbh1 {
-       vbus-supply = <&reg_usb_h1_vbus>;
-       status = "okay";
-};
-
-&usdhc3 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_usdhc3_2>;
-       cd-gpios = <&gpio7 0 0>;
-       vmmc-supply = <&reg_3p3v>;
-       status = "okay";
-};
diff --git a/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6q-gw54xx.dts b/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6q-gw54xx.dts
deleted file mode 100644 (file)
index abbf1aa..0000000
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright 2013 Gateworks Corporation
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/dts-v1/;
-#include "imx6q.dtsi"
-#include "imx6qdl-gw54xx.dtsi"
-
-/ {
-       model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX";
-       compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
-};
-
-&iomuxc {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_hog>;
-
-       hog {
-               pinctrl_hog: hoggrp {
-                       fsl,pins = <
-                               MX6Q_PAD_EIM_D22__GPIO3_IO22    0x80000000 /* OTG_PWR_EN */
-                               MX6Q_PAD_EIM_D19__GPIO3_IO19    0x80000000 /* SPINOR_CS0# */
-                               MX6Q_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */
-                               MX6Q_PAD_ENET_TXD1__GPIO1_IO29  0x80000000 /* PCIE RST */
-                               MX6Q_PAD_GPIO_0__CCM_CLKO1      0x000130b0 /* AUD4_MCK */
-                               MX6Q_PAD_GPIO_2__GPIO1_IO02     0x80000000 /* CAN_STBY */
-                               MX6Q_PAD_GPIO_17__GPIO7_IO12    0x80000000 /* TOUCH_IRQ# */
-                               MX6Q_PAD_KEY_COL0__GPIO4_IO06   0x80000000 /* user1 led */
-                               MX6Q_PAD_KEY_ROW0__GPIO4_IO07   0x80000000 /* user2 led */
-                               MX6Q_PAD_KEY_ROW4__GPIO4_IO15   0x80000000 /* user3 led */
-                               MX6Q_PAD_SD1_DAT0__GPIO1_IO16   0x80000000 /* USBHUB_RST# */
-                               MX6Q_PAD_SD1_DAT3__GPIO1_IO21   0x80000000 /* MIPI_DIO */
-                        >;
-               };
-       };
-};
-
-&ldb {  
-       status = "okay";
-       lvds-channel@0 {
-               crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
-       };
-};
-
-&sata {
-       status = "okay";
-};
diff --git a/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
deleted file mode 100644 (file)
index 146a337..0000000
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * Copyright 2013 Gateworks Corporation
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/ {
-       /* these are used by bootloader for disabling nodes */
-       aliases {
-               can0 = &can1;
-               ethernet0 = &fec;
-               i2c0 = &i2c1;
-               i2c1 = &i2c2;
-               i2c2 = &i2c3;
-               led0 = &led0;
-               led1 = &led1;
-               nand = &gpmi;
-               usb0 = &usbh1;
-               usb1 = &usbotg;
-       };
-
-       leds {
-               compatible = "gpio-leds";
-
-               led0: user1 {
-                       label = "user1";
-                       gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
-                       default-state = "on";
-                       linux,default-trigger = "heartbeat";
-               };
-
-               led1: user2 {
-                       label = "user2";
-                       gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */
-                       default-state = "off";
-               };
-       };
-
-       memory {
-               reg = <0x10000000 0x20000000>;
-       };
-
-       regulators {
-               compatible = "simple-bus";
-
-               reg_3p3v: 3p3v {
-                       compatible = "regulator-fixed";
-                       regulator-name = "3P3V";
-                       regulator-min-microvolt = <3300000>;
-                       regulator-max-microvolt = <3300000>;
-                       regulator-always-on;
-               };
-
-               reg_5p0v: 5p0v {
-                       compatible = "regulator-fixed";
-                       regulator-name = "5P0V";
-                       regulator-min-microvolt = <5000000>;
-                       regulator-max-microvolt = <5000000>;
-                       regulator-always-on;
-               };
-
-               reg_usb_otg_vbus: usb_otg_vbus {
-                       compatible = "regulator-fixed";
-                       regulator-name = "usb_otg_vbus";
-                       regulator-min-microvolt = <5000000>;
-                       regulator-max-microvolt = <5000000>;
-                       gpio = <&gpio3 22 0>;
-                       enable-active-high;
-               };
-       };
-};
-
-&fec {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_enet_1>;
-       phy-mode = "rgmii";
-       phy-reset-gpios = <&gpio1 30 0>;
-       status = "okay";
-};
-
-&gpmi {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_gpmi_nand_2>;
-       status = "okay";
-};
-
-&i2c1 {
-       clock-frequency = <100000>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_i2c1_1>;
-       status = "okay";
-
-       eeprom1: eeprom@50 {
-               compatible = "atmel,24c02";
-               reg = <0x50>;
-               pagesize = <16>;
-       };
-
-       eeprom2: eeprom@51 {
-               compatible = "atmel,24c02";
-               reg = <0x51>;
-               pagesize = <16>;
-       };
-
-       eeprom3: eeprom@52 {
-               compatible = "atmel,24c02";
-               reg = <0x52>;
-               pagesize = <16>;
-       };
-
-       eeprom4: eeprom@53 {
-               compatible = "atmel,24c02";
-               reg = <0x53>;
-               pagesize = <16>;
-       };
-
-       gpio: pca9555@23 {
-               compatible = "nxp,pca9555";
-               reg = <0x23>;
-               gpio-controller;
-               #gpio-cells = <2>;
-       };
-
-       hwmon: gsc@29 {
-               compatible = "gw,gsp";
-               reg = <0x29>;
-       };
-
-       rtc: ds1672@68 {
-               compatible = "dallas,ds1672";
-               reg = <0x68>;
-       };
-};
-
-&i2c2 {
-       clock-frequency = <100000>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_i2c2_2>;
-       status = "okay";
-
-       pmic: ltc3676@3c {
-               compatible = "ltc,ltc3676";
-               reg = <0x3c>;
-
-               regulators {
-                       sw1_reg: ltc3676__sw1 {
-                               regulator-min-microvolt = <1175000>;
-                               regulator-max-microvolt = <1175000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       sw2_reg: ltc3676__sw2 {
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       sw3_reg: ltc3676__sw3 {
-                               regulator-min-microvolt = <1175000>;
-                               regulator-max-microvolt = <1175000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       sw4_reg: ltc3676__sw4 {
-                               regulator-min-microvolt = <1500000>;
-                               regulator-max-microvolt = <1500000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       ldo2_reg: ltc3676__ldo2 {
-                               regulator-min-microvolt = <2500000>;
-                               regulator-max-microvolt = <2500000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       ldo4_reg: ltc3676__ldo4 {
-                               regulator-min-microvolt = <3000000>;
-                               regulator-max-microvolt = <3000000>;
-                       };
-               };
-       };
-};
-
-&i2c3 {
-       clock-frequency = <100000>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_i2c3_2>;
-       status = "okay";
-
-       videoin: adv7180@20 {
-               compatible = "adi,adv7180";
-               reg = <0x20>;
-       };
-};
-
-&pcie {
-       reset-gpio = <&gpio1 0 0>;
-       status = "okay";
-};
-
-&uart1 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_uart1_2>;
-       status = "okay";
-};
-
-&uart2 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_uart2_3>;
-       status = "okay";
-};
-
-&uart3 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_uart3_3>;
-       status = "okay";
-};
-
-&uart5 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_uart5_1>;
-       status = "okay";
-};
-
-&usbotg {
-       vbus-supply = <&reg_usb_otg_vbus>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_usbotg_1>;
-       disable-over-current;
-       status = "okay";
-};
-
-&usbh1 {
-       status = "okay";
-};
diff --git a/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
deleted file mode 100644 (file)
index 186ed9d..0000000
+++ /dev/null
@@ -1,344 +0,0 @@
-/*
- * Copyright 2013 Gateworks Corporation
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/ {
-       /* these are used by bootloader for disabling nodes */
-       aliases {
-               can0 = &can1;
-               ethernet0 = &fec;
-               i2c0 = &i2c1;
-               i2c1 = &i2c2;
-               i2c2 = &i2c3;
-               led0 = &led0;
-               led1 = &led1;
-               led2 = &led2;
-               nand = &gpmi;
-               ssi0 = &ssi1;
-               usb0 = &usbh1;
-               usb1 = &usbotg;
-               usdhc2 = &usdhc3;
-       };
-
-       leds {
-               compatible = "gpio-leds";
-
-               led0: user1 {
-                       label = "user1";
-                       gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
-                       default-state = "on";
-                       linux,default-trigger = "heartbeat";
-               };
-
-               led1: user2 {
-                       label = "user2";
-                       gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */
-                       default-state = "off";
-               };
-
-               led2: user3 {
-                       label = "user3";
-                       gpios = <&gpio4 15 1>; /* 111 - MX6_LOCLED# */
-                       default-state = "off";
-               };
-       };
-
-       memory {
-               reg = <0x10000000 0x20000000>;
-       };
-
-       regulators {
-               compatible = "simple-bus";
-
-               reg_1p0v: 1p0v {
-                       compatible = "regulator-fixed";
-                       regulator-name = "1P0V";
-                       regulator-min-microvolt = <1000000>;
-                       regulator-max-microvolt = <1000000>;
-                       regulator-always-on;
-               };
-
-               /* remove this fixed regulator once ltc3676__sw2 driver available */
-               reg_1p8v: 1p8v {
-                       compatible = "regulator-fixed";
-                       regulator-name = "1P8V";
-                       regulator-min-microvolt = <1800000>;
-                       regulator-max-microvolt = <1800000>;
-                       regulator-always-on;
-               };
-
-               reg_3p3v: 3p3v {
-                       compatible = "regulator-fixed";
-                       regulator-name = "3P3V";
-                       regulator-min-microvolt = <3300000>;
-                       regulator-max-microvolt = <3300000>;
-                       regulator-always-on;
-               };
-
-               reg_5p0v: 5p0v {
-                       compatible = "regulator-fixed";
-                       regulator-name = "5P0V";
-                       regulator-min-microvolt = <5000000>;
-                       regulator-max-microvolt = <5000000>;
-                       regulator-always-on;
-               };
-
-               reg_usb_otg_vbus: usb_otg_vbus {
-                       compatible = "regulator-fixed";
-                       regulator-name = "usb_otg_vbus";
-                       regulator-min-microvolt = <5000000>;
-                       regulator-max-microvolt = <5000000>;
-                       gpio = <&gpio3 22 0>;
-                       enable-active-high;
-               };
-       };
-
-       sound {
-               compatible = "fsl,imx6q-ventana-sgtl5000",
-                            "fsl,imx-audio-sgtl5000";
-               model = "sgtl5000-audio";
-               ssi-controller = <&ssi1>;
-               audio-codec = <&codec>;
-               audio-routing =
-                       "MIC_IN", "Mic Jack",
-                       "Mic Jack", "Mic Bias",
-                       "Headphone Jack", "HP_OUT";
-               mux-int-port = <1>;
-               mux-ext-port = <4>;
-       };
-};
-
-&audmux {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_audmux_1>;
-       status = "okay";
-};
-
-&can1 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_flexcan1_1>;
-       status = "okay";
-};
-
-&fec {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_enet_1>;
-       phy-mode = "rgmii";
-       phy-reset-gpios = <&gpio1 30 0>;
-       status = "okay";
-};
-
-&gpmi {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_gpmi_nand_2>;
-       status = "okay";
-};
-
-&i2c1 {
-       clock-frequency = <100000>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_i2c1_1>;
-       status = "okay";
-
-       eeprom1: eeprom@50 {
-               compatible = "atmel,24c02";
-               reg = <0x50>;
-               pagesize = <16>;
-       };
-
-       eeprom2: eeprom@51 {
-               compatible = "atmel,24c02";
-               reg = <0x51>;
-               pagesize = <16>;
-       };
-
-       eeprom3: eeprom@52 {
-               compatible = "atmel,24c02";
-               reg = <0x52>;
-               pagesize = <16>;
-       };
-
-       eeprom4: eeprom@53 {
-               compatible = "atmel,24c02";
-               reg = <0x53>;
-               pagesize = <16>;
-       };
-
-       gpio: pca9555@23 {
-               compatible = "nxp,pca9555";
-               reg = <0x23>;
-               gpio-controller;
-               #gpio-cells = <2>;
-       };
-
-       hwmon: gsc@29 {
-               compatible = "gw,gsp";
-               reg = <0x29>;
-       };
-
-       rtc: ds1672@68 {
-               compatible = "dallas,ds1672";
-               reg = <0x68>;
-       };
-};
-
-&i2c2 {
-       clock-frequency = <100000>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_i2c2_2>;
-       status = "okay";
-
-       pciswitch: pex8609@3f {
-               compatible = "plx,pex8609";
-               reg = <0x3f>;
-       };
-
-       pmic: ltc3676@3c {
-               compatible = "ltc,ltc3676";
-               reg = <0x3c>;
-
-               regulators {
-                       sw1_reg: ltc3676__sw1 {
-                               regulator-min-microvolt = <1175000>;
-                               regulator-max-microvolt = <1175000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       sw2_reg: ltc3676__sw2 {
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       sw3_reg: ltc3676__sw3 {
-                               regulator-min-microvolt = <1175000>;
-                               regulator-max-microvolt = <1175000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       sw4_reg: ltc3676__sw4 {
-                               regulator-min-microvolt = <1500000>;
-                               regulator-max-microvolt = <1500000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       ldo2_reg: ltc3676__ldo2 {
-                               regulator-min-microvolt = <2500000>;
-                               regulator-max-microvolt = <2500000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       ldo3_reg: ltc3676__ldo3 {
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       ldo4_reg: ltc3676__ldo4 {
-                               regulator-min-microvolt = <3000000>;
-                               regulator-max-microvolt = <3000000>;
-                       };
-               };
-       };
-};
-
-&i2c3 {
-       clock-frequency = <100000>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_i2c3_2>;
-       status = "okay";
-
-       accelerometer: fxos8700@1e {
-               compatible = "fsl,fxos8700";
-               reg = <0x13>;
-       };
-
-       codec: sgtl5000@0a {
-               compatible = "fsl,sgtl5000";
-               reg = <0x0a>;
-               clocks = <&clks 169>;
-               VDDA-supply = <&reg_1p8v>;
-               VDDIO-supply = <&reg_3p3v>;
-       };
-
-       touchscreen: egalax_ts@04 {
-               compatible = "eeti,egalax_ts";
-               reg = <0x04>;
-               interrupt-parent = <&gpio7>;
-               interrupts = <12 2>; /* gpio7_12 active low */
-               wakeup-gpios = <&gpio7 12 0>;
-       };
-
-       videoin: adv7180@20 {
-               compatible = "adi,adv7180";
-               reg = <0x20>;
-       };
-};
-
-&ldb {
-       status = "okay";
-       lvds-channel@0 {
-               crtcs = <&ipu1 0>, <&ipu1 1>;
-       };
-};
-
-&pcie {
-       reset-gpio = <&gpio1 29 0>;
-       status = "okay";
-};
-
-&ssi1 {
-       fsl,mode = "i2s-slave";
-       status = "okay";
-};
-
-&uart1 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_uart1_2>;
-       status = "okay";
-};
-
-&uart2 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_uart2_3>;
-       status = "okay";
-};
-
-&uart5 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_uart5_1>;
-       status = "okay";
-};
-
-&usbotg {
-       vbus-supply = <&reg_usb_otg_vbus>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_usbotg_1>;
-       disable-over-current;
-       status = "okay";
-};
-
-&usbh1 {
-       status = "okay";
-};
-
-&usdhc3 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_usdhc3_2>;
-       cd-gpios = <&gpio7 0 0>;
-       vmmc-supply = <&reg_3p3v>;
-       status = "okay";
-};
diff --git a/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
deleted file mode 100644 (file)
index e7ae350..0000000
+++ /dev/null
@@ -1,367 +0,0 @@
-/*
- * Copyright 2013 Gateworks Corporation
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/ {
-       /* these are used by bootloader for disabling nodes */
-       aliases {
-               can0 = &can1;
-               ethernet0 = &fec;
-               ethernet1 = &eth1;
-               i2c0 = &i2c1;
-               i2c1 = &i2c2;
-               i2c2 = &i2c3;
-               led0 = &led0;
-               led1 = &led1;
-               led2 = &led2;
-               nand = &gpmi;
-               sky2 = &eth1;
-               ssi0 = &ssi1;
-               usb0 = &usbh1;
-               usb1 = &usbotg;
-               usdhc2 = &usdhc3;
-       };
-
-       chosen {
-               bootargs = "console=ttymxc1,115200";
-       };
-
-       leds {
-               compatible = "gpio-leds";
-
-               led0: user1 {
-                       label = "user1";
-                       gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
-                       default-state = "on";
-                       linux,default-trigger = "heartbeat";
-               };
-
-               led1: user2 {
-                       label = "user2";
-                       gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */
-                       default-state = "off";
-               };
-
-               led2: user3 {
-                       label = "user3";
-                       gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */
-                       default-state = "off";
-               };
-       };
-
-       memory {
-               reg = <0x10000000 0x40000000>;
-       };
-
-       regulators {
-               compatible = "simple-bus";
-
-               reg_1p0v: 1p0v {
-                       compatible = "regulator-fixed";
-                       regulator-name = "1P0V";
-                       regulator-min-microvolt = <1000000>;
-                       regulator-max-microvolt = <1000000>;
-                       regulator-always-on;
-               };
-
-               /* remove this fixed regulator once ltc3676__sw2 driver available */
-               reg_1p8v: 1p8v {
-                       compatible = "regulator-fixed";
-                       regulator-name = "1P8V";
-                       regulator-min-microvolt = <1800000>;
-                       regulator-max-microvolt = <1800000>;
-                       regulator-always-on;
-               };
-
-               reg_3p3v: 3p3v {
-                       compatible = "regulator-fixed";
-                       regulator-name = "3P3V";
-                       regulator-min-microvolt = <3300000>;
-                       regulator-max-microvolt = <3300000>;
-                       regulator-always-on;
-               };
-
-               reg_usb_h1_vbus: usb_h1_vbus {
-                       compatible = "regulator-fixed";
-                       regulator-name = "usb_h1_vbus";
-                       regulator-min-microvolt = <5000000>;
-                       regulator-max-microvolt = <5000000>;
-                       regulator-always-on;
-               };
-
-               reg_usb_otg_vbus: usb_otg_vbus {
-                       compatible = "regulator-fixed";
-                       regulator-name = "usb_otg_vbus";
-                       regulator-min-microvolt = <5000000>;
-                       regulator-max-microvolt = <5000000>;
-                       gpio = <&gpio3 22 0>;
-                       enable-active-high;
-               };
-       };
-
-       sound {
-               compatible = "fsl,imx6q-ventana-sgtl5000",
-                            "fsl,imx-audio-sgtl5000";
-               model = "sgtl5000-audio";
-               ssi-controller = <&ssi1>;
-               audio-codec = <&codec>;
-               audio-routing =
-                       "MIC_IN", "Mic Jack",
-                       "Mic Jack", "Mic Bias",
-                       "Headphone Jack", "HP_OUT";
-               mux-int-port = <1>;
-               mux-ext-port = <4>;
-       };
-};
-
-&audmux {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_audmux_1>;
-       status = "okay";
-};
-
-&can1 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_flexcan1_1>;
-       status = "okay";
-};
-
-&fec {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_enet_1>;
-       phy-mode = "rgmii";
-       phy-reset-gpios = <&gpio1 30 0>;
-       status = "okay";
-};
-
-&gpmi {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_gpmi_nand_2>;
-       status = "okay";
-};
-
-&i2c1 {
-       clock-frequency = <100000>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_i2c1_1>;
-       status = "okay";
-
-       eeprom1: eeprom@50 {
-               compatible = "atmel,24c02";
-               reg = <0x50>;
-               pagesize = <16>;
-       };
-
-       eeprom2: eeprom@51 {
-               compatible = "atmel,24c02";
-               reg = <0x51>;
-               pagesize = <16>;
-       };
-
-       eeprom3: eeprom@52 {
-               compatible = "atmel,24c02";
-               reg = <0x52>;
-               pagesize = <16>;
-       };
-
-       eeprom4: eeprom@53 {
-               compatible = "atmel,24c02";
-               reg = <0x53>;
-               pagesize = <16>;
-       };
-
-       gpio: pca9555@23 {
-               compatible = "nxp,pca9555";
-               reg = <0x23>;
-               gpio-controller;
-               #gpio-cells = <2>;
-       };
-
-       hwmon: gsc@29 {
-               compatible = "gw,gsp";
-               reg = <0x29>;
-       };
-
-       rtc: ds1672@68 {
-               compatible = "dallas,ds1672";
-               reg = <0x68>;
-       };
-};
-
-&i2c2 {
-       clock-frequency = <100000>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_i2c2_2>;
-       status = "okay";
-
-       pciswitch: pex8609@3f {
-               compatible = "plx,pex8609";
-               reg = <0x3f>;
-       };
-
-       pmic: ltc3676@3c {
-               compatible = "ltc,ltc3676";
-               reg = <0x3c>;
-
-               regulators {
-                       sw1_reg: ltc3676__sw1 {
-                               regulator-min-microvolt = <1175000>;
-                               regulator-max-microvolt = <1175000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       sw2_reg: ltc3676__sw2 {
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       sw3_reg: ltc3676__sw3 {
-                               regulator-min-microvolt = <1175000>;
-                               regulator-max-microvolt = <1175000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       sw4_reg: ltc3676__sw4 {
-                               regulator-min-microvolt = <1500000>;
-                               regulator-max-microvolt = <1500000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       ldo2_reg: ltc3676__ldo2 {
-                               regulator-min-microvolt = <2500000>;
-                               regulator-max-microvolt = <2500000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       ldo3_reg: ltc3676__ldo3 {
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <1800000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       ldo4_reg: ltc3676__ldo4 {
-                               regulator-min-microvolt = <3000000>;
-                               regulator-max-microvolt = <3000000>;
-                       };
-               };
-       };
-};
-
-&i2c3 {
-       clock-frequency = <100000>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_i2c3_2>;
-       status = "okay";
-
-       accelerometer: fxos8700@1e {
-               compatible = "fsl,fxos8700";
-               reg = <0x1e>;
-       };
-
-       codec: sgtl5000@0a {
-               compatible = "fsl,sgtl5000";
-               reg = <0x0a>;
-               clocks = <&clks 169>;
-               VDDA-supply = <&reg_1p8v>;
-               VDDIO-supply = <&reg_3p3v>;
-       };
-
-       hdmiin: adv7611@4c {
-               compatible = "adi,adv7611";
-               reg = <0x4c>;
-       };
-
-       touchscreen: egalax_ts@04 {
-               compatible = "eeti,egalax_ts";
-               reg = <0x04>;
-               interrupt-parent = <&gpio7>;
-               interrupts = <12 2>; /* gpio7_12 active low */
-               wakeup-gpios = <&gpio7 12 0>;
-       };
-
-       videoout: adv7393@2a {
-               compatible = "adi,adv7393";
-               reg = <0x2a>;
-       };
-
-       videoin: adv7180@20 {
-               compatible = "adi,adv7180";
-               reg = <0x20>;
-       };
-};
-
-&ldb {
-       status = "okay";
-       lvds-channel@0 {
-               crtcs = <&ipu1 0>, <&ipu1 1>;
-       };
-};
-
-&pcie {
-       reset-gpio = <&gpio1 29 0>;
-       status = "okay";
-
-       eth1: sky2@8 { /* MAC/PHY on bus 8 */
-               compatible = "marvell,sky2";
-               /* Filled in by U-Boot */
-               mac-address = [ 00 00 00 00 00 00 ];
-       };
-};
-
-&ssi1 {
-       fsl,mode = "i2s-slave";
-       status = "okay";
-};
-
-&uart1 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_uart1_2>;
-       status = "okay";
-};
-
-&uart2 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_uart2_3>;
-       status = "okay";
-};
-
-&uart5 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_uart5_1>;
-       status = "okay";
-};
-
-&usbotg {
-       vbus-supply = <&reg_usb_otg_vbus>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_usbotg_1>;
-       disable-over-current;
-       status = "okay";
-};
-
-&usbh1 {
-       vbus-supply = <&reg_usb_h1_vbus>;
-       status = "okay";
-};
-
-&usdhc3 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_usdhc3_2>;
-       cd-gpios = <&gpio7 0 0>;
-       vmmc-supply = <&reg_3p3v>;
-       status = "okay";
-};
diff --git a/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
deleted file mode 100644 (file)
index 6f66caa..0000000
+++ /dev/null
@@ -1,408 +0,0 @@
-/*
- * Copyright 2013 Gateworks Corporation
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/ {
-       /* these are used by bootloader for disabling nodes */
-       aliases {
-               can0 = &can1;
-               ethernet0 = &fec;
-               ethernet1 = &eth1;
-               i2c0 = &i2c1;
-               i2c1 = &i2c2;
-               i2c2 = &i2c3;
-               led0 = &led0;
-               led1 = &led1;
-               led2 = &led2;
-               nand = &gpmi;
-               sky2 = &eth1;
-               ssi0 = &ssi1;
-               usb0 = &usbh1;
-               usb1 = &usbotg;
-               usdhc2 = &usdhc3;
-       };
-
-       chosen {
-               bootargs = "console=ttymxc1,115200";
-       };
-
-       leds {
-               compatible = "gpio-leds";
-
-               led0: user1 {
-                       label = "user1";
-                       gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
-                       default-state = "on";
-                       linux,default-trigger = "heartbeat";
-               };
-
-               led1: user2 {
-                       label = "user2";
-                       gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */
-                       default-state = "off";
-               };
-
-               led2: user3 {
-                       label = "user3";
-                       gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */
-                       default-state = "off";
-               };
-       };
-
-       memory {
-               reg = <0x10000000 0x40000000>;
-       };
-
-       regulators {
-               compatible = "simple-bus";
-
-               reg_1p0v: 1p0v {
-                       compatible = "regulator-fixed";
-                       regulator-name = "1P0V";
-                       regulator-min-microvolt = <1000000>;
-                       regulator-max-microvolt = <1000000>;
-                       regulator-always-on;
-               };
-
-               reg_3p3v: 3p3v {
-                       compatible = "regulator-fixed";
-                       regulator-name = "3P3V";
-                       regulator-min-microvolt = <3300000>;
-                       regulator-max-microvolt = <3300000>;
-                       regulator-always-on;
-               };
-
-               reg_usb_h1_vbus: usb_h1_vbus {
-                       compatible = "regulator-fixed";
-                       regulator-name = "usb_h1_vbus";
-                       regulator-min-microvolt = <5000000>;
-                       regulator-max-microvolt = <5000000>;
-                       regulator-always-on;
-               };
-
-               reg_usb_otg_vbus: usb_otg_vbus {
-                       compatible = "regulator-fixed";
-                       regulator-name = "usb_otg_vbus";
-                       regulator-min-microvolt = <5000000>;
-                       regulator-max-microvolt = <5000000>;
-                       gpio = <&gpio3 22 0>;
-                       enable-active-high;
-               };
-       };
-
-       sound {
-               compatible = "fsl,imx6q-ventana-sgtl5000",
-                            "fsl,imx-audio-sgtl5000";
-               model = "sgtl5000-audio";
-               ssi-controller = <&ssi1>;
-               audio-codec = <&codec>;
-               audio-routing =
-                       "MIC_IN", "Mic Jack",
-                       "Mic Jack", "Mic Bias",
-                       "Headphone Jack", "HP_OUT";
-               mux-int-port = <1>;
-               mux-ext-port = <4>;
-       };
-};
-
-&audmux {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_audmux_1>;
-       status = "okay";
-};
-
-&can1 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_flexcan1_1>;
-       status = "okay";
-};
-
-&fec {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_enet_1>;
-       phy-mode = "rgmii";
-       phy-reset-gpios = <&gpio1 30 0>;
-       status = "okay";
-};
-
-&gpmi {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_gpmi_nand_2>;
-       status = "okay";
-};
-
-&i2c1 {
-       clock-frequency = <100000>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_i2c1_1>;
-       status = "okay";
-
-       eeprom1: eeprom@50 {
-               compatible = "atmel,24c02";
-               reg = <0x50>;
-               pagesize = <16>;
-       };
-
-       eeprom2: eeprom@51 {
-               compatible = "atmel,24c02";
-               reg = <0x51>;
-               pagesize = <16>;
-       };
-
-       eeprom3: eeprom@52 {
-               compatible = "atmel,24c02";
-               reg = <0x52>;
-               pagesize = <16>;
-       };
-
-       eeprom4: eeprom@53 {
-               compatible = "atmel,24c02";
-               reg = <0x53>;
-               pagesize = <16>;
-       };
-
-       gpio: pca9555@23 {
-               compatible = "nxp,pca9555";
-               reg = <0x23>;
-               gpio-controller;
-               #gpio-cells = <2>;
-       };
-
-       hwmon: gsc@29 {
-               compatible = "gw,gsp";
-               reg = <0x29>;
-       };
-
-       rtc: ds1672@68 {
-               compatible = "dallas,ds1672";
-               reg = <0x68>;
-       };
-};
-
-&i2c2 {
-       clock-frequency = <100000>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_i2c2_2>;
-       status = "okay";
-
-       pmic: pfuze100@08 {
-               compatible = "fsl,pfuze100";
-               reg = <0x08>;
-
-               regulators {
-                       sw1a_reg: sw1ab {
-                               regulator-min-microvolt = <300000>;
-                               regulator-max-microvolt = <1875000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                               regulator-ramp-delay = <6250>;
-                       };
-
-                       sw1c_reg: sw1c {
-                               regulator-min-microvolt = <300000>;
-                               regulator-max-microvolt = <1875000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                               regulator-ramp-delay = <6250>;
-                       };
-
-                       sw2_reg: sw2 {
-                               regulator-min-microvolt = <800000>;
-                               regulator-max-microvolt = <3950000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       sw3a_reg: sw3a {
-                               regulator-min-microvolt = <400000>;
-                               regulator-max-microvolt = <1975000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       sw3b_reg: sw3b {
-                               regulator-min-microvolt = <400000>;
-                               regulator-max-microvolt = <1975000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       sw4_reg: sw4 {
-                               regulator-min-microvolt = <800000>;
-                               regulator-max-microvolt = <3300000>;
-                       };
-
-                       swbst_reg: swbst {
-                               regulator-min-microvolt = <5000000>;
-                               regulator-max-microvolt = <5150000>;
-                       };
-
-                       snvs_reg: vsnvs {
-                               regulator-min-microvolt = <1000000>;
-                               regulator-max-microvolt = <3000000>;
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       vref_reg: vrefddr {
-                               regulator-boot-on;
-                               regulator-always-on;
-                       };
-
-                       vgen1_reg: vgen1 {
-                               regulator-min-microvolt = <800000>;
-                               regulator-max-microvolt = <1550000>;
-                       };
-
-                       vgen2_reg: vgen2 {
-                               regulator-min-microvolt = <800000>;
-                               regulator-max-microvolt = <1550000>;
-                       };
-
-                       vgen3_reg: vgen3 {
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3300000>;
-                       };
-
-                       vgen4_reg: vgen4 {
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-always-on;
-                       };
-
-                       vgen5_reg: vgen5 {
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-always-on;
-                       };
-
-                       vgen6_reg: vgen6 {
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3300000>;
-                               regulator-always-on;
-                       };
-               };
-       };
-
-       pciswitch: pex8609@3f {
-               compatible = "plx,pex8609";
-               reg = <0x3f>;
-       };
-
-       pciclkgen: si52147@6b {
-               compatible = "sil,si52147";
-               reg = <0x6b>;
-       };
-};
-
-&i2c3 {
-       clock-frequency = <100000>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_i2c3_2>;
-       status = "okay";
-
-       accelerometer: fxos8700@1e {
-               compatible = "fsl,fxos8700";
-               reg = <0x1e>;
-       };
-
-       codec: sgtl5000@0a {
-               compatible = "fsl,sgtl5000";
-               reg = <0x0a>;
-               clocks = <&clks 169>;
-               VDDA-supply = <&sw4_reg>;
-               VDDIO-supply = <&reg_3p3v>;
-       };
-
-       hdmiin: adv7611@4c {
-               compatible = "adi,adv7611";
-               reg = <0x4c>;
-       };
-
-       touchscreen: egalax_ts@04 {
-               compatible = "eeti,egalax_ts";
-               reg = <0x04>;
-               interrupt-parent = <&gpio7>;
-               interrupts = <12 2>; /* gpio7_12 active low */
-               wakeup-gpios = <&gpio7 12 0>;
-       };
-
-       videoout: adv7393@2a {
-               compatible = "adi,adv7393";
-               reg = <0x2a>;
-       };
-
-       videoin: adv7180@20 {
-               compatible = "adi,adv7180";
-               reg = <0x20>;
-       };
-};
-
-&ldb {
-       status = "okay";
-       lvds-channel@0 {
-               crtcs = <&ipu1 0>, <&ipu1 1>;
-       };
-};
-
-&pcie {
-       reset-gpio = <&gpio1 29 0>;
-       status = "okay";
-
-       eth1: sky2@8 { /* MAC/PHY on bus 8 */
-               compatible = "marvell,sky2";
-               /* Filled in by U-Boot */
-               mac-address = [ 00 00 00 00 00 00 ];
-       };
-};
-
-&ssi1 {
-       fsl,mode = "i2s-slave";
-       status = "okay";
-};
-
-&uart1 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_uart1_2>;
-       status = "okay";
-};
-
-&uart2 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_uart2_3>;
-       status = "okay";
-};
-
-&uart5 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_uart5_1>;
-       status = "okay";
-};
-
-&usbotg {
-       vbus-supply = <&reg_usb_otg_vbus>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_usbotg_1>;
-       disable-over-current;
-       status = "okay";
-};
-
-&usbh1 {
-       vbus-supply = <&reg_usb_h1_vbus>;
-       status = "okay";
-};
-
-&usdhc3 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_usdhc3_2>;
-       cd-gpios = <&gpio7 0 0>;
-       vmmc-supply = <&reg_3p3v>;
-       status = "okay";
-};
diff --git a/target/linux/imx6/files-3.10/drivers/pci/host/pcie-designware.c b/target/linux/imx6/files-3.10/drivers/pci/host/pcie-designware.c
deleted file mode 100644 (file)
index c10e9ac..0000000
+++ /dev/null
@@ -1,565 +0,0 @@
-/*
- * Synopsys Designware PCIe host controller driver
- *
- * Copyright (C) 2013 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * Author: Jingoo Han <jg1.han@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/of_address.h>
-#include <linux/pci.h>
-#include <linux/pci_regs.h>
-#include <linux/types.h>
-
-#include "pcie-designware.h"
-
-/* Synopsis specific PCIE configuration registers */
-#define PCIE_PORT_LINK_CONTROL         0x710
-#define PORT_LINK_MODE_MASK            (0x3f << 16)
-#define PORT_LINK_MODE_1_LANES         (0x1 << 16)
-#define PORT_LINK_MODE_2_LANES         (0x3 << 16)
-#define PORT_LINK_MODE_4_LANES         (0x7 << 16)
-
-#define PCIE_LINK_WIDTH_SPEED_CONTROL  0x80C
-#define PORT_LOGIC_SPEED_CHANGE                (0x1 << 17)
-#define PORT_LOGIC_LINK_WIDTH_MASK     (0x1ff << 8)
-#define PORT_LOGIC_LINK_WIDTH_1_LANES  (0x1 << 8)
-#define PORT_LOGIC_LINK_WIDTH_2_LANES  (0x2 << 8)
-#define PORT_LOGIC_LINK_WIDTH_4_LANES  (0x4 << 8)
-
-#define PCIE_MSI_ADDR_LO               0x820
-#define PCIE_MSI_ADDR_HI               0x824
-#define PCIE_MSI_INTR0_ENABLE          0x828
-#define PCIE_MSI_INTR0_MASK            0x82C
-#define PCIE_MSI_INTR0_STATUS          0x830
-
-#define PCIE_ATU_VIEWPORT              0x900
-#define PCIE_ATU_REGION_INBOUND                (0x1 << 31)
-#define PCIE_ATU_REGION_OUTBOUND       (0x0 << 31)
-#define PCIE_ATU_REGION_INDEX1         (0x1 << 0)
-#define PCIE_ATU_REGION_INDEX0         (0x0 << 0)
-#define PCIE_ATU_CR1                   0x904
-#define PCIE_ATU_TYPE_MEM              (0x0 << 0)
-#define PCIE_ATU_TYPE_IO               (0x2 << 0)
-#define PCIE_ATU_TYPE_CFG0             (0x4 << 0)
-#define PCIE_ATU_TYPE_CFG1             (0x5 << 0)
-#define PCIE_ATU_CR2                   0x908
-#define PCIE_ATU_ENABLE                        (0x1 << 31)
-#define PCIE_ATU_BAR_MODE_ENABLE       (0x1 << 30)
-#define PCIE_ATU_LOWER_BASE            0x90C
-#define PCIE_ATU_UPPER_BASE            0x910
-#define PCIE_ATU_LIMIT                 0x914
-#define PCIE_ATU_LOWER_TARGET          0x918
-#define PCIE_ATU_BUS(x)                        (((x) & 0xff) << 24)
-#define PCIE_ATU_DEV(x)                        (((x) & 0x1f) << 19)
-#define PCIE_ATU_FUNC(x)               (((x) & 0x7) << 16)
-#define PCIE_ATU_UPPER_TARGET          0x91C
-
-static struct hw_pci dw_pci;
-
-unsigned long global_io_offset;
-
-static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
-{
-       return sys->private_data;
-}
-
-int cfg_read(void __iomem *addr, int where, int size, u32 *val)
-{
-       *val = readl(addr);
-
-       if (size == 1)
-               *val = (*val >> (8 * (where & 3))) & 0xff;
-       else if (size == 2)
-               *val = (*val >> (8 * (where & 3))) & 0xffff;
-       else if (size != 4)
-               return PCIBIOS_BAD_REGISTER_NUMBER;
-
-       return PCIBIOS_SUCCESSFUL;
-}
-
-int cfg_write(void __iomem *addr, int where, int size, u32 val)
-{
-       if (size == 4)
-               writel(val, addr);
-       else if (size == 2)
-               writew(val, addr + (where & 2));
-       else if (size == 1)
-               writeb(val, addr + (where & 3));
-       else
-               return PCIBIOS_BAD_REGISTER_NUMBER;
-
-       return PCIBIOS_SUCCESSFUL;
-}
-
-static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
-{
-       if (pp->ops->readl_rc)
-               pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
-       else
-               *val = readl(pp->dbi_base + reg);
-}
-
-static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
-{
-       if (pp->ops->writel_rc)
-               pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
-       else
-               writel(val, pp->dbi_base + reg);
-}
-
-int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
-                               u32 *val)
-{
-       int ret;
-
-       if (pp->ops->rd_own_conf)
-               ret = pp->ops->rd_own_conf(pp, where, size, val);
-       else
-               ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
-
-       return ret;
-}
-
-int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
-                               u32 val)
-{
-       int ret;
-
-       if (pp->ops->wr_own_conf)
-               ret = pp->ops->wr_own_conf(pp, where, size, val);
-       else
-               ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size,
-                               val);
-
-       return ret;
-}
-
-int dw_pcie_link_up(struct pcie_port *pp)
-{
-       if (pp->ops->link_up)
-               return pp->ops->link_up(pp);
-       else
-               return 0;
-}
-
-int __init dw_pcie_host_init(struct pcie_port *pp)
-{
-       struct device_node *np = pp->dev->of_node;
-       struct of_pci_range range;
-       struct of_pci_range_parser parser;
-       u32 val;
-
-       if (of_pci_range_parser_init(&parser, np)) {
-               dev_err(pp->dev, "missing ranges property\n");
-               return -EINVAL;
-       }
-
-       /* Get the I/O and memory ranges from DT */
-       for_each_of_pci_range(&parser, &range) {
-               unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
-               if (restype == IORESOURCE_IO) {
-                       of_pci_range_to_resource(&range, np, &pp->io);
-                       pp->io.name = "I/O";
-                       pp->io.start = max_t(resource_size_t,
-                                            PCIBIOS_MIN_IO,
-                                            range.pci_addr + global_io_offset);
-                       pp->io.end = min_t(resource_size_t,
-                                          IO_SPACE_LIMIT,
-                                          range.pci_addr + range.size
-                                          + global_io_offset);
-                       pp->config.io_size = resource_size(&pp->io);
-                       pp->config.io_bus_addr = range.pci_addr;
-               }
-               if (restype == IORESOURCE_MEM) {
-                       of_pci_range_to_resource(&range, np, &pp->mem);
-                       pp->mem.name = "MEM";
-                       pp->config.mem_size = resource_size(&pp->mem);
-                       pp->config.mem_bus_addr = range.pci_addr;
-               }
-               if (restype == 0) {
-                       of_pci_range_to_resource(&range, np, &pp->cfg);
-                       pp->config.cfg0_size = resource_size(&pp->cfg)/2;
-                       pp->config.cfg1_size = resource_size(&pp->cfg)/2;
-               }
-       }
-
-       if (!pp->dbi_base) {
-               pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
-                                       resource_size(&pp->cfg));
-               if (!pp->dbi_base) {
-                       dev_err(pp->dev, "error with ioremap\n");
-                       return -ENOMEM;
-               }
-       }
-
-       pp->cfg0_base = pp->cfg.start;
-       pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
-       pp->io_base = pp->io.start;
-       pp->mem_base = pp->mem.start;
-
-       pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
-                                       pp->config.cfg0_size);
-       if (!pp->va_cfg0_base) {
-               dev_err(pp->dev, "error with ioremap in function\n");
-               return -ENOMEM;
-       }
-       pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
-                                       pp->config.cfg1_size);
-       if (!pp->va_cfg1_base) {
-               dev_err(pp->dev, "error with ioremap\n");
-               return -ENOMEM;
-       }
-
-       if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
-               dev_err(pp->dev, "Failed to parse the number of lanes\n");
-               return -EINVAL;
-       }
-
-       if (pp->ops->host_init)
-               pp->ops->host_init(pp);
-
-       dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
-
-       /* program correct class for RC */
-       dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
-
-       dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
-       val |= PORT_LOGIC_SPEED_CHANGE;
-       dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
-
-       dw_pci.nr_controllers = 1;
-       dw_pci.private_data = (void **)&pp;
-
-       pci_common_init(&dw_pci);
-       pci_assign_unassigned_resources();
-#ifdef CONFIG_PCI_DOMAINS
-       dw_pci.domain++;
-#endif
-
-       return 0;
-}
-
-static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
-{
-       /* Program viewport 0 : OUTBOUND : CFG0 */
-       dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
-                         PCIE_ATU_VIEWPORT);
-       dw_pcie_writel_rc(pp, pp->cfg0_base, PCIE_ATU_LOWER_BASE);
-       dw_pcie_writel_rc(pp, (pp->cfg0_base >> 32), PCIE_ATU_UPPER_BASE);
-       dw_pcie_writel_rc(pp, pp->cfg0_base + pp->config.cfg0_size - 1,
-                         PCIE_ATU_LIMIT);
-       dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
-       dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
-       dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1);
-       dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
-}
-
-static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
-{
-       /* Program viewport 1 : OUTBOUND : CFG1 */
-       dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
-                         PCIE_ATU_VIEWPORT);
-       dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
-       dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
-       dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
-       dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
-       dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
-                         PCIE_ATU_LIMIT);
-       dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
-       dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
-}
-
-static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
-{
-       /* Program viewport 0 : OUTBOUND : MEM */
-       dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
-                         PCIE_ATU_VIEWPORT);
-       dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
-       dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
-       dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
-       dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
-       dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
-                         PCIE_ATU_LIMIT);
-       dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
-       dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
-                         PCIE_ATU_UPPER_TARGET);
-}
-
-static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
-{
-       /* Program viewport 1 : OUTBOUND : IO */
-       dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
-                         PCIE_ATU_VIEWPORT);
-       dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
-       dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
-       dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
-       dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
-       dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,
-                         PCIE_ATU_LIMIT);
-       dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
-       dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
-                         PCIE_ATU_UPPER_TARGET);
-}
-
-static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
-               u32 devfn, int where, int size, u32 *val)
-{
-       int ret = PCIBIOS_SUCCESSFUL;
-       u32 address, busdev;
-
-       busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
-                PCIE_ATU_FUNC(PCI_FUNC(devfn));
-       address = where & ~0x3;
-
-       if (bus->parent->number == pp->root_bus_nr) {
-               dw_pcie_prog_viewport_cfg0(pp, busdev);
-               ret = cfg_read(pp->va_cfg0_base + address, where, size, val);
-               dw_pcie_prog_viewport_mem_outbound(pp);
-       } else {
-               dw_pcie_prog_viewport_cfg1(pp, busdev);
-               ret = cfg_read(pp->va_cfg1_base + address, where, size, val);
-               dw_pcie_prog_viewport_io_outbound(pp);
-       }
-
-       return ret;
-}
-
-static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
-               u32 devfn, int where, int size, u32 val)
-{
-       int ret = PCIBIOS_SUCCESSFUL;
-       u32 address, busdev;
-
-       busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
-                PCIE_ATU_FUNC(PCI_FUNC(devfn));
-       address = where & ~0x3;
-
-       if (bus->parent->number == pp->root_bus_nr) {
-               dw_pcie_prog_viewport_cfg0(pp, busdev);
-               ret = cfg_write(pp->va_cfg0_base + address, where, size, val);
-               dw_pcie_prog_viewport_mem_outbound(pp);
-       } else {
-               dw_pcie_prog_viewport_cfg1(pp, busdev);
-               ret = cfg_write(pp->va_cfg1_base + address, where, size, val);
-               dw_pcie_prog_viewport_io_outbound(pp);
-       }
-
-       return ret;
-}
-
-
-static int dw_pcie_valid_config(struct pcie_port *pp,
-                               struct pci_bus *bus, int dev)
-{
-       /* If there is no link, then there is no device */
-       if (bus->number != pp->root_bus_nr) {
-               if (!dw_pcie_link_up(pp))
-                       return 0;
-       }
-
-       /* access only one slot on each root port */
-       if (bus->number == pp->root_bus_nr && dev > 0)
-               return 0;
-
-       /*
-        * do not read more than one device on the bus directly attached
-        * to RC's (Virtual Bridge's) DS side.
-        */
-       if (bus->primary == pp->root_bus_nr && dev > 0)
-               return 0;
-
-       return 1;
-}
-
-static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
-                       int size, u32 *val)
-{
-       struct pcie_port *pp = sys_to_pcie(bus->sysdata);
-       unsigned long flags;
-       int ret;
-
-       if (!pp) {
-               BUG();
-               return -EINVAL;
-       }
-
-       if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
-               *val = 0xffffffff;
-               return PCIBIOS_DEVICE_NOT_FOUND;
-       }
-
-       spin_lock_irqsave(&pp->conf_lock, flags);
-       if (bus->number != pp->root_bus_nr)
-               ret = dw_pcie_rd_other_conf(pp, bus, devfn,
-                                               where, size, val);
-       else
-               ret = dw_pcie_rd_own_conf(pp, where, size, val);
-       spin_unlock_irqrestore(&pp->conf_lock, flags);
-
-       return ret;
-}
-
-static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
-                       int where, int size, u32 val)
-{
-       struct pcie_port *pp = sys_to_pcie(bus->sysdata);
-       unsigned long flags;
-       int ret;
-
-       if (!pp) {
-               BUG();
-               return -EINVAL;
-       }
-
-       if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
-               return PCIBIOS_DEVICE_NOT_FOUND;
-
-       spin_lock_irqsave(&pp->conf_lock, flags);
-       if (bus->number != pp->root_bus_nr)
-               ret = dw_pcie_wr_other_conf(pp, bus, devfn,
-                                               where, size, val);
-       else
-               ret = dw_pcie_wr_own_conf(pp, where, size, val);
-       spin_unlock_irqrestore(&pp->conf_lock, flags);
-
-       return ret;
-}
-
-static struct pci_ops dw_pcie_ops = {
-       .read = dw_pcie_rd_conf,
-       .write = dw_pcie_wr_conf,
-};
-
-int dw_pcie_setup(int nr, struct pci_sys_data *sys)
-{
-       struct pcie_port *pp;
-
-       pp = sys_to_pcie(sys);
-
-       if (!pp)
-               return 0;
-
-       if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
-               sys->io_offset = global_io_offset - pp->config.io_bus_addr;
-               pci_ioremap_io(sys->io_offset, pp->io.start);
-               global_io_offset += SZ_64K;
-               pci_add_resource_offset(&sys->resources, &pp->io,
-                                       sys->io_offset);
-       }
-
-       sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr;
-       pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
-
-       return 1;
-}
-
-struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
-{
-       struct pci_bus *bus;
-       struct pcie_port *pp = sys_to_pcie(sys);
-
-       if (pp) {
-               pp->root_bus_nr = sys->busnr;
-               bus = pci_scan_root_bus(NULL, sys->busnr, &dw_pcie_ops,
-                                       sys, &sys->resources);
-       } else {
-               bus = NULL;
-               BUG();
-       }
-
-       return bus;
-}
-
-int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-       struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
-
-       return pp->irq;
-}
-
-static struct hw_pci dw_pci = {
-       .setup          = dw_pcie_setup,
-       .scan           = dw_pcie_scan_bus,
-       .map_irq        = dw_pcie_map_irq,
-};
-
-void dw_pcie_setup_rc(struct pcie_port *pp)
-{
-       struct pcie_port_info *config = &pp->config;
-       u32 val;
-       u32 membase;
-       u32 memlimit;
-
-       /* set the number of lines as 4 */
-       dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
-       val &= ~PORT_LINK_MODE_MASK;
-       switch (pp->lanes) {
-       case 1:
-               val |= PORT_LINK_MODE_1_LANES;
-               break;
-       case 2:
-               val |= PORT_LINK_MODE_2_LANES;
-               break;
-       case 4:
-               val |= PORT_LINK_MODE_4_LANES;
-               break;
-       }
-       dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
-
-       /* set link width speed control register */
-       dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
-       val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
-       switch (pp->lanes) {
-       case 1:
-               val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
-               break;
-       case 2:
-               val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
-               break;
-       case 4:
-               val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
-               break;
-       }
-       dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
-
-       /* setup RC BARs */
-       dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
-       dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_1);
-
-       /* setup interrupt pins */
-       dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
-       val &= 0xffff00ff;
-       val |= 0x00000100;
-       dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
-
-       /* setup bus numbers */
-       dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
-       val &= 0xff000000;
-       val |= 0x00010100;
-       dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
-
-       /* setup memory base, memory limit */
-       membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
-       memlimit = (config->mem_size + (u32)pp->mem_base) & 0xfff00000;
-       val = memlimit | membase;
-       dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
-
-       /* setup command register */
-       dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
-       val &= 0xffff0000;
-       val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
-               PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
-       dw_pcie_writel_rc(pp, val, PCI_COMMAND);
-}
-
-MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
-MODULE_DESCRIPTION("Designware PCIe host controller driver");
-MODULE_LICENSE("GPL v2");
diff --git a/target/linux/imx6/files-3.10/drivers/pci/host/pcie-designware.h b/target/linux/imx6/files-3.10/drivers/pci/host/pcie-designware.h
deleted file mode 100644 (file)
index 133820f..0000000
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Synopsys Designware PCIe host controller driver
- *
- * Copyright (C) 2013 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * Author: Jingoo Han <jg1.han@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-struct pcie_port_info {
-       u32             cfg0_size;
-       u32             cfg1_size;
-       u32             io_size;
-       u32             mem_size;
-       phys_addr_t     io_bus_addr;
-       phys_addr_t     mem_bus_addr;
-};
-
-struct pcie_port {
-       struct device           *dev;
-       u8                      root_bus_nr;
-       void __iomem            *dbi_base;
-       u64                     cfg0_base;
-       void __iomem            *va_cfg0_base;
-       u64                     cfg1_base;
-       void __iomem            *va_cfg1_base;
-       u64                     io_base;
-       u64                     mem_base;
-       spinlock_t              conf_lock;
-       struct resource         cfg;
-       struct resource         io;
-       struct resource         mem;
-       struct pcie_port_info   config;
-       int                     irq;
-       u32                     lanes;
-       struct pcie_host_ops    *ops;
-};
-
-struct pcie_host_ops {
-       void (*readl_rc)(struct pcie_port *pp,
-                       void __iomem *dbi_base, u32 *val);
-       void (*writel_rc)(struct pcie_port *pp,
-                       u32 val, void __iomem *dbi_base);
-       int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
-       int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
-       int (*link_up)(struct pcie_port *pp);
-       void (*host_init)(struct pcie_port *pp);
-};
-
-extern unsigned long global_io_offset;
-
-int cfg_read(void __iomem *addr, int where, int size, u32 *val);
-int cfg_write(void __iomem *addr, int where, int size, u32 val);
-int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, u32 val);
-int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, u32 *val);
-int dw_pcie_link_up(struct pcie_port *pp);
-void dw_pcie_setup_rc(struct pcie_port *pp);
-int dw_pcie_host_init(struct pcie_port *pp);
-int dw_pcie_setup(int nr, struct pci_sys_data *sys);
-struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys);
-int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
diff --git a/target/linux/imx6/patches-3.10/0001-usb-chipidea-improve-kconfig.patch b/target/linux/imx6/patches-3.10/0001-usb-chipidea-improve-kconfig.patch
deleted file mode 100644 (file)
index f8229d0..0000000
+++ /dev/null
@@ -1,80 +0,0 @@
-From: Peter Chen <peter.chen@freescale.com>
-Subject: [PATCH] usb: chipidea: improve kconfig
-
-Randy Dunlap <rdunlap@infradead.org> reported this problem
-on i386:
-
-> drivers/built-in.o: In function `ci_hdrc_host_init':
-> (.text+0x2ce75c): undefined reference to `ehci_init_driver'
->
-> When USB_EHCI_HCD=m and USB_CHIPIDEA=y.
-
-In fact, this problem is existed on all platforms which are using
-chipidea driver. The root cause of this problem is the chipidea host
-uses symbol exported from ehci-hcd, but chipidea core
-does not depends on USB_EHCI_HCD. So, chipidea driver
-will not be compiled as module if USB_EHCI_HCD=m.
-
-It is very hard to give a perfect solution since chipidea core
-depends on USB || USB_GADGET, and chipdiea host depends on
-both USB_EHCI_HCD and USB_CHIPIDEA, the same problem exists for
-gadget.
-
-To fix this problem, we had to have below assumptions:
-
-- If USB_EHCI_HCD=y && USB_GADGET=y, USB_CHIPIDEA can be 'y'.
-
-- If USB_EHCI_HCD=m && USB_GADGET=y, USB_CHIPIDEA=m
-or USB_CHIPIDEA_HOST can't be seen if USB_CHIPIDEA=y.
-It will cause compile error due to no glue layer for ehci:
-
-> error: #error "missing bus glue for ehci-hcd"
-
-So, we had to compile USB_CHIPIDEA=m if USB_EHCI_HCD=m,
-current ehci hcd core guarantee it.
-
-- If USB_EHCI_HCD=y && USB_GADGET=m, USB_CHIPIDEA=m
-or USB_CHIPIDEA_UDC can't be seen if USB_CHIPIDEA=y.
-Of cos, the gadget will out of working at this situation,
-so the user had to compile USB_CHIPIDEA=m.
-
-- USB_EHCI_HCD=m && USB_GADGET=m, we can't see
-USB_CHIPIDEA_HOST and USB_CHIPIDEA_UDC unless
-USB_CHIPIDEA=m.
-
-The reason why it has above assumptions:
-- If both ehci core and gadget core build as module,
-the chipidea has to build as module.
-- If one of ehci core or gadget core is built in, another
-is built as module, we can only enable the function which
-is built in, or enable both roles as modules (USB_CHIPIDEA=m),
-since chipidea core driver takes care of both host and device roles.
-
-Signed-off-by: Peter Chen <peter.chen@freescale.com>
-Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/usb/chipidea/Kconfig | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/drivers/usb/chipidea/Kconfig
-+++ b/drivers/usb/chipidea/Kconfig
-@@ -12,15 +12,15 @@ if USB_CHIPIDEA
- config USB_CHIPIDEA_UDC
-       bool "ChipIdea device controller"
--      depends on USB_GADGET=y || USB_GADGET=USB_CHIPIDEA
-+      depends on USB_GADGET=y || USB_CHIPIDEA=m
-       help
-         Say Y here to enable device controller functionality of the
-         ChipIdea driver.
- config USB_CHIPIDEA_HOST
-       bool "ChipIdea host controller"
--      depends on USB=y || USB=USB_CHIPIDEA
--      depends on USB_EHCI_HCD=y
-+      depends on USB=y
-+      depends on USB_EHCI_HCD=y || USB_CHIPIDEA=m
-       select USB_EHCI_ROOT_HUB_TT
-       help
-         Say Y here to enable host controller functionality of the
diff --git a/target/linux/imx6/patches-3.10/0002-usb-chipidea-fix-the-build-error-with-randconfig.patch b/target/linux/imx6/patches-3.10/0002-usb-chipidea-fix-the-build-error-with-randconfig.patch
deleted file mode 100644 (file)
index e44682c..0000000
+++ /dev/null
@@ -1,42 +0,0 @@
-From: Peter Chen <peter.chen@freescale.com>
-Subject: [PATCH] usb: chipidea: fix the build error with randconfig
-
-Using below  configs, the compile will have error:
-ERROR: "ehci_init_driver" undefined!
-
-.config:
-CONFIG_USB_CHIPIDEA=m
-CONFIG_USB_CHIPIDEA_HOST=y
-CONFIG_USB_CHIPIDEA_DEBUG=y
-
-The reason is chipidea host uses symbol from ehci, but ehci
-is not compiled. Let the chipidea host depend on
-ehci even it is built as module.
-
-Signed-off-by: Peter Chen <peter.chen@freescale.com>
-Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/usb/chipidea/Kconfig | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/usb/chipidea/Kconfig
-+++ b/drivers/usb/chipidea/Kconfig
-@@ -12,7 +12,7 @@ if USB_CHIPIDEA
- config USB_CHIPIDEA_UDC
-       bool "ChipIdea device controller"
--      depends on USB_GADGET=y || USB_CHIPIDEA=m
-+      depends on USB_GADGET=y || (USB_CHIPIDEA=m && USB_GADGET=m)
-       help
-         Say Y here to enable device controller functionality of the
-         ChipIdea driver.
-@@ -20,7 +20,7 @@ config USB_CHIPIDEA_UDC
- config USB_CHIPIDEA_HOST
-       bool "ChipIdea host controller"
-       depends on USB=y
--      depends on USB_EHCI_HCD=y || USB_CHIPIDEA=m
-+      depends on USB_EHCI_HCD=y || (USB_CHIPIDEA=m && USB_EHCI_HCD=m)
-       select USB_EHCI_ROOT_HUB_TT
-       help
-         Say Y here to enable host controller functionality of the
diff --git a/target/linux/imx6/patches-3.10/0003-usb-chipidea-improve-kconfig-2.0.patch b/target/linux/imx6/patches-3.10/0003-usb-chipidea-improve-kconfig-2.0.patch
deleted file mode 100644 (file)
index f90e736..0000000
+++ /dev/null
@@ -1,51 +0,0 @@
-From: Lothar Waßmann <LW@KARO-electronics.de>
-Subject: [PATCH] usb: chipidea: improve kconfig 2.0
-
-This patch provides a cleaner solution to the problem described in
-commit 20a677fd ("usb: chipidea: improve kconfig").
-
-The goal to be achieved is to force USB_CHIPIDEA=m if either
-USB_EHCI_HCD=m or USB_GADGET=m.
-If both are 'y' USB_CHIPIDEA may be selected to be 'm' or 'y'.
-
-The old patch had the drawback, that USB_CHIPIDEA could be chosen as
-'y' though USB_EHCI_HCD or USB_GADGET (or both) were 'm' leading to a
-situation where USB_CHIPIDEA_HOST or USB_CHIPIDEA_UDC vanished from
-the config options producing a compilable but dysfunctional driver.
-
-Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
-Reviewed-by: Peter Chen <peter.chen@freescale.com>
-Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/usb/chipidea/Kconfig | 7 +++----
- 1 file changed, 3 insertions(+), 4 deletions(-)
-
---- a/drivers/usb/chipidea/Kconfig
-+++ b/drivers/usb/chipidea/Kconfig
-@@ -1,6 +1,6 @@
- config USB_CHIPIDEA
-       tristate "ChipIdea Highspeed Dual Role Controller"
--      depends on USB || USB_GADGET
-+      depends on (USB_EHCI_HCD && USB_GADGET) || (USB_EHCI_HCD && !USB_GADGET) || (!USB_EHCI_HCD && USB_GADGET)
-       help
-         Say Y here if your system has a dual role high speed USB
-         controller based on ChipIdea silicon IP. Currently, only the
-@@ -12,15 +12,14 @@ if USB_CHIPIDEA
- config USB_CHIPIDEA_UDC
-       bool "ChipIdea device controller"
--      depends on USB_GADGET=y || (USB_CHIPIDEA=m && USB_GADGET=m)
-+      depends on USB_GADGET
-       help
-         Say Y here to enable device controller functionality of the
-         ChipIdea driver.
- config USB_CHIPIDEA_HOST
-       bool "ChipIdea host controller"
--      depends on USB=y
--      depends on USB_EHCI_HCD=y || (USB_CHIPIDEA=m && USB_EHCI_HCD=m)
-+      depends on USB_EHCI_HCD
-       select USB_EHCI_ROOT_HUB_TT
-       help
-         Say Y here to enable host controller functionality of the
diff --git a/target/linux/imx6/patches-3.10/0005-ahci_imx-add-ahci-sata-support-on-imx-platforms.patch b/target/linux/imx6/patches-3.10/0005-ahci_imx-add-ahci-sata-support-on-imx-platforms.patch
deleted file mode 100644 (file)
index c735517..0000000
+++ /dev/null
@@ -1,304 +0,0 @@
-From: Richard Zhu <r65037@freescale.com>
-Subject: [PATCH] ahci_imx: add ahci sata support on imx platforms
-
-imx6q contains one Synopsys AHCI SATA controller, But it can't share
-ahci_platform driver with other controllers because there are some
-misalignments of the generic AHCI controller - the bits definitions of
-the HBA registers, the Vendor Specific registers, the AHCI PHY clock
-and the AHCI signals adjustment window(GPR13 register).
-
- - CAP_SSS(bit20) of the HOST_CAP is writable, default value is '0',
-   should be configured to be '1'
-
- - bit0 (only one AHCI SATA port on imx6q) of the HOST_PORTS_IMPL
-   should be set to be '1'.(default 0)
-
- - One Vendor Specific register HOST_TIMER1MS(offset:0xe0) should be
-   configured regarding to the frequency of AHB bus clock.
-
- - Configurations of the AHCI PHY clock, and the signal parameters of
-   the GPR13
-
-Setup its own ahci sata driver, contained the imx6q specific
-initialized codes, re-use the generic ahci_platform driver, and keep
-the generic ahci_platform driver clean as much as possible.
-
-tj: patch description reformatted
-
-Signed-off-by: Richard Zhu <r65037@freescale.com>
-Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
-Signed-off-by: Tejun Heo <tj@kernel.org>
----
- drivers/ata/Kconfig    |   9 ++
- drivers/ata/Makefile   |   1 +
- drivers/ata/ahci_imx.c | 236 +++++++++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 246 insertions(+)
- create mode 100644 drivers/ata/ahci_imx.c
-
---- a/drivers/ata/Kconfig
-+++ b/drivers/ata/Kconfig
-@@ -97,6 +97,15 @@ config SATA_AHCI_PLATFORM
-         If unsure, say N.
-+config AHCI_IMX
-+      tristate "Freescale i.MX AHCI SATA support"
-+      depends on SATA_AHCI_PLATFORM
-+      help
-+        This option enables support for the Freescale i.MX SoC's
-+        onboard AHCI SATA.
-+
-+        If unsure, say N.
-+
- config SATA_FSL
-       tristate "Freescale 3.0Gbps SATA support"
-       depends on FSL_SOC
---- a/drivers/ata/Makefile
-+++ b/drivers/ata/Makefile
-@@ -10,6 +10,7 @@ obj-$(CONFIG_SATA_INIC162X)  += sata_inic
- obj-$(CONFIG_SATA_SIL24)      += sata_sil24.o
- obj-$(CONFIG_SATA_DWC)                += sata_dwc_460ex.o
- obj-$(CONFIG_SATA_HIGHBANK)   += sata_highbank.o libahci.o
-+obj-$(CONFIG_AHCI_IMX)                += ahci_imx.o
- # SFF w/ custom DMA
- obj-$(CONFIG_PDC_ADMA)                += pdc_adma.o
---- /dev/null
-+++ b/drivers/ata/ahci_imx.c
-@@ -0,0 +1,236 @@
-+/*
-+ * Freescale IMX AHCI SATA platform driver
-+ * Copyright 2013 Freescale Semiconductor, Inc.
-+ *
-+ * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/regmap.h>
-+#include <linux/ahci_platform.h>
-+#include <linux/of_device.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
-+#include "ahci.h"
-+
-+enum {
-+      HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
-+};
-+
-+struct imx_ahci_priv {
-+      struct platform_device *ahci_pdev;
-+      struct clk *sata_ref_clk;
-+      struct clk *ahb_clk;
-+      struct regmap *gpr;
-+};
-+
-+static int imx6q_sata_init(struct device *dev, void __iomem *mmio)
-+{
-+      int ret = 0;
-+      unsigned int reg_val;
-+      struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
-+
-+      imxpriv->gpr =
-+              syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
-+      if (IS_ERR(imxpriv->gpr)) {
-+              dev_err(dev, "failed to find fsl,imx6q-iomux-gpr regmap\n");
-+              return PTR_ERR(imxpriv->gpr);
-+      }
-+
-+      ret = clk_prepare_enable(imxpriv->sata_ref_clk);
-+      if (ret < 0) {
-+              dev_err(dev, "prepare-enable sata_ref clock err:%d\n", ret);
-+              return ret;
-+      }
-+
-+      /*
-+       * set PHY Paremeters, two steps to configure the GPR13,
-+       * one write for rest of parameters, mask of first write
-+       * is 0x07fffffd, and the other one write for setting
-+       * the mpll_clk_en.
-+       */
-+      regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK
-+                      | IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK
-+                      | IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK
-+                      | IMX6Q_GPR13_SATA_SPD_MODE_MASK
-+                      | IMX6Q_GPR13_SATA_MPLL_SS_EN
-+                      | IMX6Q_GPR13_SATA_TX_ATTEN_MASK
-+                      | IMX6Q_GPR13_SATA_TX_BOOST_MASK
-+                      | IMX6Q_GPR13_SATA_TX_LVL_MASK
-+                      | IMX6Q_GPR13_SATA_TX_EDGE_RATE
-+                      , IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB
-+                      | IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M
-+                      | IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F
-+                      | IMX6Q_GPR13_SATA_SPD_MODE_3P0G
-+                      | IMX6Q_GPR13_SATA_MPLL_SS_EN
-+                      | IMX6Q_GPR13_SATA_TX_ATTEN_9_16
-+                      | IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB
-+                      | IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
-+      regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
-+                      IMX6Q_GPR13_SATA_MPLL_CLK_EN);
-+      usleep_range(100, 200);
-+
-+      /*
-+       * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
-+       * and IP vendor specific register HOST_TIMER1MS.
-+       * Configure CAP_SSS (support stagered spin up).
-+       * Implement the port0.
-+       * Get the ahb clock rate, and configure the TIMER1MS register.
-+       */
-+      reg_val = readl(mmio + HOST_CAP);
-+      if (!(reg_val & HOST_CAP_SSS)) {
-+              reg_val |= HOST_CAP_SSS;
-+              writel(reg_val, mmio + HOST_CAP);
-+      }
-+      reg_val = readl(mmio + HOST_PORTS_IMPL);
-+      if (!(reg_val & 0x1)) {
-+              reg_val |= 0x1;
-+              writel(reg_val, mmio + HOST_PORTS_IMPL);
-+      }
-+
-+      reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
-+      writel(reg_val, mmio + HOST_TIMER1MS);
-+
-+      return 0;
-+}
-+
-+static void imx6q_sata_exit(struct device *dev)
-+{
-+      struct imx_ahci_priv *imxpriv =  dev_get_drvdata(dev->parent);
-+
-+      regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
-+                      !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
-+      clk_disable_unprepare(imxpriv->sata_ref_clk);
-+}
-+
-+static struct ahci_platform_data imx6q_sata_pdata = {
-+      .init = imx6q_sata_init,
-+      .exit = imx6q_sata_exit,
-+};
-+
-+static const struct of_device_id imx_ahci_of_match[] = {
-+      { .compatible = "fsl,imx6q-ahci", .data = &imx6q_sata_pdata},
-+      {},
-+};
-+MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
-+
-+static int imx_ahci_probe(struct platform_device *pdev)
-+{
-+      struct device *dev = &pdev->dev;
-+      struct resource *mem, *irq, res[2];
-+      const struct of_device_id *of_id;
-+      const struct ahci_platform_data *pdata = NULL;
-+      struct imx_ahci_priv *imxpriv;
-+      struct device *ahci_dev;
-+      struct platform_device *ahci_pdev;
-+      int ret;
-+
-+      imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
-+      if (!imxpriv) {
-+              dev_err(dev, "can't alloc ahci_host_priv\n");
-+              return -ENOMEM;
-+      }
-+
-+      ahci_pdev = platform_device_alloc("ahci", -1);
-+      if (!ahci_pdev)
-+              return -ENODEV;
-+
-+      ahci_dev = &ahci_pdev->dev;
-+      ahci_dev->parent = dev;
-+
-+      imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
-+      if (IS_ERR(imxpriv->ahb_clk)) {
-+              dev_err(dev, "can't get ahb clock.\n");
-+              ret = PTR_ERR(imxpriv->ahb_clk);
-+              goto err_out;
-+      }
-+
-+      imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
-+      if (IS_ERR(imxpriv->sata_ref_clk)) {
-+              dev_err(dev, "can't get sata_ref clock.\n");
-+              ret = PTR_ERR(imxpriv->sata_ref_clk);
-+              goto err_out;
-+      }
-+
-+      imxpriv->ahci_pdev = ahci_pdev;
-+      platform_set_drvdata(pdev, imxpriv);
-+
-+      of_id = of_match_device(imx_ahci_of_match, dev);
-+      if (of_id) {
-+              pdata = of_id->data;
-+      } else {
-+              ret = -EINVAL;
-+              goto err_out;
-+      }
-+
-+      mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+      irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-+      if (!mem || !irq) {
-+              dev_err(dev, "no mmio/irq resource\n");
-+              ret = -ENOMEM;
-+              goto err_out;
-+      }
-+
-+      res[0] = *mem;
-+      res[1] = *irq;
-+
-+      ahci_dev->coherent_dma_mask = DMA_BIT_MASK(32);
-+      ahci_dev->dma_mask = &ahci_dev->coherent_dma_mask;
-+      ahci_dev->of_node = dev->of_node;
-+
-+      ret = platform_device_add_resources(ahci_pdev, res, 2);
-+      if (ret)
-+              goto err_out;
-+
-+      ret = platform_device_add_data(ahci_pdev, pdata, sizeof(*pdata));
-+      if (ret)
-+              goto err_out;
-+
-+      ret = platform_device_add(ahci_pdev);
-+      if (ret) {
-+err_out:
-+              platform_device_put(ahci_pdev);
-+              return ret;
-+      }
-+
-+      return 0;
-+}
-+
-+static int imx_ahci_remove(struct platform_device *pdev)
-+{
-+      struct imx_ahci_priv *imxpriv = platform_get_drvdata(pdev);
-+      struct platform_device *ahci_pdev = imxpriv->ahci_pdev;
-+
-+      platform_device_unregister(ahci_pdev);
-+      return 0;
-+}
-+
-+static struct platform_driver imx_ahci_driver = {
-+      .probe = imx_ahci_probe,
-+      .remove = imx_ahci_remove,
-+      .driver = {
-+              .name = "ahci-imx",
-+              .owner = THIS_MODULE,
-+              .of_match_table = imx_ahci_of_match,
-+      },
-+};
-+module_platform_driver(imx_ahci_driver);
-+
-+MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
-+MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("ahci:imx");
diff --git a/target/linux/imx6/patches-3.10/0006-ARM-imx6q-update-the-sata-bits-definitions-of-gpr13.patch b/target/linux/imx6/patches-3.10/0006-ARM-imx6q-update-the-sata-bits-definitions-of-gpr13.patch
deleted file mode 100644 (file)
index 646273a..0000000
+++ /dev/null
@@ -1,143 +0,0 @@
-From: Richard Zhu <r65037@freescale.com>
-Subject: [PATCH] ARM: imx6q: update the sata bits definitions of gpr13
-
-Replace the SATA_PHY_# by the more readable definitons.
-
-tj: Being routed through libata branch to enable implementation of
-    ahci_imx.
-
-Signed-off-by: Richard Zhu <r65037@freescale.com>
-Acked-by: Shawn Guo <shawn.guo@linaro.org>
-Signed-off-by: Tejun Heo <tj@kernel.org>
----
- include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 121 +++++++++++++++++++---------
- 1 file changed, 84 insertions(+), 37 deletions(-)
-
---- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
-+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
-@@ -279,41 +279,88 @@
- #define IMX6Q_GPR13_CAN2_STOP_REQ             BIT(29)
- #define IMX6Q_GPR13_CAN1_STOP_REQ             BIT(28)
- #define IMX6Q_GPR13_ENET_STOP_REQ             BIT(27)
--#define IMX6Q_GPR13_SATA_PHY_8_MASK           (0x7 << 24)
--#define IMX6Q_GPR13_SATA_PHY_8_0_5_DB         (0x0 << 24)
--#define IMX6Q_GPR13_SATA_PHY_8_1_0_DB         (0x1 << 24)
--#define IMX6Q_GPR13_SATA_PHY_8_1_5_DB         (0x2 << 24)
--#define IMX6Q_GPR13_SATA_PHY_8_2_0_DB         (0x3 << 24)
--#define IMX6Q_GPR13_SATA_PHY_8_2_5_DB         (0x4 << 24)
--#define IMX6Q_GPR13_SATA_PHY_8_3_0_DB         (0x5 << 24)
--#define IMX6Q_GPR13_SATA_PHY_8_3_5_DB         (0x6 << 24)
--#define IMX6Q_GPR13_SATA_PHY_8_4_0_DB         (0x7 << 24)
--#define IMX6Q_GPR13_SATA_PHY_7_MASK           (0x1f << 19)
--#define IMX6Q_GPR13_SATA_PHY_7_SATA1I         (0x10 << 19)
--#define IMX6Q_GPR13_SATA_PHY_7_SATA1M         (0x10 << 19)
--#define IMX6Q_GPR13_SATA_PHY_7_SATA1X         (0x1a << 19)
--#define IMX6Q_GPR13_SATA_PHY_7_SATA2I         (0x12 << 19)
--#define IMX6Q_GPR13_SATA_PHY_7_SATA2M         (0x12 << 19)
--#define IMX6Q_GPR13_SATA_PHY_7_SATA2X         (0x1a << 19)
--#define IMX6Q_GPR13_SATA_PHY_6_MASK           (0x7 << 16)
--#define IMX6Q_GPR13_SATA_SPEED_MASK           BIT(15)
--#define IMX6Q_GPR13_SATA_SPEED_1P5G           0x0
--#define IMX6Q_GPR13_SATA_SPEED_3P0G           BIT(15)
--#define IMX6Q_GPR13_SATA_PHY_5                        BIT(14)
--#define IMX6Q_GPR13_SATA_PHY_4_MASK           (0x7 << 11)
--#define IMX6Q_GPR13_SATA_PHY_4_16_16          (0x0 << 11)
--#define IMX6Q_GPR13_SATA_PHY_4_14_16          (0x1 << 11)
--#define IMX6Q_GPR13_SATA_PHY_4_12_16          (0x2 << 11)
--#define IMX6Q_GPR13_SATA_PHY_4_10_16          (0x3 << 11)
--#define IMX6Q_GPR13_SATA_PHY_4_9_16           (0x4 << 11)
--#define IMX6Q_GPR13_SATA_PHY_4_8_16           (0x5 << 11)
--#define IMX6Q_GPR13_SATA_PHY_3_MASK           (0xf << 7)
--#define IMX6Q_GPR13_SATA_PHY_3_OFF            0x7
--#define IMX6Q_GPR13_SATA_PHY_2_MASK           (0x1f << 2)
--#define IMX6Q_GPR13_SATA_PHY_2_OFF            0x2
--#define IMX6Q_GPR13_SATA_PHY_1_MASK           (0x3 << 0)
--#define IMX6Q_GPR13_SATA_PHY_1_FAST           (0x0 << 0)
--#define IMX6Q_GPR13_SATA_PHY_1_MED            (0x1 << 0)
--#define IMX6Q_GPR13_SATA_PHY_1_SLOW           (0x2 << 0)
--
-+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK               (0x7 << 24)
-+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB     (0x0 << 24)
-+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB     (0x1 << 24)
-+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB     (0x2 << 24)
-+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB     (0x3 << 24)
-+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB     (0x4 << 24)
-+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB     (0x5 << 24)
-+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB     (0x6 << 24)
-+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB     (0x7 << 24)
-+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK      (0x1f << 19)
-+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1I    (0x10 << 19)
-+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1M    (0x10 << 19)
-+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1X    (0x1a << 19)
-+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2I    (0x12 << 19)
-+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M    (0x12 << 19)
-+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2X    (0x1a << 19)
-+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK    (0x7 << 16)
-+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_1F   (0x0 << 16)
-+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_2F   (0x1 << 16)
-+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_4F   (0x2 << 16)
-+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F   (0x3 << 16)
-+#define IMX6Q_GPR13_SATA_SPD_MODE_MASK                BIT(15)
-+#define IMX6Q_GPR13_SATA_SPD_MODE_1P5G                0x0
-+#define IMX6Q_GPR13_SATA_SPD_MODE_3P0G                BIT(15)
-+#define IMX6Q_GPR13_SATA_MPLL_SS_EN           BIT(14)
-+#define IMX6Q_GPR13_SATA_TX_ATTEN_MASK                (0x7 << 11)
-+#define IMX6Q_GPR13_SATA_TX_ATTEN_16_16               (0x0 << 11)
-+#define IMX6Q_GPR13_SATA_TX_ATTEN_14_16               (0x1 << 11)
-+#define IMX6Q_GPR13_SATA_TX_ATTEN_12_16               (0x2 << 11)
-+#define IMX6Q_GPR13_SATA_TX_ATTEN_10_16               (0x3 << 11)
-+#define IMX6Q_GPR13_SATA_TX_ATTEN_9_16                (0x4 << 11)
-+#define IMX6Q_GPR13_SATA_TX_ATTEN_8_16                (0x5 << 11)
-+#define IMX6Q_GPR13_SATA_TX_BOOST_MASK                (0xf << 7)
-+#define IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB     (0x0 << 7)
-+#define IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB     (0x1 << 7)
-+#define IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB     (0x2 << 7)
-+#define IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB     (0x3 << 7)
-+#define IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB     (0x4 << 7)
-+#define IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB     (0x5 << 7)
-+#define IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB     (0x6 << 7)
-+#define IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB     (0x7 << 7)
-+#define IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB     (0x8 << 7)
-+#define IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB     (0x9 << 7)
-+#define IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB     (0xa << 7)
-+#define IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB     (0xb << 7)
-+#define IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB     (0xc << 7)
-+#define IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB     (0xd << 7)
-+#define IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB     (0xe << 7)
-+#define IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB     (0xf << 7)
-+#define IMX6Q_GPR13_SATA_TX_LVL_MASK          (0x1f << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_0_937_V               (0x00 << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_0_947_V               (0x01 << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_0_957_V               (0x02 << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_0_966_V               (0x03 << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_0_976_V               (0x04 << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_0_986_V               (0x05 << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_0_996_V               (0x06 << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_005_V               (0x07 << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_015_V               (0x08 << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_025_V               (0x09 << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_035_V               (0x0a << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_045_V               (0x0b << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_054_V               (0x0c << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_064_V               (0x0d << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_074_V               (0x0e << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_084_V               (0x0f << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_094_V               (0x10 << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_104_V               (0x11 << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_113_V               (0x12 << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_123_V               (0x13 << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_133_V               (0x14 << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_143_V               (0x15 << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_152_V               (0x16 << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_162_V               (0x17 << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_172_V               (0x18 << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_182_V               (0x19 << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_191_V               (0x1a << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_201_V               (0x1b << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_211_V               (0x1c << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_221_V               (0x1d << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_230_V               (0x1e << 2)
-+#define IMX6Q_GPR13_SATA_TX_LVL_1_240_V               (0x1f << 2)
-+#define IMX6Q_GPR13_SATA_MPLL_CLK_EN          BIT(1)
-+#define IMX6Q_GPR13_SATA_TX_EDGE_RATE         BIT(0)
- #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
diff --git a/target/linux/imx6/patches-3.10/0007-ARM-dtsi-enable-ahci-sata-on-imx6q-platforms.patch b/target/linux/imx6/patches-3.10/0007-ARM-dtsi-enable-ahci-sata-on-imx6q-platforms.patch
deleted file mode 100644 (file)
index 5371524..0000000
+++ /dev/null
@@ -1,66 +0,0 @@
-From: Richard Zhu <r65037@freescale.com>
-Subject: [PATCH] ARM: dtsi: enable ahci sata on imx6q platforms
-
-Only imx6q has the ahci sata controller, enable
-it on imx6q platforms.
-
-Signed-off-by: Richard Zhu <r65037@freescale.com>
-Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
----
- arch/arm/boot/dts/imx6q-sabreauto.dts | 4 ++++
- arch/arm/boot/dts/imx6q-sabrelite.dts | 4 ++++
- arch/arm/boot/dts/imx6q-sabresd.dts   | 4 ++++
- arch/arm/boot/dts/imx6q.dtsi          | 9 +++++++++
- 4 files changed, 21 insertions(+)
-
---- a/arch/arm/boot/dts/imx6q-sabreauto.dts
-+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
-@@ -33,3 +33,7 @@
-               };
-       };
- };
-+
-+&sata {
-+      status = "okay";
-+};
---- a/arch/arm/boot/dts/imx6q-sabrelite.dts
-+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
-@@ -65,6 +65,10 @@
-       };
- };
-+&sata {
-+      status = "okay";
-+};
-+
- &ecspi1 {
-       fsl,spi-num-chipselects = <1>;
-       cs-gpios = <&gpio3 19 0>;
---- a/arch/arm/boot/dts/imx6q-sabresd.dts
-+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
-@@ -37,3 +37,7 @@
-               };
-       };
- };
-+
-+&sata {
-+      status = "okay";
-+};
---- a/arch/arm/boot/dts/imx6q.dtsi
-+++ b/arch/arm/boot/dts/imx6q.dtsi
-@@ -332,6 +332,15 @@
-                       };
-               };
-+              sata: sata@02200000 {
-+                      compatible = "fsl,imx6q-ahci";
-+                      reg = <0x02200000 0x4000>;
-+                      interrupts = <0 39 0x04>;
-+                      clocks =  <&clks 154>, <&clks 187>, <&clks 105>;
-+                      clock-names = "sata", "sata_ref", "ahb";
-+                      status = "disabled";
-+              };
-+
-               ipu2: ipu@02800000 {
-                       #crtc-cells = <1>;
-                       compatible = "fsl,imx6q-ipu";
diff --git a/target/linux/imx6/patches-3.10/0008-ahci_imx-depend-on-CONFIG_MFD_SYSCON.patch b/target/linux/imx6/patches-3.10/0008-ahci_imx-depend-on-CONFIG_MFD_SYSCON.patch
deleted file mode 100644 (file)
index 86e7d8f..0000000
+++ /dev/null
@@ -1,24 +0,0 @@
-From: Tejun Heo <tj@kernel.org>
-Subject: [PATCH] ahci_imx: depend on CONFIG_MFD_SYSCON
-
-ahci_imx makes use of regmap but the dependency wasn't specified in
-Kconfig leading build failures if CONFIG_AHCI_IMX is enabled but
-CONFIG_MFD_SYSCON is not.  Add the Kconfig dependency.
-
-Signed-off-by: Tejun Heo <tj@kernel.org>
-Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
----
- drivers/ata/Kconfig | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/ata/Kconfig
-+++ b/drivers/ata/Kconfig
-@@ -99,7 +99,7 @@ config SATA_AHCI_PLATFORM
- config AHCI_IMX
-       tristate "Freescale i.MX AHCI SATA support"
--      depends on SATA_AHCI_PLATFORM
-+      depends on SATA_AHCI_PLATFORM && MFD_SYSCON
-       help
-         This option enables support for the Freescale i.MX SoC's
-         onboard AHCI SATA.
diff --git a/target/linux/imx6/patches-3.10/0009-of-pci-Provide-support-for-parsing-PCI-DT-ranges-pro.patch b/target/linux/imx6/patches-3.10/0009-of-pci-Provide-support-for-parsing-PCI-DT-ranges-pro.patch
deleted file mode 100644 (file)
index 45e1dc2..0000000
+++ /dev/null
@@ -1,194 +0,0 @@
-From: Andrew Murray <Andrew.Murray@arm.com>
-Subject: [PATCH] of/pci: Provide support for parsing PCI DT ranges property
-
-This patch factors out common implementation patterns to reduce overall kernel
-code and provide a means for host bridge drivers to directly obtain struct
-resources from the DT's ranges property without relying on architecture specific
-DT handling. This will make it easier to write archiecture independent host bridge
-drivers and mitigate against further duplication of DT parsing code.
-
-This patch can be used in the following way:
-
-       struct of_pci_range_parser parser;
-       struct of_pci_range range;
-
-       if (of_pci_range_parser_init(&parser, np))
-               ; //no ranges property
-
-       for_each_of_pci_range(&parser, &range) {
-
-               /*
-                       directly access properties of the address range, e.g.:
-                       range.pci_space, range.pci_addr, range.cpu_addr,
-                       range.size, range.flags
-
-                       alternatively obtain a struct resource, e.g.:
-                       struct resource res;
-                       of_pci_range_to_resource(&range, np, &res);
-               */
-       }
-
-Additionally the implementation takes care of adjacent ranges and merges them
-into a single range (as was the case with powerpc and microblaze).
-
-Signed-off-by: Andrew Murray <Andrew.Murray@arm.com>
-Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Reviewed-by: Rob Herring <rob.herring@calxeda.com>
-Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Tested-by: Linus Walleij <linus.walleij@linaro.org>
-Tested-by: Jingoo Han <jg1.han@samsung.com>
-Acked-by: Grant Likely <grant.likely@secretlab.ca>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- drivers/of/address.c       | 67 ++++++++++++++++++++++++++++++++++++++++++++++
- include/linux/of_address.h | 48 +++++++++++++++++++++++++++++++++
- 2 files changed, 115 insertions(+)
-
---- a/drivers/of/address.c
-+++ b/drivers/of/address.c
-@@ -224,6 +224,73 @@ int of_pci_address_to_resource(struct de
-       return __of_address_to_resource(dev, addrp, size, flags, NULL, r);
- }
- EXPORT_SYMBOL_GPL(of_pci_address_to_resource);
-+
-+int of_pci_range_parser_init(struct of_pci_range_parser *parser,
-+                              struct device_node *node)
-+{
-+      const int na = 3, ns = 2;
-+      int rlen;
-+
-+      parser->node = node;
-+      parser->pna = of_n_addr_cells(node);
-+      parser->np = parser->pna + na + ns;
-+
-+      parser->range = of_get_property(node, "ranges", &rlen);
-+      if (parser->range == NULL)
-+              return -ENOENT;
-+
-+      parser->end = parser->range + rlen / sizeof(__be32);
-+
-+      return 0;
-+}
-+EXPORT_SYMBOL_GPL(of_pci_range_parser_init);
-+
-+struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser,
-+                                              struct of_pci_range *range)
-+{
-+      const int na = 3, ns = 2;
-+
-+      if (!range)
-+              return NULL;
-+
-+      if (!parser->range || parser->range + parser->np > parser->end)
-+              return NULL;
-+
-+      range->pci_space = parser->range[0];
-+      range->flags = of_bus_pci_get_flags(parser->range);
-+      range->pci_addr = of_read_number(parser->range + 1, ns);
-+      range->cpu_addr = of_translate_address(parser->node,
-+                              parser->range + na);
-+      range->size = of_read_number(parser->range + parser->pna + na, ns);
-+
-+      parser->range += parser->np;
-+
-+      /* Now consume following elements while they are contiguous */
-+      while (parser->range + parser->np <= parser->end) {
-+              u32 flags, pci_space;
-+              u64 pci_addr, cpu_addr, size;
-+
-+              pci_space = be32_to_cpup(parser->range);
-+              flags = of_bus_pci_get_flags(parser->range);
-+              pci_addr = of_read_number(parser->range + 1, ns);
-+              cpu_addr = of_translate_address(parser->node,
-+                              parser->range + na);
-+              size = of_read_number(parser->range + parser->pna + na, ns);
-+
-+              if (flags != range->flags)
-+                      break;
-+              if (pci_addr != range->pci_addr + range->size ||
-+                  cpu_addr != range->cpu_addr + range->size)
-+                      break;
-+
-+              range->size += size;
-+              parser->range += parser->np;
-+      }
-+
-+      return range;
-+}
-+EXPORT_SYMBOL_GPL(of_pci_range_parser_one);
-+
- #endif /* CONFIG_PCI */
- /*
---- a/include/linux/of_address.h
-+++ b/include/linux/of_address.h
-@@ -4,6 +4,36 @@
- #include <linux/errno.h>
- #include <linux/of.h>
-+struct of_pci_range_parser {
-+      struct device_node *node;
-+      const __be32 *range;
-+      const __be32 *end;
-+      int np;
-+      int pna;
-+};
-+
-+struct of_pci_range {
-+      u32 pci_space;
-+      u64 pci_addr;
-+      u64 cpu_addr;
-+      u64 size;
-+      u32 flags;
-+};
-+
-+#define for_each_of_pci_range(parser, range) \
-+      for (; of_pci_range_parser_one(parser, range);)
-+
-+static inline void of_pci_range_to_resource(struct of_pci_range *range,
-+                                          struct device_node *np,
-+                                          struct resource *res)
-+{
-+      res->flags = range->flags;
-+      res->start = range->cpu_addr;
-+      res->end = range->cpu_addr + range->size - 1;
-+      res->parent = res->child = res->sibling = NULL;
-+      res->name = np->full_name;
-+}
-+
- #ifdef CONFIG_OF_ADDRESS
- extern u64 of_translate_address(struct device_node *np, const __be32 *addr);
- extern bool of_can_translate_address(struct device_node *dev);
-@@ -27,6 +57,11 @@ static inline unsigned long pci_address_
- #define pci_address_to_pio pci_address_to_pio
- #endif
-+extern int of_pci_range_parser_init(struct of_pci_range_parser *parser,
-+                      struct device_node *node);
-+extern struct of_pci_range *of_pci_range_parser_one(
-+                                      struct of_pci_range_parser *parser,
-+                                      struct of_pci_range *range);
- #else /* CONFIG_OF_ADDRESS */
- #ifndef of_address_to_resource
- static inline int of_address_to_resource(struct device_node *dev, int index,
-@@ -53,6 +88,19 @@ static inline const __be32 *of_get_addre
- {
-       return NULL;
- }
-+
-+static inline int of_pci_range_parser_init(struct of_pci_range_parser *parser,
-+                      struct device_node *node)
-+{
-+      return -1;
-+}
-+
-+static inline struct of_pci_range *of_pci_range_parser_one(
-+                                      struct of_pci_range_parser *parser,
-+                                      struct of_pci_range *range)
-+{
-+      return NULL;
-+}
- #endif /* CONFIG_OF_ADDRESS */
diff --git a/target/linux/imx6/patches-3.10/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch b/target/linux/imx6/patches-3.10/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch
deleted file mode 100644 (file)
index 19ca079..0000000
+++ /dev/null
@@ -1,37 +0,0 @@
-From: Sean Cross <xobs@kosagi.com>
-Subject: [PATCH 1/2] ARM: imx6q: Add PCIe bits to GPR syscon definition
-
-PCIe requires additional bits be defined for GPR8 and GPR12.
-
-Signed-off-by: Sean Cross <xobs@kosagi.com>
-Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
----
- include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
-+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
-@@ -241,6 +241,12 @@
- #define IMX6Q_GPR5_L2_CLK_STOP                        BIT(8)
-+#define IMX6Q_GPR8_TX_SWING_LOW                       (0x7f << 25)
-+#define IMX6Q_GPR8_TX_SWING_FULL              (0x7f << 18)
-+#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB         (0x3f << 12)
-+#define IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB               (0x3f << 6)
-+#define IMX6Q_GPR8_TX_DEEMPH_GEN1             (0x3f << 0)
-+
- #define IMX6Q_GPR9_TZASC2_BYP                 BIT(1)
- #define IMX6Q_GPR9_TZASC1_BYP                 BIT(0)
-@@ -273,7 +279,9 @@
- #define IMX6Q_GPR12_ARMP_AHB_CLK_EN           BIT(26)
- #define IMX6Q_GPR12_ARMP_ATB_CLK_EN           BIT(25)
- #define IMX6Q_GPR12_ARMP_APB_CLK_EN           BIT(24)
-+#define IMX6Q_GPR12_DEVICE_TYPE                       (0xf << 12)
- #define IMX6Q_GPR12_PCIE_CTL_2                        BIT(10)
-+#define IMX6Q_GPR12_LOS_LEVEL                 (0x1f << 4)
- #define IMX6Q_GPR13_SDMA_STOP_REQ             BIT(30)
- #define IMX6Q_GPR13_CAN2_STOP_REQ             BIT(29)
diff --git a/target/linux/imx6/patches-3.10/0011-PCI-imx6-Add-support-for-i.MX6-PCIe-controller.patch b/target/linux/imx6/patches-3.10/0011-PCI-imx6-Add-support-for-i.MX6-PCIe-controller.patch
deleted file mode 100644 (file)
index 599cd0e..0000000
+++ /dev/null
@@ -1,616 +0,0 @@
-Subject: [PATCH 2/2] PCI: imx6: Add support for i.MX6 PCIe controller
-From: Sean Cross <xobs@kosagi.com>
-
-Add support for the PCIe port present on the i.MX6 family of controllers.
-These use the Synopsis Designware core tied to their own PHY.
-
-Signed-off-by: Sean Cross <xobs@kosagi.com>
-Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
----
- drivers/pci/host/Kconfig                           |   6 +
- drivers/pci/host/Makefile                          |   1 +
- drivers/pci/host/pci-imx6.c                        | 575 +++++++++++++++++++++
- 4 files changed, 588 insertions(+), 1 deletion(-)
- create mode 100644 drivers/pci/host/pci-imx6.c
-
---- /dev/null
-+++ b/drivers/pci/host/Kconfig
-@@ -0,0 +1,13 @@
-+menu "PCI host controller drivers"
-+      depends on PCI
-+
-+config PCIE_DW
-+      bool
-+
-+config PCI_IMX6
-+      bool "Freescale i.MX6 PCIe controller"
-+      depends on SOC_IMX6Q
-+      select PCIEPORTBUS
-+      select PCIE_DW
-+
-+endmenu
---- /dev/null
-+++ b/drivers/pci/host/Makefile
-@@ -0,0 +1,2 @@
-+obj-$(CONFIG_PCIE_DW) += pcie-designware.o
-+obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
---- /dev/null
-+++ b/drivers/pci/host/pci-imx6.c
-@@ -0,0 +1,575 @@
-+/*
-+ * PCIe host controller driver for Freescale i.MX6 SoCs
-+ *
-+ * Copyright (C) 2013 Kosagi
-+ *            http://www.kosagi.com
-+ *
-+ * Author: Sean Cross <xobs@kosagi.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/gpio.h>
-+#include <linux/kernel.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
-+#include <linux/module.h>
-+#include <linux/of_gpio.h>
-+#include <linux/pci.h>
-+#include <linux/platform_device.h>
-+#include <linux/regmap.h>
-+#include <linux/resource.h>
-+#include <linux/signal.h>
-+#include <linux/types.h>
-+
-+#include "pcie-designware.h"
-+
-+#define to_imx6_pcie(x)       container_of(x, struct imx6_pcie, pp)
-+
-+struct imx6_pcie {
-+      int                     reset_gpio;
-+      int                     power_on_gpio;
-+      int                     wake_up_gpio;
-+      int                     disable_gpio;
-+      struct clk              *lvds_gate;
-+      struct clk              *sata_ref_100m;
-+      struct clk              *pcie_ref_125m;
-+      struct clk              *pcie_axi;
-+      struct pcie_port        pp;
-+      struct regmap           *iomuxc_gpr;
-+      void __iomem            *mem_base;
-+};
-+
-+/* PCIe Port Logic registers (memory-mapped) */
-+#define PL_OFFSET 0x700
-+#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
-+#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
-+
-+#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
-+#define PCIE_PHY_CTRL_DATA_LOC 0
-+#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
-+#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
-+#define PCIE_PHY_CTRL_WR_LOC 18
-+#define PCIE_PHY_CTRL_RD_LOC 19
-+
-+#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
-+#define PCIE_PHY_STAT_ACK_LOC 16
-+
-+/* PHY registers (not memory-mapped) */
-+#define PCIE_PHY_RX_ASIC_OUT 0x100D
-+
-+#define PHY_RX_OVRD_IN_LO 0x1005
-+#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
-+#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
-+
-+static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
-+{
-+      u32 val;
-+      u32 max_iterations = 10;
-+      u32 wait_counter = 0;
-+
-+      do {
-+              val = readl(dbi_base + PCIE_PHY_STAT);
-+              val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
-+              wait_counter++;
-+
-+              if (val == exp_val)
-+                      return 0;
-+
-+              udelay(1);
-+      } while (wait_counter < max_iterations);
-+
-+      return -ETIMEDOUT;
-+}
-+
-+static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
-+{
-+      u32 val;
-+      int ret;
-+
-+      val = addr << PCIE_PHY_CTRL_DATA_LOC;
-+      writel(val, dbi_base + PCIE_PHY_CTRL);
-+
-+      val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
-+      writel(val, dbi_base + PCIE_PHY_CTRL);
-+
-+      ret = pcie_phy_poll_ack(dbi_base, 1);
-+      if (ret)
-+              return ret;
-+
-+      val = addr << PCIE_PHY_CTRL_DATA_LOC;
-+      writel(val, dbi_base + PCIE_PHY_CTRL);
-+
-+      ret = pcie_phy_poll_ack(dbi_base, 0);
-+      if (ret)
-+              return ret;
-+
-+      return 0;
-+}
-+
-+/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
-+static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
-+{
-+      u32 val, phy_ctl;
-+      int ret;
-+
-+      ret = pcie_phy_wait_ack(dbi_base, addr);
-+      if (ret)
-+              return ret;
-+
-+      /* assert Read signal */
-+      phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
-+      writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
-+
-+      ret = pcie_phy_poll_ack(dbi_base, 1);
-+      if (ret)
-+              return ret;
-+
-+      val = readl(dbi_base + PCIE_PHY_STAT);
-+      *data = val & 0xffff;
-+
-+      /* deassert Read signal */
-+      writel(0x00, dbi_base + PCIE_PHY_CTRL);
-+
-+      ret = pcie_phy_poll_ack(dbi_base, 0);
-+      if (ret)
-+              return ret;
-+
-+      return 0;
-+}
-+
-+static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
-+{
-+      u32 var;
-+      int ret;
-+
-+      /* write addr */
-+      /* cap addr */
-+      ret = pcie_phy_wait_ack(dbi_base, addr);
-+      if (ret)
-+              return ret;
-+
-+      var = data << PCIE_PHY_CTRL_DATA_LOC;
-+      writel(var, dbi_base + PCIE_PHY_CTRL);
-+
-+      /* capture data */
-+      var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
-+      writel(var, dbi_base + PCIE_PHY_CTRL);
-+
-+      ret = pcie_phy_poll_ack(dbi_base, 1);
-+      if (ret)
-+              return ret;
-+
-+      /* deassert cap data */
-+      var = data << PCIE_PHY_CTRL_DATA_LOC;
-+      writel(var, dbi_base + PCIE_PHY_CTRL);
-+
-+      /* wait for ack de-assertion */
-+      ret = pcie_phy_poll_ack(dbi_base, 0);
-+      if (ret)
-+              return ret;
-+
-+      /* assert wr signal */
-+      var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
-+      writel(var, dbi_base + PCIE_PHY_CTRL);
-+
-+      /* wait for ack */
-+      ret = pcie_phy_poll_ack(dbi_base, 1);
-+      if (ret)
-+              return ret;
-+
-+      /* deassert wr signal */
-+      var = data << PCIE_PHY_CTRL_DATA_LOC;
-+      writel(var, dbi_base + PCIE_PHY_CTRL);
-+
-+      /* wait for ack de-assertion */
-+      ret = pcie_phy_poll_ack(dbi_base, 0);
-+      if (ret)
-+              return ret;
-+
-+      writel(0x0, dbi_base + PCIE_PHY_CTRL);
-+
-+      return 0;
-+}
-+
-+/*  Added for PCI abort handling */
-+static int imx6q_pcie_abort_handler(unsigned long addr,
-+              unsigned int fsr, struct pt_regs *regs)
-+{
-+      /*
-+       * If it was an imprecise abort, then we need to correct the
-+       * return address to be _after_ the instruction.
-+       */
-+      if (fsr & (1 << 10))
-+              regs->ARM_pc += 4;
-+      return 0;
-+}
-+
-+static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
-+{
-+      struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
-+
-+      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-+                      IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
-+      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
-+                      IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
-+      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-+                      IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
-+
-+      gpio_set_value(imx6_pcie->reset_gpio, 0);
-+      msleep(100);
-+      gpio_set_value(imx6_pcie->reset_gpio, 1);
-+
-+      return 0;
-+}
-+
-+static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
-+{
-+      struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
-+      int ret;
-+
-+      if (gpio_is_valid(imx6_pcie->power_on_gpio))
-+              gpio_set_value(imx6_pcie->power_on_gpio, 1);
-+
-+      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-+                      IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
-+      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-+                      IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
-+
-+      ret = clk_prepare_enable(imx6_pcie->sata_ref_100m);
-+      if (ret) {
-+              dev_err(pp->dev, "unable to enable sata_ref_100m\n");
-+              goto err_sata_ref;
-+      }
-+
-+      ret = clk_prepare_enable(imx6_pcie->pcie_ref_125m);
-+      if (ret) {
-+              dev_err(pp->dev, "unable to enable pcie_ref_125m\n");
-+              goto err_pcie_ref;
-+      }
-+
-+      ret = clk_prepare_enable(imx6_pcie->lvds_gate);
-+      if (ret) {
-+              dev_err(pp->dev, "unable to enable lvds_gate\n");
-+              goto err_lvds_gate;
-+      }
-+
-+      ret = clk_prepare_enable(imx6_pcie->pcie_axi);
-+      if (ret) {
-+              dev_err(pp->dev, "unable to enable pcie_axi\n");
-+              goto err_pcie_axi;
-+      }
-+
-+      /* allow the clocks to stabilize */
-+      usleep_range(200, 500);
-+
-+      return 0;
-+
-+err_pcie_axi:
-+      clk_disable_unprepare(imx6_pcie->lvds_gate);
-+err_lvds_gate:
-+      clk_disable_unprepare(imx6_pcie->pcie_ref_125m);
-+err_pcie_ref:
-+      clk_disable_unprepare(imx6_pcie->sata_ref_100m);
-+err_sata_ref:
-+      return ret;
-+
-+}
-+
-+static void imx6_pcie_init_phy(struct pcie_port *pp)
-+{
-+      struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
-+
-+      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
-+                      IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
-+
-+      /* configure constant input signal to the pcie ctrl and phy */
-+      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
-+                      IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
-+      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
-+                      IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
-+
-+      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
-+                      IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
-+      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
-+                      IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6);
-+      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
-+                      IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12);
-+      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
-+                      IMX6Q_GPR8_TX_SWING_FULL, 127 << 18);
-+      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
-+                      IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
-+}
-+
-+static void imx6_pcie_host_init(struct pcie_port *pp)
-+{
-+      int count = 0;
-+      struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
-+
-+      imx6_pcie_assert_core_reset(pp);
-+
-+      imx6_pcie_init_phy(pp);
-+
-+      imx6_pcie_deassert_core_reset(pp);
-+
-+      dw_pcie_setup_rc(pp);
-+
-+      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
-+                      IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
-+
-+      while (!dw_pcie_link_up(pp)) {
-+              usleep_range(100, 1000);
-+              count++;
-+              if (count >= 10) {
-+                      dev_err(pp->dev, "phy link never came up\n");
-+                      dev_dbg(pp->dev,
-+                              "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
-+                              readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
-+                              readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
-+                      break;
-+              }
-+      }
-+
-+      return;
-+}
-+
-+static int imx6_pcie_link_up(struct pcie_port *pp)
-+{
-+      u32 rc, ltssm, rx_valid, temp;
-+
-+      /* link is debug bit 36, debug register 1 starts at bit 32 */
-+      rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & (0x1 << (36 - 32));
-+      if (rc)
-+              return -EAGAIN;
-+
-+      /*
-+       * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
-+       * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
-+       * If (MAC/LTSSM.state == Recovery.RcvrLock)
-+       * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
-+       * to gen2 is stuck
-+       */
-+      pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
-+      ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;
-+
-+      if (rx_valid & 0x01)
-+              return 0;
-+
-+      if (ltssm != 0x0d)
-+              return 0;
-+
-+      dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
-+
-+      pcie_phy_read(pp->dbi_base,
-+              PHY_RX_OVRD_IN_LO, &temp);
-+      temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN
-+              | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
-+      pcie_phy_write(pp->dbi_base,
-+              PHY_RX_OVRD_IN_LO, temp);
-+
-+      usleep_range(2000, 3000);
-+
-+      pcie_phy_read(pp->dbi_base,
-+              PHY_RX_OVRD_IN_LO, &temp);
-+      temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN
-+              | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
-+      pcie_phy_write(pp->dbi_base,
-+              PHY_RX_OVRD_IN_LO, temp);
-+
-+      return 0;
-+}
-+
-+static struct pcie_host_ops imx6_pcie_host_ops = {
-+      .link_up = imx6_pcie_link_up,
-+      .host_init = imx6_pcie_host_init,
-+};
-+
-+static int imx6_add_pcie_port(struct pcie_port *pp,
-+                      struct platform_device *pdev)
-+{
-+      int ret;
-+
-+      pp->irq = platform_get_irq(pdev, 0);
-+      if (!pp->irq) {
-+              dev_err(&pdev->dev, "failed to get irq\n");
-+              return -ENODEV;
-+      }
-+
-+      pp->root_bus_nr = -1;
-+      pp->ops = &imx6_pcie_host_ops;
-+
-+      spin_lock_init(&pp->conf_lock);
-+      ret = dw_pcie_host_init(pp);
-+      if (ret) {
-+              dev_err(&pdev->dev, "failed to initialize host\n");
-+              return ret;
-+      }
-+
-+      return 0;
-+}
-+
-+static int __init imx6_pcie_probe(struct platform_device *pdev)
-+{
-+      struct imx6_pcie *imx6_pcie;
-+      struct pcie_port *pp;
-+      struct device_node *np = pdev->dev.of_node;
-+      struct resource *dbi_base;
-+      int ret;
-+
-+      imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
-+      if (!imx6_pcie)
-+              return -ENOMEM;
-+
-+      pp = &imx6_pcie->pp;
-+      pp->dev = &pdev->dev;
-+
-+      /* Added for PCI abort handling */
-+      hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
-+              "imprecise external abort");
-+
-+      dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+      if (!dbi_base) {
-+              dev_err(&pdev->dev, "dbi_base memory resource not found\n");
-+              return -ENODEV;
-+      }
-+
-+      pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
-+      if (IS_ERR(pp->dbi_base)) {
-+              dev_err(&pdev->dev, "unable to remap dbi_base\n");
-+              ret = PTR_ERR(pp->dbi_base);
-+              goto err;
-+      }
-+
-+      /* Fetch GPIOs */
-+      imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
-+      if (!gpio_is_valid(imx6_pcie->reset_gpio)) {
-+              dev_err(&pdev->dev, "no reset-gpio defined\n");
-+              ret = -ENODEV;
-+      }
-+      ret = devm_gpio_request_one(&pdev->dev,
-+                              imx6_pcie->reset_gpio,
-+                              GPIOF_OUT_INIT_LOW,
-+                              "PCIe reset");
-+      if (ret) {
-+              dev_err(&pdev->dev, "unable to get reset gpio\n");
-+              goto err;
-+      }
-+
-+      imx6_pcie->power_on_gpio = of_get_named_gpio(np, "power-on-gpio", 0);
-+      if (gpio_is_valid(imx6_pcie->power_on_gpio)) {
-+              ret = devm_gpio_request_one(&pdev->dev,
-+                                      imx6_pcie->power_on_gpio,
-+                                      GPIOF_OUT_INIT_LOW,
-+                                      "PCIe power enable");
-+              if (ret) {
-+                      dev_err(&pdev->dev, "unable to get power-on gpio\n");
-+                      goto err;
-+              }
-+      }
-+
-+      imx6_pcie->wake_up_gpio = of_get_named_gpio(np, "wake-up-gpio", 0);
-+      if (gpio_is_valid(imx6_pcie->wake_up_gpio)) {
-+              ret = devm_gpio_request_one(&pdev->dev,
-+                                      imx6_pcie->wake_up_gpio,
-+                                      GPIOF_IN,
-+                                      "PCIe wake up");
-+              if (ret) {
-+                      dev_err(&pdev->dev, "unable to get wake-up gpio\n");
-+                      goto err;
-+              }
-+      }
-+
-+      imx6_pcie->disable_gpio = of_get_named_gpio(np, "disable-gpio", 0);
-+      if (gpio_is_valid(imx6_pcie->disable_gpio)) {
-+              ret = devm_gpio_request_one(&pdev->dev,
-+                                      imx6_pcie->disable_gpio,
-+                                      GPIOF_OUT_INIT_HIGH,
-+                                      "PCIe disable endpoint");
-+              if (ret) {
-+                      dev_err(&pdev->dev, "unable to get disable-ep gpio\n");
-+                      goto err;
-+              }
-+      }
-+
-+      /* Fetch clocks */
-+      imx6_pcie->lvds_gate = devm_clk_get(&pdev->dev, "lvds_gate");
-+      if (IS_ERR(imx6_pcie->lvds_gate)) {
-+              dev_err(&pdev->dev,
-+                      "lvds_gate clock select missing or invalid\n");
-+              ret = PTR_ERR(imx6_pcie->lvds_gate);
-+              goto err;
-+      }
-+
-+      imx6_pcie->sata_ref_100m = devm_clk_get(&pdev->dev, "sata_ref_100m");
-+      if (IS_ERR(imx6_pcie->sata_ref_100m)) {
-+              dev_err(&pdev->dev,
-+                      "sata_ref_100m clock source missing or invalid\n");
-+              ret = PTR_ERR(imx6_pcie->sata_ref_100m);
-+              goto err;
-+      }
-+
-+      imx6_pcie->pcie_ref_125m = devm_clk_get(&pdev->dev, "pcie_ref_125m");
-+      if (IS_ERR(imx6_pcie->pcie_ref_125m)) {
-+              dev_err(&pdev->dev,
-+                      "pcie_ref_125m clock source missing or invalid\n");
-+              ret = PTR_ERR(imx6_pcie->pcie_ref_125m);
-+              goto err;
-+      }
-+
-+      imx6_pcie->pcie_axi = devm_clk_get(&pdev->dev, "pcie_axi");
-+      if (IS_ERR(imx6_pcie->pcie_axi)) {
-+              dev_err(&pdev->dev,
-+                      "pcie_axi clock source missing or invalid\n");
-+              ret = PTR_ERR(imx6_pcie->pcie_axi);
-+              goto err;
-+      }
-+
-+      /* Grab GPR config register range */
-+      imx6_pcie->iomuxc_gpr =
-+               syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
-+      if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
-+              dev_err(&pdev->dev, "unable to find iomuxc registers\n");
-+              ret = PTR_ERR(imx6_pcie->iomuxc_gpr);
-+              goto err;
-+      }
-+
-+      ret = imx6_add_pcie_port(pp, pdev);
-+      if (ret < 0)
-+              goto err;
-+
-+      platform_set_drvdata(pdev, imx6_pcie);
-+      return 0;
-+
-+err:
-+      return ret;
-+}
-+
-+static const struct of_device_id imx6_pcie_of_match[] = {
-+      { .compatible = "fsl,imx6q-pcie", },
-+      {},
-+};
-+MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
-+
-+static struct platform_driver imx6_pcie_driver = {
-+      .driver = {
-+              .name   = "imx6q-pcie",
-+              .owner  = THIS_MODULE,
-+              .of_match_table = of_match_ptr(imx6_pcie_of_match),
-+      },
-+};
-+
-+/* Freescale PCIe driver does not allow module unload */
-+
-+static int __init imx6_pcie_init(void)
-+{
-+      return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
-+}
-+module_init(imx6_pcie_init);
-+
-+MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
-+MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/imx6/patches-3.10/0012-ARM-imx-Add-LVDS-general-purpose-clocks-to-i.MX6Q.patch b/target/linux/imx6/patches-3.10/0012-ARM-imx-Add-LVDS-general-purpose-clocks-to-i.MX6Q.patch
deleted file mode 100644 (file)
index 3f1b6eb..0000000
+++ /dev/null
@@ -1,70 +0,0 @@
-From: Sean Cross <xobs@kosagi.com>
-Subject: [PATCH 1/3] ARM: imx: Add LVDS general-purpose clocks to i.MX6Q
-
-The i.MX6 has two general-purpose LVDS clocks that can be driven
-from a variety of sources.  This patch adds a mux and a gate for
-both of these clocks.
-
-Signed-off-by: Sean Cross <xobs@kosagi.com>
-Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
----
- .../devicetree/bindings/clock/imx6q-clock.txt        |  4 ++++
- arch/arm/mach-imx/clk-imx6q.c                        | 20 +++++++++++++++++++-
- 2 files changed, 23 insertions(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
-+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
-@@ -208,6 +208,10 @@ clocks and IDs.
-       pll4_post_div           193
-       pll5_post_div           194
-       pll5_video_div          195
-+      lvds1_sel               204
-+      lvds2_sel               205
-+      lvds1_gate              206
-+      lvds2_gate              207
- Examples:
---- a/arch/arm/mach-imx/clk-imx6q.c
-+++ b/arch/arm/mach-imx/clk-imx6q.c
-@@ -205,6 +205,11 @@ static const char *vpu_axi_sels[] = { "a
- static const char *cko1_sels[]        = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
-                                   "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
-                                   "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", };
-+static const char *lvds_sels[] = {
-+      "dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
-+      "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",
-+      "pcie_ref", "sata_ref",
-+};
- enum mx6q_clks {
-       dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
-@@ -238,7 +243,8 @@ enum mx6q_clks {
-       pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
-       ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
-       sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
--      usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, clk_max
-+      usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div,
-+      lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, clk_max
- };
- static struct clk *clk[clk_max];
-@@ -340,6 +346,18 @@ int __init mx6q_clocks_init(void)
-                       base + 0xe0, 0, 2, 0, clk_enet_ref_table,
-                       &imx_ccm_lock);
-+      clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
-+      clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
-+
-+      /*
-+       * lvds1_gate and lvds2_gate are pseudo-gates.  Both can be
-+       * independently configured as clock inputs or outputs.  We treat
-+       * the "output_enable" bit as a gate, even though it's really just
-+       * enabling clock output.
-+       */
-+      clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10);
-+      clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11);
-+
-       /*                                name              parent_name        reg       idx */
-       clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus",     base + 0x100, 0);
-       clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus",     base + 0x100, 1);
diff --git a/target/linux/imx6/patches-3.10/0013-ARM-imx6q-clock-and-Kconfig-update-for-PCIe-support.patch b/target/linux/imx6/patches-3.10/0013-ARM-imx6q-clock-and-Kconfig-update-for-PCIe-support.patch
deleted file mode 100644 (file)
index 25f207a..0000000
+++ /dev/null
@@ -1,38 +0,0 @@
-From 4f6723e8ff497e35c8f2fb20886fccc533c58cdb Mon Sep 17 00:00:00 2001
-From: Sean Cross <xobs@kosagi.com>
-Date: Thu, 26 Sep 2013 10:45:35 +0800
-Subject: [PATCH] ARM: imx6q: clock and Kconfig update for PCIe support
-
-Update imx6q clock initialization and Kconfig for PCIe support.
-
-Signed-off-by: Sean Cross <xobs@kosagi.com>
-Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
----
- arch/arm/mach-imx/Kconfig     | 2 ++
- arch/arm/mach-imx/clk-imx6q.c | 4 ++++
- 2 files changed, 6 insertions(+)
-
---- a/arch/arm/mach-imx/Kconfig
-+++ b/arch/arm/mach-imx/Kconfig
-@@ -806,6 +806,8 @@ config SOC_IMX6Q
-       select HAVE_IMX_SRC
-       select HAVE_SMP
-       select MFD_SYSCON
-+      select MIGHT_HAVE_PCI
-+      select PCI_DOMAINS if PCI
-       select PINCTRL
-       select PINCTRL_IMX6Q
-       select PL310_ERRATA_588369 if CACHE_PL310
---- a/arch/arm/mach-imx/clk-imx6q.c
-+++ b/arch/arm/mach-imx/clk-imx6q.c
-@@ -586,6 +586,10 @@ int __init mx6q_clocks_init(void)
-               clk_prepare_enable(clk[usbphy2_gate]);
-       }
-+      /* All existing boards with PCIe use LVDS1 */
-+      if (IS_ENABLED(CONFIG_PCI_IMX6))
-+              clk_set_parent(clk[lvds1_sel], clk[sata_ref]);
-+
-       /* Set initial power mode */
-       imx6q_set_lpm(WAIT_CLOCKED);
diff --git a/target/linux/imx6/patches-3.10/0014-ARM-dts-imx6qdl-add-pcie-device-node.patch b/target/linux/imx6/patches-3.10/0014-ARM-dts-imx6qdl-add-pcie-device-node.patch
deleted file mode 100644 (file)
index e78d9ba..0000000
+++ /dev/null
@@ -1,38 +0,0 @@
-From 3a57291fa4ca7f7647d826f5b47082ef306d839f Mon Sep 17 00:00:00 2001
-From: Sean Cross <xobs@kosagi.com>
-Date: Thu, 26 Sep 2013 10:51:09 +0800
-Subject: [PATCH] ARM: dts: imx6qdl: add pcie device node
-
-Add pcie device node for imx6qdl.
-
-Signed-off-by: Sean Cross <xobs@kosagi.com>
-Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
----
- arch/arm/boot/dts/imx6qdl.dtsi | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
---- a/arch/arm/boot/dts/imx6qdl.dtsi
-+++ b/arch/arm/boot/dts/imx6qdl.dtsi
-@@ -108,6 +108,22 @@
-                       cache-level = <2>;
-               };
-+              pcie: pcie@0x01000000 {
-+                      compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
-+                      reg = <0x01ffc000 0x4000>; /* DBI */
-+                      #address-cells = <3>;
-+                      #size-cells = <2>;
-+                      device_type = "pci";
-+                      ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
-+                                0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
-+                                0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
-+                      num-lanes = <1>;
-+                      interrupts = <0 123 0x04>;
-+                      clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
-+                      clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
-+                      status = "disabled";
-+              };
-+
-               pmu {
-                       compatible = "arm,cortex-a9-pmu";
-                       interrupts = <0 94 0x04>;
diff --git a/target/linux/imx6/patches-3.10/0015-thermal-add-imx-thermal-driver-support.patch b/target/linux/imx6/patches-3.10/0015-thermal-add-imx-thermal-driver-support.patch
deleted file mode 100644 (file)
index 0b7ac7d..0000000
+++ /dev/null
@@ -1,477 +0,0 @@
-From ca3de46b50809000b5ba708634e26ad979a4a63a Mon Sep 17 00:00:00 2001
-From: Shawn Guo <shawn.guo@linaro.org>
-Date: Mon, 24 Jun 2013 14:30:44 +0800
-Subject: [PATCH] thermal: add imx thermal driver support
-
-This is based on the initial imx thermal work done by
-Rob Lee <rob.lee@linaro.org> (Not sure if the email address is still
-valid).  Since he is no longer interested in the work and I have
-rewritten a significant amount of the code, I just took the authorship
-over from him.
-
-It adds the imx thermal support using Temperature Monitor (TEMPMON)
-block found on some Freescale i.MX SoCs.  The driver uses syscon regmap
-interface to access TEMPMON control registers and calibration data, and
-supports cpufreq as the cooling device.
-
-Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
----
- .../devicetree/bindings/thermal/imx-thermal.txt    |  17 +
- drivers/thermal/Kconfig                            |  11 +
- drivers/thermal/Makefile                           |   1 +
- drivers/thermal/imx_thermal.c                      | 397 +++++++++++++++++++++
- 4 files changed, 426 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/thermal/imx-thermal.txt
- create mode 100644 drivers/thermal/imx_thermal.c
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/thermal/imx-thermal.txt
-@@ -0,0 +1,17 @@
-+* Temperature Monitor (TEMPMON) on Freescale i.MX SoCs
-+
-+Required properties:
-+- compatible : "fsl,imx6q-thermal"
-+- fsl,tempmon : phandle pointer to system controller that contains TEMPMON
-+  control registers, e.g. ANATOP on imx6q.
-+- fsl,tempmon-data : phandle pointer to fuse controller that contains TEMPMON
-+  calibration data, e.g. OCOTP on imx6q.  The details about calibration data
-+  can be found in SoC Reference Manual.
-+
-+Example:
-+
-+tempmon {
-+      compatible = "fsl,imx6q-tempmon";
-+      fsl,tempmon = <&anatop>;
-+      fsl,tempmon-data = <&ocotp>;
-+};
---- a/drivers/thermal/Kconfig
-+++ b/drivers/thermal/Kconfig
-@@ -91,6 +91,17 @@ config THERMAL_EMULATION
-         because userland can easily disable the thermal policy by simply
-         flooding this sysfs node with low temperature values.
-+config IMX_THERMAL
-+      tristate "Temperature sensor driver for Freescale i.MX SoCs"
-+      depends on CPU_THERMAL
-+      depends on MFD_SYSCON
-+      depends on OF
-+      help
-+        Support for Temperature Monitor (TEMPMON) found on Freescale i.MX SoCs.
-+        It supports one critical trip point and one passive trip point.  The
-+        cpufreq is used as the cooling device to throttle CPUs when the
-+        passive trip is crossed.
-+
- config SPEAR_THERMAL
-       bool "SPEAr thermal sensor driver"
-       depends on PLAT_SPEAR
---- a/drivers/thermal/Makefile
-+++ b/drivers/thermal/Makefile
-@@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_THERMAL) += exynos_t
- obj-$(CONFIG_DOVE_THERMAL)    += dove_thermal.o
- obj-$(CONFIG_DB8500_THERMAL)  += db8500_thermal.o
- obj-$(CONFIG_ARMADA_THERMAL)  += armada_thermal.o
-+obj-$(CONFIG_IMX_THERMAL)     += imx_thermal.o
- obj-$(CONFIG_DB8500_CPUFREQ_COOLING)  += db8500_cpufreq_cooling.o
- obj-$(CONFIG_INTEL_POWERCLAMP)        += intel_powerclamp.o
---- /dev/null
-+++ b/drivers/thermal/imx_thermal.c
-@@ -0,0 +1,397 @@
-+/*
-+ * Copyright 2013 Freescale Semiconductor, Inc.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
-+
-+#include <linux/cpu_cooling.h>
-+#include <linux/cpufreq.h>
-+#include <linux/delay.h>
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/regmap.h>
-+#include <linux/slab.h>
-+#include <linux/thermal.h>
-+#include <linux/types.h>
-+
-+#define REG_SET               0x4
-+#define REG_CLR               0x8
-+#define REG_TOG               0xc
-+
-+#define MISC0                         0x0150
-+#define MISC0_REFTOP_SELBIASOFF               (1 << 3)
-+
-+#define TEMPSENSE0                    0x0180
-+#define TEMPSENSE0_TEMP_CNT_SHIFT     8
-+#define TEMPSENSE0_TEMP_CNT_MASK      (0xfff << TEMPSENSE0_TEMP_CNT_SHIFT)
-+#define TEMPSENSE0_FINISHED           (1 << 2)
-+#define TEMPSENSE0_MEASURE_TEMP               (1 << 1)
-+#define TEMPSENSE0_POWER_DOWN         (1 << 0)
-+
-+#define TEMPSENSE1                    0x0190
-+#define TEMPSENSE1_MEASURE_FREQ               0xffff
-+
-+#define OCOTP_ANA1                    0x04e0
-+
-+/* The driver supports 1 passive trip point and 1 critical trip point */
-+enum imx_thermal_trip {
-+      IMX_TRIP_PASSIVE,
-+      IMX_TRIP_CRITICAL,
-+      IMX_TRIP_NUM,
-+};
-+
-+/*
-+ * It defines the temperature in millicelsius for passive trip point
-+ * that will trigger cooling action when crossed.
-+ */
-+#define IMX_TEMP_PASSIVE              85000
-+
-+/*
-+ * The maximum die temperature on imx parts is 105C, let's give some cushion
-+ * for noise and possible temperature rise between measurements.
-+ */
-+#define IMX_TEMP_CRITICAL             100000
-+
-+#define IMX_POLLING_DELAY             2000 /* millisecond */
-+#define IMX_PASSIVE_DELAY             1000
-+
-+struct imx_thermal_data {
-+      struct thermal_zone_device *tz;
-+      struct thermal_cooling_device *cdev;
-+      enum thermal_device_mode mode;
-+      struct regmap *tempmon;
-+      int c1, c2; /* See formula in imx_get_sensor_data() */
-+};
-+
-+static int imx_get_temp(struct thermal_zone_device *tz, unsigned long *temp)
-+{
-+      struct imx_thermal_data *data = tz->devdata;
-+      struct regmap *map = data->tempmon;
-+      static unsigned long last_temp;
-+      unsigned int n_meas;
-+      u32 val;
-+
-+      /*
-+       * Every time we measure the temperature, we will power on the
-+       * temperature sensor, enable measurements, take a reading,
-+       * disable measurements, power off the temperature sensor.
-+       */
-+      regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_POWER_DOWN);
-+      regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_MEASURE_TEMP);
-+
-+      /*
-+       * According to the temp sensor designers, it may require up to ~17us
-+       * to complete a measurement.
-+       */
-+      usleep_range(20, 50);
-+
-+      regmap_read(map, TEMPSENSE0, &val);
-+      regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_MEASURE_TEMP);
-+      regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_POWER_DOWN);
-+
-+      if ((val & TEMPSENSE0_FINISHED) == 0) {
-+              dev_dbg(&tz->device, "temp measurement never finished\n");
-+              return -EAGAIN;
-+      }
-+
-+      n_meas = (val & TEMPSENSE0_TEMP_CNT_MASK) >> TEMPSENSE0_TEMP_CNT_SHIFT;
-+
-+      /* See imx_get_sensor_data() for formula derivation */
-+      *temp = data->c2 + data->c1 * n_meas;
-+
-+      if (*temp != last_temp) {
-+              dev_dbg(&tz->device, "millicelsius: %ld\n", *temp);
-+              last_temp = *temp;
-+      }
-+
-+      return 0;
-+}
-+
-+static int imx_get_mode(struct thermal_zone_device *tz,
-+                      enum thermal_device_mode *mode)
-+{
-+      struct imx_thermal_data *data = tz->devdata;
-+
-+      *mode = data->mode;
-+
-+      return 0;
-+}
-+
-+static int imx_set_mode(struct thermal_zone_device *tz,
-+                      enum thermal_device_mode mode)
-+{
-+      struct imx_thermal_data *data = tz->devdata;
-+
-+      if (mode == THERMAL_DEVICE_ENABLED) {
-+              tz->polling_delay = IMX_POLLING_DELAY;
-+              tz->passive_delay = IMX_PASSIVE_DELAY;
-+      } else {
-+              tz->polling_delay = 0;
-+              tz->passive_delay = 0;
-+      }
-+
-+      data->mode = mode;
-+      thermal_zone_device_update(tz);
-+
-+      return 0;
-+}
-+
-+static int imx_get_trip_type(struct thermal_zone_device *tz, int trip,
-+                           enum thermal_trip_type *type)
-+{
-+      *type = (trip == IMX_TRIP_PASSIVE) ? THERMAL_TRIP_PASSIVE :
-+                                           THERMAL_TRIP_CRITICAL;
-+      return 0;
-+}
-+
-+static int imx_get_crit_temp(struct thermal_zone_device *tz,
-+                           unsigned long *temp)
-+{
-+      *temp = IMX_TEMP_CRITICAL;
-+      return 0;
-+}
-+
-+static int imx_get_trip_temp(struct thermal_zone_device *tz, int trip,
-+                           unsigned long *temp)
-+{
-+      *temp = (trip == IMX_TRIP_PASSIVE) ? IMX_TEMP_PASSIVE :
-+                                           IMX_TEMP_CRITICAL;
-+      return 0;
-+}
-+
-+static int imx_bind(struct thermal_zone_device *tz,
-+                  struct thermal_cooling_device *cdev)
-+{
-+      int ret;
-+
-+      ret = thermal_zone_bind_cooling_device(tz, IMX_TRIP_PASSIVE, cdev,
-+                                             THERMAL_NO_LIMIT,
-+                                             THERMAL_NO_LIMIT);
-+      if (ret) {
-+              dev_err(&tz->device,
-+                      "binding zone %s with cdev %s failed:%d\n",
-+                      tz->type, cdev->type, ret);
-+              return ret;
-+      }
-+
-+      return 0;
-+}
-+
-+static int imx_unbind(struct thermal_zone_device *tz,
-+                    struct thermal_cooling_device *cdev)
-+{
-+      int ret;
-+
-+      ret = thermal_zone_unbind_cooling_device(tz, IMX_TRIP_PASSIVE, cdev);
-+      if (ret) {
-+              dev_err(&tz->device,
-+                      "unbinding zone %s with cdev %s failed:%d\n",
-+                      tz->type, cdev->type, ret);
-+              return ret;
-+      }
-+
-+      return 0;
-+}
-+
-+static const struct thermal_zone_device_ops imx_tz_ops = {
-+      .bind = imx_bind,
-+      .unbind = imx_unbind,
-+      .get_temp = imx_get_temp,
-+      .get_mode = imx_get_mode,
-+      .set_mode = imx_set_mode,
-+      .get_trip_type = imx_get_trip_type,
-+      .get_trip_temp = imx_get_trip_temp,
-+      .get_crit_temp = imx_get_crit_temp,
-+};
-+
-+static int imx_get_sensor_data(struct platform_device *pdev)
-+{
-+      struct imx_thermal_data *data = platform_get_drvdata(pdev);
-+      struct regmap *map;
-+      int t1, t2, n1, n2;
-+      int ret;
-+      u32 val;
-+
-+      map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
-+                                            "fsl,tempmon-data");
-+      if (IS_ERR(map)) {
-+              ret = PTR_ERR(map);
-+              dev_err(&pdev->dev, "failed to get sensor regmap: %d\n", ret);
-+              return ret;
-+      }
-+
-+      ret = regmap_read(map, OCOTP_ANA1, &val);
-+      if (ret) {
-+              dev_err(&pdev->dev, "failed to read sensor data: %d\n", ret);
-+              return ret;
-+      }
-+
-+      if (val == 0 || val == ~0) {
-+              dev_err(&pdev->dev, "invalid sensor calibration data\n");
-+              return -EINVAL;
-+      }
-+
-+      /*
-+       * Sensor data layout:
-+       *   [31:20] - sensor value @ 25C
-+       *    [19:8] - sensor value of hot
-+       *     [7:0] - hot temperature value
-+       */
-+      n1 = val >> 20;
-+      n2 = (val & 0xfff00) >> 8;
-+      t2 = val & 0xff;
-+      t1 = 25; /* t1 always 25C */
-+
-+      /*
-+       * Derived from linear interpolation,
-+       * Tmeas = T2 + (Nmeas - N2) * (T1 - T2) / (N1 - N2)
-+       * We want to reduce this down to the minimum computation necessary
-+       * for each temperature read.  Also, we want Tmeas in millicelsius
-+       * and we don't want to lose precision from integer division. So...
-+       * milli_Tmeas = 1000 * T2 + 1000 * (Nmeas - N2) * (T1 - T2) / (N1 - N2)
-+       * Let constant c1 = 1000 * (T1 - T2) / (N1 - N2)
-+       * milli_Tmeas = (1000 * T2) + c1 * (Nmeas - N2)
-+       * milli_Tmeas = (1000 * T2) + (c1 * Nmeas) - (c1 * N2)
-+       * Let constant c2 = (1000 * T2) - (c1 * N2)
-+       * milli_Tmeas = c2 + (c1 * Nmeas)
-+       */
-+      data->c1 = 1000 * (t1 - t2) / (n1 - n2);
-+      data->c2 = 1000 * t2 - data->c1 * n2;
-+
-+      return 0;
-+}
-+
-+static int imx_thermal_probe(struct platform_device *pdev)
-+{
-+      struct imx_thermal_data *data;
-+      struct cpumask clip_cpus;
-+      struct regmap *map;
-+      int ret;
-+
-+      data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
-+      if (!data)
-+              return -ENOMEM;
-+
-+      map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "fsl,tempmon");
-+      if (IS_ERR(map)) {
-+              ret = PTR_ERR(map);
-+              dev_err(&pdev->dev, "failed to get tempmon regmap: %d\n", ret);
-+              return ret;
-+      }
-+      data->tempmon = map;
-+
-+      platform_set_drvdata(pdev, data);
-+
-+      ret = imx_get_sensor_data(pdev);
-+      if (ret) {
-+              dev_err(&pdev->dev, "failed to get sensor data\n");
-+              return ret;
-+      }
-+
-+      /* Make sure sensor is in known good state for measurements */
-+      regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_POWER_DOWN);
-+      regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_MEASURE_TEMP);
-+      regmap_write(map, TEMPSENSE1 + REG_CLR, TEMPSENSE1_MEASURE_FREQ);
-+      regmap_write(map, MISC0 + REG_SET, MISC0_REFTOP_SELBIASOFF);
-+      regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_POWER_DOWN);
-+
-+      cpumask_set_cpu(0, &clip_cpus);
-+      data->cdev = cpufreq_cooling_register(&clip_cpus);
-+      if (IS_ERR(data->cdev)) {
-+              ret = PTR_ERR(data->cdev);
-+              dev_err(&pdev->dev,
-+                      "failed to register cpufreq cooling device: %d\n", ret);
-+              return ret;
-+      }
-+
-+      data->tz = thermal_zone_device_register("imx_thermal_zone",
-+                                              IMX_TRIP_NUM, 0, data,
-+                                              &imx_tz_ops, NULL,
-+                                              IMX_PASSIVE_DELAY,
-+                                              IMX_POLLING_DELAY);
-+      if (IS_ERR(data->tz)) {
-+              ret = PTR_ERR(data->tz);
-+              dev_err(&pdev->dev,
-+                      "failed to register thermal zone device %d\n", ret);
-+              cpufreq_cooling_unregister(data->cdev);
-+              return ret;
-+      }
-+
-+      data->mode = THERMAL_DEVICE_ENABLED;
-+
-+      return 0;
-+}
-+
-+static int imx_thermal_remove(struct platform_device *pdev)
-+{
-+      struct imx_thermal_data *data = platform_get_drvdata(pdev);
-+
-+      thermal_zone_device_unregister(data->tz);
-+      cpufreq_cooling_unregister(data->cdev);
-+
-+      return 0;
-+}
-+
-+#ifdef CONFIG_PM_SLEEP
-+static int imx_thermal_suspend(struct device *dev)
-+{
-+      struct imx_thermal_data *data = dev_get_drvdata(dev);
-+      struct regmap *map = data->tempmon;
-+      u32 val;
-+
-+      regmap_read(map, TEMPSENSE0, &val);
-+      if ((val & TEMPSENSE0_POWER_DOWN) == 0) {
-+              /*
-+               * If a measurement is taking place, wait for a long enough
-+               * time for it to finish, and then check again.  If it still
-+               * does not finish, something must go wrong.
-+               */
-+              udelay(50);
-+              regmap_read(map, TEMPSENSE0, &val);
-+              if ((val & TEMPSENSE0_POWER_DOWN) == 0)
-+                      return -ETIMEDOUT;
-+      }
-+
-+      return 0;
-+}
-+
-+static int imx_thermal_resume(struct device *dev)
-+{
-+      /* Nothing to do for now */
-+      return 0;
-+}
-+#endif
-+
-+static SIMPLE_DEV_PM_OPS(imx_thermal_pm_ops,
-+                       imx_thermal_suspend, imx_thermal_resume);
-+
-+static const struct of_device_id of_imx_thermal_match[] = {
-+      { .compatible = "fsl,imx6q-tempmon", },
-+      { /* end */ }
-+};
-+
-+static struct platform_driver imx_thermal = {
-+      .driver = {
-+              .name   = "imx_thermal",
-+              .owner  = THIS_MODULE,
-+              .pm     = &imx_thermal_pm_ops,
-+              .of_match_table = of_imx_thermal_match,
-+      },
-+      .probe          = imx_thermal_probe,
-+      .remove         = imx_thermal_remove,
-+};
-+module_platform_driver(imx_thermal);
-+
-+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
-+MODULE_DESCRIPTION("Thermal driver for Freescale i.MX SoCs");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform:imx-thermal");
diff --git a/target/linux/imx6/patches-3.10/0019-regulator-pfuze100-add-pfuze100-regulator-driver.patch b/target/linux/imx6/patches-3.10/0019-regulator-pfuze100-add-pfuze100-regulator-driver.patch
deleted file mode 100644 (file)
index cbce5e7..0000000
+++ /dev/null
@@ -1,667 +0,0 @@
-From 3784b6d64dc52ed3fbebad61a85ab9b7a687a167 Mon Sep 17 00:00:00 2001
-From: Robin Gong <b38343@freescale.com>
-Date: Thu, 25 Jul 2013 11:33:18 +0800
-Subject: [PATCH] regulator: pfuze100: add pfuze100 regulator driver
-
-Add pfuze100 regulator driver.
-
-Signed-off-by: Robin Gong <b38343@freescale.com>
-Tested-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
-Signed-off-by: Mark Brown <broonie@linaro.org>
----
- .../devicetree/bindings/regulator/pfuze100.txt     | 113 +++++
- drivers/regulator/Kconfig                          |   7 +
- drivers/regulator/Makefile                         |   1 +
- drivers/regulator/pfuze100-regulator.c             | 454 +++++++++++++++++++++
- include/linux/regulator/pfuze100.h                 |  44 ++
- 5 files changed, 619 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/regulator/pfuze100.txt
- create mode 100644 drivers/regulator/pfuze100-regulator.c
- create mode 100644 include/linux/regulator/pfuze100.h
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/regulator/pfuze100.txt
-@@ -0,0 +1,113 @@
-+PFUZE100 family of regulators
-+
-+Required properties:
-+- compatible: "fsl,pfuze100"
-+- reg: I2C slave address
-+- regulators: This is the list of child nodes that specify the regulator
-+  initialization data for defined regulators. Please refer to below doc
-+  Documentation/devicetree/bindings/regulator/regulator.txt.
-+
-+  The valid names for regulators are:
-+  sw1ab,sw1c,sw2,sw3a,sw3b,sw4,swbst,vsnvs,vrefddr,vgen1~vgen6
-+
-+Each regulator is defined using the standard binding for regulators.
-+
-+Example:
-+
-+      pmic: pfuze100@08 {
-+              compatible = "fsl,pfuze100";
-+              reg = <0x08>;
-+
-+              regulators {
-+                      sw1a_reg: sw1ab {
-+                              regulator-min-microvolt = <300000>;
-+                              regulator-max-microvolt = <1875000>;
-+                              regulator-boot-on;
-+                              regulator-always-on;
-+                              regulator-ramp-delay = <6250>;
-+                      };
-+
-+                      sw1c_reg: sw1c {
-+                              regulator-min-microvolt = <300000>;
-+                              regulator-max-microvolt = <1875000>;
-+                              regulator-boot-on;
-+                              regulator-always-on;
-+                      };
-+
-+                      sw2_reg: sw2 {
-+                              regulator-min-microvolt = <800000>;
-+                              regulator-max-microvolt = <3300000>;
-+                              regulator-boot-on;
-+                              regulator-always-on;
-+                      };
-+
-+                      sw3a_reg: sw3a {
-+                              regulator-min-microvolt = <400000>;
-+                              regulator-max-microvolt = <1975000>;
-+                              regulator-boot-on;
-+                              regulator-always-on;
-+                      };
-+
-+                      sw3b_reg: sw3b {
-+                              regulator-min-microvolt = <400000>;
-+                              regulator-max-microvolt = <1975000>;
-+                              regulator-boot-on;
-+                              regulator-always-on;
-+                      };
-+
-+                      sw4_reg: sw4 {
-+                              regulator-min-microvolt = <800000>;
-+                              regulator-max-microvolt = <3300000>;
-+                      };
-+
-+                      swbst_reg: swbst {
-+                              regulator-min-microvolt = <5000000>;
-+                              regulator-max-microvolt = <5150000>;
-+                      };
-+
-+                      snvs_reg: vsnvs {
-+                              regulator-min-microvolt = <1000000>;
-+                              regulator-max-microvolt = <3000000>;
-+                              regulator-boot-on;
-+                              regulator-always-on;
-+                      };
-+
-+                      vref_reg: vrefddr {
-+                              regulator-boot-on;
-+                              regulator-always-on;
-+                      };
-+
-+                      vgen1_reg: vgen1 {
-+                              regulator-min-microvolt = <800000>;
-+                              regulator-max-microvolt = <1550000>;
-+                      };
-+
-+                      vgen2_reg: vgen2 {
-+                              regulator-min-microvolt = <800000>;
-+                              regulator-max-microvolt = <1550000>;
-+                      };
-+
-+                      vgen3_reg: vgen3 {
-+                              regulator-min-microvolt = <1800000>;
-+                              regulator-max-microvolt = <3300000>;
-+                      };
-+
-+                      vgen4_reg: vgen4 {
-+                              regulator-min-microvolt = <1800000>;
-+                              regulator-max-microvolt = <3300000>;
-+                              regulator-always-on;
-+                      };
-+
-+                      vgen5_reg: vgen5 {
-+                              regulator-min-microvolt = <1800000>;
-+                              regulator-max-microvolt = <3300000>;
-+                              regulator-always-on;
-+                      };
-+
-+                      vgen6_reg: vgen6 {
-+                              regulator-min-microvolt = <1800000>;
-+                              regulator-max-microvolt = <3300000>;
-+                              regulator-always-on;
-+                      };
-+              };
-+      };
---- a/drivers/regulator/Kconfig
-+++ b/drivers/regulator/Kconfig
-@@ -300,6 +300,13 @@ config REGULATOR_PCF50633
-        Say Y here to support the voltage regulators and convertors
-        on PCF50633
-+config REGULATOR_PFUZE100
-+      tristate "Support regulators on Freescale PFUZE100 PMIC"
-+      depends on I2C
-+      help
-+        Say y here to support the regulators found on the Freescale PFUZE100
-+        PMIC.
-+
- config REGULATOR_RC5T583
-       tristate "RICOH RC5T583 Power regulators"
-       depends on MFD_RC5T583
---- a/drivers/regulator/Makefile
-+++ b/drivers/regulator/Makefile
-@@ -45,6 +45,7 @@ obj-$(CONFIG_REGULATOR_MC13783) += mc137
- obj-$(CONFIG_REGULATOR_MC13892) += mc13892-regulator.o
- obj-$(CONFIG_REGULATOR_MC13XXX_CORE) +=  mc13xxx-regulator-core.o
- obj-$(CONFIG_REGULATOR_PALMAS) += palmas-regulator.o
-+obj-$(CONFIG_REGULATOR_PFUZE100) += pfuze100-regulator.o
- obj-$(CONFIG_REGULATOR_TPS51632) += tps51632-regulator.o
- obj-$(CONFIG_REGULATOR_PCAP) += pcap-regulator.o
- obj-$(CONFIG_REGULATOR_PCF50633) += pcf50633-regulator.o
---- /dev/null
-+++ b/drivers/regulator/pfuze100-regulator.c
-@@ -0,0 +1,454 @@
-+/*
-+ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
-+ */
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/err.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/regulator/of_regulator.h>
-+#include <linux/platform_device.h>
-+#include <linux/regulator/driver.h>
-+#include <linux/regulator/machine.h>
-+#include <linux/regulator/pfuze100.h>
-+#include <linux/i2c.h>
-+#include <linux/slab.h>
-+#include <linux/regmap.h>
-+
-+#define PFUZE_NUMREGS         128
-+#define PFUZE100_VOL_OFFSET   0
-+#define PFUZE100_STANDBY_OFFSET       1
-+#define PFUZE100_MODE_OFFSET  3
-+#define PFUZE100_CONF_OFFSET  4
-+
-+#define PFUZE100_DEVICEID     0x0
-+#define PFUZE100_REVID                0x3
-+#define PFUZE100_FABID                0x3
-+
-+#define PFUZE100_SW1ABVOL     0x20
-+#define PFUZE100_SW1CVOL      0x2e
-+#define PFUZE100_SW2VOL               0x35
-+#define PFUZE100_SW3AVOL      0x3c
-+#define PFUZE100_SW3BVOL      0x43
-+#define PFUZE100_SW4VOL               0x4a
-+#define PFUZE100_SWBSTCON1    0x66
-+#define PFUZE100_VREFDDRCON   0x6a
-+#define PFUZE100_VSNVSVOL     0x6b
-+#define PFUZE100_VGEN1VOL     0x6c
-+#define PFUZE100_VGEN2VOL     0x6d
-+#define PFUZE100_VGEN3VOL     0x6e
-+#define PFUZE100_VGEN4VOL     0x6f
-+#define PFUZE100_VGEN5VOL     0x70
-+#define PFUZE100_VGEN6VOL     0x71
-+
-+struct pfuze_regulator {
-+      struct regulator_desc desc;
-+      unsigned char stby_reg;
-+      unsigned char stby_mask;
-+};
-+
-+struct pfuze_chip {
-+      struct regmap *regmap;
-+      struct device *dev;
-+      struct pfuze_regulator regulator_descs[PFUZE100_MAX_REGULATOR];
-+      struct regulator_dev *regulators[PFUZE100_MAX_REGULATOR];
-+};
-+
-+static const int pfuze100_swbst[] = {
-+      5000000, 5050000, 5100000, 5150000,
-+};
-+
-+static const int pfuze100_vsnvs[] = {
-+      1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000,
-+};
-+
-+static const struct i2c_device_id pfuze_device_id[] = {
-+      {.name = "pfuze100"},
-+      {},
-+};
-+MODULE_DEVICE_TABLE(i2c, pfuze_device_id);
-+
-+static const struct of_device_id pfuze_dt_ids[] = {
-+      { .compatible = "fsl,pfuze100" },
-+      {},
-+};
-+MODULE_DEVICE_TABLE(of, pfuze_dt_ids);
-+
-+static int pfuze100_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
-+{
-+      struct pfuze_chip *pfuze100 = rdev_get_drvdata(rdev);
-+      int id = rdev->desc->id;
-+      unsigned int val, ramp_bits, reg;
-+      int ret;
-+
-+      if (id < PFUZE100_SWBST) {
-+              if (id == PFUZE100_SW1AB)
-+                      reg = PFUZE100_SW1ABVOL;
-+              else
-+                      reg = PFUZE100_SW1CVOL + (id - PFUZE100_SW1C) * 7;
-+              regmap_read(pfuze100->regmap, reg, &val);
-+
-+              if (id <= PFUZE100_SW1C)
-+                      ramp_delay = 25000 / (2 * ramp_delay);
-+              else if (val & 0x40)
-+                      ramp_delay = 50000 / (4 * ramp_delay);
-+              else
-+                      ramp_delay = 25000 / (2 * ramp_delay);
-+
-+              ramp_bits = (ramp_delay >> 1) - (ramp_delay >> 3);
-+              ret = regmap_update_bits(pfuze100->regmap, reg + 4 , 0xc0,
-+                              ramp_bits << 6);
-+              if (ret < 0)
-+                      dev_err(pfuze100->dev, "ramp failed, err %d\n", ret);
-+      } else
-+              ret = -EACCES;
-+
-+      return ret;
-+}
-+
-+static struct regulator_ops pfuze100_ldo_regulator_ops = {
-+      .enable = regulator_enable_regmap,
-+      .disable = regulator_disable_regmap,
-+      .is_enabled = regulator_is_enabled_regmap,
-+      .list_voltage = regulator_list_voltage_linear,
-+      .set_voltage_sel = regulator_set_voltage_sel_regmap,
-+      .get_voltage_sel = regulator_get_voltage_sel_regmap,
-+};
-+
-+static struct regulator_ops pfuze100_fixed_regulator_ops = {
-+      .list_voltage = regulator_list_voltage_linear,
-+};
-+
-+static struct regulator_ops pfuze100_sw_regulator_ops = {
-+      .list_voltage = regulator_list_voltage_linear,
-+      .set_voltage_sel = regulator_set_voltage_sel_regmap,
-+      .get_voltage_sel = regulator_get_voltage_sel_regmap,
-+      .set_voltage_time_sel = regulator_set_voltage_time_sel,
-+      .set_ramp_delay = pfuze100_set_ramp_delay,
-+};
-+
-+static struct regulator_ops pfuze100_swb_regulator_ops = {
-+      .list_voltage = regulator_list_voltage_table,
-+      .set_voltage_sel = regulator_set_voltage_sel_regmap,
-+      .get_voltage_sel = regulator_get_voltage_sel_regmap,
-+
-+};
-+
-+#define PFUZE100_FIXED_REG(_name, base, voltage)      \
-+      [PFUZE100_ ## _name] = {        \
-+              .desc = {       \
-+                      .name = #_name, \
-+                      .n_voltages = 1,        \
-+                      .ops = &pfuze100_fixed_regulator_ops,   \
-+                      .type = REGULATOR_VOLTAGE,      \
-+                      .id = PFUZE100_ ## _name,       \
-+                      .owner = THIS_MODULE,   \
-+                      .min_uV = (voltage),    \
-+                      .enable_reg = (base),   \
-+                      .enable_mask = 0x10,    \
-+              },      \
-+      }
-+
-+#define PFUZE100_SW_REG(_name, base, min, max, step)  \
-+      [PFUZE100_ ## _name] = {        \
-+              .desc = {       \
-+                      .name = #_name,\
-+                      .n_voltages = ((max) - (min)) / (step) + 1,     \
-+                      .ops = &pfuze100_sw_regulator_ops,      \
-+                      .type = REGULATOR_VOLTAGE,      \
-+                      .id = PFUZE100_ ## _name,       \
-+                      .owner = THIS_MODULE,   \
-+                      .min_uV = (min),        \
-+                      .uV_step = (step),      \
-+                      .vsel_reg = (base) + PFUZE100_VOL_OFFSET,       \
-+                      .vsel_mask = 0x3f,      \
-+              },      \
-+              .stby_reg = (base) + PFUZE100_STANDBY_OFFSET,   \
-+              .stby_mask = 0x3f,      \
-+      }
-+
-+#define PFUZE100_SWB_REG(_name, base, mask, voltages) \
-+      [PFUZE100_ ## _name] = {        \
-+              .desc = {       \
-+                      .name = #_name, \
-+                      .n_voltages = ARRAY_SIZE(voltages),     \
-+                      .ops = &pfuze100_swb_regulator_ops,     \
-+                      .type = REGULATOR_VOLTAGE,      \
-+                      .id = PFUZE100_ ## _name,       \
-+                      .owner = THIS_MODULE,   \
-+                      .volt_table = voltages, \
-+                      .vsel_reg = (base),     \
-+                      .vsel_mask = (mask),    \
-+              },      \
-+      }
-+
-+#define PFUZE100_VGEN_REG(_name, base, min, max, step)        \
-+      [PFUZE100_ ## _name] = {        \
-+              .desc = {       \
-+                      .name = #_name, \
-+                      .n_voltages = ((max) - (min)) / (step) + 1,     \
-+                      .ops = &pfuze100_ldo_regulator_ops,     \
-+                      .type = REGULATOR_VOLTAGE,      \
-+                      .id = PFUZE100_ ## _name,       \
-+                      .owner = THIS_MODULE,   \
-+                      .min_uV = (min),        \
-+                      .uV_step = (step),      \
-+                      .vsel_reg = (base),     \
-+                      .vsel_mask = 0xf,       \
-+                      .enable_reg = (base),   \
-+                      .enable_mask = 0x10,    \
-+              },      \
-+              .stby_reg = (base),     \
-+              .stby_mask = 0x20,      \
-+      }
-+
-+static struct pfuze_regulator pfuze100_regulators[] = {
-+      PFUZE100_SW_REG(SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
-+      PFUZE100_SW_REG(SW1C, PFUZE100_SW1CVOL, 300000, 1875000, 25000),
-+      PFUZE100_SW_REG(SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
-+      PFUZE100_SW_REG(SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
-+      PFUZE100_SW_REG(SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
-+      PFUZE100_SW_REG(SW4, PFUZE100_SW4VOL, 400000, 1975000, 25000),
-+      PFUZE100_SWB_REG(SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
-+      PFUZE100_SWB_REG(VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
-+      PFUZE100_FIXED_REG(VREFDDR, PFUZE100_VREFDDRCON, 750000),
-+      PFUZE100_VGEN_REG(VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
-+      PFUZE100_VGEN_REG(VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
-+      PFUZE100_VGEN_REG(VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
-+      PFUZE100_VGEN_REG(VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
-+      PFUZE100_VGEN_REG(VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
-+      PFUZE100_VGEN_REG(VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
-+};
-+
-+#ifdef CONFIG_OF
-+static struct of_regulator_match pfuze100_matches[] = {
-+      { .name = "sw1ab",      },
-+      { .name = "sw1c",       },
-+      { .name = "sw2",        },
-+      { .name = "sw3a",       },
-+      { .name = "sw3b",       },
-+      { .name = "sw4",        },
-+      { .name = "swbst",      },
-+      { .name = "vsnvs",      },
-+      { .name = "vrefddr",    },
-+      { .name = "vgen1",      },
-+      { .name = "vgen2",      },
-+      { .name = "vgen3",      },
-+      { .name = "vgen4",      },
-+      { .name = "vgen5",      },
-+      { .name = "vgen6",      },
-+};
-+
-+static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
-+{
-+      struct device *dev = chip->dev;
-+      struct device_node *np, *parent;
-+      int ret;
-+
-+      np = of_node_get(dev->parent->of_node);
-+      if (!np)
-+              return 0;
-+
-+      parent = of_find_node_by_name(np, "regulators");
-+      if (!parent) {
-+              dev_err(dev, "regulators node not found\n");
-+              return -EINVAL;
-+      }
-+
-+      ret = of_regulator_match(dev, parent, pfuze100_matches,
-+                               ARRAY_SIZE(pfuze100_matches));
-+
-+      of_node_put(parent);
-+      if (ret < 0) {
-+              dev_err(dev, "Error parsing regulator init data: %d\n",
-+                      ret);
-+              return ret;
-+      }
-+
-+      return 0;
-+}
-+
-+static inline struct regulator_init_data *match_init_data(int index)
-+{
-+      return pfuze100_matches[index].init_data;
-+}
-+
-+static inline struct device_node *match_of_node(int index)
-+{
-+      return pfuze100_matches[index].of_node;
-+}
-+#else
-+static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
-+{
-+      return NULL;
-+}
-+
-+static inline struct regulator_init_data *match_init_data(int index)
-+{
-+      return NULL;
-+}
-+
-+static inline struct device_node *match_of_node(int index)
-+{
-+      return NULL;
-+}
-+#endif
-+
-+static int pfuze_identify(struct pfuze_chip *pfuze_chip)
-+{
-+      unsigned int value;
-+      int ret;
-+
-+      ret = regmap_read(pfuze_chip->regmap, PFUZE100_DEVICEID, &value);
-+      if (ret)
-+              return ret;
-+
-+      if (value & 0x0f) {
-+              dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value);
-+              return -ENODEV;
-+      }
-+
-+      ret = regmap_read(pfuze_chip->regmap, PFUZE100_REVID, &value);
-+      if (ret)
-+              return ret;
-+      dev_info(pfuze_chip->dev,
-+               "Full lay: %x, Metal lay: %x\n",
-+               (value & 0xf0) >> 4, value & 0x0f);
-+
-+      ret = regmap_read(pfuze_chip->regmap, PFUZE100_FABID, &value);
-+      if (ret)
-+              return ret;
-+      dev_info(pfuze_chip->dev, "FAB: %x, FIN: %x\n",
-+               (value & 0xc) >> 2, value & 0x3);
-+
-+      return 0;
-+}
-+
-+static const struct regmap_config pfuze_regmap_config = {
-+      .reg_bits = 8,
-+      .val_bits = 8,
-+      .max_register = PFUZE_NUMREGS,
-+      .cache_type = REGCACHE_RBTREE,
-+};
-+
-+static int pfuze100_regulator_probe(struct i2c_client *client,
-+                                  const struct i2c_device_id *id)
-+{
-+      struct pfuze_chip *pfuze_chip;
-+      struct pfuze_regulator_platform_data *pdata =
-+          dev_get_platdata(&client->dev);
-+      struct regulator_config config = { };
-+      int i, ret;
-+
-+      pfuze_chip = devm_kzalloc(&client->dev, sizeof(*pfuze_chip),
-+                      GFP_KERNEL);
-+      if (!pfuze_chip)
-+              return -ENOMEM;
-+
-+      dev_set_drvdata(&client->dev, pfuze_chip);
-+
-+      memcpy(pfuze_chip->regulator_descs, pfuze100_regulators,
-+              sizeof(pfuze_chip->regulator_descs));
-+
-+      pfuze_chip->dev = &client->dev;
-+
-+      pfuze_chip->regmap = devm_regmap_init_i2c(client, &pfuze_regmap_config);
-+      if (IS_ERR(pfuze_chip->regmap)) {
-+              ret = PTR_ERR(pfuze_chip->regmap);
-+              dev_err(&client->dev,
-+                      "regmap allocation failed with err %d\n", ret);
-+              return ret;
-+      }
-+
-+      ret = pfuze_identify(pfuze_chip);
-+      if (ret) {
-+              dev_err(&client->dev, "unrecognized pfuze chip ID!\n");
-+              return ret;
-+      }
-+
-+      ret = pfuze_parse_regulators_dt(pfuze_chip);
-+      if (ret)
-+              return ret;
-+
-+      for (i = 0; i < PFUZE100_MAX_REGULATOR; i++) {
-+              struct regulator_init_data *init_data;
-+              int val;
-+
-+              if (pdata)
-+                      init_data = pdata->init_data[i];
-+              else
-+                      init_data = match_init_data(i);
-+
-+              /* SW2~SW4 high bit check and modify the voltage value table */
-+              if (i > PFUZE100_SW1C && i < PFUZE100_SWBST) {
-+                      regmap_read(pfuze_chip->regmap, PFUZE100_SW2VOL +
-+                                      (i - PFUZE100_SW2) * 7, &val);
-+                      if (val & 0x40) {
-+                              pfuze_chip->regulator_descs[i].desc.min_uV
-+                              = 800000;
-+                              pfuze_chip->regulator_descs[i].desc.uV_step
-+                              = 50000;
-+                      }
-+              }
-+
-+              config.dev = &client->dev;
-+              config.init_data = init_data;
-+              config.driver_data = pfuze_chip;
-+              config.of_node = match_of_node(i);
-+
-+              pfuze_chip->regulators[i] = regulator_register(&pfuze_chip
-+                      ->regulator_descs[i].desc, &config);
-+              if (IS_ERR(pfuze_chip->regulators[i])) {
-+                      dev_err(&client->dev, "register regulator%s failed\n",
-+                              pfuze100_regulators[i].desc.name);
-+                      ret = PTR_ERR(pfuze_chip->regulators[i]);
-+                      while (--i >= 0)
-+                              regulator_unregister(pfuze_chip->regulators[i]);
-+                      return ret;
-+              }
-+      }
-+
-+      return 0;
-+}
-+
-+static int pfuze100_regulator_remove(struct i2c_client *client)
-+{
-+      int i;
-+      struct pfuze_chip *pfuze_chip = dev_get_drvdata(&client->dev);
-+
-+      for (i = 0; i < PFUZE100_MAX_REGULATOR; i++)
-+              regulator_unregister(pfuze_chip->regulators[i]);
-+
-+      return 0;
-+}
-+
-+static struct i2c_driver pfuze_driver = {
-+      .id_table = pfuze_device_id,
-+      .driver = {
-+              .name = "pfuze100-regulator",
-+              .owner = THIS_MODULE,
-+              .of_match_table = pfuze_dt_ids,
-+      },
-+      .probe = pfuze100_regulator_probe,
-+      .remove = pfuze100_regulator_remove,
-+};
-+module_i2c_driver(pfuze_driver);
-+
-+MODULE_AUTHOR("Robin Gong <b38343@freescale.com>");
-+MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100 PMIC");
-+MODULE_ALIAS("pfuze100-regulator");
---- /dev/null
-+++ b/include/linux/regulator/pfuze100.h
-@@ -0,0 +1,44 @@
-+/*
-+ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-+ */
-+#ifndef __LINUX_REG_PFUZE100_H
-+#define __LINUX_REG_PFUZE100_H
-+
-+#define PFUZE100_SW1AB                0
-+#define PFUZE100_SW1C         1
-+#define PFUZE100_SW2          2
-+#define PFUZE100_SW3A         3
-+#define PFUZE100_SW3B         4
-+#define PFUZE100_SW4          5
-+#define PFUZE100_SWBST                6
-+#define PFUZE100_VSNVS                7
-+#define PFUZE100_VREFDDR      8
-+#define PFUZE100_VGEN1                9
-+#define PFUZE100_VGEN2                10
-+#define PFUZE100_VGEN3                11
-+#define PFUZE100_VGEN4                12
-+#define PFUZE100_VGEN5                13
-+#define PFUZE100_VGEN6                14
-+#define PFUZE100_MAX_REGULATOR        15
-+
-+struct regulator_init_data;
-+
-+struct pfuze_regulator_platform_data {
-+      struct regulator_init_data *init_data[PFUZE100_MAX_REGULATOR];
-+};
-+
-+#endif /* __LINUX_REG_PFUZE100_H */
diff --git a/target/linux/imx6/patches-3.10/0020-regulator-pfuze100-REGULATOR_PFUZE100-needs-to-selec.patch b/target/linux/imx6/patches-3.10/0020-regulator-pfuze100-REGULATOR_PFUZE100-needs-to-selec.patch
deleted file mode 100644 (file)
index 2a9fdff..0000000
+++ /dev/null
@@ -1,44 +0,0 @@
-From: Axel Lin <axel.lin@ingics.com>
-Subject: [PATCH] regulator: pfuze100: REGULATOR_PFUZE100 needs to select
- REGMAP_I2C
-
-This fixes below build errors:
-
-  CC [M]  drivers/regulator/pfuze100-regulator.o
-drivers/regulator/pfuze100-regulator.c:342:21: error: variable 'pfuze_regmap_config' has initializer but incomplete type
-drivers/regulator/pfuze100-regulator.c:343:2: error: unknown field 'reg_bits' specified in initializer
-drivers/regulator/pfuze100-regulator.c:343:2: warning: excess elements in struct initializer [enabled by default]
-drivers/regulator/pfuze100-regulator.c:343:2: warning: (near initialization for 'pfuze_regmap_config') [enabled by default]
-drivers/regulator/pfuze100-regulator.c:344:2: error: unknown field 'val_bits' specified in initializer
-drivers/regulator/pfuze100-regulator.c:344:2: warning: excess elements in struct initializer [enabled by default]
-drivers/regulator/pfuze100-regulator.c:344:2: warning: (near initialization for 'pfuze_regmap_config') [enabled by default]
-drivers/regulator/pfuze100-regulator.c:345:2: error: unknown field 'max_register' specified in initializer
-drivers/regulator/pfuze100-regulator.c:345:2: warning: excess elements in struct initializer [enabled by default]
-drivers/regulator/pfuze100-regulator.c:345:2: warning: (near initialization for 'pfuze_regmap_config') [enabled by default]
-drivers/regulator/pfuze100-regulator.c:346:2: error: unknown field 'cache_type' specified in initializer
-drivers/regulator/pfuze100-regulator.c:346:2: warning: excess elements in struct initializer [enabled by default]
-drivers/regulator/pfuze100-regulator.c:346:2: warning: (near initialization for 'pfuze_regmap_config') [enabled by default]
-drivers/regulator/pfuze100-regulator.c: In function 'pfuze100_regulator_probe':
-drivers/regulator/pfuze100-regulator.c:370:2: error: implicit declaration of function 'devm_regmap_init_i2c' [-Werror=implicit-function-declaration]
-drivers/regulator/pfuze100-regulator.c:370:21: warning: assignment makes pointer from integer without a cast [enabled by default]
-cc1: some warnings being treated as errors
-make[2]: *** [drivers/regulator/pfuze100-regulator.o] Error 1
-make[1]: *** [drivers/regulator] Error 2
-make: *** [drivers] Error 2
-
-Signed-off-by: Axel Lin <axel.lin@ingics.com>
-Signed-off-by: Mark Brown <broonie@linaro.org>
----
- drivers/regulator/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/regulator/Kconfig
-+++ b/drivers/regulator/Kconfig
-@@ -303,6 +303,7 @@ config REGULATOR_PCF50633
- config REGULATOR_PFUZE100
-       tristate "Support regulators on Freescale PFUZE100 PMIC"
-       depends on I2C
-+      select REGMAP_I2C
-       help
-         Say y here to support the regulators found on the Freescale PFUZE100
-         PMIC.
diff --git a/target/linux/imx6/patches-3.10/0021-regulator-pfuze100-fix-build-warning-and-correct-the.patch b/target/linux/imx6/patches-3.10/0021-regulator-pfuze100-fix-build-warning-and-correct-the.patch
deleted file mode 100644 (file)
index 488edb6..0000000
+++ /dev/null
@@ -1,35 +0,0 @@
-From: Robin Gong <b38343@freescale.com>
-Subject: [PATCH] regulator:pfuze100: fix build warning and correct the binding
- doc
-
-fix building warning and correct the binding doc
-
-Signed-off-by: Robin Gong <b38343@freescale.com>
-Signed-off-by: Mark Brown <broonie@linaro.org>
----
- Documentation/devicetree/bindings/regulator/pfuze100.txt | 2 ++
- drivers/regulator/pfuze100-regulator.c                   | 2 +-
- 2 files changed, 3 insertions(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/regulator/pfuze100.txt
-+++ b/Documentation/devicetree/bindings/regulator/pfuze100.txt
-@@ -3,6 +3,8 @@ PFUZE100 family of regulators
- Required properties:
- - compatible: "fsl,pfuze100"
- - reg: I2C slave address
-+
-+Required child node:
- - regulators: This is the list of child nodes that specify the regulator
-   initialization data for defined regulators. Please refer to below doc
-   Documentation/devicetree/bindings/regulator/regulator.txt.
---- a/drivers/regulator/pfuze100-regulator.c
-+++ b/drivers/regulator/pfuze100-regulator.c
-@@ -295,7 +295,7 @@ static inline struct device_node *match_
- #else
- static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
- {
--      return NULL;
-+      return 0;
- }
- static inline struct regulator_init_data *match_init_data(int index)
diff --git a/target/linux/imx6/patches-3.10/0022-regulator-pfuze100-add-MODULE_LICENSE-in-pfuze100-dr.patch b/target/linux/imx6/patches-3.10/0022-regulator-pfuze100-add-MODULE_LICENSE-in-pfuze100-dr.patch
deleted file mode 100644 (file)
index dfdefe7..0000000
+++ /dev/null
@@ -1,21 +0,0 @@
-From: Robin Gong <b38343@freescale.com>
-Subject: [PATCH] regulator: pfuze100: add MODULE_LICENSE() in pfuze100 driver
-
-Fix building error on x86_64 and i386:
-WARNING: modpost: missing MODULE_LICENSE() in
-drivers/regulator/pfuze100-regulator.o
-
-Signed-off-by: Robin Gong <b38343@freescale.com>
-Signed-off-by: Mark Brown <broonie@linaro.org>
----
- drivers/regulator/pfuze100-regulator.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/regulator/pfuze100-regulator.c
-+++ b/drivers/regulator/pfuze100-regulator.c
-@@ -451,4 +451,5 @@ module_i2c_driver(pfuze_driver);
- MODULE_AUTHOR("Robin Gong <b38343@freescale.com>");
- MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100 PMIC");
-+MODULE_LICENSE("GPL v2");
- MODULE_ALIAS("pfuze100-regulator");
diff --git a/target/linux/imx6/patches-3.10/0023-regulator-pfuze100-Use-i2c_-set-get-_clientdata.patch b/target/linux/imx6/patches-3.10/0023-regulator-pfuze100-Use-i2c_-set-get-_clientdata.patch
deleted file mode 100644 (file)
index 609ed05..0000000
+++ /dev/null
@@ -1,32 +0,0 @@
-From: Axel Lin <axel.lin@ingics.com>
-Subject: [PATCH] regulator: pfuze100: Use i2c_[set|get]_clientdata
-
-Since this is a i2c driver, use i2c_[set|get]_clientdata instead of
-dev_[set|get]_drvdata.
-
-Signed-off-by: Axel Lin <axel.lin@ingics.com>
-Signed-off-by: Mark Brown <broonie@linaro.org>
----
- drivers/regulator/pfuze100-regulator.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/regulator/pfuze100-regulator.c
-+++ b/drivers/regulator/pfuze100-regulator.c
-@@ -360,7 +360,7 @@ static int pfuze100_regulator_probe(stru
-       if (!pfuze_chip)
-               return -ENOMEM;
--      dev_set_drvdata(&client->dev, pfuze_chip);
-+      i2c_set_clientdata(client, pfuze_chip);
-       memcpy(pfuze_chip->regulator_descs, pfuze100_regulators,
-               sizeof(pfuze_chip->regulator_descs));
-@@ -429,7 +429,7 @@ static int pfuze100_regulator_probe(stru
- static int pfuze100_regulator_remove(struct i2c_client *client)
- {
-       int i;
--      struct pfuze_chip *pfuze_chip = dev_get_drvdata(&client->dev);
-+      struct pfuze_chip *pfuze_chip = i2c_get_clientdata(client);
-       for (i = 0; i < PFUZE100_MAX_REGULATOR; i++)
-               regulator_unregister(pfuze_chip->regulators[i]);
diff --git a/target/linux/imx6/patches-3.10/0024-regulator-pfuze100-Fix-module-alias-prefix.patch b/target/linux/imx6/patches-3.10/0024-regulator-pfuze100-Fix-module-alias-prefix.patch
deleted file mode 100644 (file)
index 41ee1fe..0000000
+++ /dev/null
@@ -1,19 +0,0 @@
-From: Axel Lin <axel.lin@ingics.com>
-Subject: [PATCH] regulator: pfuze100: Fix module alias prefix
-
-i2c drivers use "i2c:" prefix for module alias.
-
-Signed-off-by: Axel Lin <axel.lin@ingics.com>
-Signed-off-by: Mark Brown <broonie@linaro.org>
----
- drivers/regulator/pfuze100-regulator.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/regulator/pfuze100-regulator.c
-+++ b/drivers/regulator/pfuze100-regulator.c
-@@ -452,4 +452,4 @@ module_i2c_driver(pfuze_driver);
- MODULE_AUTHOR("Robin Gong <b38343@freescale.com>");
- MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100 PMIC");
- MODULE_LICENSE("GPL v2");
--MODULE_ALIAS("pfuze100-regulator");
-+MODULE_ALIAS("i2c:pfuze100-regulator");
diff --git a/target/linux/imx6/patches-3.10/0025-regulator-pfuze100-Use-regulator_map_voltage_ascend.patch b/target/linux/imx6/patches-3.10/0025-regulator-pfuze100-Use-regulator_map_voltage_ascend.patch
deleted file mode 100644 (file)
index 0821991..0000000
+++ /dev/null
@@ -1,22 +0,0 @@
-From: Axel Lin <axel.lin@ingics.com>
-Subject: [PATCH] regulator: pfuze100: Use regulator_map_voltage_ascend
-
-All table based voltage list have ascendant order.
-Use regulator_map_voltage_ascend for them.
-
-Signed-off-by: Axel Lin <axel.lin@ingics.com>
-Signed-off-by: Mark Brown <broonie@linaro.org>
----
- drivers/regulator/pfuze100-regulator.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/regulator/pfuze100-regulator.c
-+++ b/drivers/regulator/pfuze100-regulator.c
-@@ -144,6 +144,7 @@ static struct regulator_ops pfuze100_sw_
- static struct regulator_ops pfuze100_swb_regulator_ops = {
-       .list_voltage = regulator_list_voltage_table,
-+      .map_voltage = regulator_map_voltage_ascend,
-       .set_voltage_sel = regulator_set_voltage_sel_regmap,
-       .get_voltage_sel = regulator_get_voltage_sel_regmap,
diff --git a/target/linux/imx6/patches-3.10/0026-regulator-pfuze100-Fix-n_voltages-setting-for-SW2-SW.patch b/target/linux/imx6/patches-3.10/0026-regulator-pfuze100-Fix-n_voltages-setting-for-SW2-SW.patch
deleted file mode 100644 (file)
index 026ecce..0000000
+++ /dev/null
@@ -1,67 +0,0 @@
-From: Axel Lin <axel.lin@ingics.com>
-Subject: [PATCH] regulator: pfuze100: Fix n_voltages setting for SW2~SW4 with
- high bit set
-
-Current code adjust min_uV and uV_step but missed adjusting the n_voltages
-setting.
-
-When BIT6 is clear:
-        n_voltages = (1975000 - 400000) / 25000 + 1 = 64
-When BIT6 is set:
-        n_voltages = (3300000 - 800000) / 50000 + 1 = 51
-
-The n_voltages needs update because when BIT6 is set 0x73 ~ 0x7f are reserved.
-When using regulator_list_voltage_linear, the n_voltages does matter here
-because wrong n_voltages setting make the equation return wrong result.
-e.g. if selector is 63, regulator_list_voltage_linear returns
-     800000 + (50000 * 63) = 4000000
-     It should return -EINVAL if the selector is in the range of 51 ~ 63.
-
-Signed-off-by: Axel Lin <axel.lin@ingics.com>
-Signed-off-by: Mark Brown <broonie@linaro.org>
----
- drivers/regulator/pfuze100-regulator.c | 16 ++++++++--------
- 1 file changed, 8 insertions(+), 8 deletions(-)
-
---- a/drivers/regulator/pfuze100-regulator.c
-+++ b/drivers/regulator/pfuze100-regulator.c
-@@ -388,8 +388,11 @@ static int pfuze100_regulator_probe(stru
-       for (i = 0; i < PFUZE100_MAX_REGULATOR; i++) {
-               struct regulator_init_data *init_data;
-+              struct regulator_desc *desc;
-               int val;
-+              desc = &pfuze_chip->regulator_descs[i].desc;
-+
-               if (pdata)
-                       init_data = pdata->init_data[i];
-               else
-@@ -397,13 +400,11 @@ static int pfuze100_regulator_probe(stru
-               /* SW2~SW4 high bit check and modify the voltage value table */
-               if (i > PFUZE100_SW1C && i < PFUZE100_SWBST) {
--                      regmap_read(pfuze_chip->regmap, PFUZE100_SW2VOL +
--                                      (i - PFUZE100_SW2) * 7, &val);
-+                      regmap_read(pfuze_chip->regmap, desc->vsel_reg, &val);
-                       if (val & 0x40) {
--                              pfuze_chip->regulator_descs[i].desc.min_uV
--                              = 800000;
--                              pfuze_chip->regulator_descs[i].desc.uV_step
--                              = 50000;
-+                              desc->min_uV = 800000;
-+                              desc->uV_step = 50000;
-+                              desc->n_voltages = 51;
-                       }
-               }
-@@ -412,8 +413,7 @@ static int pfuze100_regulator_probe(stru
-               config.driver_data = pfuze_chip;
-               config.of_node = match_of_node(i);
--              pfuze_chip->regulators[i] = regulator_register(&pfuze_chip
--                      ->regulator_descs[i].desc, &config);
-+              pfuze_chip->regulators[i] = regulator_register(desc, &config);
-               if (IS_ERR(pfuze_chip->regulators[i])) {
-                       dev_err(&client->dev, "register regulator%s failed\n",
-                               pfuze100_regulators[i].desc.name);
diff --git a/target/linux/imx6/patches-3.10/0027-regulator-pfuze100-Simplify-pfuze100_set_ramp_delay-.patch b/target/linux/imx6/patches-3.10/0027-regulator-pfuze100-Simplify-pfuze100_set_ramp_delay-.patch
deleted file mode 100644 (file)
index 1089dff..0000000
+++ /dev/null
@@ -1,56 +0,0 @@
-From: Axel Lin <axel.lin@ingics.com>
-Subject: [PATCH] regulator: pfuze100: Simplify pfuze100_set_ramp_delay
- implementation
-
-Simplify the equation to calculate ramp_delay.
-Below equations are equivalent:
-  ramp_delay = 25000 / (2 * ramp_delay);
-  ramp_delay = 50000 / (4 * ramp_delay);
-  ramp_delay = 25000 / (2 * ramp_delay);
-  ramp_delay = 12500 / ramp_delay;
-So we don't need to read BIT6 of rdev->desc->vsel_reg for applying different
-equations.
-
-Also use rdev->desc->vsel_reg instead of run-time calculate register address.
-
-Signed-off-by: Axel Lin <axel.lin@ingics.com>
-Reviewed-by: Robin Gong <b38343@freescale.com>
-Signed-off-by: Mark Brown <broonie@linaro.org>
----
- drivers/regulator/pfuze100-regulator.c | 21 +++++----------------
- 1 file changed, 5 insertions(+), 16 deletions(-)
-
---- a/drivers/regulator/pfuze100-regulator.c
-+++ b/drivers/regulator/pfuze100-regulator.c
-@@ -93,26 +93,15 @@ static int pfuze100_set_ramp_delay(struc
- {
-       struct pfuze_chip *pfuze100 = rdev_get_drvdata(rdev);
-       int id = rdev->desc->id;
--      unsigned int val, ramp_bits, reg;
-+      unsigned int ramp_bits;
-       int ret;
-       if (id < PFUZE100_SWBST) {
--              if (id == PFUZE100_SW1AB)
--                      reg = PFUZE100_SW1ABVOL;
--              else
--                      reg = PFUZE100_SW1CVOL + (id - PFUZE100_SW1C) * 7;
--              regmap_read(pfuze100->regmap, reg, &val);
--
--              if (id <= PFUZE100_SW1C)
--                      ramp_delay = 25000 / (2 * ramp_delay);
--              else if (val & 0x40)
--                      ramp_delay = 50000 / (4 * ramp_delay);
--              else
--                      ramp_delay = 25000 / (2 * ramp_delay);
--
-+              ramp_delay = 12500 / ramp_delay;
-               ramp_bits = (ramp_delay >> 1) - (ramp_delay >> 3);
--              ret = regmap_update_bits(pfuze100->regmap, reg + 4 , 0xc0,
--                              ramp_bits << 6);
-+              ret = regmap_update_bits(pfuze100->regmap,
-+                                       rdev->desc->vsel_reg + 4,
-+                                       0xc0, ramp_bits << 6);
-               if (ret < 0)
-                       dev_err(pfuze100->dev, "ramp failed, err %d\n", ret);
-       } else
diff --git a/target/linux/imx6/patches-3.10/0028-regulator-pfuze100-Fix-off-by-one-for-max_register-s.patch b/target/linux/imx6/patches-3.10/0028-regulator-pfuze100-Fix-off-by-one-for-max_register-s.patch
deleted file mode 100644 (file)
index 34ff796..0000000
+++ /dev/null
@@ -1,23 +0,0 @@
-From: Axel Lin <axel.lin@ingics.com>
-Subject: [PATCH] regulator: pfuze100: Fix off-by-one for max_register setting
-
-max_register should be register count - 1.
-
-Signed-off-by: Axel Lin <axel.lin@ingics.com>
-Reviewed-by: Robin Gong <b38343@freescale.com>
-Signed-off-by: Mark Brown <broonie@linaro.org>
----
- drivers/regulator/pfuze100-regulator.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/regulator/pfuze100-regulator.c
-+++ b/drivers/regulator/pfuze100-regulator.c
-@@ -332,7 +332,7 @@ static int pfuze_identify(struct pfuze_c
- static const struct regmap_config pfuze_regmap_config = {
-       .reg_bits = 8,
-       .val_bits = 8,
--      .max_register = PFUZE_NUMREGS,
-+      .max_register = PFUZE_NUMREGS - 1,
-       .cache_type = REGCACHE_RBTREE,
- };
diff --git a/target/linux/imx6/patches-3.10/0029-regulator-pfuze100-allow-misprogrammed-ID.patch b/target/linux/imx6/patches-3.10/0029-regulator-pfuze100-allow-misprogrammed-ID.patch
deleted file mode 100644 (file)
index 8c0a92b..0000000
+++ /dev/null
@@ -1,32 +0,0 @@
-From: Tim Harvey <tharvey@gateworks.com>
-Subject: [PATCH] regulator: pfuze100: allow misprogrammed ID
-
-prior to week 08 of 2013 Freescale misprogrammed between 1 and 3% of
-PFUZE1000 parts with a ID=0x8 instead of the expected ID=0x0
-
-Signed-off-by: Tim Harvey <tharvey@gateworks.com>
----
- drivers/regulator/pfuze100-regulator.c | 12 +++++++++---
- 1 file changed, 9 insertions(+), 3 deletions(-)
-
---- a/drivers/regulator/pfuze100-regulator.c
-+++ b/drivers/regulator/pfuze100-regulator.c
-@@ -308,9 +308,15 @@ static int pfuze_identify(struct pfuze_c
-       if (ret)
-               return ret;
--      if (value & 0x0f) {
--              dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value);
--              return -ENODEV;
-+      switch (value & 0x0f) {
-+              /* Freescale misprogrammed 1-3% of parts prior to week 8 of 2013 as ID=8 */
-+              case 0x8:
-+                      dev_info(pfuze_chip->dev, "Assuming misprogrammed ID=0x8");
-+              case 0x0:
-+                      break;
-+              default:
-+                      dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value);
-+                      return -ENODEV;
-       }
-       ret = regmap_read(pfuze_chip->regmap, PFUZE100_REVID, &value);
diff --git a/target/linux/imx6/patches-3.10/0030-pcie-designware-fix-io-transfers.patch b/target/linux/imx6/patches-3.10/0030-pcie-designware-fix-io-transfers.patch
deleted file mode 100644 (file)
index 1d3e839..0000000
+++ /dev/null
@@ -1,58 +0,0 @@
-From: Pratyush Anand <pratyush.anand@st.com>
-
-pp->io_base which is the input of the outbound IO address translation
-unit should be the cpu address, it was programmed wrongly to realio
-address.
-
-We should pass global_io_offset rather than sys->io_offset to
-pci_ioremap_io, so we map the new window into the first available spot
-in the Linux view of the I/O space.
-
-We must also pass cpu address instead  of realio address to
-pci_ioremap_io.
-
-This patch fixes above issue. It has been tested with Lecroy PTC in AIC
-mode and Pericom PI7C9X2G303EL PCIe switch, which does not work
-otherwise.
-
-Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
-Tested-by: Mohit Kumar <mohit.kumar@st.com>
-Tested-by: Tim Harvey <tharvey@gateworks.com>
-Cc: Arnd Bergmann <arnd@arndb.de>
-Cc: Marek Vasut <marex@denx.de>
-Cc: Richard Zhu <Hong-Xing.Zhu@freescale.com>
-Cc: linux-pci@vger.kernel.org
-Cc: spear-devel@list.st.com
----
- drivers/pci/host/pcie-designware.c |    5 ++---
- 1 files changed, 2 insertions(+), 3 deletions(-)
-
-http://thread.gmane.org/gmane.linux.kernel.pci/27204
-
---- a/drivers/pci/host/pcie-designware.c
-+++ b/drivers/pci/host/pcie-designware.c
-@@ -177,6 +177,7 @@ int __init dw_pcie_host_init(struct pcie
-                                          + global_io_offset);
-                       pp->config.io_size = resource_size(&pp->io);
-                       pp->config.io_bus_addr = range.pci_addr;
-+                      pp->io_base = range.cpu_addr;
-               }
-               if (restype == IORESOURCE_MEM) {
-                       of_pci_range_to_resource(&range, np, &pp->mem);
-@@ -202,7 +203,6 @@ int __init dw_pcie_host_init(struct pcie
-       pp->cfg0_base = pp->cfg.start;
-       pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
--      pp->io_base = pp->io.start;
-       pp->mem_base = pp->mem.start;
-       pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
-@@ -449,7 +449,7 @@ int dw_pcie_setup(int nr, struct pci_sys
-       if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
-               sys->io_offset = global_io_offset - pp->config.io_bus_addr;
--              pci_ioremap_io(sys->io_offset, pp->io.start);
-+              pci_ioremap_io(global_io_offset, pp->io_base);
-               global_io_offset += SZ_64K;
-               pci_add_resource_offset(&sys->resources, &pp->io,
-                                       sys->io_offset);
diff --git a/target/linux/imx6/patches-3.10/0031-PCI-imx6-init-must-be-early.patch b/target/linux/imx6/patches-3.10/0031-PCI-imx6-init-must-be-early.patch
deleted file mode 100644 (file)
index 0546d9c..0000000
+++ /dev/null
@@ -1,24 +0,0 @@
-From 8c8c877d8490c9d51210ee9e90d5f4d740f115c9 Mon Sep 17 00:00:00 2001
-From: Tim Harvey <tharvey@gateworks.com>
-Date: Thu, 17 Oct 2013 15:55:47 -0700
-Subject: [PATCH 3/5] PCI: imx6: init must be early
-
-If driver init is not early the pcie port driver gets initalized
-first and interrupts are not configured for the imx6 pcie driver.
-
-Signed-off-by: Tim Harvey <tharvey@gateworks.com>
----
- drivers/pci/host/pci-imx6.c |    2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/pci/host/pci-imx6.c
-+++ b/drivers/pci/host/pci-imx6.c
-@@ -568,7 +568,7 @@ static int __init imx6_pcie_init(void)
- {
-       return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
- }
--module_init(imx6_pcie_init);
-+fs_initcall(imx6_pcie_init);
- MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
- MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
diff --git a/target/linux/imx6/patches-3.10/0032-PCI-imx6-fix-imprecise-abort-handler.patch b/target/linux/imx6/patches-3.10/0032-PCI-imx6-fix-imprecise-abort-handler.patch
deleted file mode 100644 (file)
index 5cef411..0000000
+++ /dev/null
@@ -1,36 +0,0 @@
-From 8590081d5328fe59d4f72aaadafb47fb91d8dc7c Mon Sep 17 00:00:00 2001
-From: Tim Harvey <tharvey@gateworks.com>
-Date: Thu, 17 Oct 2013 15:52:16 -0700
-Subject: [PATCH] PCI: imx6: fix imprecise abort handler
-
-An imprecise abort is triggered when a port behind a switch is accessed
-and no device is present.  At enumeration, imprecise aborts are not enabled
-thus this ends up getting deferred until the kernel has completed init.  At
-that point we must not adjust PC - the handler must do nothing, but a handler
-must exist.
-
-This fixes random crashes that occur right after freeing init.
-This is against linux-pci/host-imx6.
-
-Acked-by: Marek Vasut <marex@denx.de>
-Tested-by: Marek Vasut <marex@denx.de>
-Signed-off-by: Tim Harvey <tharvey@gateworks.com>
----
- drivers/pci/host/pci-imx6.c |    6 ------
- 1 file changed, 6 deletions(-)
-
---- a/drivers/pci/host/pci-imx6.c
-+++ b/drivers/pci/host/pci-imx6.c
-@@ -200,12 +200,6 @@ static int pcie_phy_write(void __iomem *
- static int imx6q_pcie_abort_handler(unsigned long addr,
-               unsigned int fsr, struct pt_regs *regs)
- {
--      /*
--       * If it was an imprecise abort, then we need to correct the
--       * return address to be _after_ the instruction.
--       */
--      if (fsr & (1 << 10))
--              regs->ARM_pc += 4;
-       return 0;
- }
diff --git a/target/linux/imx6/patches-3.10/0033-PCI-imx6-increase-link-startup.patch b/target/linux/imx6/patches-3.10/0033-PCI-imx6-increase-link-startup.patch
deleted file mode 100644 (file)
index a94a166..0000000
+++ /dev/null
@@ -1,24 +0,0 @@
-From 11e8d0ed8cc3b415767961555efc2885791a9391 Mon Sep 17 00:00:00 2001
-From: Tim Harvey <tharvey@gateworks.com>
-Date: Thu, 17 Oct 2013 15:57:28 -0700
-Subject: [PATCH 4/5] PCI: imx6: increase link startup
-
-An increase link startup delay is required when certain PCI switches are
-attached to the root complex.
-
-Signed-off-by: Tim Harvey <tharvey@gateworks.com>
----
- drivers/pci/host/pci-imx6.c |    2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/pci/host/pci-imx6.c
-+++ b/drivers/pci/host/pci-imx6.c
-@@ -318,7 +318,7 @@ static void imx6_pcie_host_init(struct p
-       while (!dw_pcie_link_up(pp)) {
-               usleep_range(100, 1000);
-               count++;
--              if (count >= 10) {
-+              if (count >= 200) {
-                       dev_err(pp->dev, "phy link never came up\n");
-                       dev_dbg(pp->dev,
-                               "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
diff --git a/target/linux/imx6/patches-3.10/0034-PCI-imx6-add-support-for-legacy-irqs.patch b/target/linux/imx6/patches-3.10/0034-PCI-imx6-add-support-for-legacy-irqs.patch
deleted file mode 100644 (file)
index 03f29f4..0000000
+++ /dev/null
@@ -1,43 +0,0 @@
-From: Tim Harvey <tharvey@gateworks.com>
-Subject: [PATCH] PCI: imx6: add support for legacy irqs
-
-The i.MX6 supports legacy IRQ's via 155,154,153,152.  When devices
-are behind a PCIe-to-PCIe switch (at least for the TI XIO2001) the 
-mapping is reversed from when they are behind a PCIe switch.
-
-This patch still needs some review and clarification before going
-upstream.
----
- drivers/pci/host/pcie-designware.c | 21 ++++++++++++++++++++-
- 1 file changed, 20 insertions(+), 1 deletion(-)
-
---- a/drivers/pci/host/pcie-designware.c
-+++ b/drivers/pci/host/pcie-designware.c
-@@ -482,7 +482,26 @@ int dw_pcie_map_irq(const struct pci_dev
- {
-       struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
--      return pp->irq;
-+      /* TI XIO2001 PCIe-to-PCI bridge IRQs are flipped it seems */
-+      if ( dev->bus && dev->bus->self
-+       && (dev->bus->self->vendor == 0x104c)
-+       && (dev->bus->self->device == 0x8240)) {
-+              switch (pin) {
-+              case 1: return pp->irq - 3;
-+              case 2: return pp->irq - 2;
-+              case 3: return pp->irq - 1;
-+              case 4: return pp->irq;
-+              default: return -1;
-+              }
-+      } else {
-+              switch (pin) {
-+              case 1: return pp->irq;
-+              case 2: return pp->irq - 1;
-+              case 3: return pp->irq - 2;
-+              case 4: return pp->irq - 3;
-+              default: return -1;
-+              }
-+      }
- }
- static struct hw_pci dw_pci = {
diff --git a/target/linux/imx6/patches-3.10/0050-sky2-allow-mac-to-come-from-dt.patch b/target/linux/imx6/patches-3.10/0050-sky2-allow-mac-to-come-from-dt.patch
deleted file mode 100644 (file)
index 54743a5..0000000
+++ /dev/null
@@ -1,69 +0,0 @@
-From: Tim Harvey <tharvey@gateworks.com>
-Subject: [PATCH] sky2: allow mac to come from dt
-
-The driver reads the mac address from the device registers which would
-need to have been programmed by the bootloader.  This patch adds
-the ability to pull the mac from devicetree via the aliases/sky2 node.
-
-Signed-off-by: Tim Harvey <tharvey@gateworks.com>
----
- drivers/net/ethernet/marvell/sky2.c | 33 ++++++++++++++++++++++++++++++++-
- 1 file changed, 32 insertions(+), 1 deletion(-)
-
---- a/drivers/net/ethernet/marvell/sky2.c
-+++ b/drivers/net/ethernet/marvell/sky2.c
-@@ -44,6 +44,8 @@
- #include <linux/prefetch.h>
- #include <linux/debugfs.h>
- #include <linux/mii.h>
-+#include <linux/of_device.h>
-+#include <linux/of_net.h>
- #include <asm/irq.h>
-@@ -4748,6 +4750,7 @@ static struct net_device *sky2_init_netd
- {
-       struct sky2_port *sky2;
-       struct net_device *dev = alloc_etherdev(sizeof(*sky2));
-+      unsigned char *iap, tmpaddr[ETH_ALEN];
-       if (!dev)
-               return NULL;
-@@ -4802,8 +4805,36 @@ static struct net_device *sky2_init_netd
-       dev->features |= dev->hw_features;
-+      /*
-+       * try to get mac address in the following order:
-+       * 1) from device tree data
-+       * 2) from internal registers set by bootloader
-+       */
-+      iap = NULL;
-+      if (IS_ENABLED(CONFIG_OF)) {
-+              struct device_node *np;
-+              np = of_find_node_by_path("/aliases");
-+              if (np) {
-+                      const char *path = of_get_property(np, "sky2", NULL);
-+                      if (path)
-+                              np = of_find_node_by_path(path);
-+                      if (np)
-+                              path = of_get_mac_address(np);
-+                      if (path)
-+                              iap = (unsigned char *) path;
-+              }
-+      }
-+
-+      /*
-+       * 2) mac registers set by bootloader
-+       */
-+      if (!iap || !is_valid_ether_addr(iap)) {
-+              memcpy_fromio(&tmpaddr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
-+              iap = &tmpaddr[0];
-+      }
-+
-       /* read the mac address */
--      memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
-+      memcpy(dev->dev_addr, iap, ETH_ALEN);
-       return dev;
- }
diff --git a/target/linux/imx6/patches-3.10/0060-flexcan.patch b/target/linux/imx6/patches-3.10/0060-flexcan.patch
deleted file mode 100644 (file)
index 11a66c5..0000000
+++ /dev/null
@@ -1,92 +0,0 @@
---- a/arch/arm/boot/dts/imx6q.dtsi
-+++ b/arch/arm/boot/dts/imx6q.dtsi
-@@ -163,6 +163,31 @@
-                                       };
-                               };
-+                              flexcan1 {
-+                                      pinctrl_flexcan1_1: flexcan1grp-1 {
-+                                              fsl,pins = <
-+                                                      MX6Q_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
-+                                                      MX6Q_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
-+                                              >;
-+                                      };
-+
-+                                      pinctrl_flexcan1_2: flexcan1grp-2 {
-+                                              fsl,pins = <
-+                                                      MX6Q_PAD_GPIO_7__FLEXCAN1_TX   0x80000000
-+                                                      MX6Q_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
-+                                              >;
-+                                      };
-+                              };
-+
-+                              flexcan2 {
-+                                      pinctrl_flexcan2_1: flexcan2grp-1 {
-+                                              fsl,pins = <
-+                                                      MX6Q_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
-+                                                      MX6Q_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
-+                                              >;
-+                                      };
-+                              };
-+
-                               gpmi-nand {
-                                       pinctrl_gpmi_nand_1: gpmi-nand-1 {
-                                               fsl,pins = <
---- a/arch/arm/boot/dts/imx6qdl.dtsi
-+++ b/arch/arm/boot/dts/imx6qdl.dtsi
-@@ -292,13 +292,21 @@
-                       };
-                       can1: flexcan@02090000 {
-+                              compatible = "fsl,imx6q-flexcan";
-                               reg = <0x02090000 0x4000>;
-                               interrupts = <0 110 0x04>;
-+                              clocks = <&clks 108>, <&clks 109>;
-+                              clock-names = "ipg", "per";
-+                              status = "disabled";
-                       };
-                       can2: flexcan@02094000 {
-+                              compatible = "fsl,imx6q-flexcan";
-                               reg = <0x02094000 0x4000>;
-                               interrupts = <0 111 0x04>;
-+                              clocks = <&clks 110>, <&clks 111>;
-+                              clock-names = "ipg", "per";
-+                              status = "disabled";
-                       };
-                       gpt: gpt@02098000 {
---- a/arch/arm/boot/dts/imx6dl.dtsi
-+++ b/arch/arm/boot/dts/imx6dl.dtsi
-@@ -80,6 +80,31 @@
-                                       };
-                               };
-+                              flexcan1 {
-+                                      pinctrl_flexcan1_1: flexcan1grp-1 {
-+                                              fsl,pins = <
-+                                                      MX6DL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
-+                                                      MX6DL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
-+                                              >;
-+                                      };
-+
-+                                      pinctrl_flexcan1_2: flexcan1grp-2 {
-+                                              fsl,pins = <
-+                                                      MX6DL_PAD_GPIO_7__FLEXCAN1_TX   0x80000000
-+                                                      MX6DL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
-+                                              >;
-+                                      };
-+                              };
-+
-+                              flexcan2 {
-+                                      pinctrl_flexcan2_1: flexcan2grp-1 {
-+                                              fsl,pins = <
-+                                                      MX6DL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
-+                                                      MX6DL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
-+                                              >;
-+                                      };
-+                              };
-+
-                               uart1 {
-                                       pinctrl_uart1_1: uart1grp-1 {
-                                               fsl,pins = <
diff --git a/target/linux/imx6/patches-3.10/0061-can-flexcan-use-correct-clock-as-base-for-bit-rate-c.patch b/target/linux/imx6/patches-3.10/0061-can-flexcan-use-correct-clock-as-base-for-bit-rate-c.patch
deleted file mode 100644 (file)
index fd90130..0000000
+++ /dev/null
@@ -1,37 +0,0 @@
-From 1a3e5173f5e72cbf7f0c8927b33082e361c16d72 Mon Sep 17 00:00:00 2001
-From: Marc Kleine-Budde <mkl@pengutronix.de>
-Date: Mon, 25 Nov 2013 22:15:20 +0100
-Subject: [PATCH] can: flexcan: use correct clock as base for bit rate
- calculation
-
-The flexcan IP core uses the peripheral clock ("per") as basic clock for the
-bit timing calculation. However the driver uses the the wrong clock ("ipg").
-This leads to wrong bit rates if the rates on both clock are different.
-
-This patch fixes the problem by using the correct clock for the bit rate
-calculation.
-
-Cc: linux-stable <stable@vger.kernel.org>
-Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
----
- drivers/net/can/flexcan.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/net/can/flexcan.c
-+++ b/drivers/net/can/flexcan.c
-@@ -1021,7 +1021,6 @@ static int flexcan_probe(struct platform
-                       err = PTR_ERR(clk_ipg);
-                       goto failed_clock;
-               }
--              clock_freq = clk_get_rate(clk_ipg);
-               clk_per = devm_clk_get(&pdev->dev, "per");
-               if (IS_ERR(clk_per)) {
-@@ -1029,6 +1028,7 @@ static int flexcan_probe(struct platform
-                       err = PTR_ERR(clk_per);
-                       goto failed_clock;
-               }
-+              clock_freq = clk_get_rate(clk_per);
-       }
-       mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
diff --git a/target/linux/imx6/patches-3.10/010-pcie-backport-fixes.patch b/target/linux/imx6/patches-3.10/010-pcie-backport-fixes.patch
deleted file mode 100644 (file)
index cb26ec8..0000000
+++ /dev/null
@@ -1,45 +0,0 @@
---- a/arch/arm/boot/dts/imx6qdl.dtsi
-+++ b/arch/arm/boot/dts/imx6qdl.dtsi
-@@ -119,7 +119,7 @@
-                                 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
-                       num-lanes = <1>;
-                       interrupts = <0 123 0x04>;
--                      clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
-+                      clocks = <&clks 189>, <&clks 187>, <&clks 198>, <&clks 144>;
-                       clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
-                       status = "disabled";
-               };
---- a/drivers/pci/Kconfig
-+++ b/drivers/pci/Kconfig
-@@ -125,3 +125,5 @@ config PCI_IOAPIC
- config PCI_LABEL
-       def_bool y if (DMI || ACPI)
-       select NLS
-+
-+source "drivers/pci/host/Kconfig"
---- a/drivers/pci/Makefile
-+++ b/drivers/pci/Makefile
-@@ -67,3 +67,6 @@ obj-$(CONFIG_XEN_PCIDEV_FRONTEND) += xen
- obj-$(CONFIG_OF) += of.o
- ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG
-+
-+# PCI host controller drivers
-+obj-y += host/
---- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
-+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
-@@ -208,10 +208,10 @@ clocks and IDs.
-       pll4_post_div           193
-       pll5_post_div           194
-       pll5_video_div          195
--      lvds1_sel               204
--      lvds2_sel               205
--      lvds1_gate              206
--      lvds2_gate              207
-+      lvds1_sel               196
-+      lvds2_sel               197
-+      lvds1_gate              198
-+      lvds2_gate              199
- Examples:
diff --git a/target/linux/imx6/patches-3.10/100-bootargs.patch b/target/linux/imx6/patches-3.10/100-bootargs.patch
deleted file mode 100644 (file)
index c10f64b..0000000
+++ /dev/null
@@ -1,13 +0,0 @@
---- a/arch/arm/boot/dts/imx6dl-wandboard.dts
-+++ b/arch/arm/boot/dts/imx6dl-wandboard.dts
-@@ -18,6 +18,10 @@
-       memory {
-               reg = <0x10000000 0x40000000>;
-       };
-+
-+      chosen {
-+              bootargs = "console=ttymxc0,115200";
-+      };
- };
- &fec {
diff --git a/target/linux/imx6/patches-3.10/110-gateworks-ventana.patch b/target/linux/imx6/patches-3.10/110-gateworks-ventana.patch
deleted file mode 100644 (file)
index 1385661..0000000
+++ /dev/null
@@ -1,263 +0,0 @@
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -117,6 +117,15 @@ dtb-$(CONFIG_ARCH_MXC) += \
-       imx6dl-sabresd.dtb \
-       imx6dl-wandboard.dtb \
-       imx6q-arm2.dtb \
-+      imx6q-gw51xx.dtb \
-+      imx6q-gw52xx.dtb \
-+      imx6q-gw53xx.dtb \
-+      imx6q-gw54xx.dtb \
-+      imx6q-gw5400-a.dtb \
-+      imx6dl-gw51xx.dtb \
-+      imx6dl-gw52xx.dtb \
-+      imx6dl-gw53xx.dtb \
-+      imx6dl-gw54xx.dtb \
-       imx6q-sabreauto.dtb \
-       imx6q-sabrelite.dtb \
-       imx6q-sabresd.dtb \
---- a/arch/arm/boot/dts/imx6q.dtsi
-+++ b/arch/arm/boot/dts/imx6q.dtsi
-@@ -212,6 +212,30 @@
-                                                       MX6Q_PAD_SD4_DAT0__NAND_DQS      0x00b1
-                                               >;
-                                       };
-+
-+                                      /* No strobe */
-+                                      pinctrl_gpmi_nand_2: gpmi-nand-2 {
-+                                              fsl,pins = <
-+                                                      MX6Q_PAD_NANDF_CLE__NAND_CLE     0xb0b1
-+                                                      MX6Q_PAD_NANDF_ALE__NAND_ALE     0xb0b1
-+                                                      MX6Q_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
-+                                                      MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
-+                                                      MX6Q_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
-+                                                      MX6Q_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
-+                                                      MX6Q_PAD_NANDF_CS2__NAND_CE2_B   0xb0b1
-+                                                      MX6Q_PAD_NANDF_CS3__NAND_CE3_B   0xb0b1
-+                                                      MX6Q_PAD_SD4_CMD__NAND_RE_B      0xb0b1
-+                                                      MX6Q_PAD_SD4_CLK__NAND_WE_B      0xb0b1
-+                                                      MX6Q_PAD_NANDF_D0__NAND_DATA00   0xb0b1
-+                                                      MX6Q_PAD_NANDF_D1__NAND_DATA01   0xb0b1
-+                                                      MX6Q_PAD_NANDF_D2__NAND_DATA02   0xb0b1
-+                                                      MX6Q_PAD_NANDF_D3__NAND_DATA03   0xb0b1
-+                                                      MX6Q_PAD_NANDF_D4__NAND_DATA04   0xb0b1
-+                                                      MX6Q_PAD_NANDF_D5__NAND_DATA05   0xb0b1
-+                                                      MX6Q_PAD_NANDF_D6__NAND_DATA06   0xb0b1
-+                                                      MX6Q_PAD_NANDF_D7__NAND_DATA07   0xb0b1
-+                                              >;
-+                                      };
-                               };
-                               i2c1 {
-@@ -230,6 +254,12 @@
-                                                       MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
-                                               >;
-                                       };
-+                                      pinctrl_i2c2_2: i2c2grp-2 {
-+                                              fsl,pins = <
-+                                                      MX6Q_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
-+                                                      MX6Q_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
-+                                              >;
-+                                      };
-                               };
-                               i2c3 {
-@@ -239,6 +269,12 @@
-                                                       MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
-                                               >;
-                                       };
-+                                      pinctrl_i2c3_2: i2c3grp-2 {
-+                                              fsl,pins = <
-+                                                      MX6Q_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
-+                                                      MX6Q_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
-+                                              >;
-+                                      };
-                               };
-                               uart1 {
-@@ -248,6 +284,12 @@
-                                                       MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
-                                               >;
-                                       };
-+                                      pinctrl_uart1_2: uart1grp-2 {
-+                                              fsl,pins = <
-+                                                      MX6Q_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
-+                                                      MX6Q_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
-+                                              >;
-+                                      };
-                               };
-                               uart2 {
-@@ -257,6 +299,21 @@
-                                                       MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
-                                               >;
-                                       };
-+                                      pinctrl_uart2_3: uart2grp-3 {
-+                                              fsl,pins = <
-+                                                      MX6Q_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
-+                                                      MX6Q_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
-+                                              >;
-+                                      };
-+                              };
-+
-+                              uart3 {
-+                                      pinctrl_uart3_3: uart3grp-3 {
-+                                              fsl,pins = <
-+                                                      MX6Q_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
-+                                                      MX6Q_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
-+                                              >;
-+                                      };
-                               };
-                               uart4 {
-@@ -267,6 +324,15 @@
-                                               >;
-                                       };
-                               };
-+
-+                              uart5 {
-+                                      pinctrl_uart5_1: uart5grp-1 {
-+                                              fsl,pins = <
-+                                                      MX6Q_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
-+                                                      MX6Q_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
-+                                              >;
-+                                      };
-+                              };
-                               usbotg {
-                                       pinctrl_usbotg_1: usbotggrp-1 {
---- a/arch/arm/boot/dts/imx6dl.dtsi
-+++ b/arch/arm/boot/dts/imx6dl.dtsi
-@@ -37,6 +37,18 @@
-                               compatible = "fsl,imx6dl-iomuxc";
-                               reg = <0x020e0000 0x4000>;
-+                              /* shared pinctrl settings */
-+                              audmux {
-+                                      pinctrl_audmux_1: audmux-1 {
-+                                              fsl,pins = <
-+                                                      MX6DL_PAD_SD2_DAT0__AUD4_RXD  0x80000000
-+                                                      MX6DL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
-+                                                      MX6DL_PAD_SD2_DAT2__AUD4_TXD  0x80000000
-+                                                      MX6DL_PAD_SD2_DAT3__AUD4_TXC  0x80000000
-+                                              >;
-+                                      };
-+                              };
-+
-                               enet {
-                                       pinctrl_enet_1: enetgrp-1 {
-                                               fsl,pins = <
-@@ -105,6 +117,59 @@
-                                       };
-                               };
-+                              gpmi-nand {
-+                                      /* No strobe */
-+                                      pinctrl_gpmi_nand_2: gpmi-nand-2 {
-+                                              fsl,pins = <
-+                                                      MX6DL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
-+                                                      MX6DL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
-+                                                      MX6DL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
-+                                                      MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
-+                                                      MX6DL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
-+                                                      MX6DL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
-+                                                      MX6DL_PAD_NANDF_CS2__NAND_CE2_B   0xb0b1
-+                                                      MX6DL_PAD_NANDF_CS3__NAND_CE3_B   0xb0b1
-+                                                      MX6DL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
-+                                                      MX6DL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
-+                                                      MX6DL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
-+                                                      MX6DL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
-+                                                      MX6DL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
-+                                                      MX6DL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
-+                                                      MX6DL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
-+                                                      MX6DL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
-+                                                      MX6DL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
-+                                                      MX6DL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
-+                                              >;
-+                                      };
-+                              };
-+
-+                              i2c1 {
-+                                      pinctrl_i2c1_1: i2c1grp-1 {
-+                                              fsl,pins = <
-+                                                      MX6DL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
-+                                                      MX6DL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
-+                                              >;
-+                                      };
-+                              };
-+
-+                              i2c2 {
-+                                      pinctrl_i2c2_2: i2c2grp-2 {
-+                                              fsl,pins = <
-+                                                      MX6DL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
-+                                                      MX6DL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
-+                                              >;
-+                                      };
-+                              };
-+
-+                              i2c3 {
-+                                      pinctrl_i2c3_2: i2c3grp-2 {
-+                                              fsl,pins = <
-+                                                      MX6DL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
-+                                                      MX6DL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
-+                                              >;
-+                                      };
-+                              };
-+
-                               uart1 {
-                                       pinctrl_uart1_1: uart1grp-1 {
-                                               fsl,pins = <
-@@ -112,6 +177,30 @@
-                                                       MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
-                                               >;
-                                       };
-+                                      pinctrl_uart1_2: uart1grp-2 {
-+                                              fsl,pins = <
-+                                                      MX6DL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
-+                                                      MX6DL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
-+                                              >;
-+                                      };
-+                              };
-+
-+                              uart2 {
-+                                      pinctrl_uart2_3: uart2grp-3 {
-+                                              fsl,pins = <
-+                                                      MX6DL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
-+                                                      MX6DL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
-+                                              >;
-+                                      };
-+                              };
-+
-+                              uart3 {
-+                                      pinctrl_uart3_3: uart3grp-3 {
-+                                              fsl,pins = <
-+                                                      MX6DL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
-+                                                      MX6DL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
-+                                              >;
-+                                      };
-                               };
-                               uart4 {
-@@ -123,7 +212,22 @@
-                                       };
-                               };
-+                              uart5 {
-+                                      pinctrl_uart5_1: uart5grp-1 {
-+                                              fsl,pins = <
-+                                                      MX6DL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
-+                                                      MX6DL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
-+                                              >;
-+                                      };
-+                              };
-+
-                               usbotg {
-+                                      pinctrl_usbotg_1: usbotggrp-1 {
-+                                              fsl,pins = <
-+                                                      MX6DL_PAD_GPIO_1__USB_OTG_ID 0x17059
-+                                              >;
-+                                      };
-+
-                                       pinctrl_usbotg_2: usbotggrp-2 {
-                                               fsl,pins = <
-                                                       MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
diff --git a/target/linux/imx6/patches-3.10/120-ventana-init.ptach b/target/linux/imx6/patches-3.10/120-ventana-init.ptach
deleted file mode 100644 (file)
index 2dd91d2..0000000
+++ /dev/null
@@ -1,70 +0,0 @@
-Many of the Gateworks Ventana boards use a PLX PEX860X PCIe Switch
-and utilize its GPIO outputs as PERST# for downstream ports.  This
-patch configures them appropriately during enumeration.
-
-Additionally many of the Ventana boards use CKO1 as the clock input for
-an analog audio codec which is setup here.
-
---- a/arch/arm/mach-imx/mach-imx6q.c
-+++ b/arch/arm/mach-imx/mach-imx6q.c
-@@ -25,6 +25,7 @@
- #include <linux/of_irq.h>
- #include <linux/of_platform.h>
- #include <linux/opp.h>
-+#include <linux/pci.h>
- #include <linux/phy.h>
- #include <linux/regmap.h>
- #include <linux/micrel_phy.h>
-@@ -145,6 +146,42 @@ static void __init imx6q_sabrelite_init(
-       imx6q_sabrelite_cko1_setup();
- }
-+/*
-+ * fixup for PEX 8909 bridge to configure GPIO1-7 as output High
-+ * as they are used for slots1-7 PERST#
-+ */
-+static void mx6_ventana_pciesw_early_fixup(struct pci_dev *dev)
-+{
-+      u32 dw;
-+
-+      if (!of_machine_is_compatible("gw,ventana"))
-+              return;
-+
-+      if (dev->devfn != 0)
-+              return;
-+
-+      pci_read_config_dword(dev, 0x62c, &dw);
-+      dw |= 0xaaa8; // GPIO1-7 outputs
-+      pci_write_config_dword(dev, 0x62c, dw);
-+
-+      pci_read_config_dword(dev, 0x644, &dw);
-+      dw |= 0xfe;   // GPIO1-7 output high
-+      pci_write_config_dword(dev, 0x644, dw);
-+
-+      mdelay(100);
-+}
-+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609,
-+      mx6_ventana_pciesw_early_fixup);
-+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606,
-+      mx6_ventana_pciesw_early_fixup);
-+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604,
-+      mx6_ventana_pciesw_early_fixup);
-+
-+static void __init imx6q_ventana_init(void)
-+{
-+      imx6q_sabrelite_cko1_setup();
-+}
-+
- static void __init imx6q_1588_init(void)
- {
-       struct regmap *gpr;
-@@ -163,6 +200,9 @@ static void __init imx6q_usb_init(void)
- static void __init imx6q_init_machine(void)
- {
-+      if (of_machine_is_compatible("gw,ventana"))
-+              imx6q_ventana_init();
-+
-       if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
-               imx6q_sabrelite_init();