ralink: refresh patches
authorJohn Crispin <john@openwrt.org>
Tue, 18 Mar 2014 19:21:56 +0000 (19:21 +0000)
committerJohn Crispin <john@openwrt.org>
Tue, 18 Mar 2014 19:21:56 +0000 (19:21 +0000)
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 39949

120 files changed:
target/linux/ramips/dts/mt7621.dtsi
target/linux/ramips/files/drivers/usb/host/mtk-phy-7621.c [deleted file]
target/linux/ramips/files/drivers/usb/host/mtk-phy-7621.h [deleted file]
target/linux/ramips/files/drivers/usb/host/mtk-phy-ahb.c [deleted file]
target/linux/ramips/files/drivers/usb/host/mtk-phy.c [deleted file]
target/linux/ramips/files/drivers/usb/host/mtk-phy.h [deleted file]
target/linux/ramips/files/drivers/usb/host/xhci-mtk-power.c [deleted file]
target/linux/ramips/files/drivers/usb/host/xhci-mtk-power.h [deleted file]
target/linux/ramips/files/drivers/usb/host/xhci-mtk-scheduler.c [deleted file]
target/linux/ramips/files/drivers/usb/host/xhci-mtk-scheduler.h [deleted file]
target/linux/ramips/files/drivers/usb/host/xhci-mtk.c [deleted file]
target/linux/ramips/files/drivers/usb/host/xhci-mtk.h [deleted file]
target/linux/ramips/mt7621/config-3.10
target/linux/ramips/mt7621/profiles/00-default.mk
target/linux/ramips/patches-3.10/0100-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch
target/linux/ramips/patches-3.10/0101-MIPS-ralink-add-verbose-pmu-info.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0102-MIPS-ralink-add-verbose-pmu-info.patch [deleted file]
target/linux/ramips/patches-3.10/0102-MIPS-ralink-adds-a-bootrom-dumper-module.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0103-MIPS-ralink-add-illegal-access-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0103-MIPS-ralink-adds-a-bootrom-dumper-module.patch [deleted file]
target/linux/ramips/patches-3.10/0104-MIPS-ralink-add-illegal-access-driver.patch [deleted file]
target/linux/ramips/patches-3.10/0104-MIPS-ralink-workaround-DTB-memory-issue.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0105-MIPS-ralink-add-missing-clk_set_rate-to-clk.c.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0105-MIPS-ralink-workaround-DTB-memory-issue.patch [deleted file]
target/linux/ramips/patches-3.10/0106-MIPS-ralink-add-support-for-MT7620n.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0106-USB-dwc2.patch [deleted file]
target/linux/ramips/patches-3.10/0107-MIPS-ralink-allow-manual-memory-override.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0107-PCI-MIPS-adds-rt2880-pci-support.patch [deleted file]
target/linux/ramips/patches-3.10/0108-MIPS-ralink-add-rt_sysc_m32-helper.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0108-PCI-MIPS-adds-mt7620a-pcie-driver.patch [deleted file]
target/linux/ramips/patches-3.10/0109-MIPS-ralink-add-pseudo-pwm-led-trigger-based-on-time.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0109-NET-multi-phy-support.patch [deleted file]
target/linux/ramips/patches-3.10/0110-MIPS-ralink-add-a-helper-for-reading-the-ECO-version.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0110-NET-add-of_get_mac_address_mtd.patch [deleted file]
target/linux/ramips/patches-3.10/0111-DMA-ralink-add-rt2880-dma-engine.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0111-NET-MIPS-add-ralink-SoC-ethernet-driver.patch [deleted file]
target/linux/ramips/patches-3.10/0112-USB-phy-add-ralink-SoC-driver.patch [deleted file]
target/linux/ramips/patches-3.10/0112-asoc-add-mt7620-support.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0113-USB-add-OHCI-EHCI-OF-binding.patch [deleted file]
target/linux/ramips/patches-3.10/0113-pinctrl-ralink-add-pinctrl-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0114-PCI-MIPS-adds-rt2880-pci-support.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0114-serial-ralink-adds-mt7620-serial.patch [deleted file]
target/linux/ramips/patches-3.10/0115-PCI-MIPS-adds-mt7620a-pcie-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0115-serial-of-allow-au1x00-and-rt288x-to-load-from-OF.patch [deleted file]
target/linux/ramips/patches-3.10/0116-NET-multi-phy-support.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0116-i2c-MIPS-adds-ralink-I2C-driver.patch [deleted file]
target/linux/ramips/patches-3.10/0117-NET-add-of_get_mac_address_mtd.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0117-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch [deleted file]
target/linux/ramips/patches-3.10/0118-NET-MIPS-add-ralink-SoC-ethernet-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0118-mtd-fix-cfi-cmdset-0002-erase-status-check.patch [deleted file]
target/linux/ramips/patches-3.10/0119-USB-phy-add-ralink-SoC-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0119-mtd-cfi-cmdset-0002-force-word-write.patch [deleted file]
target/linux/ramips/patches-3.10/0120-USB-add-OHCI-EHCI-OF-binding.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0120-spi-introduce-macros-to-set-bits_per_word_mask.patch [deleted file]
target/linux/ramips/patches-3.10/0121-MIPS-ralink-add-rt_sysc_m32-helper.patch [deleted file]
target/linux/ramips/patches-3.10/0121-USB-adds-dwc_otg.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0122-pinmux.patch [deleted file]
target/linux/ramips/patches-3.10/0122-serial-ralink-adds-mt7620-serial.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0123-serial-ralink-the-core-has-a-size-of-0x100-and-not-0.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0124-serial-of-allow-au1x00-and-rt288x-to-load-from-OF.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0125-i2c-MIPS-adds-ralink-I2C-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0126-spi-introduce-macros-to-set-bits_per_word_mask.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0127-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0128-mtd-fix-cfi-cmdset-0002-erase-status-check.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0129-mtd-cfi-cmdset-0002-force-word-write.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0130-mtd-ralink-add-mt7620-nand-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0131-mtd-add-chunked-read-io-to-m25p80.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0132-GPIO-add-gpio_export_with_name.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0133-uvc-add-iPassion-iP2970-support.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0134-mtd-split-remove-padding.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0200-MIPS-Fix-TLBR-use-hazards-for-R2-cores-in-the-TLB-re.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0200-owrt-GPIO-add-gpio_export_with_name.patch [deleted file]
target/linux/ramips/patches-3.10/0201-MIPS-GIC-Fix-gic_set_affinity-infinite-loop.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0201-owrt-MIPS-ralink-add-pseudo-pwm-led-trigger-based-on.patch [deleted file]
target/linux/ramips/patches-3.10/0202-MIPS-Fix-SMP-core-calculations-when-using-MT-support.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0202-owrt-USB-adds-dwc_otg.patch [deleted file]
target/linux/ramips/patches-3.10/0203-MIPS-Fix-accessing-to-per-cpu-data-when-flushing-the.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0203-owrt-MIPS-add-OWRTDTB-secion.patch [deleted file]
target/linux/ramips/patches-3.10/0203-serial-rt5350-fix-enable-uartf-kernel-panic.patch [deleted file]
target/linux/ramips/patches-3.10/0204-MIPS-74K-1074K-Correct-erratum-workaround.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0204-owrt-mtd-split-remove-padding.patch [deleted file]
target/linux/ramips/patches-3.10/0205-MIPS-GIC-Send-IPIs-using-the-GIC.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0205-uvc-add-iPassion-iP2970-support.patch [deleted file]
target/linux/ramips/patches-3.10/0206-MIPS-ralink-add-MT7621-support.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0206-MTD-add-chunked-read-io-to-m25p80.patch [deleted file]
target/linux/ramips/patches-3.10/0207-MIPS-ralink-add-MT7621-defconfig.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0208-MIPS-ralink-add-MT7621-dts-file.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0209-MIPS-ralink-add-MT7621-early_printk-support.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0210-MIPS-ralink-add-MT7621-pcie-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0211-watchdog-add-MT7621-support.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0212-GPIO-ralink-add-mt7621-gpio-controller.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0213-MTD-add-mt7621-nand-support.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0214-usb-add-mt7621-xhci-support.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0215-SPI-ralink-add-mt7621-support.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0216-NET-ralink-add-mt7621-SDK-ethernet-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0217-pinmux-rt2880.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0250-nand-7620.patch [deleted file]
target/linux/ramips/patches-3.10/0300-DMA-add-rt2880-dma-engine.patch [deleted file]
target/linux/ramips/patches-3.10/0300-MIPS-OWRTDTB.patch [new file with mode: 0644]
target/linux/ramips/patches-3.10/0301-asoc-add-mt7620-support.patch [deleted file]
target/linux/ramips/patches-3.10/0500-spi-mt7621.patch [deleted file]
target/linux/ramips/patches-3.10/0501-MIPS-increase-GIC_INTR_MAX.patch [deleted file]
target/linux/ramips/patches-3.10/0502-MIPS-ralink-add-MT7621-support.patch [deleted file]
target/linux/ramips/patches-3.10/0503-MIPS-ralink-add-MT7621-early_printk-support.patch [deleted file]
target/linux/ramips/patches-3.10/0504-MIPS-ralink-add-pcie-driver.patch [deleted file]
target/linux/ramips/patches-3.10/0505-watchdog-add-MT7621-support.patch [deleted file]
target/linux/ramips/patches-3.10/0506-GPIO-ralink-add-mt7621-gpio-controller.patch [deleted file]
target/linux/ramips/patches-3.10/0507-MTD-add-mt7621-nand-support.patch [deleted file]
target/linux/ramips/patches-3.10/0508-MIPS-GIC-Fix-gic_set_affinity-infinite-loop.patch [deleted file]
target/linux/ramips/patches-3.10/0509-MIPS-Kconfig-CMP-support-needs-to-select-SMP-as-well.patch [deleted file]
target/linux/ramips/patches-3.10/0510-MIPS-Fix-SMP-core-calculations-when-using-MT-support.patch [deleted file]
target/linux/ramips/patches-3.10/0511-MIPS-GIC-Send-IPIs-using-the-GIC.patch [deleted file]
target/linux/ramips/patches-3.10/0512-USB-add-xhci-support-for-mt7621.patch [deleted file]
target/linux/ramips/patches-3.10/800-eco.patch [deleted file]
target/linux/ramips/patches-3.10/999-clk.patch [deleted file]
target/linux/ramips/patches-3.10/999-memory-detect.patch [deleted file]
target/linux/ramips/patches-3.10/999-mt7620n.patch [deleted file]
target/linux/ramips/patches-3.10/999-pinctrl_fixes.patch [deleted file]
target/linux/ramips/patches-3.10/999-raeth_fixes.patch [deleted file]
target/linux/ramips/rt288x/config-3.10

index 9fa9d0a..83df878 100644 (file)
@@ -72,8 +72,8 @@
                        compatible = "ns16550a";
                        reg = <0xc00 0x100>;
 
-/*                     interrupt-parent = <&gic>;
-                       interrupts = <26>;*/
+                       interrupt-parent = <&gic>;
+                       interrupts = <26>;
 
                        reg-shift = <2>;
                        reg-io-width = <4>;
diff --git a/target/linux/ramips/files/drivers/usb/host/mtk-phy-7621.c b/target/linux/ramips/files/drivers/usb/host/mtk-phy-7621.c
deleted file mode 100644 (file)
index 4e9c0d7..0000000
+++ /dev/null
@@ -1,445 +0,0 @@
-#include "mtk-phy.h"
-
-#ifdef CONFIG_PROJECT_7621
-#include "mtk-phy-7621.h"
-
-//not used on SoC
-PHY_INT32 phy_init(struct u3phy_info *info){   
-       return PHY_TRUE;
-}
-
-//not used on SoC
-PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase){
-       return PHY_TRUE;
-}
-
-//--------------------------------------------------------
-//    Function : fgEyeScanHelper_CheckPtInRegion()
-// Description : Check if the test point is in a rectangle region.
-//               If it is in the rectangle, also check if this point
-//               is on the multiple of deltaX and deltaY.
-//   Parameter : strucScanRegion * prEye - the region
-//               BYTE bX
-//               BYTE bY
-//      Return : BYTE - TRUE :  This point needs to be tested
-//                      FALSE:  This point will be omitted
-//        Note : First check within the rectangle.
-//               Secondly, use modulous to check if the point will be tested.
-//--------------------------------------------------------
-static PHY_INT8 fgEyeScanHelper_CheckPtInRegion(struct strucScanRegion * prEye, PHY_INT8 bX, PHY_INT8 bY)
-{
-  PHY_INT8 fgValid = true;
-
-
-  /// Be careful, the axis origin is on the TOP-LEFT corner.
-  /// Therefore the top-left point has the minimum X and Y
-  /// Botton-right point is the maximum X and Y
-  if ( (prEye->bX_tl <= bX) && (bX <= prEye->bX_br)
-    && (prEye->bY_tl <= bY) && (bY <= prEye->bX_br))
-  {
-    // With the region, now check whether or not the input test point is
-    // on the multiples of X and Y
-    // Do not have to worry about negative value, because we have already
-    // check the input bX, and bY is within the region.
-    if ( ((bX - prEye->bX_tl) % (prEye->bDeltaX))
-      || ((bY - prEye->bY_tl) % (prEye->bDeltaY)) )
-    {
-      // if the division will have remainder, that means
-      // the input test point is on the multiples of X and Y
-      fgValid = false;
-    }
-    else
-    {
-    }
-  }
-  else
-  {
-    
-    fgValid = false;
-  }
-  return fgValid;
-}
-
-//--------------------------------------------------------
-//    Function : EyeScanHelper_RunTest()
-// Description : Enable the test, and wait til it is completed
-//   Parameter : None
-//      Return : None
-//        Note : None
-//--------------------------------------------------------
-static void EyeScanHelper_RunTest(struct u3phy_info *info)
-{
-       DRV_UDELAY(100);
-       // Disable the test
-       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-               , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 0);      //RG_SSUSB_RX_EYE_CNT_EN = 0
-       DRV_UDELAY(100);
-       // Run the test
-       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-               , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 1);      //RG_SSUSB_RX_EYE_CNT_EN = 1
-       DRV_UDELAY(100);
-       // Wait til it's done
-       //RGS_SSUSB_RX_EYE_CNT_RDY
-       while(!U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
-               , RGS_SSUSB_EQ_EYE_CNT_RDY_OFST, RGS_SSUSB_EQ_EYE_CNT_RDY));
-}
-
-//--------------------------------------------------------
-//    Function : fgEyeScanHelper_CalNextPoint()
-// Description : Calcualte the test point for the measurement
-//   Parameter : None
-//      Return : BOOL - TRUE :  the next point is within the
-//                              boundaryof HW limit
-//                      FALSE:  the next point is out of the HW limit
-//        Note : The next point is obtained by calculating
-//               from the bottom left of the region rectangle
-//               and then scanning up until it reaches the upper
-//               limit. At this time, the x will increment, and
-//               start scanning downwards until the y hits the
-//               zero.
-//--------------------------------------------------------
-static PHY_INT8 fgEyeScanHelper_CalNextPoint(void)
-{
-  if ( ((_bYcurr == MAX_Y) && (_eScanDir == SCAN_DN))
-    || ((_bYcurr == MIN_Y) && (_eScanDir == SCAN_UP))
-        )
-  {
-    /// Reaches the limit of Y axis
-    /// Increment X
-    _bXcurr++;
-    _fgXChged = true;
-    _eScanDir = (_eScanDir == SCAN_UP) ? SCAN_DN : SCAN_UP;
-
-    if (_bXcurr > MAX_X)
-    {
-      return false;
-    }
-  }
-  else
-  {
-    _bYcurr = (_eScanDir == SCAN_DN) ? _bYcurr + 1 : _bYcurr - 1;
-    _fgXChged = false;
-  }
-  return PHY_TRUE;
-}
-
-PHY_INT32 eyescan_init(struct u3phy_info *info){
-       //initial PHY setting
-       U3PhyWriteField32(((PHY_UINT32)&info->u3phya_regs->rega)
-               , RG_SSUSB_CDR_EPEN_OFST, RG_SSUSB_CDR_EPEN, 1);        
-       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->phyd_mix3)
-               , RG_SSUSB_FORCE_CDR_PI_PWD_OFST, RG_SSUSB_FORCE_CDR_PI_PWD, 1);
-       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
-               , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1);    //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
-       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
-               , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1);        //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
-       return PHY_TRUE;
-}
-
-PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
-               , PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt){
-       PHY_INT32 cOfst = 0;
-       PHY_UINT8 bIdxX = 0;
-       PHY_UINT8 bIdxY = 0;
-       //PHY_INT8 bCnt = 0;
-       PHY_UINT8 bIdxCycCnt = 0;
-       PHY_INT8 fgValid;
-       PHY_INT8 cX;
-       PHY_INT8 cY;
-       PHY_UINT8 bExtendCnt;
-       PHY_INT8 isContinue;
-       //PHY_INT8 isBreak;
-       PHY_UINT32 wErr0 = 0, wErr1 = 0;
-       //PHY_UINT32 temp;
-
-       PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
-       PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
-
-       _rEye1.bX_tl = x_t1;
-       _rEye1.bY_tl = y_t1;
-       _rEye1.bX_br = x_br;
-       _rEye1.bY_br = y_br;
-       _rEye1.bDeltaX = delta_x;
-       _rEye1.bDeltaY = delta_y;
-
-       _rEye2.bX_tl = x_t1;
-       _rEye2.bY_tl = y_t1;
-       _rEye2.bX_br = x_br;
-       _rEye2.bY_br = y_br;
-       _rEye2.bDeltaX = delta_x;
-       _rEye2.bDeltaY = delta_y;
-
-       _rTestCycle.wEyeCnt = eye_cnt;
-       _rTestCycle.bNumOfEyeCnt = num_cnt;
-       _rTestCycle.bNumOfIgnoreCnt = num_ignore_cnt;
-       _rTestCycle.bPICalEn = PI_cal_en;       
-
-       _bXcurr = 0;
-       _bYcurr = 0;
-       _eScanDir = SCAN_DN;
-       _fgXChged = false;
-
-       printk("x_t1: %x, y_t1: %x, x_br: %x, y_br: %x, delta_x: %x, delta_y: %x, \
-               eye_cnt: %x, num_cnt: %x, PI_cal_en: %x, num_ignore_cnt: %x\n", \
-               x_t1, y_t1, x_br, y_br, delta_x, delta_y, eye_cnt, num_cnt, PI_cal_en, num_ignore_cnt);         
-
-       //force SIGDET to OFF
-       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
-               , RG_SSUSB_RX_SIGDET_EN_SEL_OFST, RG_SSUSB_RX_SIGDET_EN_SEL, 1);                                                //RG_SSUSB_RX_SIGDET_SEL = 1
-       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
-               , RG_SSUSB_RX_SIGDET_EN_OFST, RG_SSUSB_RX_SIGDET_EN, 0);                                                //RG_SSUSB_RX_SIGDET_EN = 0
-       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
-               , RG_SSUSB_EQ_SIGDET_OFST, RG_SSUSB_EQ_SIGDET, 0);                              //RG_SSUSB_RX_SIGDET = 0
-
-       // RX_TRI_DET_EN to Disable
-       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq3)
-               , RG_SSUSB_EQ_TRI_DET_EN_OFST, RG_SSUSB_EQ_TRI_DET_EN, 0);              //RG_SSUSB_RX_TRI_DET_EN = 0
-
-       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-               , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1);              //RG_SSUSB_EYE_MON_EN = 1
-       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-               , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, 0);            //RG_SSUSB_RX_EYE_XOFFSET = 0
-       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-               , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, 0);                              //RG_SSUSB_RX_EYE0_Y = 0
-       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-               , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, 0);                              //RG_SSUSB_RX_EYE1_Y = 0
-
-
-       if (PI_cal_en){
-               // PI Calibration
-               U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
-                       , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1);        //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
-               U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
-                       , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0);                //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
-               U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
-                       , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1);                //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
-
-               DRV_UDELAY(20);
-
-               U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
-                       , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0);                //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
-               _bPIResult = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
-                       , RGS_SSUSB_EQ_PILPO_OFST, RGS_SSUSB_EQ_PILPO);                         //read RGS_SSUSB_RX_PILPO
-
-               printk(KERN_ERR "PI result: %d\n", _bPIResult);
-       }
-       // Read Initial DAC
-       // Set CYCLE
-       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye3)
-               ,RG_SSUSB_EQ_EYE_CNT_OFST, RG_SSUSB_EQ_EYE_CNT, eye_cnt);                       //RG_SSUSB_RX_EYE_CNT
-
-       // Eye Monitor Feature
-       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
-               , RG_SSUSB_EQ_EYE_MASK_OFST, RG_SSUSB_EQ_EYE_MASK, 0x3ff);              //RG_SSUSB_RX_EYE_MASK = 0x3ff
-       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-               , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1);              //RG_SSUSB_EYE_MON_EN = 1
-
-       // Move X,Y to the top-left corner
-       for (cOfst = 0; cOfst >= -64; cOfst--)
-       {
-               U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-                       ,RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
-       }
-       for (cOfst = 0; cOfst < 64; cOfst++)
-       {
-               U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-                       , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst);                  //RG_SSUSB_RX_EYE0_Y
-               U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-                       , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst);                  //RG_SSUSB_RX_EYE1_Y
-       }
-       //ClearErrorResult
-       for(bIdxCycCnt = 0; bIdxCycCnt < CYCLE_COUNT_MAX; bIdxCycCnt++){
-               for(bIdxX = 0; bIdxX < ERRCNT_MAX; bIdxX++)
-               {
-                       for(bIdxY = 0; bIdxY < ERRCNT_MAX; bIdxY++){
-                               pwErrCnt0[bIdxCycCnt][bIdxX][bIdxY] = 0;
-                               pwErrCnt1[bIdxCycCnt][bIdxX][bIdxY] = 0;
-                       }
-               }
-       }
-       isContinue = true;
-       while(isContinue){
-               //printk(KERN_ERR "_bXcurr: %d, _bYcurr: %d\n", _bXcurr, _bYcurr);
-               // The point is within the boundary, then let's check if it is within
-           // the testing region.
-           // The point is only test-able if one of the eye region
-           // includes this point.
-           fgValid = fgEyeScanHelper_CheckPtInRegion(&_rEye1, _bXcurr, _bYcurr)
-           || fgEyeScanHelper_CheckPtInRegion(&_rEye2, _bXcurr, _bYcurr);
-               // Translate bX and bY to 2's complement from where the origin was on the
-               // top left corner.
-               // 0x40 and 0x3F needs a bit of thinking!!!! >"<
-               cX = (_bXcurr ^ 0x40);
-               cY = (_bYcurr ^ 0x3F);
-
-               // Set X if necessary
-               if (_fgXChged == true)
-               {
-                       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-                               , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cX);           //RG_SSUSB_RX_EYE_XOFFSET
-               }
-               // Set Y
-               U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-                       , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cY);                     //RG_SSUSB_RX_EYE0_Y
-               U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-                       , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cY);                     //RG_SSUSB_RX_EYE1_Y
-
-               /// Test this point!
-               if (fgValid){
-                       for (bExtendCnt = 0; bExtendCnt < num_ignore_cnt; bExtendCnt++)
-                       {
-                               //run test
-                               EyeScanHelper_RunTest(info);
-                       }
-                       for (bExtendCnt = 0; bExtendCnt < num_cnt; bExtendCnt++)
-                       {
-                               EyeScanHelper_RunTest(info);
-                               wErr0 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon3)
-                                       , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0);
-                               wErr1 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon4)
-                                       , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1);
-
-                               pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr] = wErr0;
-                               pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr] = wErr1;
-
-                               //EyeScanHelper_GetResult(&_rRes.pwErrCnt0[bCnt], &_rRes.pwErrCnt1[bCnt]);
-//                             printk(KERN_ERR "cnt[%d] cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n"
-//                                     , bExtendCnt, _bXcurr, _bYcurr, cX, cY, pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr], pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr]);
-                       }
-                       //printk(KERN_ERR "cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n", _bXcurr, _bYcurr, cX, cY, pwErrCnt0[0][_bXcurr][_bYcurr], pwErrCnt1[0][_bXcurr][_bYcurr]);
-               }
-               else{
-                       
-               }
-               if (fgEyeScanHelper_CalNextPoint() == false){
-#if 0
-                       printk(KERN_ERR "Xcurr [0x%x] Ycurr [0x%x]\n", _bXcurr, _bYcurr);
-                       printk(KERN_ERR "XcurrREG [0x%x] YcurrREG [0x%x]\n", cX, cY);
-#endif
-                       printk(KERN_ERR "end of eye scan\n");
-                       isContinue = false;
-               }
-       }
-       printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
-               , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
-               , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
-
-       // Move X,Y to the top-left corner
-       for (cOfst = 63; cOfst >= 0; cOfst--)
-       {
-               U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-                       , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst);        //RG_SSUSB_RX_EYE_XOFFSET
-       }
-       for (cOfst = 63; cOfst >= 0; cOfst--)
-       {
-               U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-                       , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst);
-               U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-                       , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst);
-
-       }
-       printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
-               , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
-               , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
-
-       printk(KERN_ERR "PI result: %d\n", _bPIResult);
-       printk(KERN_ERR "pwErrCnt0 addr: 0x%x\n", (PHY_UINT32)pwErrCnt0);
-       printk(KERN_ERR "pwErrCnt1 addr: 0x%x\n", (PHY_UINT32)pwErrCnt1);
-       
-       return PHY_TRUE;
-}
-
-//not used on SoC
-PHY_INT32 u2_save_cur_en(struct u3phy_info *info){
-       return PHY_TRUE;
-}
-
-//not used on SoC
-PHY_INT32 u2_save_cur_re(struct u3phy_info *info){
-       return PHY_TRUE;
-}
-
-PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info){
-       PHY_INT32 i=0;
-       //PHY_INT32 j=0;
-       //PHY_INT8 u1SrCalVal = 0;
-       //PHY_INT8 u1Reg_addr_HSTX_SRCAL_EN;
-       PHY_INT32 fgRet = 0;    
-       PHY_INT32 u4FmOut = 0;  
-       PHY_INT32 u4Tmp = 0;
-       //PHY_INT32 temp;
-
-       // => RG_USB20_HSTX_SRCAL_EN = 1
-       // enable HS TX SR calibration
-       U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
-               , RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0x1);
-       DRV_MSLEEP(1);
-
-       // => RG_FRCK_EN = 1    
-       // Enable free run clock
-       U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
-               , RG_FRCK_EN_OFST, RG_FRCK_EN, 1);
-
-       // MT6290 HS signal quality patch
-       // => RG_CYCLECNT = 400
-       // Setting cyclecnt =400
-       U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
-               , RG_CYCLECNT_OFST, RG_CYCLECNT, 0x400);
-
-       // => RG_FREQDET_EN = 1
-       // Enable frequency meter
-       U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
-               , RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0x1);
-
-       // wait for FM detection done, set 10ms timeout
-       for(i=0; i<10; i++){
-               // => u4FmOut = USB_FM_OUT
-               // read FM_OUT
-               u4FmOut = U3PhyReadReg32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr0));
-               printk("FM_OUT value: u4FmOut = %d(0x%08X)\n", u4FmOut, u4FmOut);
-
-               // check if FM detection done 
-               if (u4FmOut != 0)
-               {
-                       fgRet = 0;
-                       printk("FM detection done! loop = %d\n", i);
-                       
-                       break;
-               }
-
-               fgRet = 1;
-               DRV_MSLEEP(1);
-       }
-       // => RG_FREQDET_EN = 0
-       // disable frequency meter
-       U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
-               , RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0);
-
-       // => RG_FRCK_EN = 0
-       // disable free run clock
-       U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
-               , RG_FRCK_EN_OFST, RG_FRCK_EN, 0);
-
-       // => RG_USB20_HSTX_SRCAL_EN = 0
-       // disable HS TX SR calibration
-       U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
-               , RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0);
-       DRV_MSLEEP(1);
-
-       if(u4FmOut == 0){
-               U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
-                       , RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, 0x4);
-               
-               fgRet = 1;
-       }
-       else{
-               // set reg = (1024/FM_OUT) * 25 * 0.028 (round to the nearest digits)
-               u4Tmp = (((1024 * 25 * U2_SR_COEF_7621) / u4FmOut) + 500) / 1000;
-               printk("SR calibration value u1SrCalVal = %d\n", (PHY_UINT8)u4Tmp);
-               U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
-                       , RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, u4Tmp);
-       }
-       return fgRet;
-}
-
-#endif
diff --git a/target/linux/ramips/files/drivers/usb/host/mtk-phy-7621.h b/target/linux/ramips/files/drivers/usb/host/mtk-phy-7621.h
deleted file mode 100644 (file)
index 41b0c77..0000000
+++ /dev/null
@@ -1,2871 +0,0 @@
-#ifdef CONFIG_PROJECT_7621
-#ifndef __MTK_PHY_7621_H
-#define __MTK_PHY_7621_H
-
-#define U2_SR_COEF_7621 28
-
-///////////////////////////////////////////////////////////////////////////////
-
-struct u2phy_reg {
-       //0x0
-       PHY_LE32 u2phyac0;
-       PHY_LE32 u2phyac1;
-       PHY_LE32 u2phyac2;
-       PHY_LE32 reserve0;
-       //0x10
-       PHY_LE32 u2phyacr0;
-       PHY_LE32 u2phyacr1;
-       PHY_LE32 u2phyacr2;
-       PHY_LE32 u2phyacr3;
-       //0x20
-       PHY_LE32 u2phyacr4;
-       PHY_LE32 u2phyamon0;
-       PHY_LE32 reserve1[2];
-       //0x30~0x50
-       PHY_LE32 reserve2[12];
-       //0x60
-       PHY_LE32 u2phydcr0;
-       PHY_LE32 u2phydcr1;
-       PHY_LE32 u2phydtm0;
-       PHY_LE32 u2phydtm1;
-       //0x70
-       PHY_LE32 u2phydmon0;
-       PHY_LE32 u2phydmon1;
-       PHY_LE32 u2phydmon2;
-       PHY_LE32 u2phydmon3;
-       //0x80
-       PHY_LE32 u2phybc12c;
-       PHY_LE32 u2phybc12c1;
-       PHY_LE32 reserve3[2];
-       //0x90~0xe0
-       PHY_LE32 reserve4[24];
-       //0xf0
-       PHY_LE32 reserve6[3];
-       PHY_LE32 regfcom;
-};
-
-//U3D_U2PHYAC0
-#define RG_USB20_USBPLL_DIVEN                     (0x7<<28) //30:28
-#define RG_USB20_USBPLL_CKCTRL                    (0x3<<26) //27:26
-#define RG_USB20_USBPLL_PREDIV                    (0x3<<24) //25:24
-#define RG_USB20_USBPLL_FORCE_ON                  (0x1<<23) //23:23
-#define RG_USB20_USBPLL_FBDIV                     (0x7f<<16) //22:16
-#define RG_USB20_REF_EN                           (0x1<<15) //15:15
-#define RG_USB20_INTR_EN                          (0x1<<14) //14:14
-#define RG_USB20_BG_TRIM                          (0xf<<8) //11:8
-#define RG_USB20_BG_RBSEL                         (0x3<<6) //7:6
-#define RG_USB20_BG_RASEL                         (0x3<<4) //5:4
-#define RG_USB20_BGR_DIV                          (0x3<<2) //3:2
-#define RG_SIFSLV_CHP_EN                          (0x1<<1) //1:1
-#define RG_SIFSLV_BGR_EN                          (0x1<<0) //0:0
-
-//U3D_U2PHYAC1
-#define RG_USB20_VRT_VREF_SEL                     (0x7<<28) //30:28
-#define RG_USB20_TERM_VREF_SEL                    (0x7<<24) //26:24
-#define RG_USB20_MPX_SEL                          (0xff<<16) //23:16
-#define RG_USB20_MPX_OUT_SEL                      (0x3<<12) //13:12
-#define RG_USB20_TX_PH_ROT_SEL                    (0x7<<8) //10:8
-#define RG_USB20_USBPLL_ACCEN                     (0x1<<3) //3:3
-#define RG_USB20_USBPLL_LF                        (0x1<<2) //2:2
-#define RG_USB20_USBPLL_BR                        (0x1<<1) //1:1
-#define RG_USB20_USBPLL_BP                        (0x1<<0) //0:0
-
-//U3D_U2PHYAC2
-#define RG_SIFSLV_MAC_BANDGAP_EN                  (0x1<<17) //17:17
-#define RG_SIFSLV_MAC_CHOPPER_EN                  (0x1<<16) //16:16
-#define RG_USB20_CLKREF_REV                       (0xff<<0) //7:0
-
-//U3D_U2PHYACR0
-#define RG_USB20_ICUSB_EN                         (0x1<<24) //24:24
-#define RG_USB20_HSTX_SRCAL_EN                    (0x1<<23) //23:23
-#define RG_USB20_HSTX_SRCTRL                      (0x7<<16) //18:16
-#define RG_USB20_LS_CR                            (0x7<<12) //14:12
-#define RG_USB20_FS_CR                            (0x7<<8) //10:8
-#define RG_USB20_LS_SR                            (0x7<<4) //6:4
-#define RG_USB20_FS_SR                            (0x7<<0) //2:0
-
-//U3D_U2PHYACR1
-#define RG_USB20_INIT_SQ_EN_DG                    (0x3<<28) //29:28
-#define RG_USB20_SQD                              (0x3<<24) //25:24
-#define RG_USB20_HSTX_TMODE_SEL                   (0x3<<20) //21:20
-#define RG_USB20_HSTX_TMODE_EN                    (0x1<<19) //19:19
-#define RG_USB20_PHYD_MONEN                       (0x1<<18) //18:18
-#define RG_USB20_INLPBK_EN                        (0x1<<17) //17:17
-#define RG_USB20_CHIRP_EN                         (0x1<<16) //16:16
-#define RG_USB20_DM_ABIST_SOURCE_EN               (0x1<<15) //15:15
-#define RG_USB20_DM_ABIST_SELE                    (0xf<<8) //11:8
-#define RG_USB20_DP_ABIST_SOURCE_EN               (0x1<<7) //7:7
-#define RG_USB20_DP_ABIST_SELE                    (0xf<<0) //3:0
-
-//U3D_U2PHYACR2
-#define RG_USB20_OTG_ABIST_SELE                   (0x7<<29) //31:29
-#define RG_USB20_OTG_ABIST_EN                     (0x1<<28) //28:28
-#define RG_USB20_OTG_VBUSCMP_EN                   (0x1<<27) //27:27
-#define RG_USB20_OTG_VBUSTH                       (0x7<<24) //26:24
-#define RG_USB20_DISC_FIT_EN                      (0x1<<22) //22:22
-#define RG_USB20_DISCD                            (0x3<<20) //21:20
-#define RG_USB20_DISCTH                           (0xf<<16) //19:16
-#define RG_USB20_SQCAL_EN                         (0x1<<15) //15:15
-#define RG_USB20_SQCAL                            (0xf<<8) //11:8
-#define RG_USB20_SQTH                             (0xf<<0) //3:0
-
-//U3D_U2PHYACR3
-#define RG_USB20_HSTX_DBIST                       (0xf<<28) //31:28
-#define RG_USB20_HSTX_BIST_EN                     (0x1<<26) //26:26
-#define RG_USB20_HSTX_I_EN_MODE                   (0x3<<24) //25:24
-#define RG_USB20_HSRX_TMODE_EN                    (0x1<<23) //23:23
-#define RG_USB20_HSRX_BIAS_EN_SEL                 (0x3<<20) //21:20
-#define RG_USB20_USB11_TMODE_EN                   (0x1<<19) //19:19
-#define RG_USB20_TMODE_FS_LS_TX_EN                (0x1<<18) //18:18
-#define RG_USB20_TMODE_FS_LS_RCV_EN               (0x1<<17) //17:17
-#define RG_USB20_TMODE_FS_LS_MODE                 (0x1<<16) //16:16
-#define RG_USB20_HS_TERM_EN_MODE                  (0x3<<13) //14:13
-#define RG_USB20_PUPD_BIST_EN                     (0x1<<12) //12:12
-#define RG_USB20_EN_PU_DM                         (0x1<<11) //11:11
-#define RG_USB20_EN_PD_DM                         (0x1<<10) //10:10
-#define RG_USB20_EN_PU_DP                         (0x1<<9) //9:9
-#define RG_USB20_EN_PD_DP                         (0x1<<8) //8:8
-#define RG_USB20_PHY_REV                          (0xff<<0) //7:0
-
-//U3D_U2PHYACR4
-#define RG_USB20_DP_100K_MODE                     (0x1<<18) //18:18
-#define RG_USB20_DM_100K_EN                       (0x1<<17) //17:17
-#define USB20_DP_100K_EN                          (0x1<<16) //16:16
-#define USB20_GPIO_DM_I                           (0x1<<15) //15:15
-#define USB20_GPIO_DP_I                           (0x1<<14) //14:14
-#define USB20_GPIO_DM_OE                          (0x1<<13) //13:13
-#define USB20_GPIO_DP_OE                          (0x1<<12) //12:12
-#define RG_USB20_GPIO_CTL                         (0x1<<9) //9:9
-#define USB20_GPIO_MODE                           (0x1<<8) //8:8
-#define RG_USB20_TX_BIAS_EN                       (0x1<<5) //5:5
-#define RG_USB20_TX_VCMPDN_EN                     (0x1<<4) //4:4
-#define RG_USB20_HS_SQ_EN_MODE                    (0x3<<2) //3:2
-#define RG_USB20_HS_RCV_EN_MODE                   (0x3<<0) //1:0
-
-//U3D_U2PHYAMON0
-#define RGO_USB20_GPIO_DM_O                       (0x1<<1) //1:1
-#define RGO_USB20_GPIO_DP_O                       (0x1<<0) //0:0
-
-//U3D_U2PHYDCR0
-#define RG_USB20_CDR_TST                          (0x3<<30) //31:30
-#define RG_USB20_GATED_ENB                        (0x1<<29) //29:29
-#define RG_USB20_TESTMODE                         (0x3<<26) //27:26
-#define RG_USB20_PLL_STABLE                       (0x1<<25) //25:25
-#define RG_USB20_PLL_FORCE_ON                     (0x1<<24) //24:24
-#define RG_USB20_PHYD_RESERVE                     (0xffff<<8) //23:8
-#define RG_USB20_EBTHRLD                          (0x1<<7) //7:7
-#define RG_USB20_EARLY_HSTX_I                     (0x1<<6) //6:6
-#define RG_USB20_TX_TST                           (0x1<<5) //5:5
-#define RG_USB20_NEGEDGE_ENB                      (0x1<<4) //4:4
-#define RG_USB20_CDR_FILT                         (0xf<<0) //3:0
-
-//U3D_U2PHYDCR1
-#define RG_USB20_PROBE_SEL                        (0xff<<24) //31:24
-#define RG_USB20_DRVVBUS                          (0x1<<23) //23:23
-#define RG_DEBUG_EN                               (0x1<<22) //22:22
-#define RG_USB20_OTG_PROBE                        (0x3<<20) //21:20
-#define RG_USB20_SW_PLLMODE                       (0x3<<18) //19:18
-#define RG_USB20_BERTH                            (0x3<<16) //17:16
-#define RG_USB20_LBMODE                           (0x3<<13) //14:13
-#define RG_USB20_FORCE_TAP                        (0x1<<12) //12:12
-#define RG_USB20_TAPSEL                           (0xfff<<0) //11:0
-
-//U3D_U2PHYDTM0
-#define RG_UART_MODE                              (0x3<<30) //31:30
-#define FORCE_UART_I                              (0x1<<29) //29:29
-#define FORCE_UART_BIAS_EN                        (0x1<<28) //28:28
-#define FORCE_UART_TX_OE                          (0x1<<27) //27:27
-#define FORCE_UART_EN                             (0x1<<26) //26:26
-#define FORCE_USB_CLKEN                           (0x1<<25) //25:25
-#define FORCE_DRVVBUS                             (0x1<<24) //24:24
-#define FORCE_DATAIN                              (0x1<<23) //23:23
-#define FORCE_TXVALID                             (0x1<<22) //22:22
-#define FORCE_DM_PULLDOWN                         (0x1<<21) //21:21
-#define FORCE_DP_PULLDOWN                         (0x1<<20) //20:20
-#define FORCE_XCVRSEL                             (0x1<<19) //19:19
-#define FORCE_SUSPENDM                            (0x1<<18) //18:18
-#define FORCE_TERMSEL                             (0x1<<17) //17:17
-#define FORCE_OPMODE                              (0x1<<16) //16:16
-#define UTMI_MUXSEL                               (0x1<<15) //15:15
-#define RG_RESET                                  (0x1<<14) //14:14
-#define RG_DATAIN                                 (0xf<<10) //13:10
-#define RG_TXVALIDH                               (0x1<<9) //9:9
-#define RG_TXVALID                                (0x1<<8) //8:8
-#define RG_DMPULLDOWN                             (0x1<<7) //7:7
-#define RG_DPPULLDOWN                             (0x1<<6) //6:6
-#define RG_XCVRSEL                                (0x3<<4) //5:4
-#define RG_SUSPENDM                               (0x1<<3) //3:3
-#define RG_TERMSEL                                (0x1<<2) //2:2
-#define RG_OPMODE                                 (0x3<<0) //1:0
-
-//U3D_U2PHYDTM1
-#define RG_USB20_PRBS7_EN                         (0x1<<31) //31:31
-#define RG_USB20_PRBS7_BITCNT                     (0x3f<<24) //29:24
-#define RG_USB20_CLK48M_EN                        (0x1<<23) //23:23
-#define RG_USB20_CLK60M_EN                        (0x1<<22) //22:22
-#define RG_UART_I                                 (0x1<<19) //19:19
-#define RG_UART_BIAS_EN                           (0x1<<18) //18:18
-#define RG_UART_TX_OE                             (0x1<<17) //17:17
-#define RG_UART_EN                                (0x1<<16) //16:16
-#define FORCE_VBUSVALID                           (0x1<<13) //13:13
-#define FORCE_SESSEND                             (0x1<<12) //12:12
-#define FORCE_BVALID                              (0x1<<11) //11:11
-#define FORCE_AVALID                              (0x1<<10) //10:10
-#define FORCE_IDDIG                               (0x1<<9) //9:9
-#define FORCE_IDPULLUP                            (0x1<<8) //8:8
-#define RG_VBUSVALID                              (0x1<<5) //5:5
-#define RG_SESSEND                                (0x1<<4) //4:4
-#define RG_BVALID                                 (0x1<<3) //3:3
-#define RG_AVALID                                 (0x1<<2) //2:2
-#define RG_IDDIG                                  (0x1<<1) //1:1
-#define RG_IDPULLUP                               (0x1<<0) //0:0
-
-//U3D_U2PHYDMON0
-#define RG_USB20_PRBS7_BERTH                      (0xff<<0) //7:0
-
-//U3D_U2PHYDMON1
-#define USB20_UART_O                              (0x1<<31) //31:31
-#define RGO_USB20_LB_PASS                         (0x1<<30) //30:30
-#define RGO_USB20_LB_DONE                         (0x1<<29) //29:29
-#define AD_USB20_BVALID                           (0x1<<28) //28:28
-#define USB20_IDDIG                               (0x1<<27) //27:27
-#define AD_USB20_VBUSVALID                        (0x1<<26) //26:26
-#define AD_USB20_SESSEND                          (0x1<<25) //25:25
-#define AD_USB20_AVALID                           (0x1<<24) //24:24
-#define USB20_LINE_STATE                          (0x3<<22) //23:22
-#define USB20_HST_DISCON                          (0x1<<21) //21:21
-#define USB20_TX_READY                            (0x1<<20) //20:20
-#define USB20_RX_ERROR                            (0x1<<19) //19:19
-#define USB20_RX_ACTIVE                           (0x1<<18) //18:18
-#define USB20_RX_VALIDH                           (0x1<<17) //17:17
-#define USB20_RX_VALID                            (0x1<<16) //16:16
-#define USB20_DATA_OUT                            (0xffff<<0) //15:0
-
-//U3D_U2PHYDMON2
-#define RGO_TXVALID_CNT                           (0xff<<24) //31:24
-#define RGO_RXACTIVE_CNT                          (0xff<<16) //23:16
-#define RGO_USB20_LB_BERCNT                       (0xff<<8) //15:8
-#define USB20_PROBE_OUT                           (0xff<<0) //7:0
-
-//U3D_U2PHYDMON3
-#define RGO_USB20_PRBS7_ERRCNT                    (0xffff<<16) //31:16
-#define RGO_USB20_PRBS7_DONE                      (0x1<<3) //3:3
-#define RGO_USB20_PRBS7_LOCK                      (0x1<<2) //2:2
-#define RGO_USB20_PRBS7_PASS                      (0x1<<1) //1:1
-#define RGO_USB20_PRBS7_PASSTH                    (0x1<<0) //0:0
-
-//U3D_U2PHYBC12C
-#define RG_SIFSLV_CHGDT_DEGLCH_CNT                (0xf<<28) //31:28
-#define RG_SIFSLV_CHGDT_CTRL_CNT                  (0xf<<24) //27:24
-#define RG_SIFSLV_CHGDT_FORCE_MODE                (0x1<<16) //16:16
-#define RG_CHGDT_ISRC_LEV                         (0x3<<14) //15:14
-#define RG_CHGDT_VDATSRC                          (0x1<<13) //13:13
-#define RG_CHGDT_BGVREF_SEL                       (0x7<<10) //12:10
-#define RG_CHGDT_RDVREF_SEL                       (0x3<<8) //9:8
-#define RG_CHGDT_ISRC_DP                          (0x1<<7) //7:7
-#define RG_SIFSLV_CHGDT_OPOUT_DM                  (0x1<<6) //6:6
-#define RG_CHGDT_VDAT_DM                          (0x1<<5) //5:5
-#define RG_CHGDT_OPOUT_DP                         (0x1<<4) //4:4
-#define RG_SIFSLV_CHGDT_VDAT_DP                   (0x1<<3) //3:3
-#define RG_SIFSLV_CHGDT_COMP_EN                   (0x1<<2) //2:2
-#define RG_SIFSLV_CHGDT_OPDRV_EN                  (0x1<<1) //1:1
-#define RG_CHGDT_EN                               (0x1<<0) //0:0
-
-//U3D_U2PHYBC12C1
-#define RG_CHGDT_REV                              (0xff<<0) //7:0
-
-//U3D_REGFCOM
-#define RG_PAGE                                   (0xff<<24) //31:24
-#define I2C_MODE                                  (0x1<<16) //16:16
-
-
-/* OFFSET  */
-
-//U3D_U2PHYAC0
-#define RG_USB20_USBPLL_DIVEN_OFST                (28)
-#define RG_USB20_USBPLL_CKCTRL_OFST               (26)
-#define RG_USB20_USBPLL_PREDIV_OFST               (24)
-#define RG_USB20_USBPLL_FORCE_ON_OFST             (23)
-#define RG_USB20_USBPLL_FBDIV_OFST                (16)
-#define RG_USB20_REF_EN_OFST                      (15)
-#define RG_USB20_INTR_EN_OFST                     (14)
-#define RG_USB20_BG_TRIM_OFST                     (8)
-#define RG_USB20_BG_RBSEL_OFST                    (6)
-#define RG_USB20_BG_RASEL_OFST                    (4)
-#define RG_USB20_BGR_DIV_OFST                     (2)
-#define RG_SIFSLV_CHP_EN_OFST                     (1)
-#define RG_SIFSLV_BGR_EN_OFST                     (0)
-
-//U3D_U2PHYAC1
-#define RG_USB20_VRT_VREF_SEL_OFST                (28)
-#define RG_USB20_TERM_VREF_SEL_OFST               (24)
-#define RG_USB20_MPX_SEL_OFST                     (16)
-#define RG_USB20_MPX_OUT_SEL_OFST                 (12)
-#define RG_USB20_TX_PH_ROT_SEL_OFST               (8)
-#define RG_USB20_USBPLL_ACCEN_OFST                (3)
-#define RG_USB20_USBPLL_LF_OFST                   (2)
-#define RG_USB20_USBPLL_BR_OFST                   (1)
-#define RG_USB20_USBPLL_BP_OFST                   (0)
-
-//U3D_U2PHYAC2
-#define RG_SIFSLV_MAC_BANDGAP_EN_OFST             (17)
-#define RG_SIFSLV_MAC_CHOPPER_EN_OFST             (16)
-#define RG_USB20_CLKREF_REV_OFST                  (0)
-
-//U3D_U2PHYACR0
-#define RG_USB20_ICUSB_EN_OFST                    (24)
-#define RG_USB20_HSTX_SRCAL_EN_OFST               (23)
-#define RG_USB20_HSTX_SRCTRL_OFST                 (16)
-#define RG_USB20_LS_CR_OFST                       (12)
-#define RG_USB20_FS_CR_OFST                       (8)
-#define RG_USB20_LS_SR_OFST                       (4)
-#define RG_USB20_FS_SR_OFST                       (0)
-
-//U3D_U2PHYACR1
-#define RG_USB20_INIT_SQ_EN_DG_OFST               (28)
-#define RG_USB20_SQD_OFST                         (24)
-#define RG_USB20_HSTX_TMODE_SEL_OFST              (20)
-#define RG_USB20_HSTX_TMODE_EN_OFST               (19)
-#define RG_USB20_PHYD_MONEN_OFST                  (18)
-#define RG_USB20_INLPBK_EN_OFST                   (17)
-#define RG_USB20_CHIRP_EN_OFST                    (16)
-#define RG_USB20_DM_ABIST_SOURCE_EN_OFST          (15)
-#define RG_USB20_DM_ABIST_SELE_OFST               (8)
-#define RG_USB20_DP_ABIST_SOURCE_EN_OFST          (7)
-#define RG_USB20_DP_ABIST_SELE_OFST               (0)
-
-//U3D_U2PHYACR2
-#define RG_USB20_OTG_ABIST_SELE_OFST              (29)
-#define RG_USB20_OTG_ABIST_EN_OFST                (28)
-#define RG_USB20_OTG_VBUSCMP_EN_OFST              (27)
-#define RG_USB20_OTG_VBUSTH_OFST                  (24)
-#define RG_USB20_DISC_FIT_EN_OFST                 (22)
-#define RG_USB20_DISCD_OFST                       (20)
-#define RG_USB20_DISCTH_OFST                      (16)
-#define RG_USB20_SQCAL_EN_OFST                    (15)
-#define RG_USB20_SQCAL_OFST                       (8)
-#define RG_USB20_SQTH_OFST                        (0)
-
-//U3D_U2PHYACR3
-#define RG_USB20_HSTX_DBIST_OFST                  (28)
-#define RG_USB20_HSTX_BIST_EN_OFST                (26)
-#define RG_USB20_HSTX_I_EN_MODE_OFST              (24)
-#define RG_USB20_HSRX_TMODE_EN_OFST               (23)
-#define RG_USB20_HSRX_BIAS_EN_SEL_OFST            (20)
-#define RG_USB20_USB11_TMODE_EN_OFST              (19)
-#define RG_USB20_TMODE_FS_LS_TX_EN_OFST           (18)
-#define RG_USB20_TMODE_FS_LS_RCV_EN_OFST          (17)
-#define RG_USB20_TMODE_FS_LS_MODE_OFST            (16)
-#define RG_USB20_HS_TERM_EN_MODE_OFST             (13)
-#define RG_USB20_PUPD_BIST_EN_OFST                (12)
-#define RG_USB20_EN_PU_DM_OFST                    (11)
-#define RG_USB20_EN_PD_DM_OFST                    (10)
-#define RG_USB20_EN_PU_DP_OFST                    (9)
-#define RG_USB20_EN_PD_DP_OFST                    (8)
-#define RG_USB20_PHY_REV_OFST                     (0)
-
-//U3D_U2PHYACR4
-#define RG_USB20_DP_100K_MODE_OFST                (18)
-#define RG_USB20_DM_100K_EN_OFST                  (17)
-#define USB20_DP_100K_EN_OFST                     (16)
-#define USB20_GPIO_DM_I_OFST                      (15)
-#define USB20_GPIO_DP_I_OFST                      (14)
-#define USB20_GPIO_DM_OE_OFST                     (13)
-#define USB20_GPIO_DP_OE_OFST                     (12)
-#define RG_USB20_GPIO_CTL_OFST                    (9)
-#define USB20_GPIO_MODE_OFST                      (8)
-#define RG_USB20_TX_BIAS_EN_OFST                  (5)
-#define RG_USB20_TX_VCMPDN_EN_OFST                (4)
-#define RG_USB20_HS_SQ_EN_MODE_OFST               (2)
-#define RG_USB20_HS_RCV_EN_MODE_OFST              (0)
-
-//U3D_U2PHYAMON0
-#define RGO_USB20_GPIO_DM_O_OFST                  (1)
-#define RGO_USB20_GPIO_DP_O_OFST                  (0)
-
-//U3D_U2PHYDCR0
-#define RG_USB20_CDR_TST_OFST                     (30)
-#define RG_USB20_GATED_ENB_OFST                   (29)
-#define RG_USB20_TESTMODE_OFST                    (26)
-#define RG_USB20_PLL_STABLE_OFST                  (25)
-#define RG_USB20_PLL_FORCE_ON_OFST                (24)
-#define RG_USB20_PHYD_RESERVE_OFST                (8)
-#define RG_USB20_EBTHRLD_OFST                     (7)
-#define RG_USB20_EARLY_HSTX_I_OFST                (6)
-#define RG_USB20_TX_TST_OFST                      (5)
-#define RG_USB20_NEGEDGE_ENB_OFST                 (4)
-#define RG_USB20_CDR_FILT_OFST                    (0)
-
-//U3D_U2PHYDCR1
-#define RG_USB20_PROBE_SEL_OFST                   (24)
-#define RG_USB20_DRVVBUS_OFST                     (23)
-#define RG_DEBUG_EN_OFST                          (22)
-#define RG_USB20_OTG_PROBE_OFST                   (20)
-#define RG_USB20_SW_PLLMODE_OFST                  (18)
-#define RG_USB20_BERTH_OFST                       (16)
-#define RG_USB20_LBMODE_OFST                      (13)
-#define RG_USB20_FORCE_TAP_OFST                   (12)
-#define RG_USB20_TAPSEL_OFST                      (0)
-
-//U3D_U2PHYDTM0
-#define RG_UART_MODE_OFST                         (30)
-#define FORCE_UART_I_OFST                         (29)
-#define FORCE_UART_BIAS_EN_OFST                   (28)
-#define FORCE_UART_TX_OE_OFST                     (27)
-#define FORCE_UART_EN_OFST                        (26)
-#define FORCE_USB_CLKEN_OFST                      (25)
-#define FORCE_DRVVBUS_OFST                        (24)
-#define FORCE_DATAIN_OFST                         (23)
-#define FORCE_TXVALID_OFST                        (22)
-#define FORCE_DM_PULLDOWN_OFST                    (21)
-#define FORCE_DP_PULLDOWN_OFST                    (20)
-#define FORCE_XCVRSEL_OFST                        (19)
-#define FORCE_SUSPENDM_OFST                       (18)
-#define FORCE_TERMSEL_OFST                        (17)
-#define FORCE_OPMODE_OFST                         (16)
-#define UTMI_MUXSEL_OFST                          (15)
-#define RG_RESET_OFST                             (14)
-#define RG_DATAIN_OFST                            (10)
-#define RG_TXVALIDH_OFST                          (9)
-#define RG_TXVALID_OFST                           (8)
-#define RG_DMPULLDOWN_OFST                        (7)
-#define RG_DPPULLDOWN_OFST                        (6)
-#define RG_XCVRSEL_OFST                           (4)
-#define RG_SUSPENDM_OFST                          (3)
-#define RG_TERMSEL_OFST                           (2)
-#define RG_OPMODE_OFST                            (0)
-
-//U3D_U2PHYDTM1
-#define RG_USB20_PRBS7_EN_OFST                    (31)
-#define RG_USB20_PRBS7_BITCNT_OFST                (24)
-#define RG_USB20_CLK48M_EN_OFST                   (23)
-#define RG_USB20_CLK60M_EN_OFST                   (22)
-#define RG_UART_I_OFST                            (19)
-#define RG_UART_BIAS_EN_OFST                      (18)
-#define RG_UART_TX_OE_OFST                        (17)
-#define RG_UART_EN_OFST                           (16)
-#define FORCE_VBUSVALID_OFST                      (13)
-#define FORCE_SESSEND_OFST                        (12)
-#define FORCE_BVALID_OFST                         (11)
-#define FORCE_AVALID_OFST                         (10)
-#define FORCE_IDDIG_OFST                          (9)
-#define FORCE_IDPULLUP_OFST                       (8)
-#define RG_VBUSVALID_OFST                         (5)
-#define RG_SESSEND_OFST                           (4)
-#define RG_BVALID_OFST                            (3)
-#define RG_AVALID_OFST                            (2)
-#define RG_IDDIG_OFST                             (1)
-#define RG_IDPULLUP_OFST                          (0)
-
-//U3D_U2PHYDMON0
-#define RG_USB20_PRBS7_BERTH_OFST                 (0)
-
-//U3D_U2PHYDMON1
-#define USB20_UART_O_OFST                         (31)
-#define RGO_USB20_LB_PASS_OFST                    (30)
-#define RGO_USB20_LB_DONE_OFST                    (29)
-#define AD_USB20_BVALID_OFST                      (28)
-#define USB20_IDDIG_OFST                          (27)
-#define AD_USB20_VBUSVALID_OFST                   (26)
-#define AD_USB20_SESSEND_OFST                     (25)
-#define AD_USB20_AVALID_OFST                      (24)
-#define USB20_LINE_STATE_OFST                     (22)
-#define USB20_HST_DISCON_OFST                     (21)
-#define USB20_TX_READY_OFST                       (20)
-#define USB20_RX_ERROR_OFST                       (19)
-#define USB20_RX_ACTIVE_OFST                      (18)
-#define USB20_RX_VALIDH_OFST                      (17)
-#define USB20_RX_VALID_OFST                       (16)
-#define USB20_DATA_OUT_OFST                       (0)
-
-//U3D_U2PHYDMON2
-#define RGO_TXVALID_CNT_OFST                      (24)
-#define RGO_RXACTIVE_CNT_OFST                     (16)
-#define RGO_USB20_LB_BERCNT_OFST                  (8)
-#define USB20_PROBE_OUT_OFST                      (0)
-
-//U3D_U2PHYDMON3
-#define RGO_USB20_PRBS7_ERRCNT_OFST               (16)
-#define RGO_USB20_PRBS7_DONE_OFST                 (3)
-#define RGO_USB20_PRBS7_LOCK_OFST                 (2)
-#define RGO_USB20_PRBS7_PASS_OFST                 (1)
-#define RGO_USB20_PRBS7_PASSTH_OFST               (0)
-
-//U3D_U2PHYBC12C
-#define RG_SIFSLV_CHGDT_DEGLCH_CNT_OFST           (28)
-#define RG_SIFSLV_CHGDT_CTRL_CNT_OFST             (24)
-#define RG_SIFSLV_CHGDT_FORCE_MODE_OFST           (16)
-#define RG_CHGDT_ISRC_LEV_OFST                    (14)
-#define RG_CHGDT_VDATSRC_OFST                     (13)
-#define RG_CHGDT_BGVREF_SEL_OFST                  (10)
-#define RG_CHGDT_RDVREF_SEL_OFST                  (8)
-#define RG_CHGDT_ISRC_DP_OFST                     (7)
-#define RG_SIFSLV_CHGDT_OPOUT_DM_OFST             (6)
-#define RG_CHGDT_VDAT_DM_OFST                     (5)
-#define RG_CHGDT_OPOUT_DP_OFST                    (4)
-#define RG_SIFSLV_CHGDT_VDAT_DP_OFST              (3)
-#define RG_SIFSLV_CHGDT_COMP_EN_OFST              (2)
-#define RG_SIFSLV_CHGDT_OPDRV_EN_OFST             (1)
-#define RG_CHGDT_EN_OFST                          (0)
-
-//U3D_U2PHYBC12C1
-#define RG_CHGDT_REV_OFST                         (0)
-
-//U3D_REGFCOM
-#define RG_PAGE_OFST                              (24)
-#define I2C_MODE_OFST                             (16)
-
-
-///////////////////////////////////////////////////////////////////////////////
-
-struct u3phya_reg {
-       //0x0
-       PHY_LE32 reg0;
-       PHY_LE32 reg1;
-       PHY_LE32 reg2;
-       PHY_LE32 reg3;
-       //0x10
-       PHY_LE32 reg4;
-       PHY_LE32 reg5;
-       PHY_LE32 reg6;
-       PHY_LE32 reg7;
-       //0x20
-       PHY_LE32 reg8;
-       PHY_LE32 reg9;
-       PHY_LE32 rega;
-       PHY_LE32 regb;
-       //0x30
-       PHY_LE32 regc;
-       PHY_LE32 regd;
-       PHY_LE32 rege;
-};
-
-//U3D_reg0
-#define RG_SSUSB_BGR_EN                           (0x1<<31) //31:31
-#define RG_SSUSB_CHPEN                            (0x1<<30) //30:30
-#define RG_SSUSB_BG_DIV                           (0x3<<28) //29:28
-#define RG_SSUSB_INTR_EN                          (0x1<<26) //26:26
-#define RG_SSUSB_MPX_OUT_SEL                      (0x3<<24) //25:24
-#define RG_SSUSB_MPX_SEL                          (0xff<<16) //23:16
-#define RG_SSUSB_REF_EN                           (0x1<<15) //15:15
-#define RG_SSUSB_VRT_VREF_SEL                     (0xf<<11) //14:11
-#define RG_SSUSB_BG_RASEL                         (0x3<<9) //10:9
-#define RG_SSUSB_BG_RBSEL                         (0x3<<7) //8:7
-#define RG_SSUSB_BG_MONEN                         (0x1<<6) //6:6
-#define RG_PCIE_CLKDRV_OFFSET                     (0x3<<0) //1:0
-
-//U3D_reg1
-#define RG_PCIE_CLKDRV_SLEW                       (0x3<<30) //31:30
-#define RG_PCIE_CLKDRV_AMP                        (0x7<<27) //29:27
-#define RG_SSUSB_XTAL_TST_A2DCK_EN                (0x1<<26) //26:26
-#define RG_SSUSB_XTAL_MON_EN                      (0x1<<25) //25:25
-#define RG_SSUSB_XTAL_HYS                         (0x1<<24) //24:24
-#define RG_SSUSB_XTAL_TOP_RESERVE                 (0xffff<<8) //23:8
-#define RG_SSUSB_SYSPLL_RESERVE                   (0xf<<4) //7:4
-#define RG_SSUSB_SYSPLL_FBSEL                     (0x3<<2) //3:2
-#define RG_SSUSB_SYSPLL_PREDIV                    (0x3<<0) //1:0
-
-//U3D_reg2
-#define RG_SSUSB_SYSPLL_LF                        (0x1<<31) //31:31
-#define RG_SSUSB_SYSPLL_FBDIV                     (0x7f<<24) //30:24
-#define RG_SSUSB_SYSPLL_POSDIV                    (0x3<<22) //23:22
-#define RG_SSUSB_SYSPLL_VCO_DIV_SEL               (0x1<<21) //21:21
-#define RG_SSUSB_SYSPLL_BLP                       (0x1<<20) //20:20
-#define RG_SSUSB_SYSPLL_BP                        (0x1<<19) //19:19
-#define RG_SSUSB_SYSPLL_BR                        (0x1<<18) //18:18
-#define RG_SSUSB_SYSPLL_BC                        (0x1<<17) //17:17
-#define RG_SSUSB_SYSPLL_DIVEN                     (0x7<<14) //16:14
-#define RG_SSUSB_SYSPLL_FPEN                      (0x1<<13) //13:13
-#define RG_SSUSB_SYSPLL_MONCK_EN                  (0x1<<12) //12:12
-#define RG_SSUSB_SYSPLL_MONVC_EN                  (0x1<<11) //11:11
-#define RG_SSUSB_SYSPLL_MONREF_EN                 (0x1<<10) //10:10
-#define RG_SSUSB_SYSPLL_VOD_EN                    (0x1<<9) //9:9
-#define RG_SSUSB_SYSPLL_CK_SEL                    (0x1<<8) //8:8
-
-//U3D_reg3
-#define RG_SSUSB_SYSPLL_TOP_RESERVE               (0xffff<<16) //31:16
-
-//U3D_reg4
-#define RG_SSUSB_SYSPLL_PCW_NCPO                  (0x7fffffff<<1) //31:1
-
-//U3D_reg5
-#define RG_SSUSB_SYSPLL_DDS_PI_C                  (0x7<<29) //31:29
-#define RG_SSUSB_SYSPLL_DDS_HF_EN                 (0x1<<28) //28:28
-#define RG_SSUSB_SYSPLL_DDS_PREDIV2               (0x1<<27) //27:27
-#define RG_SSUSB_SYSPLL_DDS_POSTDIV2              (0x1<<26) //26:26
-#define RG_SSUSB_SYSPLL_DDS_PI_PL_EN              (0x1<<25) //25:25
-#define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL            (0x1<<24) //24:24
-#define RG_SSUSB_SYSPLL_DDS_MONEN                 (0x1<<23) //23:23
-#define RG_SSUSB_SYSPLL_DDS_LPF_EN                (0x1<<22) //22:22
-#define RG_SSUSB_SYSPLL_CLK_PH_INV                (0x1<<21) //21:21
-#define RG_SSUSB_SYSPLL_DDS_SEL_EXT               (0x1<<20) //20:20
-#define RG_SSUSB_SYSPLL_DDS_DMY                   (0xffff<<0) //15:0
-
-//U3D_reg6
-#define RG_SSUSB_TX250MCK_INVB                    (0x1<<31) //31:31
-#define RG_SSUSB_IDRV_ITAILOP_EN                  (0x1<<30) //30:30
-#define RG_SSUSB_IDRV_CALIB                       (0x3f<<24) //29:24
-#define RG_SSUSB_TX_R50_FON                       (0x1<<23) //23:23
-#define RG_SSUSB_TX_SR                            (0x7<<20) //22:20
-#define RG_SSUSB_TX_EIDLE_CM                      (0xf<<16) //19:16
-#define RG_SSUSB_RXDET_RSEL                       (0x3<<14) //15:14
-#define RG_SSUSB_RXDET_VTHSEL                     (0x3<<12) //13:12
-#define RG_SSUSB_CKMON_EN                         (0x1<<11) //11:11
-#define RG_SSUSB_CKMON_SEL                        (0x7<<8) //10:8
-#define RG_SSUSB_TX_VLMON_EN                      (0x1<<7) //7:7
-#define RG_SSUSB_TX_VLMON_SEL                     (0x1<<6) //6:6
-#define RG_SSUSB_RXLBTX_EN                        (0x1<<5) //5:5
-#define RG_SSUSB_TXLBRX_EN                        (0x1<<4) //4:4
-
-//U3D_reg7
-#define RG_SSUSB_RESERVE                          (0xfffff<<12) //31:12
-#define RG_SSUSB_PLL_CKCTRL                       (0x3<<10) //11:10
-#define RG_SSUSB_PLL_POSDIV                       (0x3<<8) //9:8
-#define RG_SSUSB_PLL_AUTOK_LOAD                   (0x1<<7) //7:7
-#define RG_SSUSB_PLL_LOAD_RSTB                    (0x1<<6) //6:6
-#define RG_SSUSB_PLL_EP_EN                        (0x1<<5) //5:5
-#define RG_SSUSB_PLL_VOD_EN                       (0x1<<4) //4:4
-#define RG_SSUSB_PLL_V11_EN                       (0x1<<3) //3:3
-#define RG_SSUSB_PLL_MONREF_EN                    (0x1<<2) //2:2
-#define RG_SSUSB_PLL_MONCK_EN                     (0x1<<1) //1:1
-#define RG_SSUSB_PLL_MONVC_EN                     (0x1<<0) //0:0
-
-//U3D_reg8
-#define RG_SSUSB_PLL_RESERVE                      (0xffff<<0) //15:0
-
-//U3D_reg9
-#define RG_SSUSB_PLL_DDS_DMY                      (0xffff<<16) //31:16
-#define RG_SSUSB_PLL_SSC_PRD                      (0xffff<<0) //15:0
-
-//U3D_regA
-#define RG_SSUSB_PLL_SSC_PHASE_INI                (0x1<<31) //31:31
-#define RG_SSUSB_PLL_SSC_TRI_EN                   (0x1<<30) //30:30
-#define RG_SSUSB_PLL_CLK_PH_INV                   (0x1<<29) //29:29
-#define RG_SSUSB_PLL_DDS_LPF_EN                   (0x1<<28) //28:28
-#define RG_SSUSB_PLL_DDS_VADJ                     (0x7<<21) //23:21
-#define RG_SSUSB_PLL_DDS_MONEN                    (0x1<<20) //20:20
-#define RG_SSUSB_PLL_DDS_PS_VADJ                  (0x7<<17) //19:17
-#define RG_SSUSB_PLL_DDS_SEL_EXT                  (0x1<<16) //16:16
-#define RG_SSUSB_CDR_PD_DIV_BYPASS                (0x1<<15) //15:15
-#define RG_SSUSB_CDR_PD_DIV_SEL                   (0x1<<14) //14:14
-#define RG_SSUSB_CDR_CPBIAS_SEL                   (0x1<<13) //13:13
-#define RG_SSUSB_CDR_OSCDET_EN                    (0x1<<12) //12:12
-#define RG_SSUSB_CDR_MONMUX                       (0x1<<11) //11:11
-#define RG_SSUSB_CDR_CKCTRL                       (0x3<<9) //10:9
-#define RG_SSUSB_CDR_ACCEN                        (0x1<<8) //8:8
-#define RG_SSUSB_CDR_BYPASS                       (0x3<<6) //7:6
-#define RG_SSUSB_CDR_PI_SLEW                      (0x3<<4) //5:4
-#define RG_SSUSB_CDR_EPEN                         (0x1<<3) //3:3
-#define RG_SSUSB_CDR_AUTOK_LOAD                   (0x1<<2) //2:2
-#define RG_SSUSB_CDR_LOAD_RSTB                    (0x1<<1) //1:1
-#define RG_SSUSB_CDR_MONEN                        (0x1<<0) //0:0
-
-//U3D_regB
-#define RG_SSUSB_CDR_MONEN_DIG                    (0x1<<31) //31:31
-#define RG_SSUSB_CDR_REGOD                        (0x3<<29) //30:29
-#define RG_SSUSB_RX_DAC_EN                        (0x1<<26) //26:26
-#define RG_SSUSB_RX_DAC_PWD                       (0x1<<25) //25:25
-#define RG_SSUSB_EQ_CURSEL                        (0x1<<24) //24:24
-#define RG_SSUSB_RX_DAC_MUX                       (0x1f<<19) //23:19
-#define RG_SSUSB_RX_R2T_EN                        (0x1<<18) //18:18
-#define RG_SSUSB_RX_T2R_EN                        (0x1<<17) //17:17
-#define RG_SSUSB_RX_50_LOWER                      (0x7<<14) //16:14
-#define RG_SSUSB_RX_50_TAR                        (0x3<<12) //13:12
-#define RG_SSUSB_RX_SW_CTRL                       (0xf<<7) //10:7
-#define RG_PCIE_SIGDET_VTH                        (0x3<<5) //6:5
-#define RG_PCIE_SIGDET_LPF                        (0x3<<3) //4:3
-#define RG_SSUSB_LFPS_MON_EN                      (0x1<<2) //2:2
-
-//U3D_regC
-#define RG_SSUSB_RXAFE_DCMON_SEL                  (0xf<<28) //31:28
-#define RG_SSUSB_CDR_RESERVE                      (0xff<<16) //23:16
-#define RG_SSUSB_RXAFE_RESERVE                    (0xff<<8) //15:8
-#define RG_PCIE_RX_RESERVE                        (0xff<<0) //7:0
-
-//U3D_redD
-#define RGS_SSUSB_CDR_NO_OSC                      (0x1<<8) //8:8
-#define RGS_SSUSB_RX_DEBUG_RESERVE                (0xff<<0) //7:0
-
-//U3D_regE
-#define RG_SSUSB_INT_BIAS_SEL                     (0x1<<4) //4:4
-#define RG_SSUSB_EXT_BIAS_SEL                     (0x1<<3) //3:3
-#define RG_SSUSB_RX_P1_ENTRY_PASS                 (0x1<<2) //2:2
-#define RG_SSUSB_RX_PD_RST                        (0x1<<1) //1:1
-#define RG_SSUSB_RX_PD_RST_PASS                   (0x1<<0) //0:0
-
-
-/* OFFSET */
-
-//U3D_reg0
-#define RG_SSUSB_BGR_EN_OFST                      (31)
-#define RG_SSUSB_CHPEN_OFST                       (30)
-#define RG_SSUSB_BG_DIV_OFST                      (28)
-#define RG_SSUSB_INTR_EN_OFST                     (26)
-#define RG_SSUSB_MPX_OUT_SEL_OFST                 (24)
-#define RG_SSUSB_MPX_SEL_OFST                     (16)
-#define RG_SSUSB_REF_EN_OFST                      (15)
-#define RG_SSUSB_VRT_VREF_SEL_OFST                (11)
-#define RG_SSUSB_BG_RASEL_OFST                    (9)
-#define RG_SSUSB_BG_RBSEL_OFST                    (7)
-#define RG_SSUSB_BG_MONEN_OFST                    (6)
-#define RG_PCIE_CLKDRV_OFFSET_OFST                (0)
-
-//U3D_reg1
-#define RG_PCIE_CLKDRV_SLEW_OFST                  (30)
-#define RG_PCIE_CLKDRV_AMP_OFST                   (27)
-#define RG_SSUSB_XTAL_TST_A2DCK_EN_OFST           (26)
-#define RG_SSUSB_XTAL_MON_EN_OFST                 (25)
-#define RG_SSUSB_XTAL_HYS_OFST                    (24)
-#define RG_SSUSB_XTAL_TOP_RESERVE_OFST            (8)
-#define RG_SSUSB_SYSPLL_RESERVE_OFST              (4)
-#define RG_SSUSB_SYSPLL_FBSEL_OFST                (2)
-#define RG_SSUSB_SYSPLL_PREDIV_OFST               (0)
-
-//U3D_reg2
-#define RG_SSUSB_SYSPLL_LF_OFST                   (31)
-#define RG_SSUSB_SYSPLL_FBDIV_OFST                (24)
-#define RG_SSUSB_SYSPLL_POSDIV_OFST               (22)
-#define RG_SSUSB_SYSPLL_VCO_DIV_SEL_OFST          (21)
-#define RG_SSUSB_SYSPLL_BLP_OFST                  (20)
-#define RG_SSUSB_SYSPLL_BP_OFST                   (19)
-#define RG_SSUSB_SYSPLL_BR_OFST                   (18)
-#define RG_SSUSB_SYSPLL_BC_OFST                   (17)
-#define RG_SSUSB_SYSPLL_DIVEN_OFST                (14)
-#define RG_SSUSB_SYSPLL_FPEN_OFST                 (13)
-#define RG_SSUSB_SYSPLL_MONCK_EN_OFST             (12)
-#define RG_SSUSB_SYSPLL_MONVC_EN_OFST             (11)
-#define RG_SSUSB_SYSPLL_MONREF_EN_OFST            (10)
-#define RG_SSUSB_SYSPLL_VOD_EN_OFST               (9)
-#define RG_SSUSB_SYSPLL_CK_SEL_OFST               (8)
-
-//U3D_reg3
-#define RG_SSUSB_SYSPLL_TOP_RESERVE_OFST          (16)
-
-//U3D_reg4
-#define RG_SSUSB_SYSPLL_PCW_NCPO_OFST             (1)
-
-//U3D_reg5
-#define RG_SSUSB_SYSPLL_DDS_PI_C_OFST             (29)
-#define RG_SSUSB_SYSPLL_DDS_HF_EN_OFST            (28)
-#define RG_SSUSB_SYSPLL_DDS_PREDIV2_OFST          (27)
-#define RG_SSUSB_SYSPLL_DDS_POSTDIV2_OFST         (26)
-#define RG_SSUSB_SYSPLL_DDS_PI_PL_EN_OFST         (25)
-#define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL_OFST       (24)
-#define RG_SSUSB_SYSPLL_DDS_MONEN_OFST            (23)
-#define RG_SSUSB_SYSPLL_DDS_LPF_EN_OFST           (22)
-#define RG_SSUSB_SYSPLL_CLK_PH_INV_OFST           (21)
-#define RG_SSUSB_SYSPLL_DDS_SEL_EXT_OFST          (20)
-#define RG_SSUSB_SYSPLL_DDS_DMY_OFST              (0)
-
-//U3D_reg6
-#define RG_SSUSB_TX250MCK_INVB_OFST               (31)
-#define RG_SSUSB_IDRV_ITAILOP_EN_OFST             (30)
-#define RG_SSUSB_IDRV_CALIB_OFST                  (24)
-#define RG_SSUSB_TX_R50_FON_OFST                  (23)
-#define RG_SSUSB_TX_SR_OFST                       (20)
-#define RG_SSUSB_TX_EIDLE_CM_OFST                 (16)
-#define RG_SSUSB_RXDET_RSEL_OFST                  (14)
-#define RG_SSUSB_RXDET_VTHSEL_OFST                (12)
-#define RG_SSUSB_CKMON_EN_OFST                    (11)
-#define RG_SSUSB_CKMON_SEL_OFST                   (8)
-#define RG_SSUSB_TX_VLMON_EN_OFST                 (7)
-#define RG_SSUSB_TX_VLMON_SEL_OFST                (6)
-#define RG_SSUSB_RXLBTX_EN_OFST                   (5)
-#define RG_SSUSB_TXLBRX_EN_OFST                   (4)
-
-//U3D_reg7
-#define RG_SSUSB_RESERVE_OFST                     (12)
-#define RG_SSUSB_PLL_CKCTRL_OFST                  (10)
-#define RG_SSUSB_PLL_POSDIV_OFST                  (8)
-#define RG_SSUSB_PLL_AUTOK_LOAD_OFST              (7)
-#define RG_SSUSB_PLL_LOAD_RSTB_OFST               (6)
-#define RG_SSUSB_PLL_EP_EN_OFST                   (5)
-#define RG_SSUSB_PLL_VOD_EN_OFST                  (4)
-#define RG_SSUSB_PLL_V11_EN_OFST                  (3)
-#define RG_SSUSB_PLL_MONREF_EN_OFST               (2)
-#define RG_SSUSB_PLL_MONCK_EN_OFST                (1)
-#define RG_SSUSB_PLL_MONVC_EN_OFST                (0)
-
-//U3D_reg8
-#define RG_SSUSB_PLL_RESERVE_OFST                 (0)
-
-//U3D_reg9
-#define RG_SSUSB_PLL_DDS_DMY_OFST                 (16)
-#define RG_SSUSB_PLL_SSC_PRD_OFST                 (0)
-
-//U3D_regA
-#define RG_SSUSB_PLL_SSC_PHASE_INI_OFST           (31)
-#define RG_SSUSB_PLL_SSC_TRI_EN_OFST              (30)
-#define RG_SSUSB_PLL_CLK_PH_INV_OFST              (29)
-#define RG_SSUSB_PLL_DDS_LPF_EN_OFST              (28)
-#define RG_SSUSB_PLL_DDS_VADJ_OFST                (21)
-#define RG_SSUSB_PLL_DDS_MONEN_OFST               (20)
-#define RG_SSUSB_PLL_DDS_PS_VADJ_OFST             (17)
-#define RG_SSUSB_PLL_DDS_SEL_EXT_OFST             (16)
-#define RG_SSUSB_CDR_PD_DIV_BYPASS_OFST           (15)
-#define RG_SSUSB_CDR_PD_DIV_SEL_OFST              (14)
-#define RG_SSUSB_CDR_CPBIAS_SEL_OFST              (13)
-#define RG_SSUSB_CDR_OSCDET_EN_OFST               (12)
-#define RG_SSUSB_CDR_MONMUX_OFST                  (11)
-#define RG_SSUSB_CDR_CKCTRL_OFST                  (9)
-#define RG_SSUSB_CDR_ACCEN_OFST                   (8)
-#define RG_SSUSB_CDR_BYPASS_OFST                  (6)
-#define RG_SSUSB_CDR_PI_SLEW_OFST                 (4)
-#define RG_SSUSB_CDR_EPEN_OFST                    (3)
-#define RG_SSUSB_CDR_AUTOK_LOAD_OFST              (2)
-#define RG_SSUSB_CDR_LOAD_RSTB_OFST               (1)
-#define RG_SSUSB_CDR_MONEN_OFST                   (0)
-
-//U3D_regB
-#define RG_SSUSB_CDR_MONEN_DIG_OFST               (31)
-#define RG_SSUSB_CDR_REGOD_OFST                   (29)
-#define RG_SSUSB_RX_DAC_EN_OFST                   (26)
-#define RG_SSUSB_RX_DAC_PWD_OFST                  (25)
-#define RG_SSUSB_EQ_CURSEL_OFST                   (24)
-#define RG_SSUSB_RX_DAC_MUX_OFST                  (19)
-#define RG_SSUSB_RX_R2T_EN_OFST                   (18)
-#define RG_SSUSB_RX_T2R_EN_OFST                   (17)
-#define RG_SSUSB_RX_50_LOWER_OFST                 (14)
-#define RG_SSUSB_RX_50_TAR_OFST                   (12)
-#define RG_SSUSB_RX_SW_CTRL_OFST                  (7)
-#define RG_PCIE_SIGDET_VTH_OFST                   (5)
-#define RG_PCIE_SIGDET_LPF_OFST                   (3)
-#define RG_SSUSB_LFPS_MON_EN_OFST                 (2)
-
-//U3D_regC
-#define RG_SSUSB_RXAFE_DCMON_SEL_OFST             (28)
-#define RG_SSUSB_CDR_RESERVE_OFST                 (16)
-#define RG_SSUSB_RXAFE_RESERVE_OFST               (8)
-#define RG_PCIE_RX_RESERVE_OFST                   (0)
-
-//U3D_redD
-#define RGS_SSUSB_CDR_NO_OSC_OFST                 (8)
-#define RGS_SSUSB_RX_DEBUG_RESERVE_OFST           (0)
-
-//U3D_regE
-#define RG_SSUSB_INT_BIAS_SEL_OFST                (4)
-#define RG_SSUSB_EXT_BIAS_SEL_OFST                (3)
-#define RG_SSUSB_RX_P1_ENTRY_PASS_OFST            (2)
-#define RG_SSUSB_RX_PD_RST_OFST                   (1)
-#define RG_SSUSB_RX_PD_RST_PASS_OFST              (0)
-
-///////////////////////////////////////////////////////////////////////////////
-
-struct u3phya_da_reg {
-       //0x0
-       PHY_LE32 reg0;
-       PHY_LE32 reg1;
-       PHY_LE32 reg4;
-       PHY_LE32 reg5;
-       //0x10
-       PHY_LE32 reg6;
-       PHY_LE32 reg7;
-       PHY_LE32 reg8;
-       PHY_LE32 reg9;
-       //0x20
-       PHY_LE32 reg10;
-       PHY_LE32 reg12;
-       PHY_LE32 reg13;
-       PHY_LE32 reg14;
-       //0x30
-       PHY_LE32 reg15;
-       PHY_LE32 reg16;
-       PHY_LE32 reg19;
-       PHY_LE32 reg20;
-       //0x40
-       PHY_LE32 reg21;
-       PHY_LE32 reg23;
-       PHY_LE32 reg25;
-       PHY_LE32 reg26;
-       //0x50
-       PHY_LE32 reg28;
-       PHY_LE32 reg29;
-       PHY_LE32 reg30;
-       PHY_LE32 reg31;
-       //0x60
-       PHY_LE32 reg32;
-       PHY_LE32 reg33;
-};
-
-//U3D_reg0
-#define RG_PCIE_SPEED_PE2D                        (0x1<<24) //24:24
-#define RG_PCIE_SPEED_PE2H                        (0x1<<23) //23:23
-#define RG_PCIE_SPEED_PE1D                        (0x1<<22) //22:22
-#define RG_PCIE_SPEED_PE1H                        (0x1<<21) //21:21
-#define RG_PCIE_SPEED_U3                          (0x1<<20) //20:20
-#define RG_SSUSB_XTAL_EXT_EN_PE2D                 (0x3<<18) //19:18
-#define RG_SSUSB_XTAL_EXT_EN_PE2H                 (0x3<<16) //17:16
-#define RG_SSUSB_XTAL_EXT_EN_PE1D                 (0x3<<14) //15:14
-#define RG_SSUSB_XTAL_EXT_EN_PE1H                 (0x3<<12) //13:12
-#define RG_SSUSB_XTAL_EXT_EN_U3                   (0x3<<10) //11:10
-#define RG_SSUSB_CDR_REFCK_SEL_PE2D               (0x3<<8) //9:8
-#define RG_SSUSB_CDR_REFCK_SEL_PE2H               (0x3<<6) //7:6
-#define RG_SSUSB_CDR_REFCK_SEL_PE1D               (0x3<<4) //5:4
-#define RG_SSUSB_CDR_REFCK_SEL_PE1H               (0x3<<2) //3:2
-#define RG_SSUSB_CDR_REFCK_SEL_U3                 (0x3<<0) //1:0
-
-//U3D_reg1
-#define RG_USB20_REFCK_SEL_PE2D                   (0x1<<30) //30:30
-#define RG_USB20_REFCK_SEL_PE2H                   (0x1<<29) //29:29
-#define RG_USB20_REFCK_SEL_PE1D                   (0x1<<28) //28:28
-#define RG_USB20_REFCK_SEL_PE1H                   (0x1<<27) //27:27
-#define RG_USB20_REFCK_SEL_U3                     (0x1<<26) //26:26
-#define RG_PCIE_REFCK_DIV4_PE2D                   (0x1<<25) //25:25
-#define RG_PCIE_REFCK_DIV4_PE2H                   (0x1<<24) //24:24
-#define RG_PCIE_REFCK_DIV4_PE1D                   (0x1<<18) //18:18
-#define RG_PCIE_REFCK_DIV4_PE1H                   (0x1<<17) //17:17
-#define RG_PCIE_REFCK_DIV4_U3                     (0x1<<16) //16:16
-#define RG_PCIE_MODE_PE2D                         (0x1<<8) //8:8
-#define RG_PCIE_MODE_PE2H                         (0x1<<3) //3:3
-#define RG_PCIE_MODE_PE1D                         (0x1<<2) //2:2
-#define RG_PCIE_MODE_PE1H                         (0x1<<1) //1:1
-#define RG_PCIE_MODE_U3                           (0x1<<0) //0:0
-
-//U3D_reg4
-#define RG_SSUSB_PLL_DIVEN_PE2D                   (0x7<<22) //24:22
-#define RG_SSUSB_PLL_DIVEN_PE2H                   (0x7<<19) //21:19
-#define RG_SSUSB_PLL_DIVEN_PE1D                   (0x7<<16) //18:16
-#define RG_SSUSB_PLL_DIVEN_PE1H                   (0x7<<13) //15:13
-#define RG_SSUSB_PLL_DIVEN_U3                     (0x7<<10) //12:10
-#define RG_SSUSB_PLL_BC_PE2D                      (0x3<<8) //9:8
-#define RG_SSUSB_PLL_BC_PE2H                      (0x3<<6) //7:6
-#define RG_SSUSB_PLL_BC_PE1D                      (0x3<<4) //5:4
-#define RG_SSUSB_PLL_BC_PE1H                      (0x3<<2) //3:2
-#define RG_SSUSB_PLL_BC_U3                        (0x3<<0) //1:0
-
-//U3D_reg5
-#define RG_SSUSB_PLL_BR_PE2D                      (0x7<<27) //29:27
-#define RG_SSUSB_PLL_BR_PE2H                      (0x7<<24) //26:24
-#define RG_SSUSB_PLL_BR_PE1D                      (0x7<<21) //23:21
-#define RG_SSUSB_PLL_BR_PE1H                      (0x7<<18) //20:18
-#define RG_SSUSB_PLL_BR_U3                        (0x7<<15) //17:15
-#define RG_SSUSB_PLL_IC_PE2D                      (0x7<<12) //14:12
-#define RG_SSUSB_PLL_IC_PE2H                      (0x7<<9) //11:9
-#define RG_SSUSB_PLL_IC_PE1D                      (0x7<<6) //8:6
-#define RG_SSUSB_PLL_IC_PE1H                      (0x7<<3) //5:3
-#define RG_SSUSB_PLL_IC_U3                        (0x7<<0) //2:0
-
-//U3D_reg6
-#define RG_SSUSB_PLL_IR_PE2D                      (0xf<<24) //27:24
-#define RG_SSUSB_PLL_IR_PE2H                      (0xf<<16) //19:16
-#define RG_SSUSB_PLL_IR_PE1D                      (0xf<<8) //11:8
-#define RG_SSUSB_PLL_IR_PE1H                      (0xf<<4) //7:4
-#define RG_SSUSB_PLL_IR_U3                        (0xf<<0) //3:0
-
-//U3D_reg7
-#define RG_SSUSB_PLL_BP_PE2D                      (0xf<<24) //27:24
-#define RG_SSUSB_PLL_BP_PE2H                      (0xf<<16) //19:16
-#define RG_SSUSB_PLL_BP_PE1D                      (0xf<<8) //11:8
-#define RG_SSUSB_PLL_BP_PE1H                      (0xf<<4) //7:4
-#define RG_SSUSB_PLL_BP_U3                        (0xf<<0) //3:0
-
-//U3D_reg8
-#define RG_SSUSB_PLL_FBKSEL_PE2D                  (0x3<<24) //25:24
-#define RG_SSUSB_PLL_FBKSEL_PE2H                  (0x3<<16) //17:16
-#define RG_SSUSB_PLL_FBKSEL_PE1D                  (0x3<<8) //9:8
-#define RG_SSUSB_PLL_FBKSEL_PE1H                  (0x3<<2) //3:2
-#define RG_SSUSB_PLL_FBKSEL_U3                    (0x3<<0) //1:0
-
-//U3D_reg9
-#define RG_SSUSB_PLL_FBKDIV_PE2H                  (0x7f<<24) //30:24
-#define RG_SSUSB_PLL_FBKDIV_PE1D                  (0x7f<<16) //22:16
-#define RG_SSUSB_PLL_FBKDIV_PE1H                  (0x7f<<8) //14:8
-#define RG_SSUSB_PLL_FBKDIV_U3                    (0x7f<<0) //6:0
-
-//U3D_reg10
-#define RG_SSUSB_PLL_PREDIV_PE2D                  (0x3<<26) //27:26
-#define RG_SSUSB_PLL_PREDIV_PE2H                  (0x3<<24) //25:24
-#define RG_SSUSB_PLL_PREDIV_PE1D                  (0x3<<18) //19:18
-#define RG_SSUSB_PLL_PREDIV_PE1H                  (0x3<<16) //17:16
-#define RG_SSUSB_PLL_PREDIV_U3                    (0x3<<8) //9:8
-#define RG_SSUSB_PLL_FBKDIV_PE2D                  (0x7f<<0) //6:0
-
-//U3D_reg12
-#define RG_SSUSB_PLL_PCW_NCPO_U3                  (0x7fffffff<<0) //30:0
-
-//U3D_reg13
-#define RG_SSUSB_PLL_PCW_NCPO_PE1H                (0x7fffffff<<0) //30:0
-
-//U3D_reg14
-#define RG_SSUSB_PLL_PCW_NCPO_PE1D                (0x7fffffff<<0) //30:0
-
-//U3D_reg15
-#define RG_SSUSB_PLL_PCW_NCPO_PE2H                (0x7fffffff<<0) //30:0
-
-//U3D_reg16
-#define RG_SSUSB_PLL_PCW_NCPO_PE2D                (0x7fffffff<<0) //30:0
-
-//U3D_reg19
-#define RG_SSUSB_PLL_SSC_DELTA1_PE1H              (0xffff<<16) //31:16
-#define RG_SSUSB_PLL_SSC_DELTA1_U3                (0xffff<<0) //15:0
-
-//U3D_reg20
-#define RG_SSUSB_PLL_SSC_DELTA1_PE2H              (0xffff<<16) //31:16
-#define RG_SSUSB_PLL_SSC_DELTA1_PE1D              (0xffff<<0) //15:0
-
-//U3D_reg21
-#define RG_SSUSB_PLL_SSC_DELTA_U3                 (0xffff<<16) //31:16
-#define RG_SSUSB_PLL_SSC_DELTA1_PE2D              (0xffff<<0) //15:0
-
-//U3D_reg23
-#define RG_SSUSB_PLL_SSC_DELTA_PE1D               (0xffff<<16) //31:16
-#define RG_SSUSB_PLL_SSC_DELTA_PE1H               (0xffff<<0) //15:0
-
-//U3D_reg25
-#define RG_SSUSB_PLL_SSC_DELTA_PE2D               (0xffff<<16) //31:16
-#define RG_SSUSB_PLL_SSC_DELTA_PE2H               (0xffff<<0) //15:0
-
-//U3D_reg26
-#define RG_SSUSB_PLL_REFCKDIV_PE2D                (0x1<<25) //25:25
-#define RG_SSUSB_PLL_REFCKDIV_PE2H                (0x1<<24) //24:24
-#define RG_SSUSB_PLL_REFCKDIV_PE1D                (0x1<<16) //16:16
-#define RG_SSUSB_PLL_REFCKDIV_PE1H                (0x1<<8) //8:8
-#define RG_SSUSB_PLL_REFCKDIV_U3                  (0x1<<0) //0:0
-
-//U3D_reg28
-#define RG_SSUSB_CDR_BPA_PE2D                     (0x3<<24) //25:24
-#define RG_SSUSB_CDR_BPA_PE2H                     (0x3<<16) //17:16
-#define RG_SSUSB_CDR_BPA_PE1D                     (0x3<<10) //11:10
-#define RG_SSUSB_CDR_BPA_PE1H                     (0x3<<8) //9:8
-#define RG_SSUSB_CDR_BPA_U3                       (0x3<<0) //1:0
-
-//U3D_reg29
-#define RG_SSUSB_CDR_BPB_PE2D                     (0x7<<24) //26:24
-#define RG_SSUSB_CDR_BPB_PE2H                     (0x7<<16) //18:16
-#define RG_SSUSB_CDR_BPB_PE1D                     (0x7<<6) //8:6
-#define RG_SSUSB_CDR_BPB_PE1H                     (0x7<<3) //5:3
-#define RG_SSUSB_CDR_BPB_U3                       (0x7<<0) //2:0
-
-//U3D_reg30
-#define RG_SSUSB_CDR_BR_PE2D                      (0x7<<24) //26:24
-#define RG_SSUSB_CDR_BR_PE2H                      (0x7<<16) //18:16
-#define RG_SSUSB_CDR_BR_PE1D                      (0x7<<6) //8:6
-#define RG_SSUSB_CDR_BR_PE1H                      (0x7<<3) //5:3
-#define RG_SSUSB_CDR_BR_U3                        (0x7<<0) //2:0
-
-//U3D_reg31
-#define RG_SSUSB_CDR_FBDIV_PE2H                   (0x7f<<24) //30:24
-#define RG_SSUSB_CDR_FBDIV_PE1D                   (0x7f<<16) //22:16
-#define RG_SSUSB_CDR_FBDIV_PE1H                   (0x7f<<8) //14:8
-#define RG_SSUSB_CDR_FBDIV_U3                     (0x7f<<0) //6:0
-
-//U3D_reg32
-#define RG_SSUSB_EQ_RSTEP1_PE2D                   (0x3<<30) //31:30
-#define RG_SSUSB_EQ_RSTEP1_PE2H                   (0x3<<28) //29:28
-#define RG_SSUSB_EQ_RSTEP1_PE1D                   (0x3<<26) //27:26
-#define RG_SSUSB_EQ_RSTEP1_PE1H                   (0x3<<24) //25:24
-#define RG_SSUSB_EQ_RSTEP1_U3                     (0x3<<22) //23:22
-#define RG_SSUSB_LFPS_DEGLITCH_PE2D               (0x3<<20) //21:20
-#define RG_SSUSB_LFPS_DEGLITCH_PE2H               (0x3<<18) //19:18
-#define RG_SSUSB_LFPS_DEGLITCH_PE1D               (0x3<<16) //17:16
-#define RG_SSUSB_LFPS_DEGLITCH_PE1H               (0x3<<14) //15:14
-#define RG_SSUSB_LFPS_DEGLITCH_U3                 (0x3<<12) //13:12
-#define RG_SSUSB_CDR_KVSEL_PE2D                   (0x1<<11) //11:11
-#define RG_SSUSB_CDR_KVSEL_PE2H                   (0x1<<10) //10:10
-#define RG_SSUSB_CDR_KVSEL_PE1D                   (0x1<<9) //9:9
-#define RG_SSUSB_CDR_KVSEL_PE1H                   (0x1<<8) //8:8
-#define RG_SSUSB_CDR_KVSEL_U3                     (0x1<<7) //7:7
-#define RG_SSUSB_CDR_FBDIV_PE2D                   (0x7f<<0) //6:0
-
-//U3D_reg33
-#define RG_SSUSB_RX_CMPWD_PE2D                    (0x1<<26) //26:26
-#define RG_SSUSB_RX_CMPWD_PE2H                    (0x1<<25) //25:25
-#define RG_SSUSB_RX_CMPWD_PE1D                    (0x1<<24) //24:24
-#define RG_SSUSB_RX_CMPWD_PE1H                    (0x1<<23) //23:23
-#define RG_SSUSB_RX_CMPWD_U3                      (0x1<<16) //16:16
-#define RG_SSUSB_EQ_RSTEP2_PE2D                   (0x3<<8) //9:8
-#define RG_SSUSB_EQ_RSTEP2_PE2H                   (0x3<<6) //7:6
-#define RG_SSUSB_EQ_RSTEP2_PE1D                   (0x3<<4) //5:4
-#define RG_SSUSB_EQ_RSTEP2_PE1H                   (0x3<<2) //3:2
-#define RG_SSUSB_EQ_RSTEP2_U3                     (0x3<<0) //1:0
-
-
-/* OFFSET  */
-
-//U3D_reg0
-#define RG_PCIE_SPEED_PE2D_OFST                   (24)
-#define RG_PCIE_SPEED_PE2H_OFST                   (23)
-#define RG_PCIE_SPEED_PE1D_OFST                   (22)
-#define RG_PCIE_SPEED_PE1H_OFST                   (21)
-#define RG_PCIE_SPEED_U3_OFST                     (20)
-#define RG_SSUSB_XTAL_EXT_EN_PE2D_OFST            (18)
-#define RG_SSUSB_XTAL_EXT_EN_PE2H_OFST            (16)
-#define RG_SSUSB_XTAL_EXT_EN_PE1D_OFST            (14)
-#define RG_SSUSB_XTAL_EXT_EN_PE1H_OFST            (12)
-#define RG_SSUSB_XTAL_EXT_EN_U3_OFST              (10)
-#define RG_SSUSB_CDR_REFCK_SEL_PE2D_OFST          (8)
-#define RG_SSUSB_CDR_REFCK_SEL_PE2H_OFST          (6)
-#define RG_SSUSB_CDR_REFCK_SEL_PE1D_OFST          (4)
-#define RG_SSUSB_CDR_REFCK_SEL_PE1H_OFST          (2)
-#define RG_SSUSB_CDR_REFCK_SEL_U3_OFST            (0)
-
-//U3D_reg1
-#define RG_USB20_REFCK_SEL_PE2D_OFST              (30)
-#define RG_USB20_REFCK_SEL_PE2H_OFST              (29)
-#define RG_USB20_REFCK_SEL_PE1D_OFST              (28)
-#define RG_USB20_REFCK_SEL_PE1H_OFST              (27)
-#define RG_USB20_REFCK_SEL_U3_OFST                (26)
-#define RG_PCIE_REFCK_DIV4_PE2D_OFST              (25)
-#define RG_PCIE_REFCK_DIV4_PE2H_OFST              (24)
-#define RG_PCIE_REFCK_DIV4_PE1D_OFST              (18)
-#define RG_PCIE_REFCK_DIV4_PE1H_OFST              (17)
-#define RG_PCIE_REFCK_DIV4_U3_OFST                (16)
-#define RG_PCIE_MODE_PE2D_OFST                    (8)
-#define RG_PCIE_MODE_PE2H_OFST                    (3)
-#define RG_PCIE_MODE_PE1D_OFST                    (2)
-#define RG_PCIE_MODE_PE1H_OFST                    (1)
-#define RG_PCIE_MODE_U3_OFST                      (0)
-
-//U3D_reg4
-#define RG_SSUSB_PLL_DIVEN_PE2D_OFST              (22)
-#define RG_SSUSB_PLL_DIVEN_PE2H_OFST              (19)
-#define RG_SSUSB_PLL_DIVEN_PE1D_OFST              (16)
-#define RG_SSUSB_PLL_DIVEN_PE1H_OFST              (13)
-#define RG_SSUSB_PLL_DIVEN_U3_OFST                (10)
-#define RG_SSUSB_PLL_BC_PE2D_OFST                 (8)
-#define RG_SSUSB_PLL_BC_PE2H_OFST                 (6)
-#define RG_SSUSB_PLL_BC_PE1D_OFST                 (4)
-#define RG_SSUSB_PLL_BC_PE1H_OFST                 (2)
-#define RG_SSUSB_PLL_BC_U3_OFST                   (0)
-
-//U3D_reg5
-#define RG_SSUSB_PLL_BR_PE2D_OFST                 (27)
-#define RG_SSUSB_PLL_BR_PE2H_OFST                 (24)
-#define RG_SSUSB_PLL_BR_PE1D_OFST                 (21)
-#define RG_SSUSB_PLL_BR_PE1H_OFST                 (18)
-#define RG_SSUSB_PLL_BR_U3_OFST                   (15)
-#define RG_SSUSB_PLL_IC_PE2D_OFST                 (12)
-#define RG_SSUSB_PLL_IC_PE2H_OFST                 (9)
-#define RG_SSUSB_PLL_IC_PE1D_OFST                 (6)
-#define RG_SSUSB_PLL_IC_PE1H_OFST                 (3)
-#define RG_SSUSB_PLL_IC_U3_OFST                   (0)
-
-//U3D_reg6
-#define RG_SSUSB_PLL_IR_PE2D_OFST                 (24)
-#define RG_SSUSB_PLL_IR_PE2H_OFST                 (16)
-#define RG_SSUSB_PLL_IR_PE1D_OFST                 (8)
-#define RG_SSUSB_PLL_IR_PE1H_OFST                 (4)
-#define RG_SSUSB_PLL_IR_U3_OFST                   (0)
-
-//U3D_reg7
-#define RG_SSUSB_PLL_BP_PE2D_OFST                 (24)
-#define RG_SSUSB_PLL_BP_PE2H_OFST                 (16)
-#define RG_SSUSB_PLL_BP_PE1D_OFST                 (8)
-#define RG_SSUSB_PLL_BP_PE1H_OFST                 (4)
-#define RG_SSUSB_PLL_BP_U3_OFST                   (0)
-
-//U3D_reg8
-#define RG_SSUSB_PLL_FBKSEL_PE2D_OFST             (24)
-#define RG_SSUSB_PLL_FBKSEL_PE2H_OFST             (16)
-#define RG_SSUSB_PLL_FBKSEL_PE1D_OFST             (8)
-#define RG_SSUSB_PLL_FBKSEL_PE1H_OFST             (2)
-#define RG_SSUSB_PLL_FBKSEL_U3_OFST               (0)
-
-//U3D_reg9
-#define RG_SSUSB_PLL_FBKDIV_PE2H_OFST             (24)
-#define RG_SSUSB_PLL_FBKDIV_PE1D_OFST             (16)
-#define RG_SSUSB_PLL_FBKDIV_PE1H_OFST             (8)
-#define RG_SSUSB_PLL_FBKDIV_U3_OFST               (0)
-
-//U3D_reg10
-#define RG_SSUSB_PLL_PREDIV_PE2D_OFST             (26)
-#define RG_SSUSB_PLL_PREDIV_PE2H_OFST             (24)
-#define RG_SSUSB_PLL_PREDIV_PE1D_OFST             (18)
-#define RG_SSUSB_PLL_PREDIV_PE1H_OFST             (16)
-#define RG_SSUSB_PLL_PREDIV_U3_OFST               (8)
-#define RG_SSUSB_PLL_FBKDIV_PE2D_OFST             (0)
-
-//U3D_reg12
-#define RG_SSUSB_PLL_PCW_NCPO_U3_OFST             (0)
-
-//U3D_reg13
-#define RG_SSUSB_PLL_PCW_NCPO_PE1H_OFST           (0)
-
-//U3D_reg14
-#define RG_SSUSB_PLL_PCW_NCPO_PE1D_OFST           (0)
-
-//U3D_reg15
-#define RG_SSUSB_PLL_PCW_NCPO_PE2H_OFST           (0)
-
-//U3D_reg16
-#define RG_SSUSB_PLL_PCW_NCPO_PE2D_OFST           (0)
-
-//U3D_reg19
-#define RG_SSUSB_PLL_SSC_DELTA1_PE1H_OFST         (16)
-#define RG_SSUSB_PLL_SSC_DELTA1_U3_OFST           (0)
-
-//U3D_reg20
-#define RG_SSUSB_PLL_SSC_DELTA1_PE2H_OFST         (16)
-#define RG_SSUSB_PLL_SSC_DELTA1_PE1D_OFST         (0)
-
-//U3D_reg21
-#define RG_SSUSB_PLL_SSC_DELTA_U3_OFST            (16)
-#define RG_SSUSB_PLL_SSC_DELTA1_PE2D_OFST         (0)
-
-//U3D_reg23
-#define RG_SSUSB_PLL_SSC_DELTA_PE1D_OFST          (16)
-#define RG_SSUSB_PLL_SSC_DELTA_PE1H_OFST          (0)
-
-//U3D_reg25
-#define RG_SSUSB_PLL_SSC_DELTA_PE2D_OFST          (16)
-#define RG_SSUSB_PLL_SSC_DELTA_PE2H_OFST          (0)
-
-//U3D_reg26
-#define RG_SSUSB_PLL_REFCKDIV_PE2D_OFST           (25)
-#define RG_SSUSB_PLL_REFCKDIV_PE2H_OFST           (24)
-#define RG_SSUSB_PLL_REFCKDIV_PE1D_OFST           (16)
-#define RG_SSUSB_PLL_REFCKDIV_PE1H_OFST           (8)
-#define RG_SSUSB_PLL_REFCKDIV_U3_OFST             (0)
-
-//U3D_reg28
-#define RG_SSUSB_CDR_BPA_PE2D_OFST                (24)
-#define RG_SSUSB_CDR_BPA_PE2H_OFST                (16)
-#define RG_SSUSB_CDR_BPA_PE1D_OFST                (10)
-#define RG_SSUSB_CDR_BPA_PE1H_OFST                (8)
-#define RG_SSUSB_CDR_BPA_U3_OFST                  (0)
-
-//U3D_reg29
-#define RG_SSUSB_CDR_BPB_PE2D_OFST                (24)
-#define RG_SSUSB_CDR_BPB_PE2H_OFST                (16)
-#define RG_SSUSB_CDR_BPB_PE1D_OFST                (6)
-#define RG_SSUSB_CDR_BPB_PE1H_OFST                (3)
-#define RG_SSUSB_CDR_BPB_U3_OFST                  (0)
-
-//U3D_reg30
-#define RG_SSUSB_CDR_BR_PE2D_OFST                 (24)
-#define RG_SSUSB_CDR_BR_PE2H_OFST                 (16)
-#define RG_SSUSB_CDR_BR_PE1D_OFST                 (6)
-#define RG_SSUSB_CDR_BR_PE1H_OFST                 (3)
-#define RG_SSUSB_CDR_BR_U3_OFST                   (0)
-
-//U3D_reg31
-#define RG_SSUSB_CDR_FBDIV_PE2H_OFST              (24)
-#define RG_SSUSB_CDR_FBDIV_PE1D_OFST              (16)
-#define RG_SSUSB_CDR_FBDIV_PE1H_OFST              (8)
-#define RG_SSUSB_CDR_FBDIV_U3_OFST                (0)
-
-//U3D_reg32
-#define RG_SSUSB_EQ_RSTEP1_PE2D_OFST              (30)
-#define RG_SSUSB_EQ_RSTEP1_PE2H_OFST              (28)
-#define RG_SSUSB_EQ_RSTEP1_PE1D_OFST              (26)
-#define RG_SSUSB_EQ_RSTEP1_PE1H_OFST              (24)
-#define RG_SSUSB_EQ_RSTEP1_U3_OFST                (22)
-#define RG_SSUSB_LFPS_DEGLITCH_PE2D_OFST          (20)
-#define RG_SSUSB_LFPS_DEGLITCH_PE2H_OFST          (18)
-#define RG_SSUSB_LFPS_DEGLITCH_PE1D_OFST          (16)
-#define RG_SSUSB_LFPS_DEGLITCH_PE1H_OFST          (14)
-#define RG_SSUSB_LFPS_DEGLITCH_U3_OFST            (12)
-#define RG_SSUSB_CDR_KVSEL_PE2D_OFST              (11)
-#define RG_SSUSB_CDR_KVSEL_PE2H_OFST              (10)
-#define RG_SSUSB_CDR_KVSEL_PE1D_OFST              (9)
-#define RG_SSUSB_CDR_KVSEL_PE1H_OFST              (8)
-#define RG_SSUSB_CDR_KVSEL_U3_OFST                (7)
-#define RG_SSUSB_CDR_FBDIV_PE2D_OFST              (0)
-
-//U3D_reg33
-#define RG_SSUSB_RX_CMPWD_PE2D_OFST               (26)
-#define RG_SSUSB_RX_CMPWD_PE2H_OFST               (25)
-#define RG_SSUSB_RX_CMPWD_PE1D_OFST               (24)
-#define RG_SSUSB_RX_CMPWD_PE1H_OFST               (23)
-#define RG_SSUSB_RX_CMPWD_U3_OFST                 (16)
-#define RG_SSUSB_EQ_RSTEP2_PE2D_OFST              (8)
-#define RG_SSUSB_EQ_RSTEP2_PE2H_OFST              (6)
-#define RG_SSUSB_EQ_RSTEP2_PE1D_OFST              (4)
-#define RG_SSUSB_EQ_RSTEP2_PE1H_OFST              (2)
-#define RG_SSUSB_EQ_RSTEP2_U3_OFST                (0)
-
-
-///////////////////////////////////////////////////////////////////////////////
-
-struct u3phyd_reg {
-       //0x0
-       PHY_LE32 phyd_mix0;
-       PHY_LE32 phyd_mix1;
-       PHY_LE32 phyd_lfps0;
-       PHY_LE32 phyd_lfps1;
-       //0x10
-       PHY_LE32 phyd_impcal0;
-       PHY_LE32 phyd_impcal1;
-       PHY_LE32 phyd_txpll0;
-       PHY_LE32 phyd_txpll1;
-       //0x20
-       PHY_LE32 phyd_txpll2;
-       PHY_LE32 phyd_fl0;
-       PHY_LE32 phyd_mix2;
-       PHY_LE32 phyd_rx0;
-       //0x30
-       PHY_LE32 phyd_t2rlb;
-       PHY_LE32 phyd_cppat;
-       PHY_LE32 phyd_mix3;
-       PHY_LE32 phyd_ebufctl;
-       //0x40
-       PHY_LE32 phyd_pipe0;
-       PHY_LE32 phyd_pipe1;
-       PHY_LE32 phyd_mix4;
-       PHY_LE32 phyd_ckgen0;
-       //0x50
-       PHY_LE32 phyd_mix5;
-       PHY_LE32 phyd_reserved;
-       PHY_LE32 phyd_cdr0;
-       PHY_LE32 phyd_cdr1;
-       //0x60
-       PHY_LE32 phyd_pll_0;
-       PHY_LE32 phyd_pll_1;
-       PHY_LE32 phyd_bcn_det_1;
-       PHY_LE32 phyd_bcn_det_2;
-       //0x70
-       PHY_LE32 eq0;
-       PHY_LE32 eq1;
-       PHY_LE32 eq2;
-       PHY_LE32 eq3;
-       //0x80
-       PHY_LE32 eq_eye0;
-       PHY_LE32 eq_eye1;
-       PHY_LE32 eq_eye2;
-       PHY_LE32 eq_dfe0;
-       //0x90
-       PHY_LE32 eq_dfe1;
-       PHY_LE32 eq_dfe2;
-       PHY_LE32 eq_dfe3;
-       PHY_LE32 reserve0;
-       //0xa0
-       PHY_LE32 phyd_mon0;
-       PHY_LE32 phyd_mon1;
-       PHY_LE32 phyd_mon2;
-       PHY_LE32 phyd_mon3;
-       //0xb0
-       PHY_LE32 phyd_mon4;
-       PHY_LE32 phyd_mon5;
-       PHY_LE32 phyd_mon6;
-       PHY_LE32 phyd_mon7;
-       //0xc0
-       PHY_LE32 phya_rx_mon0;
-       PHY_LE32 phya_rx_mon1;
-       PHY_LE32 phya_rx_mon2;
-       PHY_LE32 phya_rx_mon3;
-       //0xd0
-       PHY_LE32 phya_rx_mon4;
-       PHY_LE32 phya_rx_mon5;
-       PHY_LE32 phyd_cppat2;
-       PHY_LE32 eq_eye3;
-       //0xe0
-       PHY_LE32 kband_out;
-       PHY_LE32 kband_out1;
-};
-
-//U3D_PHYD_MIX0
-#define RG_SSUSB_P_P3_TX_NG                       (0x1<<31) //31:31
-#define RG_SSUSB_TSEQ_EN                          (0x1<<30) //30:30
-#define RG_SSUSB_TSEQ_POLEN                       (0x1<<29) //29:29
-#define RG_SSUSB_TSEQ_POL                         (0x1<<28) //28:28
-#define RG_SSUSB_P_P3_PCLK_NG                     (0x1<<27) //27:27
-#define RG_SSUSB_TSEQ_TH                          (0x7<<24) //26:24
-#define RG_SSUSB_PRBS_BERTH                       (0xff<<16) //23:16
-#define RG_SSUSB_DISABLE_PHY_U2_ON                (0x1<<15) //15:15
-#define RG_SSUSB_DISABLE_PHY_U2_OFF               (0x1<<14) //14:14
-#define RG_SSUSB_PRBS_EN                          (0x1<<13) //13:13
-#define RG_SSUSB_BPSLOCK                          (0x1<<12) //12:12
-#define RG_SSUSB_RTCOMCNT                         (0xf<<8) //11:8
-#define RG_SSUSB_COMCNT                           (0xf<<4) //7:4
-#define RG_SSUSB_PRBSEL_CALIB                     (0xf<<0) //3:0
-
-//U3D_PHYD_MIX1
-#define RG_SSUSB_SLEEP_EN                         (0x1<<31) //31:31
-#define RG_SSUSB_PRBSEL_PCS                       (0x7<<28) //30:28
-#define RG_SSUSB_TXLFPS_PRD                       (0xf<<24) //27:24
-#define RG_SSUSB_P_RX_P0S_CK                      (0x1<<23) //23:23
-#define RG_SSUSB_P_TX_P0S_CK                      (0x1<<22) //22:22
-#define RG_SSUSB_PDNCTL                           (0x3f<<16) //21:16
-#define RG_SSUSB_TX_DRV_EN                        (0x1<<15) //15:15
-#define RG_SSUSB_TX_DRV_SEL                       (0x1<<14) //14:14
-#define RG_SSUSB_TX_DRV_DLY                       (0x3f<<8) //13:8
-#define RG_SSUSB_BERT_EN                          (0x1<<7) //7:7
-#define RG_SSUSB_SCP_TH                           (0x7<<4) //6:4
-#define RG_SSUSB_SCP_EN                           (0x1<<3) //3:3
-#define RG_SSUSB_RXANSIDEC_TEST                   (0x7<<0) //2:0
-
-//U3D_PHYD_LFPS0
-#define RG_SSUSB_LFPS_PWD                         (0x1<<30) //30:30
-#define RG_SSUSB_FORCE_LFPS_PWD                   (0x1<<29) //29:29
-#define RG_SSUSB_RXLFPS_OVF                       (0x1f<<24) //28:24
-#define RG_SSUSB_P3_ENTRY_SEL                     (0x1<<23) //23:23
-#define RG_SSUSB_P3_ENTRY                         (0x1<<22) //22:22
-#define RG_SSUSB_RXLFPS_CDRSEL                    (0x3<<20) //21:20
-#define RG_SSUSB_RXLFPS_CDRTH                     (0xf<<16) //19:16
-#define RG_SSUSB_LOCK5G_BLOCK                     (0x1<<15) //15:15
-#define RG_SSUSB_TFIFO_EXT_D_SEL                  (0x1<<14) //14:14
-#define RG_SSUSB_TFIFO_NO_EXTEND                  (0x1<<13) //13:13
-#define RG_SSUSB_RXLFPS_LOB                       (0x1f<<8) //12:8
-#define RG_SSUSB_TXLFPS_EN                        (0x1<<7) //7:7
-#define RG_SSUSB_TXLFPS_SEL                       (0x1<<6) //6:6
-#define RG_SSUSB_RXLFPS_CDRLOCK                   (0x1<<5) //5:5
-#define RG_SSUSB_RXLFPS_UPB                       (0x1f<<0) //4:0
-
-//U3D_PHYD_LFPS1
-#define RG_SSUSB_RX_IMP_BIAS                      (0xf<<28) //31:28
-#define RG_SSUSB_TX_IMP_BIAS                      (0xf<<24) //27:24
-#define RG_SSUSB_FWAKE_TH                         (0x3f<<16) //21:16
-#define RG_SSUSB_RXLFPS_UDF                       (0x1f<<8) //12:8
-#define RG_SSUSB_RXLFPS_P0IDLETH                  (0xff<<0) //7:0
-
-//U3D_PHYD_IMPCAL0
-#define RG_SSUSB_FORCE_TX_IMPSEL                  (0x1<<31) //31:31
-#define RG_SSUSB_TX_IMPCAL_EN                     (0x1<<30) //30:30
-#define RG_SSUSB_FORCE_TX_IMPCAL_EN               (0x1<<29) //29:29
-#define RG_SSUSB_TX_IMPSEL                        (0x1f<<24) //28:24
-#define RG_SSUSB_TX_IMPCAL_CALCYC                 (0x3f<<16) //21:16
-#define RG_SSUSB_TX_IMPCAL_STBCYC                 (0x1f<<10) //14:10
-#define RG_SSUSB_TX_IMPCAL_CYCCNT                 (0x3ff<<0) //9:0
-
-//U3D_PHYD_IMPCAL1
-#define RG_SSUSB_FORCE_RX_IMPSEL                  (0x1<<31) //31:31
-#define RG_SSUSB_RX_IMPCAL_EN                     (0x1<<30) //30:30
-#define RG_SSUSB_FORCE_RX_IMPCAL_EN               (0x1<<29) //29:29
-#define RG_SSUSB_RX_IMPSEL                        (0x1f<<24) //28:24
-#define RG_SSUSB_RX_IMPCAL_CALCYC                 (0x3f<<16) //21:16
-#define RG_SSUSB_RX_IMPCAL_STBCYC                 (0x1f<<10) //14:10
-#define RG_SSUSB_RX_IMPCAL_CYCCNT                 (0x3ff<<0) //9:0
-
-//U3D_PHYD_TXPLL0
-#define RG_SSUSB_TXPLL_DDSEN_CYC                  (0x1f<<27) //31:27
-#define RG_SSUSB_TXPLL_ON                         (0x1<<26) //26:26
-#define RG_SSUSB_FORCE_TXPLLON                    (0x1<<25) //25:25
-#define RG_SSUSB_TXPLL_STBCYC                     (0x1ff<<16) //24:16
-#define RG_SSUSB_TXPLL_NCPOCHG_CYC                (0xf<<12) //15:12
-#define RG_SSUSB_TXPLL_NCPOEN_CYC                 (0x3<<10) //11:10
-#define RG_SSUSB_TXPLL_DDSRSTB_CYC                (0x7<<0) //2:0
-
-//U3D_PHYD_TXPLL1
-#define RG_SSUSB_PLL_NCPO_EN                      (0x1<<31) //31:31
-#define RG_SSUSB_PLL_FIFO_START_MAN               (0x1<<30) //30:30
-#define RG_SSUSB_PLL_NCPO_CHG                     (0x1<<28) //28:28
-#define RG_SSUSB_PLL_DDS_RSTB                     (0x1<<27) //27:27
-#define RG_SSUSB_PLL_DDS_PWDB                     (0x1<<26) //26:26
-#define RG_SSUSB_PLL_DDSEN                        (0x1<<25) //25:25
-#define RG_SSUSB_PLL_AUTOK_VCO                    (0x1<<24) //24:24
-#define RG_SSUSB_PLL_PWD                          (0x1<<23) //23:23
-#define RG_SSUSB_RX_AFE_PWD                       (0x1<<22) //22:22
-#define RG_SSUSB_PLL_TCADJ                        (0x3f<<16) //21:16
-#define RG_SSUSB_FORCE_CDR_TCADJ                  (0x1<<15) //15:15
-#define RG_SSUSB_FORCE_CDR_AUTOK_VCO              (0x1<<14) //14:14
-#define RG_SSUSB_FORCE_CDR_PWD                    (0x1<<13) //13:13
-#define RG_SSUSB_FORCE_PLL_NCPO_EN                (0x1<<12) //12:12
-#define RG_SSUSB_FORCE_PLL_FIFO_START_MAN         (0x1<<11) //11:11
-#define RG_SSUSB_FORCE_PLL_NCPO_CHG               (0x1<<9) //9:9
-#define RG_SSUSB_FORCE_PLL_DDS_RSTB               (0x1<<8) //8:8
-#define RG_SSUSB_FORCE_PLL_DDS_PWDB               (0x1<<7) //7:7
-#define RG_SSUSB_FORCE_PLL_DDSEN                  (0x1<<6) //6:6
-#define RG_SSUSB_FORCE_PLL_TCADJ                  (0x1<<5) //5:5
-#define RG_SSUSB_FORCE_PLL_AUTOK_VCO              (0x1<<4) //4:4
-#define RG_SSUSB_FORCE_PLL_PWD                    (0x1<<3) //3:3
-#define RG_SSUSB_FLT_1_DISPERR_B                  (0x1<<2) //2:2
-
-//U3D_PHYD_TXPLL2
-#define RG_SSUSB_TX_LFPS_EN                       (0x1<<31) //31:31
-#define RG_SSUSB_FORCE_TX_LFPS_EN                 (0x1<<30) //30:30
-#define RG_SSUSB_TX_LFPS                          (0x1<<29) //29:29
-#define RG_SSUSB_FORCE_TX_LFPS                    (0x1<<28) //28:28
-#define RG_SSUSB_RXPLL_STB                        (0x1<<27) //27:27
-#define RG_SSUSB_TXPLL_STB                        (0x1<<26) //26:26
-#define RG_SSUSB_FORCE_RXPLL_STB                  (0x1<<25) //25:25
-#define RG_SSUSB_FORCE_TXPLL_STB                  (0x1<<24) //24:24
-#define RG_SSUSB_RXPLL_REFCKSEL                   (0x1<<16) //16:16
-#define RG_SSUSB_RXPLL_STBMODE                    (0x1<<11) //11:11
-#define RG_SSUSB_RXPLL_ON                         (0x1<<10) //10:10
-#define RG_SSUSB_FORCE_RXPLLON                    (0x1<<9) //9:9
-#define RG_SSUSB_FORCE_RX_AFE_PWD                 (0x1<<8) //8:8
-#define RG_SSUSB_CDR_AUTOK_VCO                    (0x1<<7) //7:7
-#define RG_SSUSB_CDR_PWD                          (0x1<<6) //6:6
-#define RG_SSUSB_CDR_TCADJ                        (0x3f<<0) //5:0
-
-//U3D_PHYD_FL0
-#define RG_SSUSB_RX_FL_TARGET                     (0xffff<<16) //31:16
-#define RG_SSUSB_RX_FL_CYCLECNT                   (0xffff<<0) //15:0
-
-//U3D_PHYD_MIX2
-#define RG_SSUSB_RX_EQ_RST                        (0x1<<31) //31:31
-#define RG_SSUSB_RX_EQ_RST_SEL                    (0x1<<30) //30:30
-#define RG_SSUSB_RXVAL_RST                        (0x1<<29) //29:29
-#define RG_SSUSB_RXVAL_CNT                        (0x1f<<24) //28:24
-#define RG_SSUSB_CDROS_EN                         (0x1<<18) //18:18
-#define RG_SSUSB_CDR_LCKOP                        (0x3<<16) //17:16
-#define RG_SSUSB_RX_FL_LOCKTH                     (0xf<<8) //11:8
-#define RG_SSUSB_RX_FL_OFFSET                     (0xff<<0) //7:0
-
-//U3D_PHYD_RX0
-#define RG_SSUSB_T2RLB_BERTH                      (0xff<<24) //31:24
-#define RG_SSUSB_T2RLB_PAT                        (0xff<<16) //23:16
-#define RG_SSUSB_T2RLB_EN                         (0x1<<15) //15:15
-#define RG_SSUSB_T2RLB_BPSCRAMB                   (0x1<<14) //14:14
-#define RG_SSUSB_T2RLB_SERIAL                     (0x1<<13) //13:13
-#define RG_SSUSB_T2RLB_MODE                       (0x3<<11) //12:11
-#define RG_SSUSB_RX_SAOSC_EN                      (0x1<<10) //10:10
-#define RG_SSUSB_RX_SAOSC_EN_SEL                  (0x1<<9) //9:9
-#define RG_SSUSB_RX_DFE_OPTION                    (0x1<<8) //8:8
-#define RG_SSUSB_RX_DFE_EN                        (0x1<<7) //7:7
-#define RG_SSUSB_RX_DFE_EN_SEL                    (0x1<<6) //6:6
-#define RG_SSUSB_RX_EQ_EN                         (0x1<<5) //5:5
-#define RG_SSUSB_RX_EQ_EN_SEL                     (0x1<<4) //4:4
-#define RG_SSUSB_RX_SAOSC_RST                     (0x1<<3) //3:3
-#define RG_SSUSB_RX_SAOSC_RST_SEL                 (0x1<<2) //2:2
-#define RG_SSUSB_RX_DFE_RST                       (0x1<<1) //1:1
-#define RG_SSUSB_RX_DFE_RST_SEL                   (0x1<<0) //0:0
-
-//U3D_PHYD_T2RLB
-#define RG_SSUSB_EQTRAIN_CH_MODE                  (0x1<<28) //28:28
-#define RG_SSUSB_PRB_OUT_CPPAT                    (0x1<<27) //27:27
-#define RG_SSUSB_BPANSIENC                        (0x1<<26) //26:26
-#define RG_SSUSB_VALID_EN                         (0x1<<25) //25:25
-#define RG_SSUSB_EBUF_SRST                        (0x1<<24) //24:24
-#define RG_SSUSB_K_EMP                            (0xf<<20) //23:20
-#define RG_SSUSB_K_FUL                            (0xf<<16) //19:16
-#define RG_SSUSB_T2RLB_BDATRST                    (0xf<<12) //15:12
-#define RG_SSUSB_P_T2RLB_SKP_EN                   (0x1<<10) //10:10
-#define RG_SSUSB_T2RLB_PATMODE                    (0x3<<8) //9:8
-#define RG_SSUSB_T2RLB_TSEQCNT                    (0xff<<0) //7:0
-
-//U3D_PHYD_CPPAT
-#define RG_SSUSB_CPPAT_PROGRAM_EN                 (0x1<<24) //24:24
-#define RG_SSUSB_CPPAT_TOZ                        (0x3<<21) //22:21
-#define RG_SSUSB_CPPAT_PRBS_EN                    (0x1<<20) //20:20
-#define RG_SSUSB_CPPAT_OUT_TMP2                   (0xf<<16) //19:16
-#define RG_SSUSB_CPPAT_OUT_TMP1                   (0xff<<8) //15:8
-#define RG_SSUSB_CPPAT_OUT_TMP0                   (0xff<<0) //7:0
-
-//U3D_PHYD_MIX3
-#define RG_SSUSB_CDR_TCADJ_MINUS                  (0x1<<31) //31:31
-#define RG_SSUSB_P_CDROS_EN                       (0x1<<30) //30:30
-#define RG_SSUSB_P_P2_TX_DRV_DIS                  (0x1<<28) //28:28
-#define RG_SSUSB_CDR_TCADJ_OFFSET                 (0x7<<24) //26:24
-#define RG_SSUSB_PLL_TCADJ_MINUS                  (0x1<<23) //23:23
-#define RG_SSUSB_FORCE_PLL_BIAS_LPF_EN            (0x1<<20) //20:20
-#define RG_SSUSB_PLL_BIAS_LPF_EN                  (0x1<<19) //19:19
-#define RG_SSUSB_PLL_TCADJ_OFFSET                 (0x7<<16) //18:16
-#define RG_SSUSB_FORCE_PLL_SSCEN                  (0x1<<15) //15:15
-#define RG_SSUSB_PLL_SSCEN                        (0x1<<14) //14:14
-#define RG_SSUSB_FORCE_CDR_PI_PWD                 (0x1<<13) //13:13
-#define RG_SSUSB_CDR_PI_PWD                       (0x1<<12) //12:12
-#define RG_SSUSB_CDR_PI_MODE                      (0x1<<11) //11:11
-#define RG_SSUSB_TXPLL_SSCEN_CYC                  (0x3ff<<0) //9:0
-
-//U3D_PHYD_EBUFCTL
-#define RG_SSUSB_EBUFCTL                          (0xffffffff<<0) //31:0
-
-//U3D_PHYD_PIPE0
-#define RG_SSUSB_RXTERMINATION                    (0x1<<30) //30:30
-#define RG_SSUSB_RXEQTRAINING                     (0x1<<29) //29:29
-#define RG_SSUSB_RXPOLARITY                       (0x1<<28) //28:28
-#define RG_SSUSB_TXDEEMPH                         (0x3<<26) //27:26
-#define RG_SSUSB_POWERDOWN                        (0x3<<24) //25:24
-#define RG_SSUSB_TXONESZEROS                      (0x1<<23) //23:23
-#define RG_SSUSB_TXELECIDLE                       (0x1<<22) //22:22
-#define RG_SSUSB_TXDETECTRX                       (0x1<<21) //21:21
-#define RG_SSUSB_PIPE_SEL                         (0x1<<20) //20:20
-#define RG_SSUSB_TXDATAK                          (0xf<<16) //19:16
-#define RG_SSUSB_CDR_STABLE_SEL                   (0x1<<15) //15:15
-#define RG_SSUSB_CDR_STABLE                       (0x1<<14) //14:14
-#define RG_SSUSB_CDR_RSTB_SEL                     (0x1<<13) //13:13
-#define RG_SSUSB_CDR_RSTB                         (0x1<<12) //12:12
-#define RG_SSUSB_P_ERROR_SEL                      (0x3<<4) //5:4
-#define RG_SSUSB_TXMARGIN                         (0x7<<1) //3:1
-#define RG_SSUSB_TXCOMPLIANCE                     (0x1<<0) //0:0
-
-//U3D_PHYD_PIPE1
-#define RG_SSUSB_TXDATA                           (0xffffffff<<0) //31:0
-
-//U3D_PHYD_MIX4
-#define RG_SSUSB_CDROS_CNT                        (0x3f<<24) //29:24
-#define RG_SSUSB_T2RLB_BER_EN                     (0x1<<16) //16:16
-#define RG_SSUSB_T2RLB_BER_RATE                   (0xffff<<0) //15:0
-
-//U3D_PHYD_CKGEN0
-#define RG_SSUSB_RFIFO_IMPLAT                     (0x1<<27) //27:27
-#define RG_SSUSB_TFIFO_PSEL                       (0x7<<24) //26:24
-#define RG_SSUSB_CKGEN_PSEL                       (0x3<<8) //9:8
-#define RG_SSUSB_RXCK_INV                         (0x1<<0) //0:0
-
-//U3D_PHYD_MIX5
-#define RG_SSUSB_PRB_SEL                          (0xffff<<16) //31:16
-#define RG_SSUSB_RXPLL_STBCYC                     (0x7ff<<0) //10:0
-
-//U3D_PHYD_RESERVED
-#define RG_SSUSB_PHYD_RESERVE                     (0xffffffff<<0) //31:0
-//#define RG_SSUSB_RX_SIGDET_SEL                    (0x1<<11)
-//#define RG_SSUSB_RX_SIGDET_EN                     (0x1<<12)
-//#define RG_SSUSB_RX_PI_CAL_MANUAL_SEL             (0x1<<9)
-//#define RG_SSUSB_RX_PI_CAL_MANUAL_EN              (0x1<<10)
-
-//U3D_PHYD_CDR0
-#define RG_SSUSB_CDR_BIC_LTR                      (0xf<<28) //31:28
-#define RG_SSUSB_CDR_BIC_LTD0                     (0xf<<24) //27:24
-#define RG_SSUSB_CDR_BC_LTD1                      (0x1f<<16) //20:16
-#define RG_SSUSB_CDR_BC_LTR                       (0x1f<<8) //12:8
-#define RG_SSUSB_CDR_BC_LTD0                      (0x1f<<0) //4:0
-
-//U3D_PHYD_CDR1
-#define RG_SSUSB_CDR_BIR_LTD1                     (0x1f<<24) //28:24
-#define RG_SSUSB_CDR_BIR_LTR                      (0x1f<<16) //20:16
-#define RG_SSUSB_CDR_BIR_LTD0                     (0x1f<<8) //12:8
-#define RG_SSUSB_CDR_BW_SEL                       (0x3<<6) //7:6
-#define RG_SSUSB_CDR_BIC_LTD1                     (0xf<<0) //3:0
-
-//U3D_PHYD_PLL_0
-#define RG_SSUSB_FORCE_CDR_BAND_5G                (0x1<<28) //28:28
-#define RG_SSUSB_FORCE_CDR_BAND_2P5G              (0x1<<27) //27:27
-#define RG_SSUSB_FORCE_PLL_BAND_5G                (0x1<<26) //26:26
-#define RG_SSUSB_FORCE_PLL_BAND_2P5G              (0x1<<25) //25:25
-#define RG_SSUSB_P_EQ_T_SEL                       (0x3ff<<15) //24:15
-#define RG_SSUSB_PLL_ISO_EN_CYC                   (0x3ff<<5) //14:5
-#define RG_SSUSB_PLLBAND_RECAL                    (0x1<<4) //4:4
-#define RG_SSUSB_PLL_DDS_ISO_EN                   (0x1<<3) //3:3
-#define RG_SSUSB_FORCE_PLL_DDS_ISO_EN             (0x1<<2) //2:2
-#define RG_SSUSB_PLL_DDS_PWR_ON                   (0x1<<1) //1:1
-#define RG_SSUSB_FORCE_PLL_DDS_PWR_ON             (0x1<<0) //0:0
-
-//U3D_PHYD_PLL_1
-#define RG_SSUSB_CDR_BAND_5G                      (0xff<<24) //31:24
-#define RG_SSUSB_CDR_BAND_2P5G                    (0xff<<16) //23:16
-#define RG_SSUSB_PLL_BAND_5G                      (0xff<<8) //15:8
-#define RG_SSUSB_PLL_BAND_2P5G                    (0xff<<0) //7:0
-
-//U3D_PHYD_BCN_DET_1
-#define RG_SSUSB_P_BCN_OBS_PRD                    (0xffff<<16) //31:16
-#define RG_SSUSB_U_BCN_OBS_PRD                    (0xffff<<0) //15:0
-
-//U3D_PHYD_BCN_DET_2
-#define RG_SSUSB_P_BCN_OBS_SEL                    (0xfff<<16) //27:16
-#define RG_SSUSB_BCN_DET_DIS                      (0x1<<12) //12:12
-#define RG_SSUSB_U_BCN_OBS_SEL                    (0xfff<<0) //11:0
-
-//U3D_EQ0
-#define RG_SSUSB_EQ_DLHL_LFI                      (0x7f<<24) //30:24
-#define RG_SSUSB_EQ_DHHL_LFI                      (0x7f<<16) //22:16
-#define RG_SSUSB_EQ_DD0HOS_LFI                    (0x7f<<8) //14:8
-#define RG_SSUSB_EQ_DD0LOS_LFI                    (0x7f<<0) //6:0
-
-//U3D_EQ1
-#define RG_SSUSB_EQ_DD1HOS_LFI                    (0x7f<<24) //30:24
-#define RG_SSUSB_EQ_DD1LOS_LFI                    (0x7f<<16) //22:16
-#define RG_SSUSB_EQ_DE0OS_LFI                     (0x7f<<8) //14:8
-#define RG_SSUSB_EQ_DE1OS_LFI                     (0x7f<<0) //6:0
-
-//U3D_EQ2
-#define RG_SSUSB_EQ_DLHLOS_LFI                    (0x7f<<24) //30:24
-#define RG_SSUSB_EQ_DHHLOS_LFI                    (0x7f<<16) //22:16
-#define RG_SSUSB_EQ_STOPTIME                      (0x1<<14) //14:14
-#define RG_SSUSB_EQ_DHHL_LF_SEL                   (0x7<<11) //13:11
-#define RG_SSUSB_EQ_DSAOS_LF_SEL                  (0x7<<8) //10:8
-#define RG_SSUSB_EQ_STARTTIME                     (0x3<<6) //7:6
-#define RG_SSUSB_EQ_DLEQ_LF_SEL                   (0x7<<3) //5:3
-#define RG_SSUSB_EQ_DLHL_LF_SEL                   (0x7<<0) //2:0
-
-//U3D_EQ3
-#define RG_SSUSB_EQ_DLEQ_LFI_GEN2                 (0xf<<28) //31:28
-#define RG_SSUSB_EQ_DLEQ_LFI_GEN1                 (0xf<<24) //27:24
-#define RG_SSUSB_EQ_DEYE0OS_LFI                   (0x7f<<16) //22:16
-#define RG_SSUSB_EQ_DEYE1OS_LFI                   (0x7f<<8) //14:8
-#define RG_SSUSB_EQ_TRI_DET_EN                    (0x1<<7) //7:7
-#define RG_SSUSB_EQ_TRI_DET_TH                    (0x7f<<0) //6:0
-
-//U3D_EQ_EYE0
-#define RG_SSUSB_EQ_EYE_XOFFSET                   (0x7f<<25) //31:25
-#define RG_SSUSB_EQ_EYE_MON_EN                    (0x1<<24) //24:24
-#define RG_SSUSB_EQ_EYE0_Y                        (0x7f<<16) //22:16
-#define RG_SSUSB_EQ_EYE1_Y                        (0x7f<<8) //14:8
-#define RG_SSUSB_EQ_PILPO_ROUT                    (0x1<<7) //7:7
-#define RG_SSUSB_EQ_PI_KPGAIN                     (0x7<<4) //6:4
-#define RG_SSUSB_EQ_EYE_CNT_EN                    (0x1<<3) //3:3
-
-//U3D_EQ_EYE1
-#define RG_SSUSB_EQ_SIGDET                        (0x7f<<24) //30:24
-#define RG_SSUSB_EQ_EYE_MASK                      (0x3ff<<7) //16:7
-
-//U3D_EQ_EYE2
-#define RG_SSUSB_EQ_RX500M_CK_SEL                 (0x1<<31) //31:31
-#define RG_SSUSB_EQ_SD_CNT1                       (0x3f<<24) //29:24
-#define RG_SSUSB_EQ_ISIFLAG_SEL                   (0x3<<22) //23:22
-#define RG_SSUSB_EQ_SD_CNT0                       (0x3f<<16) //21:16
-
-//U3D_EQ_DFE0
-#define RG_SSUSB_EQ_LEQMAX                        (0xf<<28) //31:28
-#define RG_SSUSB_EQ_DFEX_EN                       (0x1<<27) //27:27
-#define RG_SSUSB_EQ_DFEX_LF_SEL                   (0x7<<24) //26:24
-#define RG_SSUSB_EQ_CHK_EYE_H                     (0x1<<23) //23:23
-#define RG_SSUSB_EQ_PIEYE_INI                     (0x7f<<16) //22:16
-#define RG_SSUSB_EQ_PI90_INI                      (0x7f<<8) //14:8
-#define RG_SSUSB_EQ_PI0_INI                       (0x7f<<0) //6:0
-
-//U3D_EQ_DFE1
-#define RG_SSUSB_EQ_REV                           (0xffff<<16) //31:16
-#define RG_SSUSB_EQ_DFEYEN_DUR                    (0x7<<12) //14:12
-#define RG_SSUSB_EQ_DFEXEN_DUR                    (0x7<<8) //10:8
-#define RG_SSUSB_EQ_DFEX_RST                      (0x1<<7) //7:7
-#define RG_SSUSB_EQ_GATED_RXD_B                   (0x1<<6) //6:6
-#define RG_SSUSB_EQ_PI90CK_SEL                    (0x3<<4) //5:4
-#define RG_SSUSB_EQ_DFEX_DIS                      (0x1<<2) //2:2
-#define RG_SSUSB_EQ_DFEYEN_STOP_DIS               (0x1<<1) //1:1
-#define RG_SSUSB_EQ_DFEXEN_SEL                    (0x1<<0) //0:0
-
-//U3D_EQ_DFE2
-#define RG_SSUSB_EQ_MON_SEL                       (0x1f<<24) //28:24
-#define RG_SSUSB_EQ_LEQOSC_DLYCNT                 (0x7<<16) //18:16
-#define RG_SSUSB_EQ_DLEQOS_LFI                    (0x1f<<8) //12:8
-#define RG_SSUSB_EQ_LEQ_STOP_TO                   (0x3<<0) //1:0
-
-//U3D_EQ_DFE3
-#define RG_SSUSB_EQ_RESERVED                      (0xffffffff<<0) //31:0
-
-//U3D_PHYD_MON0
-#define RGS_SSUSB_BERT_BERC                       (0xffff<<16) //31:16
-#define RGS_SSUSB_LFPS                            (0xf<<12) //15:12
-#define RGS_SSUSB_TRAINDEC                        (0x7<<8) //10:8
-#define RGS_SSUSB_SCP_PAT                         (0xff<<0) //7:0
-
-//U3D_PHYD_MON1
-#define RGS_SSUSB_RX_FL_OUT                       (0xffff<<0) //15:0
-
-//U3D_PHYD_MON2
-#define RGS_SSUSB_T2RLB_ERRCNT                    (0xffff<<16) //31:16
-#define RGS_SSUSB_RETRACK                         (0xf<<12) //15:12
-#define RGS_SSUSB_RXPLL_LOCK                      (0x1<<10) //10:10
-#define RGS_SSUSB_CDR_VCOCAL_CPLT_D               (0x1<<9) //9:9
-#define RGS_SSUSB_PLL_VCOCAL_CPLT_D               (0x1<<8) //8:8
-#define RGS_SSUSB_PDNCTL                          (0xff<<0) //7:0
-
-//U3D_PHYD_MON3
-#define RGS_SSUSB_TSEQ_ERRCNT                     (0xffff<<16) //31:16
-#define RGS_SSUSB_PRBS_ERRCNT                     (0xffff<<0) //15:0
-
-//U3D_PHYD_MON4
-#define RGS_SSUSB_RX_LSLOCK_CNT                   (0xf<<24) //27:24
-#define RGS_SSUSB_SCP_DETCNT                      (0xff<<16) //23:16
-#define RGS_SSUSB_TSEQ_DETCNT                     (0xffff<<0) //15:0
-
-//U3D_PHYD_MON5
-#define RGS_SSUSB_EBUFMSG                         (0xffff<<16) //31:16
-#define RGS_SSUSB_BERT_LOCK                       (0x1<<15) //15:15
-#define RGS_SSUSB_SCP_DET                         (0x1<<14) //14:14
-#define RGS_SSUSB_TSEQ_DET                        (0x1<<13) //13:13
-#define RGS_SSUSB_EBUF_UDF                        (0x1<<12) //12:12
-#define RGS_SSUSB_EBUF_OVF                        (0x1<<11) //11:11
-#define RGS_SSUSB_PRBS_PASSTH                     (0x1<<10) //10:10
-#define RGS_SSUSB_PRBS_PASS                       (0x1<<9) //9:9
-#define RGS_SSUSB_PRBS_LOCK                       (0x1<<8) //8:8
-#define RGS_SSUSB_T2RLB_ERR                       (0x1<<6) //6:6
-#define RGS_SSUSB_T2RLB_PASSTH                    (0x1<<5) //5:5
-#define RGS_SSUSB_T2RLB_PASS                      (0x1<<4) //4:4
-#define RGS_SSUSB_T2RLB_LOCK                      (0x1<<3) //3:3
-#define RGS_SSUSB_RX_IMPCAL_DONE                  (0x1<<2) //2:2
-#define RGS_SSUSB_TX_IMPCAL_DONE                  (0x1<<1) //1:1
-#define RGS_SSUSB_RXDETECTED                      (0x1<<0) //0:0
-
-//U3D_PHYD_MON6
-#define RGS_SSUSB_SIGCAL_DONE                     (0x1<<30) //30:30
-#define RGS_SSUSB_SIGCAL_CAL_OUT                  (0x1<<29) //29:29
-#define RGS_SSUSB_SIGCAL_OFFSET                   (0x1f<<24) //28:24
-#define RGS_SSUSB_RX_IMP_SEL                      (0x1f<<16) //20:16
-#define RGS_SSUSB_TX_IMP_SEL                      (0x1f<<8) //12:8
-#define RGS_SSUSB_TFIFO_MSG                       (0xf<<4) //7:4
-#define RGS_SSUSB_RFIFO_MSG                       (0xf<<0) //3:0
-
-//U3D_PHYD_MON7
-#define RGS_SSUSB_FT_OUT                          (0xff<<8) //15:8
-#define RGS_SSUSB_PRB_OUT                         (0xff<<0) //7:0
-
-//U3D_PHYA_RX_MON0
-#define RGS_SSUSB_EQ_DCLEQ                        (0xf<<24) //27:24
-#define RGS_SSUSB_EQ_DCD0H                        (0x7f<<16) //22:16
-#define RGS_SSUSB_EQ_DCD0L                        (0x7f<<8) //14:8
-#define RGS_SSUSB_EQ_DCD1H                        (0x7f<<0) //6:0
-
-//U3D_PHYA_RX_MON1
-#define RGS_SSUSB_EQ_DCD1L                        (0x7f<<24) //30:24
-#define RGS_SSUSB_EQ_DCE0                         (0x7f<<16) //22:16
-#define RGS_SSUSB_EQ_DCE1                         (0x7f<<8) //14:8
-#define RGS_SSUSB_EQ_DCHHL                        (0x7f<<0) //6:0
-
-//U3D_PHYA_RX_MON2
-#define RGS_SSUSB_EQ_LEQ_STOP                     (0x1<<31) //31:31
-#define RGS_SSUSB_EQ_DCLHL                        (0x7f<<24) //30:24
-#define RGS_SSUSB_EQ_STATUS                       (0xff<<16) //23:16
-#define RGS_SSUSB_EQ_DCEYE0                       (0x7f<<8) //14:8
-#define RGS_SSUSB_EQ_DCEYE1                       (0x7f<<0) //6:0
-
-//U3D_PHYA_RX_MON3
-#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0         (0xfffff<<0) //19:0
-
-//U3D_PHYA_RX_MON4
-#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1         (0xfffff<<0) //19:0
-
-//U3D_PHYA_RX_MON5
-#define RGS_SSUSB_EQ_DCLEQOS                      (0x1f<<8) //12:8
-#define RGS_SSUSB_EQ_EYE_CNT_RDY                  (0x1<<7) //7:7
-#define RGS_SSUSB_EQ_PILPO                        (0x7f<<0) //6:0
-
-//U3D_PHYD_CPPAT2
-#define RG_SSUSB_CPPAT_OUT_H_TMP2                 (0xf<<16) //19:16
-#define RG_SSUSB_CPPAT_OUT_H_TMP1                 (0xff<<8) //15:8
-#define RG_SSUSB_CPPAT_OUT_H_TMP0                 (0xff<<0) //7:0
-
-//U3D_EQ_EYE3
-#define RG_SSUSB_EQ_LEQ_SHIFT                     (0x7<<24) //26:24
-#define RG_SSUSB_EQ_EYE_CNT                       (0xfffff<<0) //19:0
-
-//U3D_KBAND_OUT
-#define RGS_SSUSB_CDR_BAND_5G                     (0xff<<24) //31:24
-#define RGS_SSUSB_CDR_BAND_2P5G                   (0xff<<16) //23:16
-#define RGS_SSUSB_PLL_BAND_5G                     (0xff<<8) //15:8
-#define RGS_SSUSB_PLL_BAND_2P5G                   (0xff<<0) //7:0
-
-//U3D_KBAND_OUT1
-#define RGS_SSUSB_CDR_VCOCAL_FAIL                 (0x1<<24) //24:24
-#define RGS_SSUSB_CDR_VCOCAL_STATE                (0xff<<16) //23:16
-#define RGS_SSUSB_PLL_VCOCAL_FAIL                 (0x1<<8) //8:8
-#define RGS_SSUSB_PLL_VCOCAL_STATE                (0xff<<0) //7:0
-
-
-/* OFFSET */
-
-//U3D_PHYD_MIX0
-#define RG_SSUSB_P_P3_TX_NG_OFST                  (31)
-#define RG_SSUSB_TSEQ_EN_OFST                     (30)
-#define RG_SSUSB_TSEQ_POLEN_OFST                  (29)
-#define RG_SSUSB_TSEQ_POL_OFST                    (28)
-#define RG_SSUSB_P_P3_PCLK_NG_OFST                (27)
-#define RG_SSUSB_TSEQ_TH_OFST                     (24)
-#define RG_SSUSB_PRBS_BERTH_OFST                  (16)
-#define RG_SSUSB_DISABLE_PHY_U2_ON_OFST           (15)
-#define RG_SSUSB_DISABLE_PHY_U2_OFF_OFST          (14)
-#define RG_SSUSB_PRBS_EN_OFST                     (13)
-#define RG_SSUSB_BPSLOCK_OFST                     (12)
-#define RG_SSUSB_RTCOMCNT_OFST                    (8)
-#define RG_SSUSB_COMCNT_OFST                      (4)
-#define RG_SSUSB_PRBSEL_CALIB_OFST                (0)
-
-//U3D_PHYD_MIX1
-#define RG_SSUSB_SLEEP_EN_OFST                    (31)
-#define RG_SSUSB_PRBSEL_PCS_OFST                  (28)
-#define RG_SSUSB_TXLFPS_PRD_OFST                  (24)
-#define RG_SSUSB_P_RX_P0S_CK_OFST                 (23)
-#define RG_SSUSB_P_TX_P0S_CK_OFST                 (22)
-#define RG_SSUSB_PDNCTL_OFST                      (16)
-#define RG_SSUSB_TX_DRV_EN_OFST                   (15)
-#define RG_SSUSB_TX_DRV_SEL_OFST                  (14)
-#define RG_SSUSB_TX_DRV_DLY_OFST                  (8)
-#define RG_SSUSB_BERT_EN_OFST                     (7)
-#define RG_SSUSB_SCP_TH_OFST                      (4)
-#define RG_SSUSB_SCP_EN_OFST                      (3)
-#define RG_SSUSB_RXANSIDEC_TEST_OFST              (0)
-
-//U3D_PHYD_LFPS0
-#define RG_SSUSB_LFPS_PWD_OFST                    (30)
-#define RG_SSUSB_FORCE_LFPS_PWD_OFST              (29)
-#define RG_SSUSB_RXLFPS_OVF_OFST                  (24)
-#define RG_SSUSB_P3_ENTRY_SEL_OFST                (23)
-#define RG_SSUSB_P3_ENTRY_OFST                    (22)
-#define RG_SSUSB_RXLFPS_CDRSEL_OFST               (20)
-#define RG_SSUSB_RXLFPS_CDRTH_OFST                (16)
-#define RG_SSUSB_LOCK5G_BLOCK_OFST                (15)
-#define RG_SSUSB_TFIFO_EXT_D_SEL_OFST             (14)
-#define RG_SSUSB_TFIFO_NO_EXTEND_OFST             (13)
-#define RG_SSUSB_RXLFPS_LOB_OFST                  (8)
-#define RG_SSUSB_TXLFPS_EN_OFST                   (7)
-#define RG_SSUSB_TXLFPS_SEL_OFST                  (6)
-#define RG_SSUSB_RXLFPS_CDRLOCK_OFST              (5)
-#define RG_SSUSB_RXLFPS_UPB_OFST                  (0)
-
-//U3D_PHYD_LFPS1
-#define RG_SSUSB_RX_IMP_BIAS_OFST                 (28)
-#define RG_SSUSB_TX_IMP_BIAS_OFST                 (24)
-#define RG_SSUSB_FWAKE_TH_OFST                    (16)
-#define RG_SSUSB_RXLFPS_UDF_OFST                  (8)
-#define RG_SSUSB_RXLFPS_P0IDLETH_OFST             (0)
-
-//U3D_PHYD_IMPCAL0
-#define RG_SSUSB_FORCE_TX_IMPSEL_OFST             (31)
-#define RG_SSUSB_TX_IMPCAL_EN_OFST                (30)
-#define RG_SSUSB_FORCE_TX_IMPCAL_EN_OFST          (29)
-#define RG_SSUSB_TX_IMPSEL_OFST                   (24)
-#define RG_SSUSB_TX_IMPCAL_CALCYC_OFST            (16)
-#define RG_SSUSB_TX_IMPCAL_STBCYC_OFST            (10)
-#define RG_SSUSB_TX_IMPCAL_CYCCNT_OFST            (0)
-
-//U3D_PHYD_IMPCAL1
-#define RG_SSUSB_FORCE_RX_IMPSEL_OFST             (31)
-#define RG_SSUSB_RX_IMPCAL_EN_OFST                (30)
-#define RG_SSUSB_FORCE_RX_IMPCAL_EN_OFST          (29)
-#define RG_SSUSB_RX_IMPSEL_OFST                   (24)
-#define RG_SSUSB_RX_IMPCAL_CALCYC_OFST            (16)
-#define RG_SSUSB_RX_IMPCAL_STBCYC_OFST            (10)
-#define RG_SSUSB_RX_IMPCAL_CYCCNT_OFST            (0)
-
-//U3D_PHYD_TXPLL0
-#define RG_SSUSB_TXPLL_DDSEN_CYC_OFST             (27)
-#define RG_SSUSB_TXPLL_ON_OFST                    (26)
-#define RG_SSUSB_FORCE_TXPLLON_OFST               (25)
-#define RG_SSUSB_TXPLL_STBCYC_OFST                (16)
-#define RG_SSUSB_TXPLL_NCPOCHG_CYC_OFST           (12)
-#define RG_SSUSB_TXPLL_NCPOEN_CYC_OFST            (10)
-#define RG_SSUSB_TXPLL_DDSRSTB_CYC_OFST           (0)
-
-//U3D_PHYD_TXPLL1
-#define RG_SSUSB_PLL_NCPO_EN_OFST                 (31)
-#define RG_SSUSB_PLL_FIFO_START_MAN_OFST          (30)
-#define RG_SSUSB_PLL_NCPO_CHG_OFST                (28)
-#define RG_SSUSB_PLL_DDS_RSTB_OFST                (27)
-#define RG_SSUSB_PLL_DDS_PWDB_OFST                (26)
-#define RG_SSUSB_PLL_DDSEN_OFST                   (25)
-#define RG_SSUSB_PLL_AUTOK_VCO_OFST               (24)
-#define RG_SSUSB_PLL_PWD_OFST                     (23)
-#define RG_SSUSB_RX_AFE_PWD_OFST                  (22)
-#define RG_SSUSB_PLL_TCADJ_OFST                   (16)
-#define RG_SSUSB_FORCE_CDR_TCADJ_OFST             (15)
-#define RG_SSUSB_FORCE_CDR_AUTOK_VCO_OFST         (14)
-#define RG_SSUSB_FORCE_CDR_PWD_OFST               (13)
-#define RG_SSUSB_FORCE_PLL_NCPO_EN_OFST           (12)
-#define RG_SSUSB_FORCE_PLL_FIFO_START_MAN_OFST    (11)
-#define RG_SSUSB_FORCE_PLL_NCPO_CHG_OFST          (9)
-#define RG_SSUSB_FORCE_PLL_DDS_RSTB_OFST          (8)
-#define RG_SSUSB_FORCE_PLL_DDS_PWDB_OFST          (7)
-#define RG_SSUSB_FORCE_PLL_DDSEN_OFST             (6)
-#define RG_SSUSB_FORCE_PLL_TCADJ_OFST             (5)
-#define RG_SSUSB_FORCE_PLL_AUTOK_VCO_OFST         (4)
-#define RG_SSUSB_FORCE_PLL_PWD_OFST               (3)
-#define RG_SSUSB_FLT_1_DISPERR_B_OFST             (2)
-
-//U3D_PHYD_TXPLL2
-#define RG_SSUSB_TX_LFPS_EN_OFST                  (31)
-#define RG_SSUSB_FORCE_TX_LFPS_EN_OFST            (30)
-#define RG_SSUSB_TX_LFPS_OFST                     (29)
-#define RG_SSUSB_FORCE_TX_LFPS_OFST               (28)
-#define RG_SSUSB_RXPLL_STB_OFST                   (27)
-#define RG_SSUSB_TXPLL_STB_OFST                   (26)
-#define RG_SSUSB_FORCE_RXPLL_STB_OFST             (25)
-#define RG_SSUSB_FORCE_TXPLL_STB_OFST             (24)
-#define RG_SSUSB_RXPLL_REFCKSEL_OFST              (16)
-#define RG_SSUSB_RXPLL_STBMODE_OFST               (11)
-#define RG_SSUSB_RXPLL_ON_OFST                    (10)
-#define RG_SSUSB_FORCE_RXPLLON_OFST               (9)
-#define RG_SSUSB_FORCE_RX_AFE_PWD_OFST            (8)
-#define RG_SSUSB_CDR_AUTOK_VCO_OFST               (7)
-#define RG_SSUSB_CDR_PWD_OFST                     (6)
-#define RG_SSUSB_CDR_TCADJ_OFST                   (0)
-
-//U3D_PHYD_FL0
-#define RG_SSUSB_RX_FL_TARGET_OFST                (16)
-#define RG_SSUSB_RX_FL_CYCLECNT_OFST              (0)
-
-//U3D_PHYD_MIX2
-#define RG_SSUSB_RX_EQ_RST_OFST                   (31)
-#define RG_SSUSB_RX_EQ_RST_SEL_OFST               (30)
-#define RG_SSUSB_RXVAL_RST_OFST                   (29)
-#define RG_SSUSB_RXVAL_CNT_OFST                   (24)
-#define RG_SSUSB_CDROS_EN_OFST                    (18)
-#define RG_SSUSB_CDR_LCKOP_OFST                   (16)
-#define RG_SSUSB_RX_FL_LOCKTH_OFST                (8)
-#define RG_SSUSB_RX_FL_OFFSET_OFST                (0)
-
-//U3D_PHYD_RX0
-#define RG_SSUSB_T2RLB_BERTH_OFST                 (24)
-#define RG_SSUSB_T2RLB_PAT_OFST                   (16)
-#define RG_SSUSB_T2RLB_EN_OFST                    (15)
-#define RG_SSUSB_T2RLB_BPSCRAMB_OFST              (14)
-#define RG_SSUSB_T2RLB_SERIAL_OFST                (13)
-#define RG_SSUSB_T2RLB_MODE_OFST                  (11)
-#define RG_SSUSB_RX_SAOSC_EN_OFST                 (10)
-#define RG_SSUSB_RX_SAOSC_EN_SEL_OFST             (9)
-#define RG_SSUSB_RX_DFE_OPTION_OFST               (8)
-#define RG_SSUSB_RX_DFE_EN_OFST                   (7)
-#define RG_SSUSB_RX_DFE_EN_SEL_OFST               (6)
-#define RG_SSUSB_RX_EQ_EN_OFST                    (5)
-#define RG_SSUSB_RX_EQ_EN_SEL_OFST                (4)
-#define RG_SSUSB_RX_SAOSC_RST_OFST                (3)
-#define RG_SSUSB_RX_SAOSC_RST_SEL_OFST            (2)
-#define RG_SSUSB_RX_DFE_RST_OFST                  (1)
-#define RG_SSUSB_RX_DFE_RST_SEL_OFST              (0)
-
-//U3D_PHYD_T2RLB
-#define RG_SSUSB_EQTRAIN_CH_MODE_OFST             (28)
-#define RG_SSUSB_PRB_OUT_CPPAT_OFST               (27)
-#define RG_SSUSB_BPANSIENC_OFST                   (26)
-#define RG_SSUSB_VALID_EN_OFST                    (25)
-#define RG_SSUSB_EBUF_SRST_OFST                   (24)
-#define RG_SSUSB_K_EMP_OFST                       (20)
-#define RG_SSUSB_K_FUL_OFST                       (16)
-#define RG_SSUSB_T2RLB_BDATRST_OFST               (12)
-#define RG_SSUSB_P_T2RLB_SKP_EN_OFST              (10)
-#define RG_SSUSB_T2RLB_PATMODE_OFST               (8)
-#define RG_SSUSB_T2RLB_TSEQCNT_OFST               (0)
-
-//U3D_PHYD_CPPAT
-#define RG_SSUSB_CPPAT_PROGRAM_EN_OFST            (24)
-#define RG_SSUSB_CPPAT_TOZ_OFST                   (21)
-#define RG_SSUSB_CPPAT_PRBS_EN_OFST               (20)
-#define RG_SSUSB_CPPAT_OUT_TMP2_OFST              (16)
-#define RG_SSUSB_CPPAT_OUT_TMP1_OFST              (8)
-#define RG_SSUSB_CPPAT_OUT_TMP0_OFST              (0)
-
-//U3D_PHYD_MIX3
-#define RG_SSUSB_CDR_TCADJ_MINUS_OFST             (31)
-#define RG_SSUSB_P_CDROS_EN_OFST                  (30)
-#define RG_SSUSB_P_P2_TX_DRV_DIS_OFST             (28)
-#define RG_SSUSB_CDR_TCADJ_OFFSET_OFST            (24)
-#define RG_SSUSB_PLL_TCADJ_MINUS_OFST             (23)
-#define RG_SSUSB_FORCE_PLL_BIAS_LPF_EN_OFST       (20)
-#define RG_SSUSB_PLL_BIAS_LPF_EN_OFST             (19)
-#define RG_SSUSB_PLL_TCADJ_OFFSET_OFST            (16)
-#define RG_SSUSB_FORCE_PLL_SSCEN_OFST             (15)
-#define RG_SSUSB_PLL_SSCEN_OFST                   (14)
-#define RG_SSUSB_FORCE_CDR_PI_PWD_OFST            (13)
-#define RG_SSUSB_CDR_PI_PWD_OFST                  (12)
-#define RG_SSUSB_CDR_PI_MODE_OFST                 (11)
-#define RG_SSUSB_TXPLL_SSCEN_CYC_OFST             (0)
-
-//U3D_PHYD_EBUFCTL
-#define RG_SSUSB_EBUFCTL_OFST                     (0)
-
-//U3D_PHYD_PIPE0
-#define RG_SSUSB_RXTERMINATION_OFST               (30)
-#define RG_SSUSB_RXEQTRAINING_OFST                (29)
-#define RG_SSUSB_RXPOLARITY_OFST                  (28)
-#define RG_SSUSB_TXDEEMPH_OFST                    (26)
-#define RG_SSUSB_POWERDOWN_OFST                   (24)
-#define RG_SSUSB_TXONESZEROS_OFST                 (23)
-#define RG_SSUSB_TXELECIDLE_OFST                  (22)
-#define RG_SSUSB_TXDETECTRX_OFST                  (21)
-#define RG_SSUSB_PIPE_SEL_OFST                    (20)
-#define RG_SSUSB_TXDATAK_OFST                     (16)
-#define RG_SSUSB_CDR_STABLE_SEL_OFST              (15)
-#define RG_SSUSB_CDR_STABLE_OFST                  (14)
-#define RG_SSUSB_CDR_RSTB_SEL_OFST                (13)
-#define RG_SSUSB_CDR_RSTB_OFST                    (12)
-#define RG_SSUSB_P_ERROR_SEL_OFST                 (4)
-#define RG_SSUSB_TXMARGIN_OFST                    (1)
-#define RG_SSUSB_TXCOMPLIANCE_OFST                (0)
-
-//U3D_PHYD_PIPE1
-#define RG_SSUSB_TXDATA_OFST                      (0)
-
-//U3D_PHYD_MIX4
-#define RG_SSUSB_CDROS_CNT_OFST                   (24)
-#define RG_SSUSB_T2RLB_BER_EN_OFST                (16)
-#define RG_SSUSB_T2RLB_BER_RATE_OFST              (0)
-
-//U3D_PHYD_CKGEN0
-#define RG_SSUSB_RFIFO_IMPLAT_OFST                (27)
-#define RG_SSUSB_TFIFO_PSEL_OFST                  (24)
-#define RG_SSUSB_CKGEN_PSEL_OFST                  (8)
-#define RG_SSUSB_RXCK_INV_OFST                    (0)
-
-//U3D_PHYD_MIX5
-#define RG_SSUSB_PRB_SEL_OFST                     (16)
-#define RG_SSUSB_RXPLL_STBCYC_OFST                (0)
-
-//U3D_PHYD_RESERVED
-#define RG_SSUSB_PHYD_RESERVE_OFST                (0)
-//#define RG_SSUSB_RX_SIGDET_SEL_OFST               (11)
-//#define RG_SSUSB_RX_SIGDET_EN_OFST                (12)
-//#define RG_SSUSB_RX_PI_CAL_MANUAL_SEL_OFST        (9)
-//#define RG_SSUSB_RX_PI_CAL_MANUAL_EN_OFST         (10)
-
-//U3D_PHYD_CDR0
-#define RG_SSUSB_CDR_BIC_LTR_OFST                 (28)
-#define RG_SSUSB_CDR_BIC_LTD0_OFST                (24)
-#define RG_SSUSB_CDR_BC_LTD1_OFST                 (16)
-#define RG_SSUSB_CDR_BC_LTR_OFST                  (8)
-#define RG_SSUSB_CDR_BC_LTD0_OFST                 (0)
-
-//U3D_PHYD_CDR1
-#define RG_SSUSB_CDR_BIR_LTD1_OFST                (24)
-#define RG_SSUSB_CDR_BIR_LTR_OFST                 (16)
-#define RG_SSUSB_CDR_BIR_LTD0_OFST                (8)
-#define RG_SSUSB_CDR_BW_SEL_OFST                  (6)
-#define RG_SSUSB_CDR_BIC_LTD1_OFST                (0)
-
-//U3D_PHYD_PLL_0
-#define RG_SSUSB_FORCE_CDR_BAND_5G_OFST           (28)
-#define RG_SSUSB_FORCE_CDR_BAND_2P5G_OFST         (27)
-#define RG_SSUSB_FORCE_PLL_BAND_5G_OFST           (26)
-#define RG_SSUSB_FORCE_PLL_BAND_2P5G_OFST         (25)
-#define RG_SSUSB_P_EQ_T_SEL_OFST                  (15)
-#define RG_SSUSB_PLL_ISO_EN_CYC_OFST              (5)
-#define RG_SSUSB_PLLBAND_RECAL_OFST               (4)
-#define RG_SSUSB_PLL_DDS_ISO_EN_OFST              (3)
-#define RG_SSUSB_FORCE_PLL_DDS_ISO_EN_OFST        (2)
-#define RG_SSUSB_PLL_DDS_PWR_ON_OFST              (1)
-#define RG_SSUSB_FORCE_PLL_DDS_PWR_ON_OFST        (0)
-
-//U3D_PHYD_PLL_1
-#define RG_SSUSB_CDR_BAND_5G_OFST                 (24)
-#define RG_SSUSB_CDR_BAND_2P5G_OFST               (16)
-#define RG_SSUSB_PLL_BAND_5G_OFST                 (8)
-#define RG_SSUSB_PLL_BAND_2P5G_OFST               (0)
-
-//U3D_PHYD_BCN_DET_1
-#define RG_SSUSB_P_BCN_OBS_PRD_OFST               (16)
-#define RG_SSUSB_U_BCN_OBS_PRD_OFST               (0)
-
-//U3D_PHYD_BCN_DET_2
-#define RG_SSUSB_P_BCN_OBS_SEL_OFST               (16)
-#define RG_SSUSB_BCN_DET_DIS_OFST                 (12)
-#define RG_SSUSB_U_BCN_OBS_SEL_OFST               (0)
-
-//U3D_EQ0
-#define RG_SSUSB_EQ_DLHL_LFI_OFST                 (24)
-#define RG_SSUSB_EQ_DHHL_LFI_OFST                 (16)
-#define RG_SSUSB_EQ_DD0HOS_LFI_OFST               (8)
-#define RG_SSUSB_EQ_DD0LOS_LFI_OFST               (0)
-
-//U3D_EQ1
-#define RG_SSUSB_EQ_DD1HOS_LFI_OFST               (24)
-#define RG_SSUSB_EQ_DD1LOS_LFI_OFST               (16)
-#define RG_SSUSB_EQ_DE0OS_LFI_OFST                (8)
-#define RG_SSUSB_EQ_DE1OS_LFI_OFST                (0)
-
-//U3D_EQ2
-#define RG_SSUSB_EQ_DLHLOS_LFI_OFST               (24)
-#define RG_SSUSB_EQ_DHHLOS_LFI_OFST               (16)
-#define RG_SSUSB_EQ_STOPTIME_OFST                 (14)
-#define RG_SSUSB_EQ_DHHL_LF_SEL_OFST              (11)
-#define RG_SSUSB_EQ_DSAOS_LF_SEL_OFST             (8)
-#define RG_SSUSB_EQ_STARTTIME_OFST                (6)
-#define RG_SSUSB_EQ_DLEQ_LF_SEL_OFST              (3)
-#define RG_SSUSB_EQ_DLHL_LF_SEL_OFST              (0)
-
-//U3D_EQ3
-#define RG_SSUSB_EQ_DLEQ_LFI_GEN2_OFST            (28)
-#define RG_SSUSB_EQ_DLEQ_LFI_GEN1_OFST            (24)
-#define RG_SSUSB_EQ_DEYE0OS_LFI_OFST              (16)
-#define RG_SSUSB_EQ_DEYE1OS_LFI_OFST              (8)
-#define RG_SSUSB_EQ_TRI_DET_EN_OFST               (7)
-#define RG_SSUSB_EQ_TRI_DET_TH_OFST               (0)
-
-//U3D_EQ_EYE0
-#define RG_SSUSB_EQ_EYE_XOFFSET_OFST              (25)
-#define RG_SSUSB_EQ_EYE_MON_EN_OFST               (24)
-#define RG_SSUSB_EQ_EYE0_Y_OFST                   (16)
-#define RG_SSUSB_EQ_EYE1_Y_OFST                   (8)
-#define RG_SSUSB_EQ_PILPO_ROUT_OFST               (7)
-#define RG_SSUSB_EQ_PI_KPGAIN_OFST                (4)
-#define RG_SSUSB_EQ_EYE_CNT_EN_OFST               (3)
-
-//U3D_EQ_EYE1
-#define RG_SSUSB_EQ_SIGDET_OFST                   (24)
-#define RG_SSUSB_EQ_EYE_MASK_OFST                 (7)
-
-//U3D_EQ_EYE2
-#define RG_SSUSB_EQ_RX500M_CK_SEL_OFST            (31)
-#define RG_SSUSB_EQ_SD_CNT1_OFST                  (24)
-#define RG_SSUSB_EQ_ISIFLAG_SEL_OFST              (22)
-#define RG_SSUSB_EQ_SD_CNT0_OFST                  (16)
-
-//U3D_EQ_DFE0
-#define RG_SSUSB_EQ_LEQMAX_OFST                   (28)
-#define RG_SSUSB_EQ_DFEX_EN_OFST                  (27)
-#define RG_SSUSB_EQ_DFEX_LF_SEL_OFST              (24)
-#define RG_SSUSB_EQ_CHK_EYE_H_OFST                (23)
-#define RG_SSUSB_EQ_PIEYE_INI_OFST                (16)
-#define RG_SSUSB_EQ_PI90_INI_OFST                 (8)
-#define RG_SSUSB_EQ_PI0_INI_OFST                  (0)
-
-//U3D_EQ_DFE1
-#define RG_SSUSB_EQ_REV_OFST                      (16)
-#define RG_SSUSB_EQ_DFEYEN_DUR_OFST               (12)
-#define RG_SSUSB_EQ_DFEXEN_DUR_OFST               (8)
-#define RG_SSUSB_EQ_DFEX_RST_OFST                 (7)
-#define RG_SSUSB_EQ_GATED_RXD_B_OFST              (6)
-#define RG_SSUSB_EQ_PI90CK_SEL_OFST               (4)
-#define RG_SSUSB_EQ_DFEX_DIS_OFST                 (2)
-#define RG_SSUSB_EQ_DFEYEN_STOP_DIS_OFST          (1)
-#define RG_SSUSB_EQ_DFEXEN_SEL_OFST               (0)
-
-//U3D_EQ_DFE2
-#define RG_SSUSB_EQ_MON_SEL_OFST                  (24)
-#define RG_SSUSB_EQ_LEQOSC_DLYCNT_OFST            (16)
-#define RG_SSUSB_EQ_DLEQOS_LFI_OFST               (8)
-#define RG_SSUSB_EQ_LEQ_STOP_TO_OFST              (0)
-
-//U3D_EQ_DFE3
-#define RG_SSUSB_EQ_RESERVED_OFST                 (0)
-
-//U3D_PHYD_MON0
-#define RGS_SSUSB_BERT_BERC_OFST                  (16)
-#define RGS_SSUSB_LFPS_OFST                       (12)
-#define RGS_SSUSB_TRAINDEC_OFST                   (8)
-#define RGS_SSUSB_SCP_PAT_OFST                    (0)
-
-//U3D_PHYD_MON1
-#define RGS_SSUSB_RX_FL_OUT_OFST                  (0)
-
-//U3D_PHYD_MON2
-#define RGS_SSUSB_T2RLB_ERRCNT_OFST               (16)
-#define RGS_SSUSB_RETRACK_OFST                    (12)
-#define RGS_SSUSB_RXPLL_LOCK_OFST                 (10)
-#define RGS_SSUSB_CDR_VCOCAL_CPLT_D_OFST          (9)
-#define RGS_SSUSB_PLL_VCOCAL_CPLT_D_OFST          (8)
-#define RGS_SSUSB_PDNCTL_OFST                     (0)
-
-//U3D_PHYD_MON3
-#define RGS_SSUSB_TSEQ_ERRCNT_OFST                (16)
-#define RGS_SSUSB_PRBS_ERRCNT_OFST                (0)
-
-//U3D_PHYD_MON4
-#define RGS_SSUSB_RX_LSLOCK_CNT_OFST              (24)
-#define RGS_SSUSB_SCP_DETCNT_OFST                 (16)
-#define RGS_SSUSB_TSEQ_DETCNT_OFST                (0)
-
-//U3D_PHYD_MON5
-#define RGS_SSUSB_EBUFMSG_OFST                    (16)
-#define RGS_SSUSB_BERT_LOCK_OFST                  (15)
-#define RGS_SSUSB_SCP_DET_OFST                    (14)
-#define RGS_SSUSB_TSEQ_DET_OFST                   (13)
-#define RGS_SSUSB_EBUF_UDF_OFST                   (12)
-#define RGS_SSUSB_EBUF_OVF_OFST                   (11)
-#define RGS_SSUSB_PRBS_PASSTH_OFST                (10)
-#define RGS_SSUSB_PRBS_PASS_OFST                  (9)
-#define RGS_SSUSB_PRBS_LOCK_OFST                  (8)
-#define RGS_SSUSB_T2RLB_ERR_OFST                  (6)
-#define RGS_SSUSB_T2RLB_PASSTH_OFST               (5)
-#define RGS_SSUSB_T2RLB_PASS_OFST                 (4)
-#define RGS_SSUSB_T2RLB_LOCK_OFST                 (3)
-#define RGS_SSUSB_RX_IMPCAL_DONE_OFST             (2)
-#define RGS_SSUSB_TX_IMPCAL_DONE_OFST             (1)
-#define RGS_SSUSB_RXDETECTED_OFST                 (0)
-
-//U3D_PHYD_MON6
-#define RGS_SSUSB_SIGCAL_DONE_OFST                (30)
-#define RGS_SSUSB_SIGCAL_CAL_OUT_OFST             (29)
-#define RGS_SSUSB_SIGCAL_OFFSET_OFST              (24)
-#define RGS_SSUSB_RX_IMP_SEL_OFST                 (16)
-#define RGS_SSUSB_TX_IMP_SEL_OFST                 (8)
-#define RGS_SSUSB_TFIFO_MSG_OFST                  (4)
-#define RGS_SSUSB_RFIFO_MSG_OFST                  (0)
-
-//U3D_PHYD_MON7
-#define RGS_SSUSB_FT_OUT_OFST                     (8)
-#define RGS_SSUSB_PRB_OUT_OFST                    (0)
-
-//U3D_PHYA_RX_MON0
-#define RGS_SSUSB_EQ_DCLEQ_OFST                   (24)
-#define RGS_SSUSB_EQ_DCD0H_OFST                   (16)
-#define RGS_SSUSB_EQ_DCD0L_OFST                   (8)
-#define RGS_SSUSB_EQ_DCD1H_OFST                   (0)
-
-//U3D_PHYA_RX_MON1
-#define RGS_SSUSB_EQ_DCD1L_OFST                   (24)
-#define RGS_SSUSB_EQ_DCE0_OFST                    (16)
-#define RGS_SSUSB_EQ_DCE1_OFST                    (8)
-#define RGS_SSUSB_EQ_DCHHL_OFST                   (0)
-
-//U3D_PHYA_RX_MON2
-#define RGS_SSUSB_EQ_LEQ_STOP_OFST                (31)
-#define RGS_SSUSB_EQ_DCLHL_OFST                   (24)
-#define RGS_SSUSB_EQ_STATUS_OFST                  (16)
-#define RGS_SSUSB_EQ_DCEYE0_OFST                  (8)
-#define RGS_SSUSB_EQ_DCEYE1_OFST                  (0)
-
-//U3D_PHYA_RX_MON3
-#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST    (0)
-
-//U3D_PHYA_RX_MON4
-#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST    (0)
-
-//U3D_PHYA_RX_MON5
-#define RGS_SSUSB_EQ_DCLEQOS_OFST                 (8)
-#define RGS_SSUSB_EQ_EYE_CNT_RDY_OFST             (7)
-#define RGS_SSUSB_EQ_PILPO_OFST                   (0)
-
-//U3D_PHYD_CPPAT2
-#define RG_SSUSB_CPPAT_OUT_H_TMP2_OFST            (16)
-#define RG_SSUSB_CPPAT_OUT_H_TMP1_OFST            (8)
-#define RG_SSUSB_CPPAT_OUT_H_TMP0_OFST            (0)
-
-//U3D_EQ_EYE3
-#define RG_SSUSB_EQ_LEQ_SHIFT_OFST                (24)
-#define RG_SSUSB_EQ_EYE_CNT_OFST                  (0)
-
-//U3D_KBAND_OUT
-#define RGS_SSUSB_CDR_BAND_5G_OFST                (24)
-#define RGS_SSUSB_CDR_BAND_2P5G_OFST              (16)
-#define RGS_SSUSB_PLL_BAND_5G_OFST                (8)
-#define RGS_SSUSB_PLL_BAND_2P5G_OFST              (0)
-
-//U3D_KBAND_OUT1
-#define RGS_SSUSB_CDR_VCOCAL_FAIL_OFST            (24)
-#define RGS_SSUSB_CDR_VCOCAL_STATE_OFST           (16)
-#define RGS_SSUSB_PLL_VCOCAL_FAIL_OFST            (8)
-#define RGS_SSUSB_PLL_VCOCAL_STATE_OFST           (0)
-
-
-///////////////////////////////////////////////////////////////////////////////
-
-struct u3phyd_bank2_reg {
-       //0x0
-       PHY_LE32 b2_phyd_top1;
-       PHY_LE32 b2_phyd_top2;
-       PHY_LE32 b2_phyd_top3;
-       PHY_LE32 b2_phyd_top4;
-       //0x10
-       PHY_LE32 b2_phyd_top5;
-       PHY_LE32 b2_phyd_top6;
-       PHY_LE32 b2_phyd_top7;
-       PHY_LE32 b2_phyd_p_sigdet1;
-       //0x20
-       PHY_LE32 b2_phyd_p_sigdet2;
-       PHY_LE32 b2_phyd_p_sigdet_cal1;
-       PHY_LE32 b2_phyd_rxdet1;
-       PHY_LE32 b2_phyd_rxdet2;
-       //0x30
-       PHY_LE32 b2_phyd_misc0;
-       PHY_LE32 b2_phyd_misc2;
-       PHY_LE32 b2_phyd_misc3;
-       PHY_LE32 reserve0;
-       //0x40
-       PHY_LE32 b2_rosc_0;
-       PHY_LE32 b2_rosc_1;
-       PHY_LE32 b2_rosc_2;
-       PHY_LE32 b2_rosc_3;
-       //0x50
-       PHY_LE32 b2_rosc_4;
-       PHY_LE32 b2_rosc_5;
-       PHY_LE32 b2_rosc_6;
-       PHY_LE32 b2_rosc_7;
-       //0x60
-       PHY_LE32 b2_rosc_8;
-       PHY_LE32 b2_rosc_9;
-       PHY_LE32 b2_rosc_a;
-       PHY_LE32 reserve1;
-       //0x70~0xd0
-       PHY_LE32 reserve2[28];
-       //0xe0
-       PHY_LE32 phyd_version;
-       PHY_LE32 phyd_model;
-};
-
-//U3D_B2_PHYD_TOP1
-#define RG_SSUSB_PCIE2_K_EMP                      (0xf<<28) //31:28
-#define RG_SSUSB_PCIE2_K_FUL                      (0xf<<24) //27:24
-#define RG_SSUSB_TX_EIDLE_LP_EN                   (0x1<<17) //17:17
-#define RG_SSUSB_FORCE_TX_EIDLE_LP_EN             (0x1<<16) //16:16
-#define RG_SSUSB_SIGDET_EN                        (0x1<<15) //15:15
-#define RG_SSUSB_FORCE_SIGDET_EN                  (0x1<<14) //14:14
-#define RG_SSUSB_CLKRX_EN                         (0x1<<13) //13:13
-#define RG_SSUSB_FORCE_CLKRX_EN                   (0x1<<12) //12:12
-#define RG_SSUSB_CLKTX_EN                         (0x1<<11) //11:11
-#define RG_SSUSB_FORCE_CLKTX_EN                   (0x1<<10) //10:10
-#define RG_SSUSB_CLK_REQ_N_I                      (0x1<<9) //9:9
-#define RG_SSUSB_FORCE_CLK_REQ_N_I                (0x1<<8) //8:8
-#define RG_SSUSB_RATE                             (0x1<<6) //6:6
-#define RG_SSUSB_FORCE_RATE                       (0x1<<5) //5:5
-#define RG_SSUSB_PCIE_MODE_SEL                    (0x1<<4) //4:4
-#define RG_SSUSB_FORCE_PCIE_MODE_SEL              (0x1<<3) //3:3
-#define RG_SSUSB_PHY_MODE                         (0x3<<1) //2:1
-#define RG_SSUSB_FORCE_PHY_MODE                   (0x1<<0) //0:0
-
-//U3D_B2_PHYD_TOP2
-#define RG_SSUSB_FORCE_IDRV_6DB                   (0x1<<30) //30:30
-#define RG_SSUSB_IDRV_6DB                         (0x3f<<24) //29:24
-#define RG_SSUSB_FORCE_IDEM_3P5DB                 (0x1<<22) //22:22
-#define RG_SSUSB_IDEM_3P5DB                       (0x3f<<16) //21:16
-#define RG_SSUSB_FORCE_IDRV_3P5DB                 (0x1<<14) //14:14
-#define RG_SSUSB_IDRV_3P5DB                       (0x3f<<8) //13:8
-#define RG_SSUSB_FORCE_IDRV_0DB                   (0x1<<6) //6:6
-#define RG_SSUSB_IDRV_0DB                         (0x3f<<0) //5:0
-
-//U3D_B2_PHYD_TOP3
-#define RG_SSUSB_TX_BIASI                         (0x7<<25) //27:25
-#define RG_SSUSB_FORCE_TX_BIASI_EN                (0x1<<24) //24:24
-#define RG_SSUSB_TX_BIASI_EN                      (0x1<<16) //16:16
-#define RG_SSUSB_FORCE_TX_BIASI                   (0x1<<13) //13:13
-#define RG_SSUSB_FORCE_IDEM_6DB                   (0x1<<8) //8:8
-#define RG_SSUSB_IDEM_6DB                         (0x3f<<0) //5:0
-
-//U3D_B2_PHYD_TOP4
-#define RG_SSUSB_G1_CDR_BIC_LTR                   (0xf<<28) //31:28
-#define RG_SSUSB_G1_CDR_BIC_LTD0                  (0xf<<24) //27:24
-#define RG_SSUSB_G1_CDR_BC_LTD1                   (0x1f<<16) //20:16
-#define RG_SSUSB_G1_CDR_BC_LTR                    (0x1f<<8) //12:8
-#define RG_SSUSB_G1_CDR_BC_LTD0                   (0x1f<<0) //4:0
-
-//U3D_B2_PHYD_TOP5
-#define RG_SSUSB_G1_CDR_BIR_LTD1                  (0x1f<<24) //28:24
-#define RG_SSUSB_G1_CDR_BIR_LTR                   (0x1f<<16) //20:16
-#define RG_SSUSB_G1_CDR_BIR_LTD0                  (0x1f<<8) //12:8
-#define RG_SSUSB_G1_CDR_BIC_LTD1                  (0xf<<0) //3:0
-
-//U3D_B2_PHYD_TOP6
-#define RG_SSUSB_G2_CDR_BIC_LTR                   (0xf<<28) //31:28
-#define RG_SSUSB_G2_CDR_BIC_LTD0                  (0xf<<24) //27:24
-#define RG_SSUSB_G2_CDR_BC_LTD1                   (0x1f<<16) //20:16
-#define RG_SSUSB_G2_CDR_BC_LTR                    (0x1f<<8) //12:8
-#define RG_SSUSB_G2_CDR_BC_LTD0                   (0x1f<<0) //4:0
-
-//U3D_B2_PHYD_TOP7
-#define RG_SSUSB_G2_CDR_BIR_LTD1                  (0x1f<<24) //28:24
-#define RG_SSUSB_G2_CDR_BIR_LTR                   (0x1f<<16) //20:16
-#define RG_SSUSB_G2_CDR_BIR_LTD0                  (0x1f<<8) //12:8
-#define RG_SSUSB_G2_CDR_BIC_LTD1                  (0xf<<0) //3:0
-
-//U3D_B2_PHYD_P_SIGDET1
-#define RG_SSUSB_P_SIGDET_FLT_DIS                 (0x1<<31) //31:31
-#define RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL        (0x7f<<24) //30:24
-#define RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL        (0x7f<<16) //22:16
-#define RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL          (0x7f<<8) //14:8
-#define RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL          (0x7f<<0) //6:0
-
-//U3D_B2_PHYD_P_SIGDET2
-#define RG_SSUSB_P_SIGDET_RX_VAL_S                (0x1<<29) //29:29
-#define RG_SSUSB_P_SIGDET_L0S_DEAS_SEL            (0x1<<28) //28:28
-#define RG_SSUSB_P_SIGDET_L0_EXIT_S               (0x1<<27) //27:27
-#define RG_SSUSB_P_SIGDET_L0S_EXIT_T_S            (0x3<<25) //26:25
-#define RG_SSUSB_P_SIGDET_L0S_EXIT_S              (0x1<<24) //24:24
-#define RG_SSUSB_P_SIGDET_L0S_ENTRY_S             (0x1<<16) //16:16
-#define RG_SSUSB_P_SIGDET_PRB_SEL                 (0x1<<10) //10:10
-#define RG_SSUSB_P_SIGDET_BK_SIG_T                (0x3<<8) //9:8
-#define RG_SSUSB_P_SIGDET_P2_RXLFPS               (0x1<<6) //6:6
-#define RG_SSUSB_P_SIGDET_NON_BK_AD               (0x1<<5) //5:5
-#define RG_SSUSB_P_SIGDET_BK_B_RXEQ               (0x1<<4) //4:4
-#define RG_SSUSB_P_SIGDET_G2_KO_SEL               (0x3<<2) //3:2
-#define RG_SSUSB_P_SIGDET_G1_KO_SEL               (0x3<<0) //1:0
-
-//U3D_B2_PHYD_P_SIGDET_CAL1
-#define RG_SSUSB_P_SIGDET_CAL_OFFSET              (0x1f<<24) //28:24
-#define RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET        (0x1<<16) //16:16
-#define RG_SSUSB_P_SIGDET_CAL_EN                  (0x1<<8) //8:8
-#define RG_SSUSB_P_FORCE_SIGDET_CAL_EN            (0x1<<3) //3:3
-#define RG_SSUSB_P_SIGDET_FLT_EN                  (0x1<<2) //2:2
-#define RG_SSUSB_P_SIGDET_SAMPLE_PRD              (0x1<<1) //1:1
-#define RG_SSUSB_P_SIGDET_REK                     (0x1<<0) //0:0
-
-//U3D_B2_PHYD_RXDET1
-#define RG_SSUSB_RXDET_PRB_SEL                    (0x1<<31) //31:31
-#define RG_SSUSB_FORCE_CMDET                      (0x1<<30) //30:30
-#define RG_SSUSB_RXDET_EN                         (0x1<<29) //29:29
-#define RG_SSUSB_FORCE_RXDET_EN                   (0x1<<28) //28:28
-#define RG_SSUSB_RXDET_K_TWICE                    (0x1<<27) //27:27
-#define RG_SSUSB_RXDET_STB3_SET                   (0x1ff<<18) //26:18
-#define RG_SSUSB_RXDET_STB2_SET                   (0x1ff<<9) //17:9
-#define RG_SSUSB_RXDET_STB1_SET                   (0x1ff<<0) //8:0
-
-//U3D_B2_PHYD_RXDET2
-#define RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN         (0x1<<31) //31:31
-#define RG_SSUSB_PHYD_BERTLB_FORCE_CGEN           (0x1<<30) //30:30
-#define RG_SSUSB_PHYD_T2RLB_FORCE_CGEN            (0x1<<29) //29:29
-#define RG_SSUSB_PDN_T_SEL                        (0x3<<18) //19:18
-#define RG_SSUSB_RXDET_STB3_SET_P3                (0x1ff<<9) //17:9
-#define RG_SSUSB_RXDET_STB2_SET_P3                (0x1ff<<0) //8:0
-
-//U3D_B2_PHYD_MISC0
-#define RG_SSUSB_FORCE_PLL_DDS_HF_EN              (0x1<<22) //22:22
-#define RG_SSUSB_PLL_DDS_HF_EN_MAN                (0x1<<21) //21:21
-#define RG_SSUSB_RXLFPS_ENTXDRV                   (0x1<<20) //20:20
-#define RG_SSUSB_RX_FL_UNLOCKTH                   (0xf<<16) //19:16
-#define RG_SSUSB_LFPS_PSEL                        (0x1<<15) //15:15
-#define RG_SSUSB_RX_SIGDET_EN                     (0x1<<14) //14:14
-#define RG_SSUSB_RX_SIGDET_EN_SEL                 (0x1<<13) //13:13
-#define RG_SSUSB_RX_PI_CAL_EN                     (0x1<<12) //12:12
-#define RG_SSUSB_RX_PI_CAL_EN_SEL                 (0x1<<11) //11:11
-#define RG_SSUSB_P3_CLS_CK_SEL                    (0x1<<10) //10:10
-#define RG_SSUSB_T2RLB_PSEL                       (0x3<<8) //9:8
-#define RG_SSUSB_PPCTL_PSEL                       (0x7<<5) //7:5
-#define RG_SSUSB_PHYD_TX_DATA_INV                 (0x1<<4) //4:4
-#define RG_SSUSB_BERTLB_PSEL                      (0x3<<2) //3:2
-#define RG_SSUSB_RETRACK_DIS                      (0x1<<1) //1:1
-#define RG_SSUSB_PPERRCNT_CLR                     (0x1<<0) //0:0
-
-//U3D_B2_PHYD_MISC2
-#define RG_SSUSB_FRC_PLL_DDS_PREDIV2              (0x1<<31) //31:31
-#define RG_SSUSB_FRC_PLL_DDS_IADJ                 (0xf<<27) //30:27
-#define RG_SSUSB_P_SIGDET_125FILTER               (0x1<<26) //26:26
-#define RG_SSUSB_P_SIGDET_RST_FILTER              (0x1<<25) //25:25
-#define RG_SSUSB_P_SIGDET_EID_USE_RAW             (0x1<<24) //24:24
-#define RG_SSUSB_P_SIGDET_LTD_USE_RAW             (0x1<<23) //23:23
-#define RG_SSUSB_EIDLE_BF_RXDET                   (0x1<<22) //22:22
-#define RG_SSUSB_EIDLE_LP_STBCYC                  (0x1ff<<13) //21:13
-#define RG_SSUSB_TX_EIDLE_LP_POSTDLY              (0x3f<<7) //12:7
-#define RG_SSUSB_TX_EIDLE_LP_PREDLY               (0x3f<<1) //6:1
-#define RG_SSUSB_TX_EIDLE_LP_EN_ADV               (0x1<<0) //0:0
-
-//U3D_B2_PHYD_MISC3
-#define RGS_SSUSB_DDS_CALIB_C_STATE               (0x7<<16) //18:16
-#define RGS_SSUSB_PPERRCNT                        (0xffff<<0) //15:0
-
-//U3D_B2_ROSC_0
-#define RG_SSUSB_RING_OSC_CNTEND                  (0x1ff<<23) //31:23
-#define RG_SSUSB_XTAL_OSC_CNTEND                  (0x7f<<16) //22:16
-#define RG_SSUSB_RING_OSC_EN                      (0x1<<3) //3:3
-#define RG_SSUSB_RING_OSC_FORCE_EN                (0x1<<2) //2:2
-#define RG_SSUSB_FRC_RING_BYPASS_DET              (0x1<<1) //1:1
-#define RG_SSUSB_RING_BYPASS_DET                  (0x1<<0) //0:0
-
-//U3D_B2_ROSC_1
-#define RG_SSUSB_RING_OSC_FRC_P3                  (0x1<<20) //20:20
-#define RG_SSUSB_RING_OSC_P3                      (0x1<<19) //19:19
-#define RG_SSUSB_RING_OSC_FRC_RECAL               (0x3<<17) //18:17
-#define RG_SSUSB_RING_OSC_RECAL                   (0x1<<16) //16:16
-#define RG_SSUSB_RING_OSC_SEL                     (0xff<<8) //15:8
-#define RG_SSUSB_RING_OSC_FRC_SEL                 (0x1<<0) //0:0
-
-//U3D_B2_ROSC_2
-#define RG_SSUSB_RING_DET_STRCYC2                 (0xffff<<16) //31:16
-#define RG_SSUSB_RING_DET_STRCYC1                 (0xffff<<0) //15:0
-
-//U3D_B2_ROSC_3
-#define RG_SSUSB_RING_DET_DETWIN1                 (0xffff<<16) //31:16
-#define RG_SSUSB_RING_DET_STRCYC3                 (0xffff<<0) //15:0
-
-//U3D_B2_ROSC_4
-#define RG_SSUSB_RING_DET_DETWIN3                 (0xffff<<16) //31:16
-#define RG_SSUSB_RING_DET_DETWIN2                 (0xffff<<0) //15:0
-
-//U3D_B2_ROSC_5
-#define RG_SSUSB_RING_DET_LBOND1                  (0xffff<<16) //31:16
-#define RG_SSUSB_RING_DET_UBOND1                  (0xffff<<0) //15:0
-
-//U3D_B2_ROSC_6
-#define RG_SSUSB_RING_DET_LBOND2                  (0xffff<<16) //31:16
-#define RG_SSUSB_RING_DET_UBOND2                  (0xffff<<0) //15:0
-
-//U3D_B2_ROSC_7
-#define RG_SSUSB_RING_DET_LBOND3                  (0xffff<<16) //31:16
-#define RG_SSUSB_RING_DET_UBOND3                  (0xffff<<0) //15:0
-
-//U3D_B2_ROSC_8
-#define RG_SSUSB_RING_RESERVE                     (0xffff<<16) //31:16
-#define RG_SSUSB_ROSC_PROB_SEL                    (0xf<<2) //5:2
-#define RG_SSUSB_RING_FREQMETER_EN                (0x1<<1) //1:1
-#define RG_SSUSB_RING_DET_BPS_UBOND               (0x1<<0) //0:0
-
-//U3D_B2_ROSC_9
-#define RGS_FM_RING_CNT                           (0xffff<<16) //31:16
-#define RGS_SSUSB_RING_OSC_STATE                  (0x3<<10) //11:10
-#define RGS_SSUSB_RING_OSC_STABLE                 (0x1<<9) //9:9
-#define RGS_SSUSB_RING_OSC_CAL_FAIL               (0x1<<8) //8:8
-#define RGS_SSUSB_RING_OSC_CAL                    (0xff<<0) //7:0
-
-//U3D_B2_ROSC_A
-#define RGS_SSUSB_ROSC_PROB_OUT                   (0xff<<0) //7:0
-
-//U3D_PHYD_VERSION
-#define RGS_SSUSB_PHYD_VERSION                    (0xffffffff<<0) //31:0
-
-//U3D_PHYD_MODEL
-#define RGS_SSUSB_PHYD_MODEL                      (0xffffffff<<0) //31:0
-
-
-/* OFFSET */
-
-//U3D_B2_PHYD_TOP1
-#define RG_SSUSB_PCIE2_K_EMP_OFST                 (28)
-#define RG_SSUSB_PCIE2_K_FUL_OFST                 (24)
-#define RG_SSUSB_TX_EIDLE_LP_EN_OFST              (17)
-#define RG_SSUSB_FORCE_TX_EIDLE_LP_EN_OFST        (16)
-#define RG_SSUSB_SIGDET_EN_OFST                   (15)
-#define RG_SSUSB_FORCE_SIGDET_EN_OFST             (14)
-#define RG_SSUSB_CLKRX_EN_OFST                    (13)
-#define RG_SSUSB_FORCE_CLKRX_EN_OFST              (12)
-#define RG_SSUSB_CLKTX_EN_OFST                    (11)
-#define RG_SSUSB_FORCE_CLKTX_EN_OFST              (10)
-#define RG_SSUSB_CLK_REQ_N_I_OFST                 (9)
-#define RG_SSUSB_FORCE_CLK_REQ_N_I_OFST           (8)
-#define RG_SSUSB_RATE_OFST                        (6)
-#define RG_SSUSB_FORCE_RATE_OFST                  (5)
-#define RG_SSUSB_PCIE_MODE_SEL_OFST               (4)
-#define RG_SSUSB_FORCE_PCIE_MODE_SEL_OFST         (3)
-#define RG_SSUSB_PHY_MODE_OFST                    (1)
-#define RG_SSUSB_FORCE_PHY_MODE_OFST              (0)
-
-//U3D_B2_PHYD_TOP2
-#define RG_SSUSB_FORCE_IDRV_6DB_OFST              (30)
-#define RG_SSUSB_IDRV_6DB_OFST                    (24)
-#define RG_SSUSB_FORCE_IDEM_3P5DB_OFST            (22)
-#define RG_SSUSB_IDEM_3P5DB_OFST                  (16)
-#define RG_SSUSB_FORCE_IDRV_3P5DB_OFST            (14)
-#define RG_SSUSB_IDRV_3P5DB_OFST                  (8)
-#define RG_SSUSB_FORCE_IDRV_0DB_OFST              (6)
-#define RG_SSUSB_IDRV_0DB_OFST                    (0)
-
-//U3D_B2_PHYD_TOP3
-#define RG_SSUSB_TX_BIASI_OFST                    (25)
-#define RG_SSUSB_FORCE_TX_BIASI_EN_OFST           (24)
-#define RG_SSUSB_TX_BIASI_EN_OFST                 (16)
-#define RG_SSUSB_FORCE_TX_BIASI_OFST              (13)
-#define RG_SSUSB_FORCE_IDEM_6DB_OFST              (8)
-#define RG_SSUSB_IDEM_6DB_OFST                    (0)
-
-//U3D_B2_PHYD_TOP4
-#define RG_SSUSB_G1_CDR_BIC_LTR_OFST              (28)
-#define RG_SSUSB_G1_CDR_BIC_LTD0_OFST             (24)
-#define RG_SSUSB_G1_CDR_BC_LTD1_OFST              (16)
-#define RG_SSUSB_G1_CDR_BC_LTR_OFST               (8)
-#define RG_SSUSB_G1_CDR_BC_LTD0_OFST              (0)
-
-//U3D_B2_PHYD_TOP5
-#define RG_SSUSB_G1_CDR_BIR_LTD1_OFST             (24)
-#define RG_SSUSB_G1_CDR_BIR_LTR_OFST              (16)
-#define RG_SSUSB_G1_CDR_BIR_LTD0_OFST             (8)
-#define RG_SSUSB_G1_CDR_BIC_LTD1_OFST             (0)
-
-//U3D_B2_PHYD_TOP6
-#define RG_SSUSB_G2_CDR_BIC_LTR_OFST              (28)
-#define RG_SSUSB_G2_CDR_BIC_LTD0_OFST             (24)
-#define RG_SSUSB_G2_CDR_BC_LTD1_OFST              (16)
-#define RG_SSUSB_G2_CDR_BC_LTR_OFST               (8)
-#define RG_SSUSB_G2_CDR_BC_LTD0_OFST              (0)
-
-//U3D_B2_PHYD_TOP7
-#define RG_SSUSB_G2_CDR_BIR_LTD1_OFST             (24)
-#define RG_SSUSB_G2_CDR_BIR_LTR_OFST              (16)
-#define RG_SSUSB_G2_CDR_BIR_LTD0_OFST             (8)
-#define RG_SSUSB_G2_CDR_BIC_LTD1_OFST             (0)
-
-//U3D_B2_PHYD_P_SIGDET1
-#define RG_SSUSB_P_SIGDET_FLT_DIS_OFST            (31)
-#define RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL_OFST   (24)
-#define RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL_OFST   (16)
-#define RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL_OFST     (8)
-#define RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL_OFST     (0)
-
-//U3D_B2_PHYD_P_SIGDET2
-#define RG_SSUSB_P_SIGDET_RX_VAL_S_OFST           (29)
-#define RG_SSUSB_P_SIGDET_L0S_DEAS_SEL_OFST       (28)
-#define RG_SSUSB_P_SIGDET_L0_EXIT_S_OFST          (27)
-#define RG_SSUSB_P_SIGDET_L0S_EXIT_T_S_OFST       (25)
-#define RG_SSUSB_P_SIGDET_L0S_EXIT_S_OFST         (24)
-#define RG_SSUSB_P_SIGDET_L0S_ENTRY_S_OFST        (16)
-#define RG_SSUSB_P_SIGDET_PRB_SEL_OFST            (10)
-#define RG_SSUSB_P_SIGDET_BK_SIG_T_OFST           (8)
-#define RG_SSUSB_P_SIGDET_P2_RXLFPS_OFST          (6)
-#define RG_SSUSB_P_SIGDET_NON_BK_AD_OFST          (5)
-#define RG_SSUSB_P_SIGDET_BK_B_RXEQ_OFST          (4)
-#define RG_SSUSB_P_SIGDET_G2_KO_SEL_OFST          (2)
-#define RG_SSUSB_P_SIGDET_G1_KO_SEL_OFST          (0)
-
-//U3D_B2_PHYD_P_SIGDET_CAL1
-#define RG_SSUSB_P_SIGDET_CAL_OFFSET_OFST         (24)
-#define RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET_OFST   (16)
-#define RG_SSUSB_P_SIGDET_CAL_EN_OFST             (8)
-#define RG_SSUSB_P_FORCE_SIGDET_CAL_EN_OFST       (3)
-#define RG_SSUSB_P_SIGDET_FLT_EN_OFST             (2)
-#define RG_SSUSB_P_SIGDET_SAMPLE_PRD_OFST         (1)
-#define RG_SSUSB_P_SIGDET_REK_OFST                (0)
-
-//U3D_B2_PHYD_RXDET1
-#define RG_SSUSB_RXDET_PRB_SEL_OFST               (31)
-#define RG_SSUSB_FORCE_CMDET_OFST                 (30)
-#define RG_SSUSB_RXDET_EN_OFST                    (29)
-#define RG_SSUSB_FORCE_RXDET_EN_OFST              (28)
-#define RG_SSUSB_RXDET_K_TWICE_OFST               (27)
-#define RG_SSUSB_RXDET_STB3_SET_OFST              (18)
-#define RG_SSUSB_RXDET_STB2_SET_OFST              (9)
-#define RG_SSUSB_RXDET_STB1_SET_OFST              (0)
-
-//U3D_B2_PHYD_RXDET2
-#define RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN_OFST    (31)
-#define RG_SSUSB_PHYD_BERTLB_FORCE_CGEN_OFST      (30)
-#define RG_SSUSB_PHYD_T2RLB_FORCE_CGEN_OFST       (29)
-#define RG_SSUSB_PDN_T_SEL_OFST                   (18)
-#define RG_SSUSB_RXDET_STB3_SET_P3_OFST           (9)
-#define RG_SSUSB_RXDET_STB2_SET_P3_OFST           (0)
-
-//U3D_B2_PHYD_MISC0
-#define RG_SSUSB_FORCE_PLL_DDS_HF_EN_OFST         (22)
-#define RG_SSUSB_PLL_DDS_HF_EN_MAN_OFST           (21)
-#define RG_SSUSB_RXLFPS_ENTXDRV_OFST              (20)
-#define RG_SSUSB_RX_FL_UNLOCKTH_OFST              (16)
-#define RG_SSUSB_LFPS_PSEL_OFST                   (15)
-#define RG_SSUSB_RX_SIGDET_EN_OFST                (14)
-#define RG_SSUSB_RX_SIGDET_EN_SEL_OFST            (13)
-#define RG_SSUSB_RX_PI_CAL_EN_OFST                (12)
-#define RG_SSUSB_RX_PI_CAL_EN_SEL_OFST            (11)
-#define RG_SSUSB_P3_CLS_CK_SEL_OFST               (10)
-#define RG_SSUSB_T2RLB_PSEL_OFST                  (8)
-#define RG_SSUSB_PPCTL_PSEL_OFST                  (5)
-#define RG_SSUSB_PHYD_TX_DATA_INV_OFST            (4)
-#define RG_SSUSB_BERTLB_PSEL_OFST                 (2)
-#define RG_SSUSB_RETRACK_DIS_OFST                 (1)
-#define RG_SSUSB_PPERRCNT_CLR_OFST                (0)
-
-//U3D_B2_PHYD_MISC2
-#define RG_SSUSB_FRC_PLL_DDS_PREDIV2_OFST         (31)
-#define RG_SSUSB_FRC_PLL_DDS_IADJ_OFST            (27)
-#define RG_SSUSB_P_SIGDET_125FILTER_OFST          (26)
-#define RG_SSUSB_P_SIGDET_RST_FILTER_OFST         (25)
-#define RG_SSUSB_P_SIGDET_EID_USE_RAW_OFST        (24)
-#define RG_SSUSB_P_SIGDET_LTD_USE_RAW_OFST        (23)
-#define RG_SSUSB_EIDLE_BF_RXDET_OFST              (22)
-#define RG_SSUSB_EIDLE_LP_STBCYC_OFST             (13)
-#define RG_SSUSB_TX_EIDLE_LP_POSTDLY_OFST         (7)
-#define RG_SSUSB_TX_EIDLE_LP_PREDLY_OFST          (1)
-#define RG_SSUSB_TX_EIDLE_LP_EN_ADV_OFST          (0)
-
-//U3D_B2_PHYD_MISC3
-#define RGS_SSUSB_DDS_CALIB_C_STATE_OFST          (16)
-#define RGS_SSUSB_PPERRCNT_OFST                   (0)
-
-//U3D_B2_ROSC_0
-#define RG_SSUSB_RING_OSC_CNTEND_OFST             (23)
-#define RG_SSUSB_XTAL_OSC_CNTEND_OFST             (16)
-#define RG_SSUSB_RING_OSC_EN_OFST                 (3)
-#define RG_SSUSB_RING_OSC_FORCE_EN_OFST           (2)
-#define RG_SSUSB_FRC_RING_BYPASS_DET_OFST         (1)
-#define RG_SSUSB_RING_BYPASS_DET_OFST             (0)
-
-//U3D_B2_ROSC_1
-#define RG_SSUSB_RING_OSC_FRC_P3_OFST             (20)
-#define RG_SSUSB_RING_OSC_P3_OFST                 (19)
-#define RG_SSUSB_RING_OSC_FRC_RECAL_OFST          (17)
-#define RG_SSUSB_RING_OSC_RECAL_OFST              (16)
-#define RG_SSUSB_RING_OSC_SEL_OFST                (8)
-#define RG_SSUSB_RING_OSC_FRC_SEL_OFST            (0)
-
-//U3D_B2_ROSC_2
-#define RG_SSUSB_RING_DET_STRCYC2_OFST            (16)
-#define RG_SSUSB_RING_DET_STRCYC1_OFST            (0)
-
-//U3D_B2_ROSC_3
-#define RG_SSUSB_RING_DET_DETWIN1_OFST            (16)
-#define RG_SSUSB_RING_DET_STRCYC3_OFST            (0)
-
-//U3D_B2_ROSC_4
-#define RG_SSUSB_RING_DET_DETWIN3_OFST            (16)
-#define RG_SSUSB_RING_DET_DETWIN2_OFST            (0)
-
-//U3D_B2_ROSC_5
-#define RG_SSUSB_RING_DET_LBOND1_OFST             (16)
-#define RG_SSUSB_RING_DET_UBOND1_OFST             (0)
-
-//U3D_B2_ROSC_6
-#define RG_SSUSB_RING_DET_LBOND2_OFST             (16)
-#define RG_SSUSB_RING_DET_UBOND2_OFST             (0)
-
-//U3D_B2_ROSC_7
-#define RG_SSUSB_RING_DET_LBOND3_OFST             (16)
-#define RG_SSUSB_RING_DET_UBOND3_OFST             (0)
-
-//U3D_B2_ROSC_8
-#define RG_SSUSB_RING_RESERVE_OFST                (16)
-#define RG_SSUSB_ROSC_PROB_SEL_OFST               (2)
-#define RG_SSUSB_RING_FREQMETER_EN_OFST           (1)
-#define RG_SSUSB_RING_DET_BPS_UBOND_OFST          (0)
-
-//U3D_B2_ROSC_9
-#define RGS_FM_RING_CNT_OFST                      (16)
-#define RGS_SSUSB_RING_OSC_STATE_OFST             (10)
-#define RGS_SSUSB_RING_OSC_STABLE_OFST            (9)
-#define RGS_SSUSB_RING_OSC_CAL_FAIL_OFST          (8)
-#define RGS_SSUSB_RING_OSC_CAL_OFST               (0)
-
-//U3D_B2_ROSC_A
-#define RGS_SSUSB_ROSC_PROB_OUT_OFST              (0)
-
-//U3D_PHYD_VERSION
-#define RGS_SSUSB_PHYD_VERSION_OFST               (0)
-
-//U3D_PHYD_MODEL
-#define RGS_SSUSB_PHYD_MODEL_OFST                 (0)
-
-
-///////////////////////////////////////////////////////////////////////////////
-
-struct sifslv_chip_reg {
-       PHY_LE32 xtalbias;
-       PHY_LE32 syspll1;
-       PHY_LE32 gpio_ctla;
-       PHY_LE32 gpio_ctlb;
-       PHY_LE32 gpio_ctlc;
-};
-
-//U3D_GPIO_CTLA
-#define RG_C60802_GPIO_CTLA                       (0xffffffff<<0) //31:0
-
-//U3D_GPIO_CTLB
-#define RG_C60802_GPIO_CTLB                       (0xffffffff<<0) //31:0
-
-//U3D_GPIO_CTLC
-#define RG_C60802_GPIO_CTLC                       (0xffffffff<<0) //31:0
-
-/* OFFSET */
-
-//U3D_GPIO_CTLA
-#define RG_C60802_GPIO_CTLA_OFST                  (0)
-
-//U3D_GPIO_CTLB
-#define RG_C60802_GPIO_CTLB_OFST                  (0)
-
-//U3D_GPIO_CTLC
-#define RG_C60802_GPIO_CTLC_OFST                  (0)
-
-///////////////////////////////////////////////////////////////////////////////
-
-struct sifslv_fm_feg {
-       //0x0
-       PHY_LE32 fmcr0;
-       PHY_LE32 fmcr1;
-       PHY_LE32 fmcr2;
-       PHY_LE32 fmmonr0;
-       //0x10
-       PHY_LE32 fmmonr1;
-};
-
-//U3D_FMCR0
-#define RG_LOCKTH                                 (0xf<<28) //31:28
-#define RG_MONCLK_SEL                             (0x3<<26) //27:26
-#define RG_FM_MODE                                (0x1<<25) //25:25
-#define RG_FREQDET_EN                             (0x1<<24) //24:24
-#define RG_CYCLECNT                               (0xffffff<<0) //23:0
-
-//U3D_FMCR1
-#define RG_TARGET                                 (0xffffffff<<0) //31:0
-
-//U3D_FMCR2
-#define RG_OFFSET                                 (0xffffffff<<0) //31:0
-
-//U3D_FMMONR0
-#define USB_FM_OUT                                (0xffffffff<<0) //31:0
-
-//U3D_FMMONR1
-#define RG_MONCLK_SEL_3                           (0x1<<9) //9:9
-#define RG_FRCK_EN                                (0x1<<8) //8:8
-#define USBPLL_LOCK                               (0x1<<1) //1:1
-#define USB_FM_VLD                                (0x1<<0) //0:0
-
-
-/* OFFSET */
-
-//U3D_FMCR0
-#define RG_LOCKTH_OFST                            (28)
-#define RG_MONCLK_SEL_OFST                        (26)
-#define RG_FM_MODE_OFST                           (25)
-#define RG_FREQDET_EN_OFST                        (24)
-#define RG_CYCLECNT_OFST                          (0)
-
-//U3D_FMCR1
-#define RG_TARGET_OFST                            (0)
-
-//U3D_FMCR2
-#define RG_OFFSET_OFST                            (0)
-
-//U3D_FMMONR0
-#define USB_FM_OUT_OFST                           (0)
-
-//U3D_FMMONR1
-#define RG_MONCLK_SEL_3_OFST                      (9)
-#define RG_FRCK_EN_OFST                           (8)
-#define USBPLL_LOCK_OFST                          (1)
-#define USB_FM_VLD_OFST                           (0)
-
-
-///////////////////////////////////////////////////////////////////////////////
-
-PHY_INT32 phy_init(struct u3phy_info *info);
-PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
-PHY_INT32 eyescan_init(struct u3phy_info *info);
-PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
-               , PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
-PHY_INT32 u2_save_cur_en(struct u3phy_info *info);
-PHY_INT32 u2_save_cur_re(struct u3phy_info *info);
-PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info);
-
-#endif
-#endif
diff --git a/target/linux/ramips/files/drivers/usb/host/mtk-phy-ahb.c b/target/linux/ramips/files/drivers/usb/host/mtk-phy-ahb.c
deleted file mode 100644 (file)
index ebaf7c8..0000000
+++ /dev/null
@@ -1,58 +0,0 @@
-#include "mtk-phy.h"
-#ifdef CONFIG_U3D_HAL_SUPPORT
-#include "mu3d_hal_osal.h"
-#endif
-
-#ifdef CONFIG_U3_PHY_AHB_SUPPORT
-#include <linux/gfp.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-
-#ifndef CONFIG_U3D_HAL_SUPPORT
-#define os_writel(addr,data) {\
-               (*((volatile PHY_UINT32*)(addr)) = data);\
-       }
-#define os_readl(addr)  *((volatile PHY_UINT32*)(addr))
-#define os_writelmsk(addr, data, msk) \
-               { os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk)))); \
-       }
-#define os_setmsk(addr, msk) \
-       { os_writel(addr, os_readl(addr) | msk); \
-       }
-#define os_clrmsk(addr, msk) \
-   { os_writel(addr, os_readl(addr) &~ msk); \
-   }
-/*msk the data first, then umsk with the umsk.*/
-#define os_writelmskumsk(addr, data, msk, umsk) \
-{\
-   os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk))) & (umsk));\
-}
-
-#endif
-
-PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data)
-{
-       os_writel(addr, data);
-
-       return 0;
-}
-
-PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr)
-{
-       return os_readl(addr);
-}
-
-PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data)
-{
-       os_writelmsk(addr&0xfffffffc, data<<((addr%4)*8), 0xff<<((addr%4)*8));
-       
-       return 0;
-}
-
-PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr)
-{
-       return ((os_readl(addr)>>((addr%4)*8))&0xff);
-}
-
-#endif
-
diff --git a/target/linux/ramips/files/drivers/usb/host/mtk-phy.c b/target/linux/ramips/files/drivers/usb/host/mtk-phy.c
deleted file mode 100644 (file)
index 7ed8f01..0000000
+++ /dev/null
@@ -1,102 +0,0 @@
-#include <linux/gfp.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#define U3_PHY_LIB
-#include "mtk-phy.h"
-#ifdef CONFIG_PROJECT_7621
-#include "mtk-phy-7621.h"
-#endif
-#ifdef CONFIG_PROJECT_PHY
-static struct u3phy_operator project_operators = {
-       .init = phy_init,
-       .change_pipe_phase = phy_change_pipe_phase,
-       .eyescan_init = eyescan_init,
-       .eyescan = phy_eyescan,
-       .u2_slew_rate_calibration = u2_slew_rate_calibration,
-};
-#endif
-
-
-PHY_INT32 u3phy_init(){
-#ifndef CONFIG_PROJECT_PHY
-       PHY_INT32 u3phy_version;
-#endif
-       
-       if(u3phy != NULL){
-               return PHY_TRUE;
-       }
-
-       u3phy = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
-#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-       u3phy_p1 = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
-#endif
-#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
-       u3phy->phyd_version_addr = 0x2000e4;
-#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-       u3phy_p1->phyd_version_addr = 0x2000e4;
-#endif
-#else
-       u3phy->phyd_version_addr = U3_PHYD_B2_BASE + 0xe4;
-#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-       u3phy_p1->phyd_version_addr = U3_PHYD_B2_BASE_P1 + 0xe4;
-#endif
-#endif
-
-#ifdef CONFIG_PROJECT_PHY
-
-       u3phy->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE;
-       u3phy->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE;
-       u3phy->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE;
-       u3phy->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE;
-       u3phy->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE;
-       u3phy->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;           
-       u3phy->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;     
-       u3phy_ops = &project_operators;
-
-#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-       u3phy_p1->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE_P1;
-       u3phy_p1->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE_P1;
-       u3phy_p1->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE_P1;
-       u3phy_p1->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE_P1;
-       u3phy_p1->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE_P1;
-       u3phy_p1->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
-       u3phy_p1->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
-#endif
-#endif
-
-       return PHY_TRUE;
-}
-
-PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
-       PHY_INT8 cur_value;
-       PHY_INT8 new_value;
-
-       cur_value = U3PhyReadReg8(addr);
-       new_value = (cur_value & (~mask)) | (value << offset);
-       //udelay(i2cdelayus);
-       U3PhyWriteReg8(addr, new_value);
-       return PHY_TRUE;
-}
-
-PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
-       PHY_INT32 cur_value;
-       PHY_INT32 new_value;
-
-       cur_value = U3PhyReadReg32(addr);
-       new_value = (cur_value & (~mask)) | ((value << offset) & mask);
-       U3PhyWriteReg32(addr, new_value);
-       //DRV_MDELAY(100);
-
-       return PHY_TRUE;
-}
-
-PHY_INT32 U3PhyReadField8(PHY_INT32 addr,PHY_INT32 offset,PHY_INT32 mask){
-       
-       return ((U3PhyReadReg8(addr) & mask) >> offset);
-}
-
-PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask){
-
-       return ((U3PhyReadReg32(addr) & mask) >> offset);
-}
-
diff --git a/target/linux/ramips/files/drivers/usb/host/mtk-phy.h b/target/linux/ramips/files/drivers/usb/host/mtk-phy.h
deleted file mode 100644 (file)
index 07ed410..0000000
+++ /dev/null
@@ -1,179 +0,0 @@
-#ifndef __MTK_PHY_NEW_H
-#define __MTK_PHY_NEW_H
-
-//#define CONFIG_U3D_HAL_SUPPORT
-
-/* include system library */
-#include <linux/gfp.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-
-/* Choose PHY R/W implementation */
-//#define CONFIG_U3_PHY_GPIO_SUPPORT   //SW I2C implemented by GPIO
-#define CONFIG_U3_PHY_AHB_SUPPORT      //AHB, only on SoC
-
-/* Choose PHY version */
-//Select your project by defining one of the followings
-#define CONFIG_PROJECT_7621 //7621
-#define CONFIG_PROJECT_PHY
-
-/* BASE ADDRESS DEFINE, should define this on ASIC */
-#define PHY_BASE               0xBE1D0000
-#define SIFSLV_FM_FEG_BASE     (PHY_BASE+0x100)
-#define SIFSLV_CHIP_BASE       (PHY_BASE+0x700)
-#define U2_PHY_BASE            (PHY_BASE+0x800)
-#define U3_PHYD_BASE           (PHY_BASE+0x900)
-#define U3_PHYD_B2_BASE                (PHY_BASE+0xa00)
-#define U3_PHYA_BASE           (PHY_BASE+0xb00)
-#define U3_PHYA_DA_BASE                (PHY_BASE+0xc00)
-
-#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-#define SIFSLV_FM_FEG_BASE_P1  (PHY_BASE+0x100)
-#define SIFSLV_CHIP_BASE_P1    (PHY_BASE+0x700)
-#define U2_PHY_BASE_P1         (PHY_BASE+0x1000)
-#define U3_PHYD_BASE_P1                (PHY_BASE+0x1100)
-#define U3_PHYD_B2_BASE_P1     (PHY_BASE+0x1200)
-#define U3_PHYA_BASE_P1                (PHY_BASE+0x1300)
-#define U3_PHYA_DA_BASE_P1     (PHY_BASE+0x1400)
-#endif
-
-/*
-
-0x00000100     MODULE  ssusb_sifslv_fmreg      ssusb_sifslv_fmreg
-0x00000700     MODULE  ssusb_sifslv_ippc       ssusb_sifslv_ippc
-0x00000800     MODULE  ssusb_sifslv_u2phy_com  ssusb_sifslv_u2_phy_com_T28
-0x00000900     MODULE  ssusb_sifslv_u3phyd     ssusb_sifslv_u3phyd_T28
-0x00000a00     MODULE  ssusb_sifslv_u3phyd_bank2       ssusb_sifslv_u3phyd_bank2_T28
-0x00000b00     MODULE  ssusb_sifslv_u3phya     ssusb_sifslv_u3phya_T28
-0x00000c00     MODULE  ssusb_sifslv_u3phya_da  ssusb_sifslv_u3phya_da_T28
-*/
-
-
-/* TYPE DEFINE */
-typedef unsigned int   PHY_UINT32;
-typedef int                            PHY_INT32;
-typedef        unsigned short  PHY_UINT16;
-typedef short                  PHY_INT16;
-typedef unsigned char  PHY_UINT8;
-typedef char                   PHY_INT8;
-
-typedef PHY_UINT32 __bitwise   PHY_LE32;
-
-/* CONSTANT DEFINE */
-#define PHY_FALSE      0
-#define PHY_TRUE       1
-
-/* MACRO DEFINE */
-#define DRV_WriteReg32(addr,data)       ((*(volatile PHY_UINT32 *)(addr)) = (unsigned long)(data))
-#define DRV_Reg32(addr)                 (*(volatile PHY_UINT32 *)(addr))
-
-#define DRV_MDELAY     mdelay
-#define DRV_MSLEEP     msleep
-#define DRV_UDELAY     udelay
-#define DRV_USLEEP     usleep
-
-/* PHY FUNCTION DEFINE, implemented in platform files, ex. ahb, gpio */
-PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data);
-PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr);
-PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data);
-PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr);
-
-/* PHY GENERAL USAGE FUNC, implemented in mtk-phy.c */
-PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
-PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
-PHY_INT32 U3PhyReadField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
-PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
-
-struct u3phy_info {
-       PHY_INT32 phy_version;
-       PHY_INT32 phyd_version_addr;
-       
-#ifdef CONFIG_PROJECT_PHY      
-       struct u2phy_reg *u2phy_regs;
-       struct u3phya_reg *u3phya_regs;
-       struct u3phya_da_reg *u3phya_da_regs;
-       struct u3phyd_reg *u3phyd_regs;
-       struct u3phyd_bank2_reg *u3phyd_bank2_regs;
-       struct sifslv_chip_reg *sifslv_chip_regs;       
-       struct sifslv_fm_feg *sifslv_fm_regs;   
-#endif
-};
-
-struct u3phy_operator {
-       PHY_INT32 (*init) (struct u3phy_info *info);
-       PHY_INT32 (*change_pipe_phase) (struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
-       PHY_INT32 (*eyescan_init) (struct u3phy_info *info);
-       PHY_INT32 (*eyescan) (struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y, PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
-       PHY_INT32 (*u2_save_current_entry) (struct u3phy_info *info);
-       PHY_INT32 (*u2_save_current_recovery) (struct u3phy_info *info);
-       PHY_INT32 (*u2_slew_rate_calibration) (struct u3phy_info *info);
-};
-
-#ifdef U3_PHY_LIB
-#define AUTOEXT
-#else
-#define AUTOEXT extern
-#endif
-
-AUTOEXT struct u3phy_info *u3phy;
-AUTOEXT struct u3phy_info *u3phy_p1;
-AUTOEXT struct u3phy_operator *u3phy_ops;
-
-/*********eye scan required*********/
-
-#define LO_BYTE(x)                   ((PHY_UINT8)((x) & 0xFF))
-#define HI_BYTE(x)                   ((PHY_UINT8)(((x) & 0xFF00) >> 8))
-
-typedef enum
-{
-  SCAN_UP,
-  SCAN_DN
-} enumScanDir;
-
-struct strucScanRegion
-{
-  PHY_INT8 bX_tl;
-  PHY_INT8 bY_tl;
-  PHY_INT8 bX_br;
-  PHY_INT8 bY_br;
-  PHY_INT8 bDeltaX;
-  PHY_INT8 bDeltaY;
-};
-
-struct strucTestCycle
-{
-  PHY_UINT16 wEyeCnt;
-  PHY_INT8 bNumOfEyeCnt;
-  PHY_INT8 bPICalEn;
-  PHY_INT8 bNumOfIgnoreCnt;
-};
-
-#define ERRCNT_MAX             128
-#define CYCLE_COUNT_MAX        15
-
-/// the map resolution is 128 x 128 pts
-#define MAX_X                 127
-#define MAX_Y                 127
-#define MIN_X                 0
-#define MIN_Y                 0
-
-PHY_INT32 u3phy_init(void);
-
-AUTOEXT struct strucScanRegion           _rEye1;
-AUTOEXT struct strucScanRegion           _rEye2;
-AUTOEXT struct strucTestCycle            _rTestCycle;
-AUTOEXT PHY_UINT8                      _bXcurr;
-AUTOEXT PHY_UINT8                      _bYcurr;
-AUTOEXT enumScanDir               _eScanDir;
-AUTOEXT PHY_INT8                      _fgXChged;
-AUTOEXT PHY_INT8                      _bPIResult;
-/* use local variable instead to save memory use */
-#if 0
-AUTOEXT PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
-AUTOEXT PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
-#endif
-
-/***********************************/
-#endif
-
diff --git a/target/linux/ramips/files/drivers/usb/host/xhci-mtk-power.c b/target/linux/ramips/files/drivers/usb/host/xhci-mtk-power.c
deleted file mode 100644 (file)
index 9d93526..0000000
+++ /dev/null
@@ -1,115 +0,0 @@
-#include "xhci-mtk.h"
-#include "xhci-mtk-power.h"
-#include "xhci.h"
-#include <linux/kernel.h>       /* printk() */
-#include <linux/slab.h>
-#include <linux/delay.h>
-
-static int g_num_u3_port;
-static int g_num_u2_port;
-
-
-void enableXhciAllPortPower(struct xhci_hcd *xhci){
-       int i;
-       u32 port_id, temp;
-       u32 __iomem *addr;
-
-       g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
-       g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
-       
-       for(i=1; i<=g_num_u3_port; i++){
-               port_id=i;
-               addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
-               temp = xhci_readl(xhci, addr);
-               temp = xhci_port_state_to_neutral(temp);
-               temp |= PORT_POWER;
-               xhci_writel(xhci, temp, addr);
-       }
-       for(i=1; i<=g_num_u2_port; i++){
-               port_id=i+g_num_u3_port;
-               addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
-               temp = xhci_readl(xhci, addr);
-               temp = xhci_port_state_to_neutral(temp);
-               temp |= PORT_POWER;
-               xhci_writel(xhci, temp, addr);
-       }
-}
-
-void enableAllClockPower(){
-
-       int i;
-       u32 temp;
-
-       g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
-       g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
-
-       //2.    Enable xHC
-       writel(readl(SSUSB_IP_PW_CTRL) | (SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
-       writel(readl(SSUSB_IP_PW_CTRL) & (~SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
-       writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
-       
-       //1.    Enable target ports 
-       for(i=0; i<g_num_u3_port; i++){
-               temp = readl(SSUSB_U3_CTRL(i));
-               temp = temp & (~SSUSB_U3_PORT_PDN) & (~SSUSB_U3_PORT_DIS);
-               writel(temp, SSUSB_U3_CTRL(i));
-       }
-       for(i=0; i<g_num_u2_port; i++){
-               temp = readl(SSUSB_U2_CTRL(i));
-               temp = temp & (~SSUSB_U2_PORT_PDN) & (~SSUSB_U2_PORT_DIS);
-               writel(temp, SSUSB_U2_CTRL(i));
-       }
-       msleep(100);
-}
-
-
-//(X)disable clock/power of a port 
-//(X)if all ports are disabled, disable IP ctrl power
-//disable all ports and IP clock/power, this is just mention HW that the power/clock of port 
-//and IP could be disable if suspended.
-//If doesn't not disable all ports at first, the IP clock/power will never be disabled
-//(some U2 and U3 ports are binded to the same connection, that is, they will never enter suspend at the same time
-//port_index: port number
-//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
-void disablePortClockPower(void){
-       int i;
-       u32 temp;
-
-       g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
-       g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
-       
-       for(i=0; i<g_num_u3_port; i++){
-               temp = readl(SSUSB_U3_CTRL(i));
-               temp = temp | (SSUSB_U3_PORT_PDN);
-               writel(temp, SSUSB_U3_CTRL(i));
-       }
-       for(i=0; i<g_num_u2_port; i++){
-               temp = readl(SSUSB_U2_CTRL(i));
-               temp = temp | (SSUSB_U2_PORT_PDN);
-               writel(temp, SSUSB_U2_CTRL(i));
-       }
-       writel(readl(SSUSB_IP_PW_CTRL_1) | (SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
-}
-
-//if IP ctrl power is disabled, enable it
-//enable clock/power of a port
-//port_index: port number
-//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
-void enablePortClockPower(int port_index, int port_rev){
-       int i;
-       u32 temp;
-       
-       writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
-
-       if(port_rev == 0x3){
-               temp = readl(SSUSB_U3_CTRL(port_index));
-               temp = temp & (~SSUSB_U3_PORT_PDN);
-               writel(temp, SSUSB_U3_CTRL(port_index));
-       }
-       else if(port_rev == 0x2){
-               temp = readl(SSUSB_U2_CTRL(port_index));
-               temp = temp & (~SSUSB_U2_PORT_PDN);
-               writel(temp, SSUSB_U2_CTRL(port_index));
-       }
-}
-
diff --git a/target/linux/ramips/files/drivers/usb/host/xhci-mtk-power.h b/target/linux/ramips/files/drivers/usb/host/xhci-mtk-power.h
deleted file mode 100644 (file)
index e57c243..0000000
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _XHCI_MTK_POWER_H
-#define _XHCI_MTK_POWER_H
-
-#include <linux/usb.h>
-#include "xhci.h"
-#include "xhci-mtk.h"
-
-void enableXhciAllPortPower(struct xhci_hcd *xhci);
-void enableAllClockPower(void);
-void disablePortClockPower(void);
-void enablePortClockPower(int port_index, int port_rev);
-
-#endif
diff --git a/target/linux/ramips/files/drivers/usb/host/xhci-mtk-scheduler.c b/target/linux/ramips/files/drivers/usb/host/xhci-mtk-scheduler.c
deleted file mode 100644 (file)
index bf6a8bd..0000000
+++ /dev/null
@@ -1,608 +0,0 @@
-#include "xhci-mtk-scheduler.h"
-#include <linux/kernel.h>       /* printk() */
-
-static struct sch_ep **ss_out_eps[MAX_EP_NUM];
-static struct sch_ep **ss_in_eps[MAX_EP_NUM];
-static struct sch_ep **hs_eps[MAX_EP_NUM];     //including tt isoc
-static struct sch_ep **tt_intr_eps[MAX_EP_NUM];
-
-
-int mtk_xhci_scheduler_init(void){
-       int i;
-
-       for(i=0; i<MAX_EP_NUM; i++){
-               ss_out_eps[i] = NULL;
-       }
-       for(i=0; i<MAX_EP_NUM; i++){
-               ss_in_eps[i] = NULL;
-       }
-       for(i=0; i<MAX_EP_NUM; i++){
-               hs_eps[i] = NULL;
-       }
-       for(i=0; i<MAX_EP_NUM; i++){
-               tt_intr_eps[i] = NULL;
-       }
-       return 0;
-}
-
-int add_sch_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
-       , int mult, int offset, int repeat, int pkts, int cs_count, int burst_mode
-       , int bw_cost, mtk_u32 *ep, struct sch_ep *tmp_ep){
-
-       struct sch_ep **ep_array;
-       int i;
-
-       if(is_in && dev_speed == USB_SPEED_SUPER ){
-               ep_array = (struct sch_ep **)ss_in_eps;
-       }
-       else if(dev_speed == USB_SPEED_SUPER){
-               ep_array = (struct sch_ep **)ss_out_eps;
-       }
-       else if(dev_speed == USB_SPEED_HIGH || (isTT && ep_type == USB_EP_ISOC)){
-               ep_array = (struct sch_ep **)hs_eps;
-       }
-       else{
-               ep_array = (struct sch_ep **)tt_intr_eps;
-       }
-       for(i=0; i<MAX_EP_NUM; i++){
-               if(ep_array[i] == NULL){
-                       tmp_ep->dev_speed = dev_speed;
-                       tmp_ep->isTT = isTT;
-                       tmp_ep->is_in = is_in;
-                       tmp_ep->ep_type = ep_type;
-                       tmp_ep->maxp = maxp;
-                       tmp_ep->interval = interval;
-                       tmp_ep->burst = burst;
-                       tmp_ep->mult = mult;
-                       tmp_ep->offset = offset;
-                       tmp_ep->repeat = repeat;
-                       tmp_ep->pkts = pkts;
-                       tmp_ep->cs_count = cs_count;
-                       tmp_ep->burst_mode = burst_mode;
-                       tmp_ep->bw_cost = bw_cost;
-                       tmp_ep->ep = ep;
-                       ep_array[i] = tmp_ep;
-                       return SCH_SUCCESS;
-               }
-       }
-       return SCH_FAIL;
-}
-
-int count_ss_bw(int is_in, int ep_type, int maxp, int interval, int burst, int mult, int offset, int repeat
-       , int td_size){
-       int i, j, k;
-       int bw_required[3];
-       int final_bw_required;
-       int bw_required_per_repeat;
-       int tmp_bw_required;
-       struct sch_ep *cur_sch_ep;
-       struct sch_ep **ep_array;
-       int cur_offset;
-       int cur_ep_offset;
-       int tmp_offset;
-       int tmp_interval;
-       int ep_offset;
-       int ep_interval;
-       int ep_repeat;
-       int ep_mult;
-       
-       if(is_in){
-               ep_array = (struct sch_ep **)ss_in_eps;
-       }
-       else{
-               ep_array = (struct sch_ep **)ss_out_eps;
-       }
-       
-       bw_required[0] = 0;
-       bw_required[1] = 0;
-       bw_required[2] = 0;
-       
-       if(repeat == 0){
-               final_bw_required = 0;
-               for(i=0; i<MAX_EP_NUM; i++){
-                       cur_sch_ep = ep_array[i];
-                       if(cur_sch_ep == NULL){
-                               continue;
-                       }
-                       ep_interval = cur_sch_ep->interval;
-                       ep_offset = cur_sch_ep->offset;
-                       if(cur_sch_ep->repeat == 0){
-                               if(ep_interval >= interval){
-                                       tmp_offset = ep_offset + ep_interval - offset;
-                                       tmp_interval = interval;
-                               }
-                               else{
-                                       tmp_offset = offset + interval - ep_offset;
-                                       tmp_interval = ep_interval;
-                               }
-                               if(tmp_offset % tmp_interval == 0){
-                                       final_bw_required += cur_sch_ep->bw_cost;
-                               }
-                       }
-                       else{
-                               ep_repeat = cur_sch_ep->repeat;
-                               ep_mult = cur_sch_ep->mult;
-                               for(k=0; k<=ep_mult; k++){
-                                       cur_ep_offset = ep_offset+(k*ep_mult);
-                                       if(ep_interval >= interval){
-                                               tmp_offset = cur_ep_offset + ep_interval - offset;
-                                               tmp_interval = interval;
-                                       }
-                                       else{
-                                               tmp_offset = offset + interval - cur_ep_offset;
-                                               tmp_interval = ep_interval;
-                                       }
-                                       if(tmp_offset % tmp_interval == 0){
-                                               final_bw_required += cur_sch_ep->bw_cost;
-                                               break;
-                                       }
-                               }
-                       }
-               }
-               final_bw_required += td_size;
-       }
-       else{
-               bw_required_per_repeat = maxp * (burst+1);
-               for(j=0; j<=mult; j++){
-                       tmp_bw_required = 0;
-                       cur_offset = offset+(j*repeat);
-                       for(i=0; i<MAX_EP_NUM; i++){
-                               cur_sch_ep = ep_array[i];
-                               if(cur_sch_ep == NULL){
-                                       continue;
-                               }
-                               ep_interval = cur_sch_ep->interval;
-                               ep_offset = cur_sch_ep->offset;
-                               if(cur_sch_ep->repeat == 0){
-                                       if(ep_interval >= interval){
-                                               tmp_offset = ep_offset + ep_interval - cur_offset;
-                                               tmp_interval = interval;
-                                       }
-                                       else{
-                                               tmp_offset = cur_offset + interval - ep_offset;
-                                               tmp_interval = ep_interval;
-                                       }
-                                       if(tmp_offset % tmp_interval == 0){
-                                               tmp_bw_required += cur_sch_ep->bw_cost;
-                                       }
-                               }
-                               else{
-                                       ep_repeat = cur_sch_ep->repeat;
-                                       ep_mult = cur_sch_ep->mult;
-                                       for(k=0; k<=ep_mult; k++){
-                                               cur_ep_offset = ep_offset+(k*ep_repeat);
-                                               if(ep_interval >= interval){
-                                                       tmp_offset = cur_ep_offset + ep_interval - cur_offset;
-                                                       tmp_interval = interval;
-                                               }
-                                               else{
-                                                       tmp_offset = cur_offset + interval - cur_ep_offset;
-                                                       tmp_interval = ep_interval;
-                                               }
-                                               if(tmp_offset % tmp_interval == 0){
-                                                       tmp_bw_required += cur_sch_ep->bw_cost;
-                                                       break;
-                                               }
-                                       }
-                               }
-                       }
-                       bw_required[j] = tmp_bw_required;
-               }
-               final_bw_required = SS_BW_BOUND;
-               for(j=0; j<=mult; j++){
-                       if(bw_required[j] < final_bw_required){
-                               final_bw_required = bw_required[j];
-                       }
-               }
-               final_bw_required += bw_required_per_repeat;
-       }
-       return final_bw_required;
-}
-
-int count_hs_bw(int ep_type, int maxp, int interval, int offset, int td_size){
-       int i;
-       int bw_required;
-       struct sch_ep *cur_sch_ep;
-       int tmp_offset;
-       int tmp_interval;
-       int ep_offset;
-       int ep_interval;
-       int cur_tt_isoc_interval;       //for isoc tt check
-       
-       bw_required = 0;
-       for(i=0; i<MAX_EP_NUM; i++){
-               
-               cur_sch_ep = (struct sch_ep *)hs_eps[i];
-               if(cur_sch_ep == NULL){
-                               continue;
-               }
-               ep_offset = cur_sch_ep->offset;
-               ep_interval = cur_sch_ep->interval;
-               
-               if(cur_sch_ep->isTT && cur_sch_ep->ep_type == USB_EP_ISOC){
-                       cur_tt_isoc_interval = ep_interval<<3;
-                       if(ep_interval >= interval){
-                               tmp_offset = ep_offset + cur_tt_isoc_interval - offset;
-                               tmp_interval = interval;
-                       }
-                       else{
-                               tmp_offset = offset + interval - ep_offset;
-                               tmp_interval = cur_tt_isoc_interval;
-                       }
-                       if(cur_sch_ep->is_in){
-                               if((tmp_offset%tmp_interval >=2) && (tmp_offset%tmp_interval <= cur_sch_ep->cs_count)){
-                                       bw_required += 188;
-                               }
-                       }
-                       else{
-                               if(tmp_offset%tmp_interval <= cur_sch_ep->cs_count){
-                                       bw_required += 188;
-                               }
-                       }
-               }
-               else{
-                       if(ep_interval >= interval){
-                               tmp_offset = ep_offset + ep_interval - offset;
-                               tmp_interval = interval;
-                       }
-                       else{
-                               tmp_offset = offset + interval - ep_offset;
-                               tmp_interval = ep_interval;
-                       }
-                       if(tmp_offset%tmp_interval == 0){
-                               bw_required += cur_sch_ep->bw_cost;
-                       }
-               }
-       }
-       bw_required += td_size;
-       return bw_required;
-}
-
-int count_tt_isoc_bw(int is_in, int maxp, int interval, int offset, int td_size){
-       char is_cs;
-       int mframe_idx, frame_idx, s_frame, s_mframe, cur_mframe;
-       int bw_required, max_bw;
-       int ss_cs_count;
-       int cs_mframe;
-       int max_frame;
-       int i,j;
-       struct sch_ep *cur_sch_ep;
-       int ep_offset;
-       int ep_interval;
-       int ep_cs_count;
-       int tt_isoc_interval;   //for isoc tt check
-       int cur_tt_isoc_interval;       //for isoc tt check
-       int tmp_offset;
-       int tmp_interval;
-       
-       is_cs = 0;
-       
-       tt_isoc_interval = interval<<3; //frame to mframe
-       if(is_in){
-               is_cs = 1;
-       }
-       s_frame = offset/8;
-       s_mframe = offset%8;
-       ss_cs_count = (maxp + (188 - 1))/188;
-       if(is_cs){
-               cs_mframe = offset%8 + 2 + ss_cs_count;
-               if (cs_mframe <= 6)
-                       ss_cs_count += 2;
-               else if (cs_mframe == 7)
-                       ss_cs_count++;
-               else if (cs_mframe > 8)
-                       return -1;
-       }
-       max_bw = 0;
-       if(is_in){
-               i=2;
-       }
-       for(cur_mframe = offset+i; i<ss_cs_count; cur_mframe++, i++){
-               bw_required = 0;
-               for(j=0; j<MAX_EP_NUM; j++){
-                       cur_sch_ep = (struct sch_ep *)hs_eps[j];
-                       if(cur_sch_ep == NULL){
-                               continue;
-                       }
-                       ep_offset = cur_sch_ep->offset;
-                       ep_interval = cur_sch_ep->interval;
-                       if(cur_sch_ep->isTT && cur_sch_ep->ep_type == USB_EP_ISOC){
-                               //isoc tt
-                               //check if mframe offset overlap
-                               //if overlap, add 188 to the bw
-                               cur_tt_isoc_interval = ep_interval<<3;
-                               if(cur_tt_isoc_interval >= tt_isoc_interval){
-                                       tmp_offset = (ep_offset+cur_tt_isoc_interval)  - cur_mframe;
-                                       tmp_interval = tt_isoc_interval;
-                               }
-                               else{
-                                       tmp_offset = (cur_mframe+tt_isoc_interval) - ep_offset;
-                                       tmp_interval = cur_tt_isoc_interval;
-                               }
-                               if(cur_sch_ep->is_in){
-                                       if((tmp_offset%tmp_interval >=2) && (tmp_offset%tmp_interval <= cur_sch_ep->cs_count)){
-                                               bw_required += 188;
-                                       }
-                               }
-                               else{
-                                       if(tmp_offset%tmp_interval <= cur_sch_ep->cs_count){
-                                               bw_required += 188;
-                                       }
-                               }
-                               
-                       }
-                       else if(cur_sch_ep->ep_type == USB_EP_INT || cur_sch_ep->ep_type == USB_EP_ISOC){
-                               //check if mframe
-                               if(ep_interval >= tt_isoc_interval){
-                                       tmp_offset = (ep_offset+ep_interval) - cur_mframe;
-                                       tmp_interval = tt_isoc_interval;
-                               }
-                               else{
-                                       tmp_offset = (cur_mframe+tt_isoc_interval) - ep_offset;
-                                       tmp_interval = ep_interval;
-                               }
-                               if(tmp_offset%tmp_interval == 0){
-                                       bw_required += cur_sch_ep->bw_cost;
-                               }
-                       }
-               }
-               bw_required += 188;
-               if(bw_required > max_bw){
-                       max_bw = bw_required;
-               }
-       }
-       return max_bw;
-}
-
-int count_tt_intr_bw(int interval, int frame_offset){
-       //check all eps in tt_intr_eps
-       int ret;
-       int i,j;
-       int ep_offset;
-       int ep_interval;
-       int tmp_offset;
-       int tmp_interval;
-       ret = SCH_SUCCESS;
-       struct sch_ep *cur_sch_ep;
-       
-       for(i=0; i<MAX_EP_NUM; i++){
-               cur_sch_ep = (struct sch_ep *)tt_intr_eps[i];
-               if(cur_sch_ep == NULL){
-                       continue;
-               }
-               ep_offset = cur_sch_ep->offset;
-               ep_interval = cur_sch_ep->interval;
-               if(ep_interval  >= interval){
-                       tmp_offset = ep_offset + ep_interval - frame_offset;
-                       tmp_interval = interval;
-               }
-               else{
-                       tmp_offset = frame_offset + interval - ep_offset;
-                       tmp_interval = ep_interval;
-               }
-               
-               if(tmp_offset%tmp_interval==0){
-                       return SCH_FAIL;
-               }
-       }
-       return SCH_SUCCESS;
-}
-
-struct sch_ep * mtk_xhci_scheduler_remove_ep(int dev_speed, int is_in, int isTT, int ep_type, mtk_u32 *ep){
-       int i;
-       struct sch_ep **ep_array;
-       struct sch_ep *cur_ep;
-
-       if (is_in && dev_speed == USB_SPEED_SUPER) {
-               ep_array = (struct sch_ep **)ss_in_eps;
-       }
-       else if (dev_speed == USB_SPEED_SUPER) {
-               ep_array = (struct sch_ep **)ss_out_eps;
-       }
-       else if (dev_speed == USB_SPEED_HIGH || (isTT && ep_type == USB_EP_ISOC)) {
-               ep_array = (struct sch_ep **)hs_eps;
-       }
-       else {
-               ep_array = (struct sch_ep **)tt_intr_eps;
-       }
-       for (i = 0; i < MAX_EP_NUM; i++) {
-               cur_ep = (struct sch_ep *)ep_array[i];
-               if(cur_ep != NULL && cur_ep->ep == ep){
-                       ep_array[i] = NULL;
-                       return cur_ep;
-               }
-       }
-       return NULL;
-}
-
-int mtk_xhci_scheduler_add_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
-       , int mult, mtk_u32 *ep, mtk_u32 *ep_ctx, struct sch_ep *sch_ep){
-       mtk_u32 bPkts = 0;
-       mtk_u32 bCsCount = 0;
-       mtk_u32 bBm = 1;
-       mtk_u32 bOffset = 0;
-       mtk_u32 bRepeat = 0;
-       int ret;
-       struct mtk_xhci_ep_ctx *temp_ep_ctx;
-       int td_size;
-       int mframe_idx, frame_idx;
-       int bw_cost;
-       int cur_bw, best_bw, best_bw_idx,repeat, max_repeat, best_bw_repeat;
-       int cur_offset, cs_mframe;
-       int break_out;
-       int frame_interval;
-
-       printk(KERN_ERR "add_ep parameters, dev_speed %d, is_in %d, isTT %d, ep_type %d, maxp %d, interval %d, burst %d, mult %d, ep 0x%x, ep_ctx 0x%x, sch_ep 0x%x\n", dev_speed, is_in, isTT, ep_type, maxp
-               , interval, burst, mult, ep, ep_ctx, sch_ep);
-       if(isTT && ep_type == USB_EP_INT && ((dev_speed == USB_SPEED_LOW) || (dev_speed == USB_SPEED_FULL))){
-               frame_interval = interval >> 3;
-               for(frame_idx=0; frame_idx<frame_interval; frame_idx++){
-                       printk(KERN_ERR "check tt_intr_bw interval %d, frame_idx %d\n", frame_interval, frame_idx);
-                       if(count_tt_intr_bw(frame_interval, frame_idx) == SCH_SUCCESS){
-                               printk(KERN_ERR "check OK............\n");
-                               bOffset = frame_idx<<3;
-                               bPkts = 1;
-                               bCsCount = 3;
-                               bw_cost = maxp;
-                               bRepeat = 0;
-                               if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, frame_interval, burst, mult
-                                       , bOffset, bRepeat, bPkts, bCsCount, bBm, maxp, ep, sch_ep) == SCH_FAIL){
-                                       return SCH_FAIL;
-                               }
-                               ret = SCH_SUCCESS;
-                               break;
-                       }
-               }
-       }
-       else if(isTT && ep_type == USB_EP_ISOC){
-               best_bw = HS_BW_BOUND;
-               best_bw_idx = -1;
-               cur_bw = 0;
-               td_size = maxp;
-               break_out = 0;
-               frame_interval = interval>>3;
-               for(frame_idx=0; frame_idx<frame_interval && !break_out; frame_idx++){
-                       for(mframe_idx=0; mframe_idx<8; mframe_idx++){
-                               cur_offset = (frame_idx*8) + mframe_idx;
-                               cur_bw = count_tt_isoc_bw(is_in, maxp, frame_interval, cur_offset, td_size);
-                               if(cur_bw > 0 && cur_bw < best_bw){
-                                       best_bw_idx = cur_offset;
-                                       best_bw = cur_bw;
-                                       if(cur_bw == td_size || cur_bw < (HS_BW_BOUND>>1)){
-                                               break_out = 1;
-                                               break;
-                                       }
-                               }
-                       }
-               }
-               if(best_bw_idx == -1){
-                       return SCH_FAIL;
-               }
-               else{
-                       bOffset = best_bw_idx;
-                       bPkts = 1;
-                       bCsCount = (maxp + (188 - 1)) / 188;
-                       if(is_in){
-                               cs_mframe = bOffset%8 + 2 + bCsCount;
-                               if (cs_mframe <= 6)
-                                       bCsCount += 2;
-                               else if (cs_mframe == 7)
-                                       bCsCount++;
-                       }
-                       bw_cost = 188;
-                       bRepeat = 0;
-                       if(add_sch_ep( dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
-                               , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
-                               return SCH_FAIL;
-                       }
-                       ret = SCH_SUCCESS;
-               }
-       }
-       else if((dev_speed == USB_SPEED_FULL || dev_speed == USB_SPEED_LOW) && ep_type == USB_EP_INT){
-               bPkts = 1;
-               ret = SCH_SUCCESS;
-       }
-       else if(dev_speed == USB_SPEED_FULL && ep_type == USB_EP_ISOC){
-               bPkts = 1;
-               ret = SCH_SUCCESS;
-       }
-       else if(dev_speed == USB_SPEED_HIGH && (ep_type == USB_EP_INT || ep_type == USB_EP_ISOC)){
-               best_bw = HS_BW_BOUND;
-               best_bw_idx = -1;
-               cur_bw = 0;
-               td_size = maxp*(burst+1);
-               for(cur_offset = 0; cur_offset<interval; cur_offset++){
-                       cur_bw = count_hs_bw(ep_type, maxp, interval, cur_offset, td_size);
-                       if(cur_bw > 0 && cur_bw < best_bw){
-                               best_bw_idx = cur_offset;
-                               best_bw = cur_bw;
-                               if(cur_bw == td_size || cur_bw < (HS_BW_BOUND>>1)){
-                                       break;
-                               }
-                       }
-               }
-               if(best_bw_idx == -1){
-                       return SCH_FAIL;
-               }
-               else{
-                       bOffset = best_bw_idx;
-                       bPkts = burst + 1;
-                       bCsCount = 0;
-                       bw_cost = td_size;
-                       bRepeat = 0;
-                       if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
-                               , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
-                               return SCH_FAIL;
-                       }
-                       ret = SCH_SUCCESS;
-               }
-       }
-       else if(dev_speed == USB_SPEED_SUPER && (ep_type == USB_EP_INT || ep_type == USB_EP_ISOC)){
-               best_bw = SS_BW_BOUND;
-               best_bw_idx = -1;
-               cur_bw = 0;
-               td_size = maxp * (mult+1) * (burst+1);
-               if(mult == 0){
-                       max_repeat = 0;
-               }
-               else{
-                       max_repeat = (interval-1)/(mult+1);
-               }
-               break_out = 0;
-               for(frame_idx = 0; (frame_idx < interval) && !break_out; frame_idx++){
-                       for(repeat = max_repeat; repeat >= 0; repeat--){
-                               cur_bw = count_ss_bw(is_in, ep_type, maxp, interval, burst, mult, frame_idx
-                                       , repeat, td_size);
-                               printk(KERN_ERR "count_ss_bw, frame_idx %d, repeat %d, td_size %d, result bw %d\n"
-                                       , frame_idx, repeat, td_size, cur_bw);
-                               if(cur_bw > 0 && cur_bw < best_bw){
-                                       best_bw_idx = frame_idx;
-                                       best_bw_repeat = repeat;
-                                       best_bw = cur_bw;
-                                       if(cur_bw <= td_size || cur_bw < (HS_BW_BOUND>>1)){
-                                               break_out = 1;
-                                               break;
-                                       }
-                               }
-                       }
-               }
-               printk(KERN_ERR "final best idx %d, best repeat %d\n", best_bw_idx, best_bw_repeat);
-               if(best_bw_idx == -1){
-                       return SCH_FAIL;
-               }
-               else{
-                       bOffset = best_bw_idx;
-                       bCsCount = 0;
-                       bRepeat = best_bw_repeat;
-                       if(bRepeat == 0){
-                               bw_cost = (burst+1)*(mult+1)*maxp;
-                               bPkts = (burst+1)*(mult+1);
-                       }
-                       else{
-                               bw_cost = (burst+1)*maxp;
-                               bPkts = (burst+1);
-                       }
-                       if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
-                               , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
-                               return SCH_FAIL;
-                       }
-                       ret = SCH_SUCCESS;
-               }
-       }
-       else{
-               bPkts = 1;
-               ret = SCH_SUCCESS;
-       }
-       if(ret == SCH_SUCCESS){
-               temp_ep_ctx = (struct mtk_xhci_ep_ctx *)ep_ctx;
-               temp_ep_ctx->reserved[0] |= (BPKTS(bPkts) | BCSCOUNT(bCsCount) | BBM(bBm));
-               temp_ep_ctx->reserved[1] |= (BOFFSET(bOffset) | BREPEAT(bRepeat));
-
-               printk(KERN_DEBUG "[DBG] BPKTS: %x, BCSCOUNT: %x, BBM: %x\n", bPkts, bCsCount, bBm);
-               printk(KERN_DEBUG "[DBG] BOFFSET: %x, BREPEAT: %x\n", bOffset, bRepeat);
-               return SCH_SUCCESS;
-       }
-       else{
-               return SCH_FAIL;
-       }
-}
diff --git a/target/linux/ramips/files/drivers/usb/host/xhci-mtk-scheduler.h b/target/linux/ramips/files/drivers/usb/host/xhci-mtk-scheduler.h
deleted file mode 100644 (file)
index c55dfb1..0000000
+++ /dev/null
@@ -1,77 +0,0 @@
-#ifndef _XHCI_MTK_SCHEDULER_H
-#define _XHCI_MTK_SCHEDULER_H
-
-#define MTK_SCH_NEW            1
-
-#define SCH_SUCCESS            1
-#define SCH_FAIL               0
-
-#define MAX_EP_NUM             64
-#define SS_BW_BOUND            51000
-#define HS_BW_BOUND            6144
-
-#define USB_EP_CONTROL         0
-#define USB_EP_ISOC            1
-#define USB_EP_BULK            2
-#define USB_EP_INT             3
-
-#define USB_SPEED_LOW          1
-#define USB_SPEED_FULL         2
-#define USB_SPEED_HIGH         3
-#define USB_SPEED_SUPER                5
-
-/* mtk scheduler bitmasks */
-#define BPKTS(p)               ((p) & 0x3f)
-#define BCSCOUNT(p)            (((p) & 0x7) << 8)
-#define BBM(p)                 ((p) << 11)
-#define BOFFSET(p)             ((p) & 0x3fff)
-#define BREPEAT(p)             (((p) & 0x7fff) << 16)
-
-
-#if 1
-typedef unsigned int mtk_u32;
-typedef unsigned long long mtk_u64;
-#endif
-
-#define NULL ((void *)0)
-
-struct mtk_xhci_ep_ctx {
-       mtk_u32 ep_info;
-       mtk_u32 ep_info2;
-       mtk_u64 deq;
-       mtk_u32 tx_info;
-       /* offset 0x14 - 0x1f reserved for HC internal use */
-       mtk_u32 reserved[3];
-};
-
-
-struct sch_ep
-{
-       //device info
-       int dev_speed;
-       int isTT;
-       //ep info
-       int is_in;
-       int ep_type;
-       int maxp;
-       int interval;
-       int burst;
-       int mult;
-       //scheduling info
-       int offset;
-       int repeat;
-       int pkts;
-       int cs_count;
-       int burst_mode;
-       //other
-       int bw_cost;    //bandwidth cost in each repeat; including overhead
-       mtk_u32 *ep;            //address of usb_endpoint pointer
-};
-
-int mtk_xhci_scheduler_init(void);
-int mtk_xhci_scheduler_add_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
-       , int mult, mtk_u32 *ep, mtk_u32 *ep_ctx, struct sch_ep *sch_ep);
-struct sch_ep * mtk_xhci_scheduler_remove_ep(int dev_speed, int is_in, int isTT, int ep_type, mtk_u32 *ep);
-
-
-#endif
diff --git a/target/linux/ramips/files/drivers/usb/host/xhci-mtk.c b/target/linux/ramips/files/drivers/usb/host/xhci-mtk.c
deleted file mode 100644 (file)
index 2eed0a1..0000000
+++ /dev/null
@@ -1,265 +0,0 @@
-#include "xhci-mtk.h"
-#include "xhci-mtk-power.h"
-#include "xhci.h"
-#include "mtk-phy.h"
-#ifdef CONFIG_C60802_SUPPORT
-#include "mtk-phy-c60802.h"
-#endif
-#include "xhci-mtk-scheduler.h"
-#include <linux/kernel.h>       /* printk() */
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include <asm/uaccess.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-
-void setInitialReg(void )
-{
-       __u32 __iomem *addr;
-       u32 temp;
-
-       /* set SSUSB DMA burst size to 128B */
-       addr = SSUSB_U3_XHCI_BASE + SSUSB_HDMA_CFG;
-       temp = SSUSB_HDMA_CFG_MT7621_VALUE;
-       writel(temp, addr);
-
-       /* extend U3 LTSSM Polling.LFPS timeout value */
-       addr = SSUSB_U3_XHCI_BASE + U3_LTSSM_TIMING_PARAMETER3;
-       temp = U3_LTSSM_TIMING_PARAMETER3_VALUE;
-       writel(temp, addr);
-
-       /* EOF */
-       addr = SSUSB_U3_XHCI_BASE + SYNC_HS_EOF;
-       temp = SYNC_HS_EOF_VALUE;
-       writel(temp, addr);
-
-#if defined (CONFIG_PERIODIC_ENP)
-       /* HSCH_CFG1: SCH2_FIFO_DEPTH */
-       addr = SSUSB_U3_XHCI_BASE + HSCH_CFG1;
-       temp = readl(addr);
-       temp &= ~(0x3 << SCH2_FIFO_DEPTH_OFFSET);
-       writel(temp, addr);
-#endif
-
-       /* Doorbell handling */
-       addr = SIFSLV_IPPC + SSUSB_IP_SPAR0;
-       temp = 0x1;
-       writel(temp, addr);
-
-       /* Set SW PLL Stable mode to 1 for U2 LPM device remote wakeup */
-       /* Port 0 */
-       addr = U2_PHY_BASE + U2_PHYD_CR1;
-       temp = readl(addr);
-       temp &= ~(0x3 << 18);
-       temp |= (1 << 18);
-       writel(temp, addr);
-
-       /* Port 1 */
-       addr = U2_PHY_BASE_P1 + U2_PHYD_CR1;
-       temp = readl(addr);
-       temp &= ~(0x3 << 18);
-       temp |= (1 << 18);
-       writel(temp, addr);
-}
-
-
-void setLatchSel(void){
-       __u32 __iomem *latch_sel_addr;
-       u32 latch_sel_value;
-       latch_sel_addr = U3_PIPE_LATCH_SEL_ADD;
-       latch_sel_value = ((U3_PIPE_LATCH_TX)<<2) | (U3_PIPE_LATCH_RX);
-       writel(latch_sel_value, latch_sel_addr);
-}
-
-void reinitIP(void){
-       __u32 __iomem *ip_reset_addr;
-       u32 ip_reset_value;
-
-       enableAllClockPower();
-       mtk_xhci_scheduler_init();
-}
-
-void dbg_prb_out(void){
-       mtk_probe_init(0x0f0f0f0f);
-       mtk_probe_out(0xffffffff);
-       mtk_probe_out(0x01010101);
-       mtk_probe_out(0x02020202);
-       mtk_probe_out(0x04040404);
-       mtk_probe_out(0x08080808);
-       mtk_probe_out(0x10101010);
-       mtk_probe_out(0x20202020);
-       mtk_probe_out(0x40404040);
-       mtk_probe_out(0x80808080);
-       mtk_probe_out(0x55555555);
-       mtk_probe_out(0xaaaaaaaa);
-}
-
-
-
-///////////////////////////////////////////////////////////////////////////////
-
-#define RET_SUCCESS 0
-#define RET_FAIL 1
-
-static int dbg_u3w(int argc, char**argv)
-{
-       int u4TimingValue;
-       char u1TimingValue;
-       int u4TimingAddress;
-
-       if (argc<3)
-    {
-        printk(KERN_ERR "Arg: address value\n");
-        return RET_FAIL;
-    }
-       u3phy_init();
-       
-       u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
-       u4TimingValue = (int)simple_strtol(argv[2], &argv[2], 16);
-       u1TimingValue = u4TimingValue & 0xff;
-       /* access MMIO directly */
-       writel(u1TimingValue, u4TimingAddress);
-       printk(KERN_ERR "Write done\n");
-       return RET_SUCCESS;
-       
-}
-
-static int dbg_u3r(int argc, char**argv)
-{
-       char u1ReadTimingValue;
-       int u4TimingAddress;
-       if (argc<2)
-    {
-        printk(KERN_ERR "Arg: address\n");
-        return 0;
-    }
-       u3phy_init();
-       mdelay(500);
-       u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
-       /* access MMIO directly */
-       u1ReadTimingValue = readl(u4TimingAddress);
-       printk(KERN_ERR "Value = 0x%x\n", u1ReadTimingValue);
-       return 0;
-}
-
-static int dbg_u3init(int argc, char**argv)
-{
-       int ret;
-       ret = u3phy_init();
-       printk(KERN_ERR "phy registers and operations initial done\n");
-       if(u3phy_ops->u2_slew_rate_calibration){
-               u3phy_ops->u2_slew_rate_calibration(u3phy);
-       }
-       else{
-               printk(KERN_ERR "WARN: PHY doesn't implement u2 slew rate calibration function\n");
-       }
-       if(u3phy_ops->init(u3phy) == PHY_TRUE)
-               return RET_SUCCESS;
-       return RET_FAIL;
-}
-
-void dbg_setU1U2(int argc, char**argv){
-       struct xhci_hcd *xhci;
-       int u1_value;
-       int u2_value;
-       u32 port_id, temp;
-       u32 __iomem *addr;
-       
-       if (argc<3)
-    {
-        printk(KERN_ERR "Arg: u1value u2value\n");
-        return RET_FAIL;
-    }
-
-       u1_value = (int)simple_strtol(argv[1], &argv[1], 10);
-       u2_value = (int)simple_strtol(argv[2], &argv[2], 10);
-       addr = (SSUSB_U3_XHCI_BASE + 0x424);
-       temp = readl(addr);
-       temp = temp & (~(0x0000ffff));
-       temp = temp | u1_value | (u2_value<<8);
-       writel(temp, addr);
-}
-///////////////////////////////////////////////////////////////////////////////
-
-int call_function(char *buf)
-{
-       int i;
-       int argc;
-       char *argv[80];
-
-       argc = 0;
-       do
-       {
-               argv[argc] = strsep(&buf, " ");
-               printk(KERN_DEBUG "[%d] %s\r\n", argc, argv[argc]);
-               argc++;
-       } while (buf);
-       if (!strcmp("dbg.r", argv[0]))
-               dbg_prb_out();
-       else if (!strcmp("dbg.u3w", argv[0]))
-               dbg_u3w(argc, argv);
-       else if (!strcmp("dbg.u3r", argv[0]))
-               dbg_u3r(argc, argv);
-       else if (!strcmp("dbg.u3i", argv[0]))
-               dbg_u3init(argc, argv);
-       else if (!strcmp("pw.u1u2", argv[0]))
-               dbg_setU1U2(argc, argv);
-       return 0;
-}
-
-long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
-       char w_buf[200];
-       char r_buf[200] = "this is a test";
-       int len = 200;
-
-       switch (cmd) {
-               case IOCTL_READ:
-                       copy_to_user((char *) arg, r_buf, len);
-                       printk(KERN_DEBUG "IOCTL_READ: %s\r\n", r_buf);
-                       break;
-               case IOCTL_WRITE:
-                       copy_from_user(w_buf, (char *) arg, len);
-                       printk(KERN_DEBUG "IOCTL_WRITE: %s\r\n", w_buf);
-
-                       //invoke function
-                       return call_function(w_buf);
-                       break;
-               default:
-                       return -ENOTTY;
-       }
-
-       return len;
-}
-
-int xhci_mtk_test_open(struct inode *inode, struct file *file)
-{
-
-    printk(KERN_DEBUG "xhci_mtk_test open: successful\n");
-    return 0;
-}
-
-int xhci_mtk_test_release(struct inode *inode, struct file *file)
-{
-
-    printk(KERN_DEBUG "xhci_mtk_test release: successful\n");
-    return 0;
-}
-
-ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr)
-{
-
-    printk(KERN_DEBUG "xhci_mtk_test read: returning zero bytes\n");
-    return 0;
-}
-
-ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos)
-{
-
-    printk(KERN_DEBUG "xhci_mtk_test write: accepting zero bytes\n");
-    return 0;
-}
-
-
-
-
diff --git a/target/linux/ramips/files/drivers/usb/host/xhci-mtk.h b/target/linux/ramips/files/drivers/usb/host/xhci-mtk.h
deleted file mode 100644 (file)
index 0f2d5e8..0000000
+++ /dev/null
@@ -1,120 +0,0 @@
-#ifndef _XHCI_MTK_H
-#define _XHCI_MTK_H
-
-#include <linux/usb.h>
-#include "xhci.h"
-
-#define SSUSB_U3_XHCI_BASE             0xBE1C0000
-#define SSUSB_U3_MAC_BASE              0xBE1C2400
-#define SSUSB_U3_SYS_BASE              0xBE1C2600
-#define SSUSB_U2_SYS_BASE              0xBE1C3400
-#define SSUB_SIF_SLV_TOP               0xBE1D0000
-#define SIFSLV_IPPC                    (SSUB_SIF_SLV_TOP + 0x700)
-
-#define U3_PIPE_LATCH_SEL_ADD          SSUSB_U3_MAC_BASE + 0x130
-#define U3_PIPE_LATCH_TX               0
-#define U3_PIPE_LATCH_RX               0
-
-#define U3_UX_EXIT_LFPS_TIMING_PAR     0xa0
-#define U3_REF_CK_PAR                  0xb0
-#define U3_RX_UX_EXIT_LFPS_REF_OFFSET  8
-#define U3_RX_UX_EXIT_LFPS_REF         3
-#define        U3_REF_CK_VAL                   10
-
-#define U3_TIMING_PULSE_CTRL           0xb4
-#define CNT_1US_VALUE                  63 //62.5MHz:63, 70MHz:70, 80MHz:80, 100MHz:100, 125MHz:125
-
-#define USB20_TIMING_PARAMETER         0x40
-#define TIME_VALUE_1US                 63 //62.5MHz:63, 80MHz:80, 100MHz:100, 125MHz:125
-
-#define LINK_PM_TIMER                  0x8
-#define PM_LC_TIMEOUT_VALUE            3
-
-#define XHCI_IMOD                      0x624
-#define XHCI_IMOD_MT7621_VALUE         0x10
-
-#define SSUSB_HDMA_CFG                 0x950
-#define SSUSB_HDMA_CFG_MT7621_VALUE    0x10E0E0C
-
-#define U3_LTSSM_TIMING_PARAMETER3             0x2514
-#define U3_LTSSM_TIMING_PARAMETER3_VALUE       0x3E8012C
-
-#define U2_PHYD_CR1                    0x64
-
-#define SSUSB_IP_SPAR0                 0xC8
-
-#define SYNC_HS_EOF                    0x938
-#define SYNC_HS_EOF_VALUE              0x201F3
-
-#define HSCH_CFG1                      0x960
-#define SCH2_FIFO_DEPTH_OFFSET         16
-
-
-#define SSUSB_IP_PW_CTRL               (SIFSLV_IPPC+0x0)
-#define SSUSB_IP_SW_RST                        (1<<0)
-#define SSUSB_IP_PW_CTRL_1             (SIFSLV_IPPC+0x4)
-#define SSUSB_IP_PDN                   (1<<0)
-#define SSUSB_U3_CTRL(p)               (SIFSLV_IPPC+0x30+(p*0x08))
-#define SSUSB_U3_PORT_DIS              (1<<0)
-#define SSUSB_U3_PORT_PDN              (1<<1)
-#define SSUSB_U3_PORT_HOST_SEL         (1<<2)
-#define SSUSB_U3_PORT_CKBG_EN          (1<<3)
-#define SSUSB_U3_PORT_MAC_RST          (1<<4)
-#define SSUSB_U3_PORT_PHYD_RST         (1<<5)
-#define SSUSB_U2_CTRL(p)               (SIFSLV_IPPC+(0x50)+(p*0x08))
-#define SSUSB_U2_PORT_DIS              (1<<0)
-#define SSUSB_U2_PORT_PDN              (1<<1)
-#define SSUSB_U2_PORT_HOST_SEL         (1<<2)
-#define SSUSB_U2_PORT_CKBG_EN          (1<<3)
-#define SSUSB_U2_PORT_MAC_RST          (1<<4)
-#define SSUSB_U2_PORT_PHYD_RST         (1<<5)
-#define SSUSB_IP_CAP                   (SIFSLV_IPPC+0x024)
-
-#define SSUSB_U3_PORT_NUM(p)           (p & 0xff)
-#define SSUSB_U2_PORT_NUM(p)           ((p>>8) & 0xff)
-
-
-#define XHCI_MTK_TEST_MAJOR            234
-#define DEVICE_NAME                    "xhci_mtk_test"
-
-#define CLI_MAGIC                      'CLI'
-#define IOCTL_READ                     _IOR(CLI_MAGIC, 0, int)
-#define IOCTL_WRITE                    _IOW(CLI_MAGIC, 1, int)
-
-void reinitIP(void);
-void setInitialReg(void);
-void dbg_prb_out(void);
-int call_function(char *buf);
-
-long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
-int xhci_mtk_test_open(struct inode *inode, struct file *file);
-int xhci_mtk_test_release(struct inode *inode, struct file *file);
-ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr);
-ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos);
-
-/*
-  mediatek probe out
-*/
-/************************************************************************************/
-
-#define SW_PRB_OUT_ADDR                (SIFSLV_IPPC+0xc0)
-#define PRB_MODULE_SEL_ADDR    (SIFSLV_IPPC+0xbc)
-
-static inline void mtk_probe_init(const u32 byte){
-       __u32 __iomem *ptr = (__u32 __iomem *) PRB_MODULE_SEL_ADDR;
-       writel(byte, ptr);
-}
-
-static inline void mtk_probe_out(const u32 value){
-       __u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
-       writel(value, ptr);
-}
-
-static inline u32 mtk_probe_value(void){
-       __u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
-
-       return readl(ptr);
-}
-
-
-#endif
index 194bb4a..86bc7be 100644 (file)
@@ -1,6 +1,8 @@
+# CONFIG_32B_DESC is not set
 CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
 CONFIG_ARCH_DISCARD_MEMBLOCK=y
 CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
 CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
 CONFIG_ARCH_REQUIRE_GPIOLIB=y
 CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
@@ -35,6 +37,14 @@ CONFIG_DMA_NONCOHERENT=y
 CONFIG_DTB_RT_NONE=y
 CONFIG_DTC=y
 CONFIG_EARLY_PRINTK=y
+CONFIG_ESW_DOUBLE_VLAN_TAG=y
+# CONFIG_GE1_MII_AN is not set
+# CONFIG_GE1_MII_FORCE_100 is not set
+# CONFIG_GE1_RGMII_AN is not set
+CONFIG_GE1_RGMII_FORCE_1000=y
+# CONFIG_GE1_RGMII_NONE is not set
+# CONFIG_GE1_RVMII_FORCE_100 is not set
+# CONFIG_GE1_TRGMII_FORCE_1200 is not set
 CONFIG_GENERIC_ATOMIC64=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
@@ -88,6 +98,7 @@ CONFIG_IRQ_DOMAIN=y
 CONFIG_IRQ_FORCED_THREADING=y
 CONFIG_IRQ_GIC=y
 CONFIG_IRQ_WORK=y
+# CONFIG_LAN_WAN_SUPPORT is not set
 CONFIG_M25PXX_USE_FAST_READ=y
 CONFIG_MDIO_BOARDINFO=y
 # CONFIG_MII is not set
@@ -105,6 +116,7 @@ CONFIG_MIPS_MT_SMP=y
 CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
 # CONFIG_MIPS_VPE_LOADER is not set
 CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MT7621_ASIC=y
 # CONFIG_MT7621_WDT is not set
 # CONFIG_MTD_CFI_INTELEXT is not set
 CONFIG_MTD_CMDLINE_PARTS=y
@@ -137,6 +149,7 @@ CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_PCI=y
 CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
 CONFIG_PCI_DOMAINS=y
+CONFIG_PDMA_NEW=y
 CONFIG_PERF_USE_VMALLOC=y
 CONFIG_PHYLIB=y
 # CONFIG_PINCONF is not set
@@ -145,12 +158,30 @@ CONFIG_PINCTRL_RT2880=y
 # CONFIG_PINCTRL_SINGLE is not set
 CONFIG_PINMUX=y
 # CONFIG_PREEMPT_RCU is not set
+CONFIG_RAETH=y
+CONFIG_RAETH_CHECKSUM_OFFLOAD=y
+# CONFIG_RAETH_GMAC2 is not set
+# CONFIG_RAETH_HW_VLAN_RX is not set
+# CONFIG_RAETH_HW_VLAN_TX is not set
+# CONFIG_RAETH_LRO is not set
+# CONFIG_RAETH_NAPI is not set
+# CONFIG_RAETH_QDMA is not set
+CONFIG_RAETH_SCATTER_GATHER_RX_DMA=y
+# CONFIG_RAETH_SKB_RECYCLE_2K is not set
+# CONFIG_RAETH_SPECIAL_TAG is not set
+# CONFIG_RAETH_TSO is not set
 CONFIG_RALINK=y
+CONFIG_RALINK_MT7621=y
 CONFIG_RALINK_USBPHY=y
+# CONFIG_RALINK_WDT is not set
+CONFIG_RA_NAT_NONE=y
+# CONFIG_RA_NETWORK_TASKLET_BH is not set
+CONFIG_RA_NETWORK_WORKQUEUE_BH=y
 CONFIG_RCU_STALL_COMMON=y
 CONFIG_RESET_CONTROLLER=y
 CONFIG_RFS_ACCEL=y
 CONFIG_RPS=y
+CONFIG_RT_3052_ESW=y
 # CONFIG_SAMSUNG_USB2PHY is not set
 # CONFIG_SAMSUNG_USB3PHY is not set
 # CONFIG_SAMSUNG_USBPHY is not set
@@ -199,6 +230,8 @@ CONFIG_USB_XHCI_HCD=m
 CONFIG_USB_XHCI_PLATFORM=y
 CONFIG_USE_GENERIC_SMP_HELPERS=y
 CONFIG_USE_OF=y
+CONFIG_WAN_AT_P0=y
+# CONFIG_WAN_AT_P4 is not set
 CONFIG_WATCHDOG_CORE=y
 CONFIG_WEAK_ORDERING=y
 CONFIG_XPS=y
index a905d1e..fb04ba7 100644 (file)
@@ -8,7 +8,7 @@
 define Profile/Default
        NAME:=Default Profile
        PACKAGES:=\
-               kmod-usb-core kmod-usb-dwc2 \
+               kmod-usb-core kmod-usb3 \
                kmod-ledtrig-usbdev
 endef
 
index e87eb4d..1d2e728 100644 (file)
@@ -1,7 +1,7 @@
-From cdc1b12b3debaf5b3894fd146e73221a8acd0152 Mon Sep 17 00:00:00 2001
+From 1be15a87eea5f26fb24b6aac332530cd3e2d984e Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Sun, 14 Jul 2013 23:08:11 +0200
-Subject: [PATCH 20/25] MIPS: use set_mode() to enable/disable the cevt-r4k
+Subject: [PATCH 100/133] MIPS: use set_mode() to enable/disable the cevt-r4k
  irq
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
@@ -24,13 +24,14 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
  int cp0_timer_irq_installed;
  
-@@ -90,6 +84,32 @@ struct irqaction c0_compare_irqaction =
+@@ -90,9 +84,38 @@ struct irqaction c0_compare_irqaction =
        .name = "timer",
  };
  
 +void mips_set_clock_mode(enum clock_event_mode mode,
 +                              struct clock_event_device *evt)
 +{
++#ifdef CONFIG_CEVT_SYSTICK_QUIRK
 +      switch (mode) {
 +      case CLOCK_EVT_MODE_ONESHOT:
 +              if (cp0_timer_irq_installed)
@@ -53,21 +54,27 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +              pr_err("Unhandeled mips clock_mode\n");
 +              break;
 +      }
++#endif
 +}
  
  void mips_event_handler(struct clock_event_device *dev)
  {
-@@ -215,13 +235,6 @@ int __cpuinit r4k_clockevent_init(void)
++
+ }
+ /*
+@@ -215,12 +238,14 @@ int __cpuinit r4k_clockevent_init(void)
  #endif
        clockevents_register_device(cd);
  
--      if (cp0_timer_irq_installed)
--              return 0;
--
--      cp0_timer_irq_installed = 1;
--
--      setup_irq(irq, &c0_compare_irqaction);
--
++#ifndef CONFIG_CEVT_SYSTICK_QUIRK
+       if (cp0_timer_irq_installed)
+               return 0;
+       cp0_timer_irq_installed = 1;
+       setup_irq(irq, &c0_compare_irqaction);
++#endif
        return 0;
  }
diff --git a/target/linux/ramips/patches-3.10/0101-MIPS-ralink-add-verbose-pmu-info.patch b/target/linux/ramips/patches-3.10/0101-MIPS-ralink-add-verbose-pmu-info.patch
new file mode 100644 (file)
index 0000000..5a7d5f9
--- /dev/null
@@ -0,0 +1,59 @@
+From 5689333e7e4396a827a2cb6fa1242159e9af56de Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 20 May 2013 20:57:09 +0200
+Subject: [PATCH 101/133] MIPS: ralink: add verbose pmu info
+
+Print the PMU and LDO settings on boot.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/mt7620.c |   26 ++++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -26,6 +26,22 @@
+ #define CLKCFG_FFRAC_MASK     0x001f
+ #define CLKCFG_FFRAC_USB_VAL  0x0003
++/* analog */
++#define PMU0_CFG              0x88
++#define PMU_SW_SET            BIT(28)
++#define A_DCDC_EN             BIT(24)
++#define A_SSC_PERI            BIT(19)
++#define A_SSC_GEN             BIT(18)
++#define A_SSC_M                       0x3
++#define A_SSC_S                       16
++#define A_DLY_M                       0x7
++#define A_DLY_S                       8
++#define A_VTUNE_M             0xff
++
++/* digital */
++#define PMU1_CFG              0x8C
++#define DIG_SW_SEL            BIT(25)
++
+ /* does the board have sdram or ddram */
+ static int dram_type;
+@@ -208,6 +224,8 @@ void prom_soc_init(struct ralink_soc_inf
+       u32 n1;
+       u32 rev;
+       u32 cfg0;
++      u32 pmu0;
++      u32 pmu1;
+       n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
+       n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
+@@ -255,4 +273,12 @@ void prom_soc_init(struct ralink_soc_inf
+               BUG();
+       }
+       soc_info->mem_base = MT7620_DRAM_BASE;
++
++      pmu0 = __raw_readl(sysc + PMU0_CFG);
++      pmu1 = __raw_readl(sysc + PMU1_CFG);
++
++      pr_info("Analog PMU set to %s control\n",
++              (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
++      pr_info("Digital PMU set to %s control\n",
++              (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
+ }
diff --git a/target/linux/ramips/patches-3.10/0102-MIPS-ralink-add-verbose-pmu-info.patch b/target/linux/ramips/patches-3.10/0102-MIPS-ralink-add-verbose-pmu-info.patch
deleted file mode 100644 (file)
index 687b883..0000000
+++ /dev/null
@@ -1,59 +0,0 @@
-From 74339d6eab7a37f7c629b737bf686d30e5014ce2 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 20 May 2013 20:57:09 +0200
-Subject: [PATCH 06/33] MIPS: ralink: add verbose pmu info
-
-Print the PMU and LDO settings on boot.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/mt7620.c |   26 ++++++++++++++++++++++++++
- 1 file changed, 26 insertions(+)
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -26,6 +26,22 @@
- #define CLKCFG_FFRAC_MASK     0x001f
- #define CLKCFG_FFRAC_USB_VAL  0x0003
-+/* analog */
-+#define PMU0_CFG              0x88
-+#define PMU_SW_SET            BIT(28)
-+#define A_DCDC_EN             BIT(24)
-+#define A_SSC_PERI            BIT(19)
-+#define A_SSC_GEN             BIT(18)
-+#define A_SSC_M                       0x3
-+#define A_SSC_S                       16
-+#define A_DLY_M                       0x7
-+#define A_DLY_S                       8
-+#define A_VTUNE_M             0xff
-+
-+/* digital */
-+#define PMU1_CFG              0x8C
-+#define DIG_SW_SEL            BIT(25)
-+
- /* does the board have sdram or ddram */
- static int dram_type;
-@@ -208,6 +224,8 @@ void prom_soc_init(struct ralink_soc_inf
-       u32 n1;
-       u32 rev;
-       u32 cfg0;
-+      u32 pmu0;
-+      u32 pmu1;
-       n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
-       n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
-@@ -255,4 +273,12 @@ void prom_soc_init(struct ralink_soc_inf
-               BUG();
-       }
-       soc_info->mem_base = MT7620_DRAM_BASE;
-+
-+      pmu0 = __raw_readl(sysc + PMU0_CFG);
-+      pmu1 = __raw_readl(sysc + PMU1_CFG);
-+
-+      pr_info("Analog PMU set to %s control\n",
-+              (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
-+      pr_info("Digital PMU set to %s control\n",
-+              (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
- }
diff --git a/target/linux/ramips/patches-3.10/0102-MIPS-ralink-adds-a-bootrom-dumper-module.patch b/target/linux/ramips/patches-3.10/0102-MIPS-ralink-adds-a-bootrom-dumper-module.patch
new file mode 100644 (file)
index 0000000..e295a4a
--- /dev/null
@@ -0,0 +1,75 @@
+From 23d18a1b3d0a7e5faa08b6bece6692667c930975 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Tue, 21 May 2013 15:50:31 +0200
+Subject: [PATCH 102/133] MIPS: ralink: adds a bootrom dumper module
+
+This patch adds a trivial driver that allows userland to extract the bootrom of
+a SoC via debugfs.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/Makefile  |    2 ++
+ arch/mips/ralink/bootrom.c |   48 ++++++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 50 insertions(+)
+ create mode 100644 arch/mips/ralink/bootrom.c
+
+--- a/arch/mips/ralink/Makefile
++++ b/arch/mips/ralink/Makefile
+@@ -17,4 +17,6 @@ obj-$(CONFIG_SOC_MT7620) += mt7620.o
+ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
++obj-$(CONFIG_DEBUG_FS) += bootrom.o
++
+ obj-y += dts/
+--- /dev/null
++++ b/arch/mips/ralink/bootrom.c
+@@ -0,0 +1,48 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/debugfs.h>
++#include <linux/seq_file.h>
++
++#define BOOTROM_OFFSET        0x10118000
++#define BOOTROM_SIZE  0x8000
++
++static void __iomem *membase = (void __iomem*) KSEG1ADDR(BOOTROM_OFFSET);
++
++static int bootrom_show(struct seq_file *s, void *unused)
++{
++      seq_write(s, membase, BOOTROM_SIZE);
++
++      return 0;
++}
++
++static int bootrom_open(struct inode *inode, struct file *file)
++{
++      return single_open(file, bootrom_show, NULL);
++}
++
++static const struct file_operations bootrom_file_ops = {
++      .open           = bootrom_open,
++      .read           = seq_read,
++      .llseek         = seq_lseek,
++      .release        = single_release,
++};
++
++static int bootrom_setup(void)
++{
++      if (!debugfs_create_file("bootrom", 0444,
++                      NULL, NULL, &bootrom_file_ops)) {
++              pr_err("Failed to create bootrom debugfs file\n");
++
++              return -EINVAL;
++      }
++
++      return 0;
++}
++
++postcore_initcall(bootrom_setup);
diff --git a/target/linux/ramips/patches-3.10/0103-MIPS-ralink-add-illegal-access-driver.patch b/target/linux/ramips/patches-3.10/0103-MIPS-ralink-add-illegal-access-driver.patch
new file mode 100644 (file)
index 0000000..4dfa7b5
--- /dev/null
@@ -0,0 +1,113 @@
+From c5fe00f24f56b15f982dda355089986d57488b36 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 16 May 2013 23:28:23 +0200
+Subject: [PATCH 103/133] MIPS: ralink: add illegal access driver
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/Makefile  |    2 +
+ arch/mips/ralink/ill_acc.c |   87 ++++++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 89 insertions(+)
+ create mode 100644 arch/mips/ralink/ill_acc.c
+
+--- a/arch/mips/ralink/Makefile
++++ b/arch/mips/ralink/Makefile
+@@ -10,6 +10,8 @@ obj-y := prom.o of.o reset.o clk.o irq.o
+ obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
++obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
++
+ obj-$(CONFIG_SOC_RT288X) += rt288x.o
+ obj-$(CONFIG_SOC_RT305X) += rt305x.o
+ obj-$(CONFIG_SOC_RT3883) += rt3883.o
+--- /dev/null
++++ b/arch/mips/ralink/ill_acc.c
+@@ -0,0 +1,87 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/interrupt.h>
++#include <linux/of_platform.h>
++#include <linux/of_irq.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#define REG_ILL_ACC_ADDR      0x10
++#define REG_ILL_ACC_TYPE      0x14
++
++#define ILL_INT_STATUS                BIT(31)
++#define ILL_ACC_WRITE         BIT(30)
++#define ILL_ACC_LEN_M         0xff
++#define ILL_ACC_OFF_M         0xf
++#define ILL_ACC_OFF_S         16
++#define ILL_ACC_ID_M          0x7
++#define ILL_ACC_ID_S          8
++
++#define       DRV_NAME                "ill_acc"
++
++static const char *ill_acc_ids[] = {
++      "cpu", "dma", "ppe", "pdma rx","pdma tx", "pci/e", "wmac", "usb",
++};
++
++static irqreturn_t ill_acc_irq_handler(int irq, void *_priv)
++{
++      struct device *dev = (struct device *) _priv;
++      u32 addr = rt_memc_r32(REG_ILL_ACC_ADDR);
++      u32 type = rt_memc_r32(REG_ILL_ACC_TYPE);
++
++      dev_err(dev, "illegal %s access from %s - addr:0x%08x offset:%d len:%d\n",
++              (type & ILL_ACC_WRITE) ? ("write") : ("read"),
++              ill_acc_ids[(type >> ILL_ACC_ID_S) & ILL_ACC_ID_M],
++              addr, (type >> ILL_ACC_OFF_S) & ILL_ACC_OFF_M,
++              type & ILL_ACC_LEN_M);
++
++      rt_memc_w32(REG_ILL_ACC_TYPE, REG_ILL_ACC_TYPE);
++
++      return IRQ_HANDLED;
++}
++
++static int __init ill_acc_of_setup(void)
++{
++      struct platform_device *pdev;
++      struct device_node *np;
++      int irq;
++
++      /* somehow this driver breaks on RT5350 */
++      if (of_machine_is_compatible("ralink,rt5350-soc"))
++              return -EINVAL;
++
++      np = of_find_compatible_node(NULL, NULL, "ralink,rt3050-memc");
++      if (!np)
++              return -EINVAL;
++
++      pdev = of_find_device_by_node(np);
++      if (!pdev) {
++              pr_err("%s: failed to lookup pdev\n", np->name);
++              return -EINVAL;
++      }
++
++      irq = irq_of_parse_and_map(np, 0);
++        if (!irq) {
++              dev_err(&pdev->dev, "failed to get irq\n");
++              return -EINVAL;
++      }
++
++      if (request_irq(irq, ill_acc_irq_handler, 0, "ill_acc", &pdev->dev)) {
++              dev_err(&pdev->dev, "failed to request irq\n");
++              return -EINVAL;
++      }
++
++      rt_memc_w32(ILL_INT_STATUS, REG_ILL_ACC_TYPE);
++
++      dev_info(&pdev->dev, "irq registered\n");
++
++      return 0;
++}
++
++arch_initcall(ill_acc_of_setup);
diff --git a/target/linux/ramips/patches-3.10/0103-MIPS-ralink-adds-a-bootrom-dumper-module.patch b/target/linux/ramips/patches-3.10/0103-MIPS-ralink-adds-a-bootrom-dumper-module.patch
deleted file mode 100644 (file)
index c091032..0000000
+++ /dev/null
@@ -1,75 +0,0 @@
-From 71409a190a0c8e3597cae7d46321742e29d8994b Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Tue, 21 May 2013 15:50:31 +0200
-Subject: [PATCH 07/33] MIPS: ralink: adds a bootrom dumper module
-
-This patch adds a trivial driver that allows userland to extract the bootrom of
-a SoC via debugfs.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/Makefile  |    2 ++
- arch/mips/ralink/bootrom.c |   48 ++++++++++++++++++++++++++++++++++++++++++++
- 2 files changed, 50 insertions(+)
- create mode 100644 arch/mips/ralink/bootrom.c
-
---- a/arch/mips/ralink/Makefile
-+++ b/arch/mips/ralink/Makefile
-@@ -17,4 +17,6 @@ obj-$(CONFIG_SOC_MT7620) += mt7620.o
- obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
-+obj-$(CONFIG_DEBUG_FS) += bootrom.o
-+
- obj-y += dts/
---- /dev/null
-+++ b/arch/mips/ralink/bootrom.c
-@@ -0,0 +1,48 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/debugfs.h>
-+#include <linux/seq_file.h>
-+
-+#define BOOTROM_OFFSET        0x10118000
-+#define BOOTROM_SIZE  0x8000
-+
-+static void __iomem *membase = (void __iomem*) KSEG1ADDR(BOOTROM_OFFSET);
-+
-+static int bootrom_show(struct seq_file *s, void *unused)
-+{
-+      seq_write(s, membase, BOOTROM_SIZE);
-+
-+      return 0;
-+}
-+
-+static int bootrom_open(struct inode *inode, struct file *file)
-+{
-+      return single_open(file, bootrom_show, NULL);
-+}
-+
-+static const struct file_operations bootrom_file_ops = {
-+      .open           = bootrom_open,
-+      .read           = seq_read,
-+      .llseek         = seq_lseek,
-+      .release        = single_release,
-+};
-+
-+static int bootrom_setup(void)
-+{
-+      if (!debugfs_create_file("bootrom", 0444,
-+                      NULL, NULL, &bootrom_file_ops)) {
-+              pr_err("Failed to create bootrom debugfs file\n");
-+
-+              return -EINVAL;
-+      }
-+
-+      return 0;
-+}
-+
-+postcore_initcall(bootrom_setup);
diff --git a/target/linux/ramips/patches-3.10/0104-MIPS-ralink-add-illegal-access-driver.patch b/target/linux/ramips/patches-3.10/0104-MIPS-ralink-add-illegal-access-driver.patch
deleted file mode 100644 (file)
index 082c324..0000000
+++ /dev/null
@@ -1,113 +0,0 @@
-From 46446fcfc6e823005ebe71357b5995524e75542c Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 16 May 2013 23:28:23 +0200
-Subject: [PATCH 08/33] MIPS: ralink: add illegal access driver
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/Makefile  |    2 +
- arch/mips/ralink/ill_acc.c |   87 ++++++++++++++++++++++++++++++++++++++++++++
- 2 files changed, 89 insertions(+)
- create mode 100644 arch/mips/ralink/ill_acc.c
-
---- a/arch/mips/ralink/Makefile
-+++ b/arch/mips/ralink/Makefile
-@@ -10,6 +10,8 @@ obj-y := prom.o of.o reset.o clk.o irq.o
- obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
-+obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
-+
- obj-$(CONFIG_SOC_RT288X) += rt288x.o
- obj-$(CONFIG_SOC_RT305X) += rt305x.o
- obj-$(CONFIG_SOC_RT3883) += rt3883.o
---- /dev/null
-+++ b/arch/mips/ralink/ill_acc.c
-@@ -0,0 +1,87 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/interrupt.h>
-+#include <linux/of_platform.h>
-+#include <linux/of_irq.h>
-+
-+#include <asm/mach-ralink/ralink_regs.h>
-+
-+#define REG_ILL_ACC_ADDR      0x10
-+#define REG_ILL_ACC_TYPE      0x14
-+
-+#define ILL_INT_STATUS                BIT(31)
-+#define ILL_ACC_WRITE         BIT(30)
-+#define ILL_ACC_LEN_M         0xff
-+#define ILL_ACC_OFF_M         0xf
-+#define ILL_ACC_OFF_S         16
-+#define ILL_ACC_ID_M          0x7
-+#define ILL_ACC_ID_S          8
-+
-+#define       DRV_NAME                "ill_acc"
-+
-+static const char *ill_acc_ids[] = {
-+      "cpu", "dma", "ppe", "pdma rx","pdma tx", "pci/e", "wmac", "usb",
-+};
-+
-+static irqreturn_t ill_acc_irq_handler(int irq, void *_priv)
-+{
-+      struct device *dev = (struct device *) _priv;
-+      u32 addr = rt_memc_r32(REG_ILL_ACC_ADDR);
-+      u32 type = rt_memc_r32(REG_ILL_ACC_TYPE);
-+
-+      dev_err(dev, "illegal %s access from %s - addr:0x%08x offset:%d len:%d\n",
-+              (type & ILL_ACC_WRITE) ? ("write") : ("read"),
-+              ill_acc_ids[(type >> ILL_ACC_ID_S) & ILL_ACC_ID_M],
-+              addr, (type >> ILL_ACC_OFF_S) & ILL_ACC_OFF_M,
-+              type & ILL_ACC_LEN_M);
-+
-+      rt_memc_w32(REG_ILL_ACC_TYPE, REG_ILL_ACC_TYPE);
-+
-+      return IRQ_HANDLED;
-+}
-+
-+static int __init ill_acc_of_setup(void)
-+{
-+      struct platform_device *pdev;
-+      struct device_node *np;
-+      int irq;
-+
-+      /* somehow this driver breaks on RT5350 */
-+      if (of_machine_is_compatible("ralink,rt5350-soc"))
-+              return -EINVAL;
-+
-+      np = of_find_compatible_node(NULL, NULL, "ralink,rt3050-memc");
-+      if (!np)
-+              return -EINVAL;
-+
-+      pdev = of_find_device_by_node(np);
-+      if (!pdev) {
-+              pr_err("%s: failed to lookup pdev\n", np->name);
-+              return -EINVAL;
-+      }
-+
-+      irq = irq_of_parse_and_map(np, 0);
-+        if (!irq) {
-+              dev_err(&pdev->dev, "failed to get irq\n");
-+              return -EINVAL;
-+      }
-+
-+      if (request_irq(irq, ill_acc_irq_handler, 0, "ill_acc", &pdev->dev)) {
-+              dev_err(&pdev->dev, "failed to request irq\n");
-+              return -EINVAL;
-+      }
-+
-+      rt_memc_w32(ILL_INT_STATUS, REG_ILL_ACC_TYPE);
-+
-+      dev_info(&pdev->dev, "irq registered\n");
-+
-+      return 0;
-+}
-+
-+arch_initcall(ill_acc_of_setup);
diff --git a/target/linux/ramips/patches-3.10/0104-MIPS-ralink-workaround-DTB-memory-issue.patch b/target/linux/ramips/patches-3.10/0104-MIPS-ralink-workaround-DTB-memory-issue.patch
new file mode 100644 (file)
index 0000000..c9a12b3
--- /dev/null
@@ -0,0 +1,24 @@
+From b83808826ac7a5c727f5314b5a3bf07fcd6ec929 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 23 May 2013 18:50:56 +0200
+Subject: [PATCH 104/133] MIPS: ralink: workaround DTB memory issue
+
+If the DTB is too big a bug happens on boot when init ram is freed.
+This is a temporary fix until the real cause is found.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/of.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/ralink/of.c
++++ b/arch/mips/ralink/of.c
+@@ -74,7 +74,7 @@ void __init device_tree_init(void)
+       unflatten_device_tree();
+       /* free the space reserved for the dt blob */
+-      free_bootmem(base, size);
++      //free_bootmem(base, size);
+ }
+ void __init plat_mem_setup(void)
diff --git a/target/linux/ramips/patches-3.10/0105-MIPS-ralink-add-missing-clk_set_rate-to-clk.c.patch b/target/linux/ramips/patches-3.10/0105-MIPS-ralink-add-missing-clk_set_rate-to-clk.c.patch
new file mode 100644 (file)
index 0000000..e9b30e0
--- /dev/null
@@ -0,0 +1,25 @@
+From 6f72aea69951479b7daad1d38b506ede4f8a1676 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 16 Mar 2014 04:38:07 +0000
+Subject: [PATCH 105/133] MIPS: ralink: add missing clk_set_rate() to clk.c
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/clk.c |    6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/arch/mips/ralink/clk.c
++++ b/arch/mips/ralink/clk.c
+@@ -56,6 +56,12 @@ unsigned long clk_get_rate(struct clk *c
+ }
+ EXPORT_SYMBOL_GPL(clk_get_rate);
++int clk_set_rate(struct clk *clk, unsigned long rate)
++{
++      return -1;
++}
++EXPORT_SYMBOL_GPL(clk_set_rate);
++
+ void __init plat_time_init(void)
+ {
+       struct clk *clk;
diff --git a/target/linux/ramips/patches-3.10/0105-MIPS-ralink-workaround-DTB-memory-issue.patch b/target/linux/ramips/patches-3.10/0105-MIPS-ralink-workaround-DTB-memory-issue.patch
deleted file mode 100644 (file)
index 662b356..0000000
+++ /dev/null
@@ -1,24 +0,0 @@
-From 070a389ae536a75b9184784f625949c215c533b6 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 23 May 2013 18:50:56 +0200
-Subject: [PATCH 09/33] MIPS: ralink: workaround DTB memory issue
-
-If the DTB is too big a bug happens on boot when init ram is freed.
-This is a temporary fix until the real cause is found.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/of.c |    2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/mips/ralink/of.c
-+++ b/arch/mips/ralink/of.c
-@@ -74,7 +74,7 @@ void __init device_tree_init(void)
-       unflatten_device_tree();
-       /* free the space reserved for the dt blob */
--      free_bootmem(base, size);
-+      //free_bootmem(base, size);
- }
- void __init plat_mem_setup(void)
diff --git a/target/linux/ramips/patches-3.10/0106-MIPS-ralink-add-support-for-MT7620n.patch b/target/linux/ramips/patches-3.10/0106-MIPS-ralink-add-support-for-MT7620n.patch
new file mode 100644 (file)
index 0000000..bb1ff7d
--- /dev/null
@@ -0,0 +1,66 @@
+From 45ba0675286e2a71f6a577833ab13b951bb7e31a Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 16 Mar 2014 04:40:02 +0000
+Subject: [PATCH 106/133] MIPS: ralink: add support for MT7620n
+
+This is the small version of MT7620a.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/mach-ralink/mt7620.h |    7 ++-----
+ arch/mips/ralink/mt7620.c                  |   19 ++++++++++++-------
+ 2 files changed, 14 insertions(+), 12 deletions(-)
+
+--- a/arch/mips/include/asm/mach-ralink/mt7620.h
++++ b/arch/mips/include/asm/mach-ralink/mt7620.h
+@@ -24,11 +24,8 @@
+ #define SYSC_REG_CPLL_CONFIG0         0x54
+ #define SYSC_REG_CPLL_CONFIG1         0x58
+-#define MT7620N_CHIP_NAME0            0x33365452
+-#define MT7620N_CHIP_NAME1            0x20203235
+-
+-#define MT7620A_CHIP_NAME0            0x3637544d
+-#define MT7620A_CHIP_NAME1            0x20203032
++#define MT7620_CHIP_NAME0             0x3637544d
++#define MT7620_CHIP_NAME1             0x20203032
+ #define CHIP_REV_PKG_MASK             0x1
+ #define CHIP_REV_PKG_SHIFT            16
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -226,22 +226,27 @@ void prom_soc_init(struct ralink_soc_inf
+       u32 cfg0;
+       u32 pmu0;
+       u32 pmu1;
++      u32 bga;
+       n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
+       n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
++      rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
++      bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
+-      if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) {
+-              name = "MT7620N";
+-              soc_info->compatible = "ralink,mt7620n-soc";
+-      } else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) {
++      if (n0 != MT7620_CHIP_NAME0 || n1 != MT7620_CHIP_NAME1)
++              panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
++
++      if (bga) {
+               name = "MT7620A";
+               soc_info->compatible = "ralink,mt7620a-soc";
+       } else {
+-              panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
++              name = "MT7620N";
++              soc_info->compatible = "ralink,mt7620n-soc";
++#ifdef CONFIG_PCI
++              panic("mt7620n is only supported for non pci kernels");
++#endif
+       }
+-      rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
+-
+       snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
+               "Ralink %s ver:%u eco:%u",
+               name,
diff --git a/target/linux/ramips/patches-3.10/0106-USB-dwc2.patch b/target/linux/ramips/patches-3.10/0106-USB-dwc2.patch
deleted file mode 100644 (file)
index 90e8ee5..0000000
+++ /dev/null
@@ -1,19 +0,0 @@
---- a/drivers/staging/dwc2/hcd.c
-+++ b/drivers/staging/dwc2/hcd.c
-@@ -47,6 +47,7 @@
- #include <linux/io.h>
- #include <linux/slab.h>
- #include <linux/usb.h>
-+#include <linux/reset.h>
- #include <linux/usb/hcd.h>
- #include <linux/usb/ch11.h>
-@@ -2712,6 +2713,8 @@ int dwc2_hcd_init(struct dwc2_hsotg *hso
-       dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
-+      device_reset(hsotg->dev);
-+
-       /*
-        * Attempt to ensure this device is really a DWC_otg Controller.
-        * Read and verify the GSNPSID register contents. The value should be
diff --git a/target/linux/ramips/patches-3.10/0107-MIPS-ralink-allow-manual-memory-override.patch b/target/linux/ramips/patches-3.10/0107-MIPS-ralink-allow-manual-memory-override.patch
new file mode 100644 (file)
index 0000000..4fb2b2b
--- /dev/null
@@ -0,0 +1,45 @@
+From ee46d05eefefb0fb40b5682b4f6f3876b496044b Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 16 Mar 2014 04:40:48 +0000
+Subject: [PATCH 107/133] MIPS: ralink: allow manual memory override
+
+RT5350 relies on the bootloader setting up the memc correctly.
+On sme boards the setup is incorrect leading to 32 MB being available but only 16 being recognized. Allow these boards to manually override the memory range
+.
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/of.c |   16 +++++++++++++++-
+ 1 file changed, 15 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ralink/of.c
++++ b/arch/mips/ralink/of.c
+@@ -77,6 +77,17 @@ void __init device_tree_init(void)
+       //free_bootmem(base, size);
+ }
++static int memory_dtb;
++
++static int __init early_init_dt_find_memory(unsigned long node, const char *uname,
++                                   int depth, void *data)
++{
++      if (depth == 1 && !strcmp(uname, "memory@0"))
++              memory_dtb = 1;
++
++      return 0;
++}
++
+ void __init plat_mem_setup(void)
+ {
+       set_io_port_base(KSEG1);
+@@ -87,7 +98,10 @@ void __init plat_mem_setup(void)
+        */
+       __dt_setup_arch(&__dtb_start);
+-      if (soc_info.mem_size)
++      of_scan_flat_dt(early_init_dt_find_memory, NULL);
++      if (memory_dtb)
++              of_scan_flat_dt(early_init_dt_scan_memory, NULL);
++      else if (soc_info.mem_size)
+               add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M,
+                                 BOOT_MEM_RAM);
+       else
diff --git a/target/linux/ramips/patches-3.10/0107-PCI-MIPS-adds-rt2880-pci-support.patch b/target/linux/ramips/patches-3.10/0107-PCI-MIPS-adds-rt2880-pci-support.patch
deleted file mode 100644 (file)
index 7136f15..0000000
+++ /dev/null
@@ -1,319 +0,0 @@
-From 5d57ace094803c95230643941a47d749ff81d022 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 21 Mar 2013 18:27:29 +0100
-Subject: [PATCH 11/33] PCI: MIPS: adds rt2880 pci support
-
-Add support for the pci found on the rt2880 SoC.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/pci/Makefile     |    1 +
- arch/mips/pci/pci-rt2880.c |  281 ++++++++++++++++++++++++++++++++++++++++++++
- arch/mips/ralink/Kconfig   |    1 +
- 3 files changed, 283 insertions(+)
- create mode 100644 arch/mips/pci/pci-rt2880.c
-
---- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1
- obj-$(CONFIG_SNI_RM)          += fixup-sni.o ops-sni.o
- obj-$(CONFIG_LANTIQ)          += fixup-lantiq.o
- obj-$(CONFIG_PCI_LANTIQ)      += pci-lantiq.o ops-lantiq.o
-+obj-$(CONFIG_SOC_RT2880)      += pci-rt2880.o
- obj-$(CONFIG_SOC_RT3883)      += pci-rt3883.o
- obj-$(CONFIG_TANBAC_TB0219)   += fixup-tb0219.o
- obj-$(CONFIG_TANBAC_TB0226)   += fixup-tb0226.o
---- /dev/null
-+++ b/arch/mips/pci/pci-rt2880.c
-@@ -0,0 +1,281 @@
-+/*
-+ *  Ralink RT288x SoC PCI register definitions
-+ *
-+ *  Copyright (C) 2009 John Crispin <blogic@openwrt.org>
-+ *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
-+ *
-+ *  Parts of this file are based on Ralink's 2.6.21 BSP
-+ *
-+ *  This program is free software; you can redistribute it and/or modify it
-+ *  under the terms of the GNU General Public License version 2 as published
-+ *  by the Free Software Foundation.
-+ */
-+
-+#include <linux/types.h>
-+#include <linux/pci.h>
-+#include <linux/io.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/of_platform.h>
-+#include <linux/of_irq.h>
-+#include <linux/of_pci.h>
-+
-+#include <asm/mach-ralink/rt288x.h>
-+
-+#define RT2880_PCI_BASE               0x00440000
-+#define RT288X_CPU_IRQ_PCI    4
-+
-+#define RT2880_PCI_MEM_BASE   0x20000000
-+#define RT2880_PCI_MEM_SIZE   0x10000000
-+#define RT2880_PCI_IO_BASE    0x00460000
-+#define RT2880_PCI_IO_SIZE    0x00010000
-+
-+#define RT2880_PCI_REG_PCICFG_ADDR    0x00
-+#define RT2880_PCI_REG_PCIMSK_ADDR    0x0c
-+#define RT2880_PCI_REG_BAR0SETUP_ADDR 0x10
-+#define RT2880_PCI_REG_IMBASEBAR0_ADDR        0x18
-+#define RT2880_PCI_REG_CONFIG_ADDR    0x20
-+#define RT2880_PCI_REG_CONFIG_DATA    0x24
-+#define RT2880_PCI_REG_MEMBASE                0x28
-+#define RT2880_PCI_REG_IOBASE         0x2c
-+#define RT2880_PCI_REG_ID             0x30
-+#define RT2880_PCI_REG_CLASS          0x34
-+#define RT2880_PCI_REG_SUBID          0x38
-+#define RT2880_PCI_REG_ARBCTL         0x80
-+
-+static void __iomem *rt2880_pci_base;
-+static DEFINE_SPINLOCK(rt2880_pci_lock);
-+
-+static u32 rt2880_pci_reg_read(u32 reg)
-+{
-+      return readl(rt2880_pci_base + reg);
-+}
-+
-+static void rt2880_pci_reg_write(u32 val, u32 reg)
-+{
-+      writel(val, rt2880_pci_base + reg);
-+}
-+
-+static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
-+                                       unsigned int func, unsigned int where)
-+{
-+      return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
-+              0x80000000);
-+}
-+
-+static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
-+                                int where, int size, u32 *val)
-+{
-+      unsigned long flags;
-+      u32 address;
-+      u32 data;
-+
-+      address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
-+                                       PCI_FUNC(devfn), where);
-+
-+      spin_lock_irqsave(&rt2880_pci_lock, flags);
-+      rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
-+      data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
-+      spin_unlock_irqrestore(&rt2880_pci_lock, flags);
-+
-+      switch (size) {
-+      case 1:
-+              *val = (data >> ((where & 3) << 3)) & 0xff;
-+              break;
-+      case 2:
-+              *val = (data >> ((where & 3) << 3)) & 0xffff;
-+              break;
-+      case 4:
-+              *val = data;
-+              break;
-+      }
-+
-+      return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
-+                                 int where, int size, u32 val)
-+{
-+      unsigned long flags;
-+      u32 address;
-+      u32 data;
-+
-+      address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
-+                                       PCI_FUNC(devfn), where);
-+
-+      spin_lock_irqsave(&rt2880_pci_lock, flags);
-+      rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
-+      data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
-+
-+      switch (size) {
-+      case 1:
-+              data = (data & ~(0xff << ((where & 3) << 3))) |
-+                     (val << ((where & 3) << 3));
-+              break;
-+      case 2:
-+              data = (data & ~(0xffff << ((where & 3) << 3))) |
-+                     (val << ((where & 3) << 3));
-+              break;
-+      case 4:
-+              data = val;
-+              break;
-+      }
-+
-+      rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA);
-+      spin_unlock_irqrestore(&rt2880_pci_lock, flags);
-+
-+      return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static struct pci_ops rt2880_pci_ops = {
-+      .read   = rt2880_pci_config_read,
-+      .write  = rt2880_pci_config_write,
-+};
-+
-+static struct resource rt2880_pci_mem_resource = {
-+      .name   = "PCI MEM space",
-+      .start  = RT2880_PCI_MEM_BASE,
-+      .end    = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1,
-+      .flags  = IORESOURCE_MEM,
-+};
-+
-+static struct resource rt2880_pci_io_resource = {
-+      .name   = "PCI IO space",
-+      .start  = RT2880_PCI_IO_BASE,
-+      .end    = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1,
-+      .flags  = IORESOURCE_IO,
-+};
-+
-+static struct pci_controller rt2880_pci_controller = {
-+      .pci_ops        = &rt2880_pci_ops,
-+      .mem_resource   = &rt2880_pci_mem_resource,
-+      .io_resource    = &rt2880_pci_io_resource,
-+};
-+
-+static inline u32 rt2880_pci_read_u32(unsigned long reg)
-+{
-+      unsigned long flags;
-+      u32 address;
-+      u32 ret;
-+
-+      address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
-+
-+      spin_lock_irqsave(&rt2880_pci_lock, flags);
-+      rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
-+      ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
-+      spin_unlock_irqrestore(&rt2880_pci_lock, flags);
-+
-+      return ret;
-+}
-+
-+static inline void rt2880_pci_write_u32(unsigned long reg, u32 val)
-+{
-+      unsigned long flags;
-+      u32 address;
-+
-+      address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
-+
-+      spin_lock_irqsave(&rt2880_pci_lock, flags);
-+      rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
-+      rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
-+      spin_unlock_irqrestore(&rt2880_pci_lock, flags);
-+}
-+
-+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+      u16 cmd;
-+      int irq = -1;
-+
-+      if (dev->bus->number != 0)
-+              return irq;
-+
-+      switch (PCI_SLOT(dev->devfn)) {
-+      case 0x00:
-+              rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
-+              (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
-+              break;
-+      case 0x11:
-+              irq = RT288X_CPU_IRQ_PCI;
-+              break;
-+      default:
-+              printk("%s:%s[%d] trying to alloc unknown pci irq\n",
-+                     __FILE__, __func__, __LINE__);
-+              BUG();
-+              break;
-+      }
-+
-+      pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14);
-+      pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF);
-+      pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd);
-+      cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
-+             PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK |
-+             PCI_COMMAND_SERR | PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
-+      pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd);
-+      pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE,
-+                            dev->irq);
-+      return irq;
-+}
-+
-+static int rt288x_pci_probe(struct platform_device *pdev)
-+{
-+      void __iomem *io_map_base;
-+      int i;
-+
-+      rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
-+
-+      io_map_base = ioremap(RT2880_PCI_IO_BASE, RT2880_PCI_IO_SIZE);
-+      rt2880_pci_controller.io_map_base = (unsigned long) io_map_base;
-+      set_io_port_base((unsigned long) io_map_base);
-+
-+      ioport_resource.start = RT2880_PCI_IO_BASE;
-+      ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1;
-+
-+      rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
-+      for(i = 0; i < 0xfffff; i++) {}
-+
-+      rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
-+      rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
-+      rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE);
-+      rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE);
-+      rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
-+      rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
-+      rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
-+      rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
-+      rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
-+
-+      rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
-+      (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
-+
-+      register_pci_controller(&rt2880_pci_controller);
-+      return 0;
-+}
-+
-+int pcibios_plat_dev_init(struct pci_dev *dev)
-+{
-+      return 0;
-+}
-+
-+static const struct of_device_id rt288x_pci_match[] = {
-+      { .compatible = "ralink,rt288x-pci" },
-+      {},
-+};
-+MODULE_DEVICE_TABLE(of, rt288x_pci_match);
-+
-+static struct platform_driver rt288x_pci_driver = {
-+      .probe = rt288x_pci_probe,
-+      .driver = {
-+              .name = "rt288x-pci",
-+              .owner = THIS_MODULE,
-+              .of_match_table = rt288x_pci_match,
-+      },
-+};
-+
-+int __init pcibios_init(void)
-+{
-+      int ret = platform_driver_register(&rt288x_pci_driver);
-+      if (ret)
-+              pr_info("rt288x-pci: Error registering platform driver!");
-+      return ret;
-+}
-+
-+arch_initcall(pcibios_init);
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -15,6 +15,7 @@ choice
-       config SOC_RT288X
-               bool "RT288x"
-+              select HW_HAS_PCI
-       config SOC_RT305X
-               bool "RT305x"
diff --git a/target/linux/ramips/patches-3.10/0108-MIPS-ralink-add-rt_sysc_m32-helper.patch b/target/linux/ramips/patches-3.10/0108-MIPS-ralink-add-rt_sysc_m32-helper.patch
new file mode 100644 (file)
index 0000000..6d9c0d3
--- /dev/null
@@ -0,0 +1,26 @@
+From 1fe4d719d1c973c01f4b6a4c0de47bfac77e3eca Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 19 May 2013 00:42:23 +0200
+Subject: [PATCH 108/133] MIPS: ralink: add rt_sysc_m32 helper
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/mach-ralink/ralink_regs.h |    7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
++++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
+@@ -26,6 +26,13 @@ static inline u32 rt_sysc_r32(unsigned r
+       return __raw_readl(rt_sysc_membase + reg);
+ }
++static inline void rt_sysc_m32(u32 clr, u32 set, unsigned reg)
++{
++      u32 val = rt_sysc_r32(reg) & ~clr;
++
++      __raw_writel(val | set, rt_sysc_membase + reg);
++}
++
+ static inline void rt_memc_w32(u32 val, unsigned reg)
+ {
+       __raw_writel(val, rt_memc_membase + reg);
diff --git a/target/linux/ramips/patches-3.10/0108-PCI-MIPS-adds-mt7620a-pcie-driver.patch b/target/linux/ramips/patches-3.10/0108-PCI-MIPS-adds-mt7620a-pcie-driver.patch
deleted file mode 100644 (file)
index 2f883b3..0000000
+++ /dev/null
@@ -1,399 +0,0 @@
-From ded577553b06a85c12a89b8fbcfa2b51f30bc037 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sat, 18 May 2013 22:06:15 +0200
-Subject: [PATCH 13/33] PCI: MIPS: adds mt7620a pcie driver
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/pci/Makefile      |    1 +
- arch/mips/pci/pci-mt7620a.c |  363 +++++++++++++++++++++++++++++++++++++++++++
- arch/mips/ralink/Kconfig    |    1 +
- 3 files changed, 365 insertions(+)
- create mode 100644 arch/mips/pci/pci-mt7620a.c
-
---- /dev/null
-+++ b/arch/mips/pci/pci-mt7620a.c
-@@ -0,0 +1,363 @@
-+/*
-+ *  Ralink MT7620A SoC PCI support
-+ *
-+ *  Copyright (C) 2007-2013 Bruce Chang
-+ *  Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ *
-+ *  This program is free software; you can redistribute it and/or modify it
-+ *  under the terms of the GNU General Public License version 2 as published
-+ *  by the Free Software Foundation.
-+ */
-+
-+#include <linux/types.h>
-+#include <linux/pci.h>
-+#include <linux/io.h>
-+#include <linux/init.h>
-+#include <linux/delay.h>
-+#include <linux/interrupt.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_irq.h>
-+#include <linux/of_pci.h>
-+#include <linux/reset.h>
-+#include <linux/platform_device.h>
-+
-+#include <asm/mach-ralink/ralink_regs.h>
-+
-+#define RALINK_PCI_MM_MAP_BASE                0x20000000
-+#define RALINK_PCI_IO_MAP_BASE                0x10160000
-+
-+#define RALINK_INT_PCIE0              4
-+#define RALINK_SYSTEM_CONTROL_BASE    0xb0000000
-+#define RALINK_SYSCFG1                        0x14
-+#define RALINK_CLKCFG1                        0x30
-+#define RALINK_GPIOMODE                       0x60
-+#define RALINK_PCIE_CLK_GEN           0x7c
-+#define RALINK_PCIE_CLK_GEN1          0x80
-+#define PCIEPHY0_CFG                  0x90
-+#define PPLL_CFG1                     0x9c
-+#define PPLL_DRV                      0xa0
-+#define RALINK_PCI_HOST_MODE_EN               (1<<7)
-+#define RALINK_PCIE_RC_MODE_EN                (1<<8)
-+#define RALINK_PCIE_RST                       (1<<23)
-+#define RALINK_PCI_RST                        (1<<24)
-+#define RALINK_PCI_CLK_EN             (1<<19)
-+#define RALINK_PCIE_CLK_EN            (1<<21)
-+#define PCI_SLOTx2                    (1<<11)
-+#define PCI_SLOTx1                    (2<<11)
-+#define PDRV_SW_SET                   (1<<31)
-+#define LC_CKDRVPD_                   (1<<19)
-+
-+#define RALINK_PCI_CONFIG_ADDR                0x20
-+#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG    0x24
-+#define MEMORY_BASE                   0x0
-+#define RALINK_PCIE0_RST              (1<<26)
-+#define RALINK_PCI_BASE                       0xB0140000
-+#define RALINK_PCI_MEMBASE            0x28
-+#define RALINK_PCI_IOBASE             0x2C
-+
-+#define RT6855_PCIE0_OFFSET           0x2000
-+
-+#define RALINK_PCI_PCICFG_ADDR                0x00
-+#define RALINK_PCI0_BAR0SETUP_ADDR    0x10
-+#define RALINK_PCI0_IMBASEBAR0_ADDR   0x18
-+#define RALINK_PCI0_ID                        0x30
-+#define RALINK_PCI0_CLASS             0x34
-+#define RALINK_PCI0_SUBID             0x38
-+#define RALINK_PCI0_STATUS            0x50
-+#define RALINK_PCI_PCIMSK_ADDR                0x0C
-+
-+#define RALINK_PCIE0_CLK_EN           (1 << 26)
-+
-+#define BUSY                          0x80000000
-+#define WAITRETRY_MAX                 10
-+#define WRITE_MODE                    (1UL << 23)
-+#define DATA_SHIFT                    0
-+#define ADDR_SHIFT                    8
-+
-+
-+static void __iomem *bridge_base;
-+static void __iomem *pcie_base;
-+
-+static struct reset_control *rstpcie0;
-+
-+static inline void bridge_w32(u32 val, unsigned reg)
-+{
-+      iowrite32(val, bridge_base + reg);
-+}
-+
-+static inline u32 bridge_r32(unsigned reg)
-+{
-+      return ioread32(bridge_base + reg);
-+}
-+
-+static inline void pcie_w32(u32 val, unsigned reg)
-+{
-+      iowrite32(val, pcie_base + reg);
-+}
-+
-+static inline u32 pcie_r32(unsigned reg)
-+{
-+      return ioread32(pcie_base + reg);
-+}
-+
-+static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
-+{
-+      u32 val = pcie_r32(reg);
-+      val &= ~clr;
-+      val |= set;
-+      pcie_w32(val, reg);
-+}
-+
-+int wait_pciephy_busy(void)
-+{
-+      unsigned long reg_value = 0x0, retry = 0;
-+
-+      while (1) {
-+              //reg_value = rareg(READMODE, PCIEPHY0_CFG, 0);
-+              reg_value = pcie_r32(PCIEPHY0_CFG);
-+
-+              if (reg_value & BUSY)
-+                      mdelay(100);
-+              else
-+                      break;
-+              if (retry++ > WAITRETRY_MAX){
-+                      printk("PCIE-PHY retry failed.\n");
-+                      return -1;
-+              }
-+      }
-+      return 0;
-+}
-+
-+static void pcie_phy(unsigned long addr, unsigned long val)
-+{
-+      wait_pciephy_busy();
-+      pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT), PCIEPHY0_CFG);
-+      mdelay(1);
-+      wait_pciephy_busy();
-+}
-+
-+static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
-+{
-+      unsigned int slot = PCI_SLOT(devfn);
-+      u8 func = PCI_FUNC(devfn);
-+      u32 address;
-+      u32 data;
-+
-+      address = (((where & 0xF00) >> 8) << 24) | (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
-+      bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
-+      data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
-+
-+      switch (size) {
-+      case 1:
-+              *val = (data >> ((where & 3) << 3)) & 0xff;
-+              break;
-+      case 2:
-+              *val = (data >> ((where & 3) << 3)) & 0xffff;
-+              break;
-+      case 4:
-+              *val = data;
-+              break;
-+      }
-+
-+      return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
-+{
-+      unsigned int slot = PCI_SLOT(devfn);
-+      u8 func = PCI_FUNC(devfn);
-+      u32 address;
-+      u32 data;
-+
-+      address = (((where & 0xF00) >> 8) << 24) | (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
-+      bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
-+      data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
-+
-+      switch (size) {
-+      case 1:
-+              data = (data & ~(0xff << ((where & 3) << 3))) |
-+                      (val << ((where & 3) << 3));
-+              break;
-+      case 2:
-+              data = (data & ~(0xffff << ((where & 3) << 3))) |
-+                      (val << ((where & 3) << 3));
-+              break;
-+      case 4:
-+              data = val;
-+              break;
-+      }
-+
-+      bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
-+
-+      return PCIBIOS_SUCCESSFUL;
-+}
-+
-+struct pci_ops mt7620a_pci_ops= {
-+      .read   = pci_config_read,
-+      .write  = pci_config_write,
-+};
-+
-+static struct resource mt7620a_res_pci_mem1 = {
-+      .name   = "pci memory",
-+      .start  = RALINK_PCI_MM_MAP_BASE,
-+      .end    = (u32) ((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
-+      .flags  = IORESOURCE_MEM,
-+};
-+static struct resource mt7620a_res_pci_io1 = {
-+      .name   = "pci io",
-+      .start  = RALINK_PCI_IO_MAP_BASE,
-+      .end    = (u32) ((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
-+      .flags  = IORESOURCE_IO,
-+};
-+
-+struct pci_controller mt7620a_controller = {
-+      .pci_ops        = &mt7620a_pci_ops,
-+      .mem_resource   = &mt7620a_res_pci_mem1,
-+      .io_resource    = &mt7620a_res_pci_io1,
-+      .mem_offset     = 0x00000000UL,
-+      .io_offset      = 0x00000000UL,
-+      .io_map_base    = 0xa0000000,
-+};
-+
-+static int mt7620a_pci_probe(struct platform_device *pdev)
-+{
-+      struct resource *bridge_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+      struct resource *pcie_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-+
-+      rstpcie0 = devm_reset_control_get(&pdev->dev, "pcie0");
-+      if (IS_ERR(rstpcie0))
-+              return PTR_ERR(rstpcie0);
-+
-+      bridge_base = devm_request_and_ioremap(&pdev->dev, bridge_res);
-+        if (!bridge_base)
-+              return -ENOMEM;
-+
-+      pcie_base = devm_request_and_ioremap(&pdev->dev, pcie_res);
-+        if (!pcie_base)
-+              return -ENOMEM;
-+
-+      iomem_resource.start = 0;
-+      iomem_resource.end= ~0;
-+      ioport_resource.start= 0;
-+      ioport_resource.end = ~0;
-+
-+      /* PCIE: bypass PCIe DLL */
-+      pcie_phy(0x0, 0x80);
-+      pcie_phy(0x1, 0x04);
-+      /* PCIE: Elastic buffer control */
-+      pcie_phy(0x68, 0xB4);
-+
-+      reset_control_assert(rstpcie0);
-+      rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
-+      rt_sysc_m32(1<<19, 1<<31, PPLL_DRV);
-+      rt_sysc_m32(0x3 << 16, 0, RALINK_GPIOMODE);
-+
-+      reset_control_deassert(rstpcie0);
-+      rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
-+
-+      mdelay(100);
-+
-+      if (!(rt_sysc_r32(PPLL_CFG1) & 1<<23)) {
-+              printk("MT7620 PPLL unlock\n");
-+              reset_control_assert(rstpcie0);
-+              rt_sysc_m32(BIT(26), 0, RALINK_CLKCFG1);
-+              return 0;
-+      }
-+      rt_sysc_m32((0x1<<18) | (0x1<<17), (0x1 << 19) | (0x1 << 31), PPLL_DRV);
-+
-+      mdelay(100);
-+      reset_control_assert(rstpcie0);
-+      rt_sysc_m32(0x30, 2 << 4, RALINK_SYSCFG1);
-+
-+      rt_sysc_m32(~0x7fffffff, 0x80000000, RALINK_PCIE_CLK_GEN);
-+      rt_sysc_m32(~0x80ffffff, 0xa << 24, RALINK_PCIE_CLK_GEN1);
-+
-+      mdelay(50);
-+      reset_control_deassert(rstpcie0);
-+      pcie_m32(BIT(1), 0, RALINK_PCI_PCICFG_ADDR);
-+      mdelay(100);
-+
-+      if (( pcie_r32(RALINK_PCI0_STATUS) & 0x1) == 0) {
-+              reset_control_assert(rstpcie0);
-+              rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
-+              rt_sysc_m32(LC_CKDRVPD_, PDRV_SW_SET, PPLL_DRV);
-+              printk("PCIE0 no card, disable it(RST&CLK)\n");
-+      }
-+
-+      bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
-+      bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
-+
-+      pcie_w32(0x7FFF0000, RALINK_PCI0_BAR0SETUP_ADDR);
-+      pcie_w32(MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
-+      pcie_w32(0x08021814, RALINK_PCI0_ID);
-+      pcie_w32(0x06040001, RALINK_PCI0_CLASS);
-+      pcie_w32(0x28801814, RALINK_PCI0_SUBID);
-+      pcie_m32(0, BIT(20), RALINK_PCI_PCIMSK_ADDR);
-+
-+      register_pci_controller(&mt7620a_controller);
-+
-+      return 0;
-+}
-+
-+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+      const struct resource *res;
-+      u16 cmd;
-+      u32 val;
-+      int i, irq = 0;
-+
-+      if ((dev->bus->number == 0) && (slot == 0)) {
-+              pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR); //open 7FFF:2G; ENABLE
-+              pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, MEMORY_BASE);
-+              pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
-+      } else if ((dev->bus->number == 1) && (slot == 0x0)) {
-+              irq = RALINK_INT_PCIE0;
-+      } else {
-+              printk("bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
-+              return 0;
-+      }
-+
-+      for (i = 0; i < 6; i++) {
-+              res = &dev->resource[i];
-+      }
-+
-+      pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);  //configure cache line size 0x14
-+      pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF);  //configure latency timer 0x10
-+      pci_read_config_word(dev, PCI_COMMAND, &cmd);
-+
-+      // FIXME
-+      cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
-+      pci_write_config_word(dev, PCI_COMMAND, cmd);
-+      pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
-+      //pci_write_config_byte(dev, PCI_INTERRUPT_PIN, dev->irq);
-+
-+      return irq;
-+}
-+
-+int pcibios_plat_dev_init(struct pci_dev *dev)
-+{
-+      return 0;
-+}
-+
-+static const struct of_device_id mt7620a_pci_ids[] = {
-+      { .compatible = "ralink,mt7620a-pci" },
-+      {},
-+};
-+MODULE_DEVICE_TABLE(of, mt7620a_pci_ids);
-+
-+static struct platform_driver mt7620a_pci_driver = {
-+      .probe = mt7620a_pci_probe,
-+      .driver = {
-+              .name = "mt7620a-pci",
-+              .owner = THIS_MODULE,
-+              .of_match_table = of_match_ptr(mt7620a_pci_ids),
-+      },
-+};
-+
-+static int __init mt7620a_pci_init(void)
-+{
-+      return platform_driver_register(&mt7620a_pci_driver);
-+}
-+
-+arch_initcall(mt7620a_pci_init);
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -33,6 +33,7 @@ choice
-               bool "MT7620"
-               select USB_ARCH_HAS_OHCI
-               select USB_ARCH_HAS_EHCI
-+              select HW_HAS_PCI
- endchoice
---- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1
- obj-$(CONFIG_SNI_RM)          += fixup-sni.o ops-sni.o
- obj-$(CONFIG_LANTIQ)          += fixup-lantiq.o
- obj-$(CONFIG_PCI_LANTIQ)      += pci-lantiq.o ops-lantiq.o
-+obj-$(CONFIG_SOC_MT7620)      += pci-mt7620a.o
- obj-$(CONFIG_SOC_RT2880)      += pci-rt2880.o
- obj-$(CONFIG_SOC_RT3883)      += pci-rt3883.o
- obj-$(CONFIG_TANBAC_TB0219)   += fixup-tb0219.o
diff --git a/target/linux/ramips/patches-3.10/0109-MIPS-ralink-add-pseudo-pwm-led-trigger-based-on-time.patch b/target/linux/ramips/patches-3.10/0109-MIPS-ralink-add-pseudo-pwm-led-trigger-based-on-time.patch
new file mode 100644 (file)
index 0000000..193374e
--- /dev/null
@@ -0,0 +1,301 @@
+From ca21f813087ca5a8b02ec00efcd9c3f3fbf3bc1f Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 24 Mar 2013 17:17:17 +0100
+Subject: [PATCH 109/133] MIPS: ralink: add pseudo pwm led trigger based on
+ timer0
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/timer.c |  213 ++++++++++++++++++++++++++++++++++++++++++----
+ 1 file changed, 197 insertions(+), 16 deletions(-)
+
+--- a/arch/mips/ralink/timer.c
++++ b/arch/mips/ralink/timer.c
+@@ -12,6 +12,8 @@
+ #include <linux/timer.h>
+ #include <linux/of_gpio.h>
+ #include <linux/clk.h>
++#include <linux/leds.h>
++#include <linux/slab.h>
+ #include <asm/mach-ralink/ralink_regs.h>
+@@ -23,16 +25,34 @@
+ #define TMR0CTL_ENABLE                        BIT(7)
+ #define TMR0CTL_MODE_PERIODIC         BIT(4)
+-#define TMR0CTL_PRESCALER             1
++#define TMR0CTL_PRESCALER             2
+ #define TMR0CTL_PRESCALE_VAL          (0xf - TMR0CTL_PRESCALER)
+ #define TMR0CTL_PRESCALE_DIV          (65536 / BIT(TMR0CTL_PRESCALER))
++struct rt_timer_gpio {
++      struct list_head        list;
++      struct led_classdev     *led;
++};
++
+ struct rt_timer {
+-      struct device   *dev;
+-      void __iomem    *membase;
+-      int             irq;
+-      unsigned long   timer_freq;
+-      unsigned long   timer_div;
++      struct device           *dev;
++      void __iomem            *membase;
++      int                     irq;
++
++      unsigned long           timer_freq;
++      unsigned long           timer_div;
++
++      struct list_head        gpios;
++      struct led_trigger      led_trigger;
++      unsigned int            duty_cycle;
++      unsigned int            duty;
++
++      unsigned int            fade;
++      unsigned int            fade_min;
++      unsigned int            fade_max;
++      unsigned int            fade_speed;
++      unsigned int            fade_dir;
++      unsigned int            fade_count;
+ };
+ static inline void rt_timer_w32(struct rt_timer *rt, u8 reg, u32 val)
+@@ -48,18 +68,46 @@ static inline u32 rt_timer_r32(struct rt
+ static irqreturn_t rt_timer_irq(int irq, void *_rt)
+ {
+       struct rt_timer *rt =  (struct rt_timer *) _rt;
++      struct rt_timer_gpio *gpio;
++      unsigned int val;
+-      rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
++      if (rt->fade && (rt->fade_count++ > rt->fade_speed)) {
++              rt->fade_count = 0;
++              if (rt->duty_cycle <= rt->fade_min)
++                      rt->fade_dir = 1;
++              else if (rt->duty_cycle >= rt->fade_max)
++                      rt->fade_dir = 0;
++
++              if (rt->fade_dir)
++                      rt->duty_cycle += 1;
++              else
++                      rt->duty_cycle -= 1;
++
++      }
++
++      val = rt->timer_freq / rt->timer_div;
++      if (rt->duty)
++              val *= rt->duty_cycle;
++      else
++              val *= (100 - rt->duty_cycle);
++      val /= 100;
++
++      if (!list_empty(&rt->gpios))
++              list_for_each_entry(gpio, &rt->gpios, list)
++                      led_set_brightness(gpio->led, !!rt->duty);
++
++      rt->duty = !rt->duty;
++
++      rt_timer_w32(rt, TIMER_REG_TMR0LOAD, val + 1);
+       rt_timer_w32(rt, TIMER_REG_TMRSTAT, TMRSTAT_TMR0INT);
+       return IRQ_HANDLED;
+ }
+-
+ static int rt_timer_request(struct rt_timer *rt)
+ {
+-      int err = request_irq(rt->irq, rt_timer_irq, IRQF_DISABLED,
+-                                              dev_name(rt->dev), rt);
++      int err = devm_request_irq(rt->dev, rt->irq, rt_timer_irq,
++                                      IRQF_DISABLED, dev_name(rt->dev), rt);
+       if (err) {
+               dev_err(rt->dev, "failed to request irq\n");
+       } else {
+@@ -81,8 +129,6 @@ static int rt_timer_config(struct rt_tim
+       else
+               rt->timer_div = divisor;
+-      rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
+-
+       return 0;
+ }
+@@ -108,11 +154,128 @@ static void rt_timer_disable(struct rt_t
+       rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
+ }
++static ssize_t led_fade_show(struct device *dev,
++                              struct device_attribute *attr, char *buf)
++{
++      struct led_classdev *led_cdev = dev_get_drvdata(dev);
++      struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
++
++      return sprintf(buf, "speed: %d, min: %d, max: %d\n", rt->fade_speed, rt->fade_min, rt->fade_max);
++}
++
++static ssize_t led_fade_store(struct device *dev,
++              struct device_attribute *attr, const char *buf, size_t size)
++{
++      struct led_classdev *led_cdev = dev_get_drvdata(dev);
++      struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
++      unsigned int speed = 0, min = 0, max = 0;
++      ssize_t ret = -EINVAL;
++
++      ret = sscanf(buf, "%u %u %u", &speed, &min, &max);
++
++      if (ret == 3) {
++              rt->fade_speed = speed;
++              rt->fade_min = min;
++              rt->fade_max = max;
++              rt->fade = 1;
++      } else {
++              rt->fade = 0;
++      }
++
++      return size;
++}
++
++static DEVICE_ATTR(fade, 0644, led_fade_show, led_fade_store);
++
++static ssize_t led_duty_cycle_show(struct device *dev,
++                              struct device_attribute *attr, char *buf)
++{
++      struct led_classdev *led_cdev = dev_get_drvdata(dev);
++      struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
++
++      return sprintf(buf, "%u\n", rt->duty_cycle);
++}
++
++static ssize_t led_duty_cycle_store(struct device *dev,
++              struct device_attribute *attr, const char *buf, size_t size)
++{
++      struct led_classdev *led_cdev = dev_get_drvdata(dev);
++      struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
++      unsigned long state;
++      ssize_t ret = -EINVAL;
++
++      ret = kstrtoul(buf, 10, &state);
++      if (ret)
++              return ret;
++
++      if (state <= 100)
++              rt->duty_cycle = state;
++      else
++              rt->duty_cycle = 100;
++
++      rt->fade = 0;
++
++      return size;
++}
++
++static DEVICE_ATTR(duty_cycle, 0644, led_duty_cycle_show, led_duty_cycle_store);
++
++static void rt_timer_trig_activate(struct led_classdev *led_cdev)
++{
++      struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
++      struct rt_timer_gpio *gpio_data;
++      int rc;
++
++      led_cdev->trigger_data = NULL;
++      gpio_data = kzalloc(sizeof(*gpio_data), GFP_KERNEL);
++      if (!gpio_data)
++              return;
++
++      rc = device_create_file(led_cdev->dev, &dev_attr_duty_cycle);
++      if (rc)
++              goto err_gpio;
++      rc = device_create_file(led_cdev->dev, &dev_attr_fade);
++      if (rc)
++              goto err_out_duty_cycle;
++
++      led_cdev->activated = true;
++      led_cdev->trigger_data = gpio_data;
++      gpio_data->led = led_cdev;
++      list_add(&gpio_data->list, &rt->gpios);
++      led_cdev->trigger_data = gpio_data;
++      rt_timer_enable(rt);
++      return;
++
++err_out_duty_cycle:
++      device_remove_file(led_cdev->dev, &dev_attr_duty_cycle);
++
++err_gpio:
++      kfree(gpio_data);
++}
++
++static void rt_timer_trig_deactivate(struct led_classdev *led_cdev)
++{
++      struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
++      struct rt_timer_gpio *gpio_data = (struct rt_timer_gpio*) led_cdev->trigger_data;
++
++      if (led_cdev->activated) {
++              device_remove_file(led_cdev->dev, &dev_attr_duty_cycle);
++              device_remove_file(led_cdev->dev, &dev_attr_fade);
++              led_cdev->activated = false;
++      }
++
++      list_del(&gpio_data->list);
++      rt_timer_disable(rt);
++      led_set_brightness(led_cdev, LED_OFF);
++}
++
+ static int rt_timer_probe(struct platform_device *pdev)
+ {
+       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++      const __be32 *divisor;
+       struct rt_timer *rt;
+       struct clk *clk;
++      int ret;
+       rt = devm_kzalloc(&pdev->dev, sizeof(*rt), GFP_KERNEL);
+       if (!rt) {
+@@ -140,12 +303,29 @@ static int rt_timer_probe(struct platfor
+       if (!rt->timer_freq)
+               return -EINVAL;
++      rt->duty_cycle = 100;
+       rt->dev = &pdev->dev;
+       platform_set_drvdata(pdev, rt);
+-      rt_timer_request(rt);
+-      rt_timer_config(rt, 2);
+-      rt_timer_enable(rt);
++      ret = rt_timer_request(rt);
++      if (ret)
++              return ret;
++
++      divisor = of_get_property(pdev->dev.of_node, "ralink,divisor", NULL);
++      if (divisor)
++              rt_timer_config(rt, be32_to_cpu(*divisor));
++      else
++              rt_timer_config(rt, 200);
++
++      rt->led_trigger.name = "pwmtimer",
++      rt->led_trigger.activate = rt_timer_trig_activate,
++      rt->led_trigger.deactivate = rt_timer_trig_deactivate,
++
++      ret = led_trigger_register(&rt->led_trigger);
++      if (ret)
++              return ret;
++
++      INIT_LIST_HEAD(&rt->gpios);
+       dev_info(&pdev->dev, "maximum frequncy is %luHz\n", rt->timer_freq);
+@@ -156,6 +336,7 @@ static int rt_timer_remove(struct platfo
+ {
+       struct rt_timer *rt = platform_get_drvdata(pdev);
++      led_trigger_unregister(&rt->led_trigger);
+       rt_timer_disable(rt);
+       rt_timer_free(rt);
+@@ -180,6 +361,6 @@ static struct platform_driver rt_timer_d
+ module_platform_driver(rt_timer_driver);
+-MODULE_DESCRIPTION("Ralink RT2880 timer");
++MODULE_DESCRIPTION("Ralink RT2880 timer / pseudo pwm");
+ MODULE_AUTHOR("John Crispin <blogic@openwrt.org");
+ MODULE_LICENSE("GPL");
diff --git a/target/linux/ramips/patches-3.10/0109-NET-multi-phy-support.patch b/target/linux/ramips/patches-3.10/0109-NET-multi-phy-support.patch
deleted file mode 100644 (file)
index 345ee14..0000000
+++ /dev/null
@@ -1,54 +0,0 @@
-From 7407b7d178e783074861a73da858b099f870270d Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sat, 11 May 2013 23:40:19 +0200
-Subject: [PATCH 14/33] NET: multi phy support
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/net/phy/phy.c |    9 ++++++---
- include/linux/phy.h   |    2 +-
- 2 files changed, 7 insertions(+), 4 deletions(-)
-
---- a/drivers/net/phy/phy.c
-+++ b/drivers/net/phy/phy.c
-@@ -820,7 +820,8 @@ void phy_state_machine(struct work_struc
-                        * negotiation for now */
-                       if (!phydev->link) {
-                               phydev->state = PHY_NOLINK;
--                              netif_carrier_off(phydev->attached_dev);
-+                              if (!phydev->no_auto_carrier_off)
-+                                      netif_carrier_off(phydev->attached_dev);
-                               phydev->adjust_link(phydev->attached_dev);
-                               break;
-                       }
-@@ -890,7 +891,8 @@ void phy_state_machine(struct work_struc
-                               netif_carrier_on(phydev->attached_dev);
-                       } else {
-                               phydev->state = PHY_NOLINK;
--                              netif_carrier_off(phydev->attached_dev);
-+                              if (!phydev->no_auto_carrier_off)
-+                                      netif_carrier_off(phydev->attached_dev);
-                       }
-                       phydev->adjust_link(phydev->attached_dev);
-@@ -902,7 +904,8 @@ void phy_state_machine(struct work_struc
-               case PHY_HALTED:
-                       if (phydev->link) {
-                               phydev->link = 0;
--                              netif_carrier_off(phydev->attached_dev);
-+                              if (!phydev->no_auto_carrier_off)
-+                                      netif_carrier_off(phydev->attached_dev);
-                               phydev->adjust_link(phydev->attached_dev);
-                       }
-                       break;
---- a/include/linux/phy.h
-+++ b/include/linux/phy.h
-@@ -298,7 +298,7 @@ struct phy_device {
-       struct phy_c45_device_ids c45_ids;
-       bool is_c45;
--
-+      bool no_auto_carrier_off;
-       enum phy_state state;
-       u32 dev_flags;
diff --git a/target/linux/ramips/patches-3.10/0110-MIPS-ralink-add-a-helper-for-reading-the-ECO-version.patch b/target/linux/ramips/patches-3.10/0110-MIPS-ralink-add-a-helper-for-reading-the-ECO-version.patch
new file mode 100644 (file)
index 0000000..7a64640
--- /dev/null
@@ -0,0 +1,23 @@
+From f57edea9db0f7f437bc4f2ae408f6dd8bfbb9062 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 16 Mar 2014 04:53:02 +0000
+Subject: [PATCH 110/133] MIPS: ralink: add a helper for reading the ECO
+ version
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/mach-ralink/mt7620.h |    5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/mips/include/asm/mach-ralink/mt7620.h
++++ b/arch/mips/include/asm/mach-ralink/mt7620.h
+@@ -79,4 +79,9 @@
+ #define MT7620_GPIO_MODE_EPHY         BIT(15)
+ #define MT7620_GPIO_MODE_WDT          BIT(22)
++static inline int mt7620_get_eco(void)
++{
++      return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;
++}
++
+ #endif
diff --git a/target/linux/ramips/patches-3.10/0110-NET-add-of_get_mac_address_mtd.patch b/target/linux/ramips/patches-3.10/0110-NET-add-of_get_mac_address_mtd.patch
deleted file mode 100644 (file)
index 408326d..0000000
+++ /dev/null
@@ -1,76 +0,0 @@
-From 2a41724b2d0af9b4444572c4302570a3af377715 Mon Sep 17 00:00:00 2001<