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perf: fix build on PowerPC
[openwrt/openwrt.git] / package / kernel / lantiq / ltq-atm / src / ltq_atm.c
1 /******************************************************************************
2 **
3 ** FILE NAME : ifxmips_atm_core.c
4 ** PROJECT : UEIP
5 ** MODULES : ATM
6 **
7 ** DATE : 7 Jul 2009
8 ** AUTHOR : Xu Liang
9 ** DESCRIPTION : ATM driver common source file (core functions)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
13 **
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
18 **
19 ** HISTORY
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
22 **
23 ** Copyright 2017 Alexander Couzens <lynxis@fe80.eu>
24 *******************************************************************************/
25
26 #define IFX_ATM_VER_MAJOR 1
27 #define IFX_ATM_VER_MID 0
28 #define IFX_ATM_VER_MINOR 26
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/version.h>
33 #include <linux/types.h>
34 #include <linux/errno.h>
35 #include <linux/proc_fs.h>
36 #include <linux/init.h>
37 #include <linux/ioctl.h>
38 #include <linux/atmdev.h>
39 #include <linux/platform_device.h>
40 #include <linux/of_device.h>
41 #include <linux/atm.h>
42 #include <linux/clk.h>
43 #include <linux/interrupt.h>
44 #include <linux/version.h>
45 #ifdef CONFIG_XFRM
46 #include <net/xfrm.h>
47 #endif
48
49 #include <lantiq_soc.h>
50
51 #include "ifxmips_atm_core.h"
52
53 #define MODULE_PARM_ARRAY(a, b) module_param_array(a, int, NULL, 0)
54 #define MODULE_PARM(a, b) module_param(a, int, 0)
55
56 /*!
57 \brief QSB cell delay variation due to concurrency
58 */
59 static int qsb_tau = 1; /* QSB cell delay variation due to concurrency */
60 /*!
61 \brief QSB scheduler burst length
62 */
63 static int qsb_srvm = 0x0F; /* QSB scheduler burst length */
64 /*!
65 \brief QSB time step, all legal values are 1, 2, 4
66 */
67 static int qsb_tstep = 4 ; /* QSB time step, all legal values are 1, 2, 4 */
68
69 /*!
70 \brief Write descriptor delay
71 */
72 static int write_descriptor_delay = 0x20; /* Write descriptor delay */
73
74 /*!
75 \brief AAL5 padding byte ('~')
76 */
77 static int aal5_fill_pattern = 0x007E; /* AAL5 padding byte ('~') */
78 /*!
79 \brief Max frame size for RX
80 */
81 static int aal5r_max_packet_size = 0x0700; /* Max frame size for RX */
82 /*!
83 \brief Min frame size for RX
84 */
85 static int aal5r_min_packet_size = 0x0000; /* Min frame size for RX */
86 /*!
87 \brief Max frame size for TX
88 */
89 static int aal5s_max_packet_size = 0x0700; /* Max frame size for TX */
90 /*!
91 \brief Min frame size for TX
92 */
93 static int aal5s_min_packet_size = 0x0000; /* Min frame size for TX */
94 /*!
95 \brief Drop error packet in RX path
96 */
97 static int aal5r_drop_error_packet = 1; /* Drop error packet in RX path */
98
99 /*!
100 \brief Number of descriptors per DMA RX channel
101 */
102 static int dma_rx_descriptor_length = 128; /* Number of descriptors per DMA RX channel */
103 /*!
104 \brief Number of descriptors per DMA TX channel
105 */
106 static int dma_tx_descriptor_length = 64; /* Number of descriptors per DMA TX channel */
107 /*!
108 \brief PPE core clock cycles between descriptor write and effectiveness in external RAM
109 */
110 static int dma_rx_clp1_descriptor_threshold = 38;
111 /*@}*/
112
113 MODULE_PARM(qsb_tau, "i");
114 MODULE_PARM_DESC(qsb_tau, "Cell delay variation. Value must be > 0");
115 MODULE_PARM(qsb_srvm, "i");
116 MODULE_PARM_DESC(qsb_srvm, "Maximum burst size");
117 MODULE_PARM(qsb_tstep, "i");
118 MODULE_PARM_DESC(qsb_tstep, "n*32 cycles per sbs cycles n=1,2,4");
119
120 MODULE_PARM(write_descriptor_delay, "i");
121 MODULE_PARM_DESC(write_descriptor_delay, "PPE core clock cycles between descriptor write and effectiveness in external RAM");
122
123 MODULE_PARM(aal5_fill_pattern, "i");
124 MODULE_PARM_DESC(aal5_fill_pattern, "Filling pattern (PAD) for AAL5 frames");
125 MODULE_PARM(aal5r_max_packet_size, "i");
126 MODULE_PARM_DESC(aal5r_max_packet_size, "Max packet size in byte for downstream AAL5 frames");
127 MODULE_PARM(aal5r_min_packet_size, "i");
128 MODULE_PARM_DESC(aal5r_min_packet_size, "Min packet size in byte for downstream AAL5 frames");
129 MODULE_PARM(aal5s_max_packet_size, "i");
130 MODULE_PARM_DESC(aal5s_max_packet_size, "Max packet size in byte for upstream AAL5 frames");
131 MODULE_PARM(aal5s_min_packet_size, "i");
132 MODULE_PARM_DESC(aal5s_min_packet_size, "Min packet size in byte for upstream AAL5 frames");
133 MODULE_PARM(aal5r_drop_error_packet, "i");
134 MODULE_PARM_DESC(aal5r_drop_error_packet, "Non-zero value to drop error packet for downstream");
135
136 MODULE_PARM(dma_rx_descriptor_length, "i");
137 MODULE_PARM_DESC(dma_rx_descriptor_length, "Number of descriptor assigned to DMA RX channel (>16)");
138 MODULE_PARM(dma_tx_descriptor_length, "i");
139 MODULE_PARM_DESC(dma_tx_descriptor_length, "Number of descriptor assigned to DMA TX channel (>16)");
140 MODULE_PARM(dma_rx_clp1_descriptor_threshold, "i");
141 MODULE_PARM_DESC(dma_rx_clp1_descriptor_threshold, "Descriptor threshold for cells with cell loss priority 1");
142
143
144
145 /*
146 * ####################################
147 * Definition
148 * ####################################
149 */
150
151 #ifdef CONFIG_AMAZON_SE
152 #define ENABLE_LESS_CACHE_INV 1
153 #define LESS_CACHE_INV_LEN 96
154 #endif
155
156 #define DUMP_SKB_LEN ~0
157
158
159
160 /*
161 * ####################################
162 * Declaration
163 * ####################################
164 */
165
166 /*
167 * Network Operations
168 */
169 static int ppe_ioctl(struct atm_dev *, unsigned int, void *);
170 static int ppe_open(struct atm_vcc *);
171 static void ppe_close(struct atm_vcc *);
172 static int ppe_send(struct atm_vcc *, struct sk_buff *);
173 static int ppe_send_oam(struct atm_vcc *, void *, int);
174 static int ppe_change_qos(struct atm_vcc *, struct atm_qos *, int);
175
176 /*
177 * ADSL LED
178 */
179 static inline void adsl_led_flash(void);
180
181 /*
182 * 64-bit operation used by MIB calculation
183 */
184 static inline void u64_add_u32(ppe_u64_t, unsigned int, ppe_u64_t *);
185
186 /*
187 * buffer manage functions
188 */
189 static inline struct sk_buff* alloc_skb_rx(void);
190 static inline struct sk_buff* alloc_skb_tx(unsigned int);
191 static inline void atm_free_tx_skb_vcc(struct sk_buff *, struct atm_vcc *);
192 static inline struct sk_buff *get_skb_rx_pointer(unsigned int);
193 static inline int get_tx_desc(unsigned int);
194
195 /*
196 * mailbox handler and signal function
197 */
198 static inline void mailbox_oam_rx_handler(void);
199 static inline void mailbox_aal_rx_handler(void);
200 static irqreturn_t mailbox_irq_handler(int, void *);
201 static inline void mailbox_signal(unsigned int, int);
202 static void do_ppe_tasklet(unsigned long);
203 #if LINUX_VERSION_CODE < KERNEL_VERSION(5,9,0)
204 DECLARE_TASKLET(g_dma_tasklet, do_ppe_tasklet, 0);
205 #else
206 DECLARE_TASKLET_OLD(g_dma_tasklet, do_ppe_tasklet);
207 #endif
208
209 /*
210 * QSB & HTU setting functions
211 */
212 static void set_qsb(struct atm_vcc *, struct atm_qos *, unsigned int);
213 static void qsb_global_set(void);
214 static inline void set_htu_entry(unsigned int, unsigned int, unsigned int, int, int);
215 static inline void clear_htu_entry(unsigned int);
216 static void validate_oam_htu_entry(void);
217 static void invalidate_oam_htu_entry(void);
218
219 /*
220 * look up for connection ID
221 */
222 static inline int find_vpi(unsigned int);
223 static inline int find_vpivci(unsigned int, unsigned int);
224 static inline int find_vcc(struct atm_vcc *);
225
226 static inline int ifx_atm_version(const struct ltq_atm_ops *ops, char *);
227
228 /*
229 * Init & clean-up functions
230 */
231 static inline void check_parameters(void);
232 static inline int init_priv_data(void);
233 static inline void clear_priv_data(void);
234 static inline void init_rx_tables(void);
235 static inline void init_tx_tables(void);
236
237 /*
238 * Exteranl Function
239 */
240 #if defined(CONFIG_IFX_OAM) || defined(CONFIG_IFX_OAM_MODULE)
241 extern void ifx_push_oam(unsigned char *);
242 #else
243 static inline void ifx_push_oam(unsigned char *dummy) {}
244 #endif
245
246 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
247 extern int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr);
248 extern int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *);
249
250 extern int (*ifx_mei_atm_showtime_exit)(void);
251 extern int ifx_mei_atm_led_blink(void);
252 #else
253 static inline int ifx_mei_atm_led_blink(void) { return 0; }
254 static inline int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr)
255 {
256 if ( is_showtime != NULL )
257 *is_showtime = 0;
258 return 0;
259 }
260 int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL;
261 EXPORT_SYMBOL(ifx_mei_atm_showtime_enter);
262
263 int (*ifx_mei_atm_showtime_exit)(void) = NULL;
264 EXPORT_SYMBOL(ifx_mei_atm_showtime_exit);
265
266 #endif
267
268 static struct atm_priv_data g_atm_priv_data;
269
270 static struct atmdev_ops g_ifx_atm_ops = {
271 .open = ppe_open,
272 .close = ppe_close,
273 .ioctl = ppe_ioctl,
274 .send = ppe_send,
275 .send_oam = ppe_send_oam,
276 .change_qos = ppe_change_qos,
277 .owner = THIS_MODULE,
278 };
279
280 static int g_showtime = 0;
281 static void *g_xdata_addr = NULL;
282
283 static int ppe_ioctl(struct atm_dev *dev, unsigned int cmd, void *arg)
284 {
285 int ret = 0;
286 atm_cell_ifEntry_t mib_cell;
287 atm_aal5_ifEntry_t mib_aal5;
288 atm_aal5_vcc_x_t mib_vcc;
289 unsigned int value;
290 int conn;
291
292 if ( _IOC_TYPE(cmd) != PPE_ATM_IOC_MAGIC
293 || _IOC_NR(cmd) >= PPE_ATM_IOC_MAXNR )
294 return -ENOTTY;
295
296 if ( _IOC_DIR(cmd) & _IOC_READ )
297 ret = !access_ok(arg, _IOC_SIZE(cmd));
298 else if ( _IOC_DIR(cmd) & _IOC_WRITE )
299 ret = !access_ok(arg, _IOC_SIZE(cmd));
300 if ( ret )
301 return -EFAULT;
302
303 switch (cmd) {
304 case PPE_ATM_MIB_CELL: /* cell level MIB */
305 /* These MIB should be read at ARC side, now put zero only. */
306 mib_cell.ifHCInOctets_h = 0;
307 mib_cell.ifHCInOctets_l = 0;
308 mib_cell.ifHCOutOctets_h = 0;
309 mib_cell.ifHCOutOctets_l = 0;
310 mib_cell.ifInErrors = 0;
311 mib_cell.ifInUnknownProtos = WAN_MIB_TABLE->wrx_drophtu_cell;
312 mib_cell.ifOutErrors = 0;
313
314 ret = sizeof(mib_cell) - copy_to_user(arg, &mib_cell, sizeof(mib_cell));
315 break;
316
317 case PPE_ATM_MIB_AAL5: /* AAL5 MIB */
318 value = WAN_MIB_TABLE->wrx_total_byte;
319 u64_add_u32(g_atm_priv_data.wrx_total_byte, value - g_atm_priv_data.prev_wrx_total_byte, &g_atm_priv_data.wrx_total_byte);
320 g_atm_priv_data.prev_wrx_total_byte = value;
321 mib_aal5.ifHCInOctets_h = g_atm_priv_data.wrx_total_byte.h;
322 mib_aal5.ifHCInOctets_l = g_atm_priv_data.wrx_total_byte.l;
323
324 value = WAN_MIB_TABLE->wtx_total_byte;
325 u64_add_u32(g_atm_priv_data.wtx_total_byte, value - g_atm_priv_data.prev_wtx_total_byte, &g_atm_priv_data.wtx_total_byte);
326 g_atm_priv_data.prev_wtx_total_byte = value;
327 mib_aal5.ifHCOutOctets_h = g_atm_priv_data.wtx_total_byte.h;
328 mib_aal5.ifHCOutOctets_l = g_atm_priv_data.wtx_total_byte.l;
329
330 mib_aal5.ifInUcastPkts = g_atm_priv_data.wrx_pdu;
331 mib_aal5.ifOutUcastPkts = WAN_MIB_TABLE->wtx_total_pdu;
332 mib_aal5.ifInErrors = WAN_MIB_TABLE->wrx_err_pdu;
333 mib_aal5.ifInDiscards = WAN_MIB_TABLE->wrx_dropdes_pdu + g_atm_priv_data.wrx_drop_pdu;
334 mib_aal5.ifOutErros = g_atm_priv_data.wtx_err_pdu;
335 mib_aal5.ifOutDiscards = g_atm_priv_data.wtx_drop_pdu;
336
337 ret = sizeof(mib_aal5) - copy_to_user(arg, &mib_aal5, sizeof(mib_aal5));
338 break;
339
340 case PPE_ATM_MIB_VCC: /* VCC related MIB */
341 copy_from_user(&mib_vcc, arg, sizeof(mib_vcc));
342 conn = find_vpivci(mib_vcc.vpi, mib_vcc.vci);
343 if (conn >= 0) {
344 mib_vcc.mib_vcc.aal5VccCrcErrors = g_atm_priv_data.conn[conn].aal5_vcc_crc_err;
345 mib_vcc.mib_vcc.aal5VccOverSizedSDUs = g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu;
346 mib_vcc.mib_vcc.aal5VccSarTimeOuts = 0; /* no timer support */
347 ret = sizeof(mib_vcc) - copy_to_user(arg, &mib_vcc, sizeof(mib_vcc));
348 } else
349 ret = -EINVAL;
350 break;
351
352 default:
353 ret = -ENOIOCTLCMD;
354 }
355
356 return ret;
357 }
358
359 static int ppe_open(struct atm_vcc *vcc)
360 {
361 int ret;
362 short vpi = vcc->vpi;
363 int vci = vcc->vci;
364 struct port *port = &g_atm_priv_data.port[(int)vcc->dev->dev_data];
365 int conn;
366 int f_enable_irq = 0;
367
368 if ( vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0 )
369 return -EPROTONOSUPPORT;
370
371 #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND
372 /* check bandwidth */
373 if ( (vcc->qos.txtp.traffic_class == ATM_CBR && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
374 || (vcc->qos.txtp.traffic_class == ATM_VBR_RT && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
375 #if 0
376 || (vcc->qos.txtp.traffic_class == ATM_VBR_NRT && vcc->qos.txtp.scr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
377 #endif
378 || (vcc->qos.txtp.traffic_class == ATM_UBR_PLUS && vcc->qos.txtp.min_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) )
379 {
380 ret = -EINVAL;
381 goto PPE_OPEN_EXIT;
382 }
383 #endif
384
385 /* check existing vpi,vci */
386 conn = find_vpivci(vpi, vci);
387 if ( conn >= 0 ) {
388 ret = -EADDRINUSE;
389 goto PPE_OPEN_EXIT;
390 }
391
392 /* check whether it need to enable irq */
393 if ( g_atm_priv_data.conn_table == 0 )
394 f_enable_irq = 1;
395
396 /* allocate connection */
397 for ( conn = 0; conn < MAX_PVC_NUMBER; conn++ ) {
398 if ( test_and_set_bit(conn, &g_atm_priv_data.conn_table) == 0 ) {
399 g_atm_priv_data.conn[conn].vcc = vcc;
400 break;
401 }
402 }
403 if ( conn == MAX_PVC_NUMBER ) {
404 ret = -EINVAL;
405 goto PPE_OPEN_EXIT;
406 }
407
408 /* reserve bandwidth */
409 switch ( vcc->qos.txtp.traffic_class ) {
410 case ATM_CBR:
411 case ATM_VBR_RT:
412 port->tx_current_cell_rate += vcc->qos.txtp.max_pcr;
413 break;
414 case ATM_VBR_NRT:
415 #if 0
416 port->tx_current_cell_rate += vcc->qos.txtp.scr;
417 #endif
418 break;
419 case ATM_UBR_PLUS:
420 port->tx_current_cell_rate += vcc->qos.txtp.min_pcr;
421 break;
422 }
423
424 /* set qsb */
425 set_qsb(vcc, &vcc->qos, conn);
426
427 /* update atm_vcc structure */
428 vcc->itf = (int)vcc->dev->dev_data;
429 vcc->vpi = vpi;
430 vcc->vci = vci;
431 set_bit(ATM_VF_READY, &vcc->flags);
432
433 /* enable irq */
434 if ( f_enable_irq ) {
435 *MBOX_IGU1_ISRC = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM);
436 *MBOX_IGU1_IER = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM);
437
438 enable_irq(PPE_MAILBOX_IGU1_INT);
439 }
440
441 /* set port */
442 WTX_QUEUE_CONFIG(conn + FIRST_QSB_QID)->sbid = (int)vcc->dev->dev_data;
443
444 /* set htu entry */
445 set_htu_entry(vpi, vci, conn, vcc->qos.aal == ATM_AAL5 ? 1 : 0, 0);
446
447 *MBOX_IGU1_ISRC |= (1 << (conn + FIRST_QSB_QID + 16));
448 *MBOX_IGU1_IER |= (1 << (conn + FIRST_QSB_QID + 16));
449
450 ret = 0;
451
452 PPE_OPEN_EXIT:
453 return ret;
454 }
455
456 static void ppe_close(struct atm_vcc *vcc)
457 {
458 int conn;
459 struct port *port;
460 struct connection *connection;
461 if ( vcc == NULL )
462 return;
463
464 /* get connection id */
465 conn = find_vcc(vcc);
466 if ( conn < 0 ) {
467 pr_err("can't find vcc\n");
468 goto PPE_CLOSE_EXIT;
469 }
470 connection = &g_atm_priv_data.conn[conn];
471 port = &g_atm_priv_data.port[connection->port];
472
473 /* clear htu */
474 clear_htu_entry(conn);
475
476 /* release connection */
477 connection->vcc = NULL;
478 connection->aal5_vcc_crc_err = 0;
479 connection->aal5_vcc_oversize_sdu = 0;
480 clear_bit(conn, &g_atm_priv_data.conn_table);
481
482 /* disable irq */
483 if ( g_atm_priv_data.conn_table == 0 )
484 disable_irq(PPE_MAILBOX_IGU1_INT);
485
486 /* release bandwidth */
487 switch ( vcc->qos.txtp.traffic_class )
488 {
489 case ATM_CBR:
490 case ATM_VBR_RT:
491 port->tx_current_cell_rate -= vcc->qos.txtp.max_pcr;
492 break;
493 case ATM_VBR_NRT:
494 #if 0
495 port->tx_current_cell_rate -= vcc->qos.txtp.scr;
496 #endif
497 break;
498 case ATM_UBR_PLUS:
499 port->tx_current_cell_rate -= vcc->qos.txtp.min_pcr;
500 break;
501 }
502
503 /* wait for incoming packets to be processed by upper layers */
504 tasklet_unlock_wait(&g_dma_tasklet);
505
506 PPE_CLOSE_EXIT:
507 return;
508 }
509
510 static int ppe_send(struct atm_vcc *vcc, struct sk_buff *skb)
511 {
512 int ret;
513 int conn;
514 int desc_base;
515 int byteoff;
516 int required;
517 /* the len of the data without offset and header */
518 int datalen;
519 unsigned long flags;
520 struct tx_descriptor reg_desc = {0};
521 struct tx_inband_header *header;
522
523 if ( vcc == NULL || skb == NULL )
524 return -EINVAL;
525
526
527 conn = find_vcc(vcc);
528 if ( conn < 0 ) {
529 ret = -EINVAL;
530 goto FIND_VCC_FAIL;
531 }
532
533 if ( !g_showtime ) {
534 pr_debug("not in showtime\n");
535 ret = -EIO;
536 goto PPE_SEND_FAIL;
537 }
538
539 byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);
540 required = sizeof(*header) + byteoff;
541 if (!skb_clone_writable(skb, required)) {
542 int expand_by = 0;
543 int ret;
544
545 if (skb_headroom(skb) < required)
546 expand_by = required - skb_headroom(skb);
547
548 ret = pskb_expand_head(skb, expand_by, 0, GFP_ATOMIC);
549 if (ret) {
550 printk("pskb_expand_head failed.\n");
551 atm_free_tx_skb_vcc(skb, vcc);
552 return ret;
553 }
554 }
555
556 datalen = skb->len;
557 header = (void *)skb_push(skb, byteoff + TX_INBAND_HEADER_LENGTH);
558
559
560 if ( vcc->qos.aal == ATM_AAL5 ) {
561 /* setup inband trailer */
562 header->uu = 0;
563 header->cpi = 0;
564 header->pad = aal5_fill_pattern;
565 header->res1 = 0;
566
567 /* setup cell header */
568 header->clp = (vcc->atm_options & ATM_ATMOPT_CLP) ? 1 : 0;
569 header->pti = ATM_PTI_US0;
570 header->vci = vcc->vci;
571 header->vpi = vcc->vpi;
572 header->gfc = 0;
573
574 /* setup descriptor */
575 reg_desc.dataptr = (unsigned int)skb->data >> 2;
576 reg_desc.datalen = datalen;
577 reg_desc.byteoff = byteoff;
578 reg_desc.iscell = 0;
579 } else {
580 reg_desc.dataptr = (unsigned int)skb->data >> 2;
581 reg_desc.datalen = skb->len;
582 reg_desc.byteoff = byteoff;
583 reg_desc.iscell = 1;
584 }
585
586 reg_desc.own = 1;
587 reg_desc.c = 1;
588 reg_desc.sop = reg_desc.eop = 1;
589
590 spin_lock_irqsave(&g_atm_priv_data.conn[conn].lock, flags);
591 desc_base = get_tx_desc(conn);
592 if ( desc_base < 0 ) {
593 spin_unlock_irqrestore(&g_atm_priv_data.conn[conn].lock, flags);
594 pr_debug("ALLOC_TX_CONNECTION_FAIL\n");
595 ret = -EIO;
596 goto PPE_SEND_FAIL;
597 }
598 /* update descriptor send pointer */
599 if ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL )
600 dev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]);
601 g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb;
602
603 spin_unlock_irqrestore(&g_atm_priv_data.conn[conn].lock, flags);
604
605 if ( vcc->stats )
606 atomic_inc(&vcc->stats->tx);
607 if ( vcc->qos.aal == ATM_AAL5 )
608 g_atm_priv_data.wtx_pdu++;
609 /* write discriptor to memory and write back cache */
610 g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc;
611 dma_cache_wback((unsigned long)skb->data, skb->len);
612
613 mailbox_signal(conn, 1);
614
615 adsl_led_flash();
616
617 return 0;
618
619 FIND_VCC_FAIL:
620 pr_err("FIND_VCC_FAIL\n");
621 g_atm_priv_data.wtx_err_pdu++;
622 dev_kfree_skb_any(skb);
623 return ret;
624
625 PPE_SEND_FAIL:
626 if ( vcc->qos.aal == ATM_AAL5 )
627 g_atm_priv_data.wtx_drop_pdu++;
628 if ( vcc->stats )
629 atomic_inc(&vcc->stats->tx_err);
630 dev_kfree_skb_any(skb);
631 return ret;
632 }
633
634 /* operation and maintainance */
635 static int ppe_send_oam(struct atm_vcc *vcc, void *cell, int flags)
636 {
637 int conn;
638 struct uni_cell_header *uni_cell_header = (struct uni_cell_header *)cell;
639 int desc_base;
640 struct sk_buff *skb;
641 struct tx_descriptor reg_desc = {0};
642
643 if ( ((uni_cell_header->pti == ATM_PTI_SEGF5 || uni_cell_header->pti == ATM_PTI_E2EF5)
644 && find_vpivci(uni_cell_header->vpi, uni_cell_header->vci) < 0)
645 || ((uni_cell_header->vci == 0x03 || uni_cell_header->vci == 0x04)
646 && find_vpi(uni_cell_header->vpi) < 0) )
647 {
648 g_atm_priv_data.wtx_err_oam++;
649 return -EINVAL;
650 }
651
652 if ( !g_showtime ) {
653 pr_err("not in showtime\n");
654 g_atm_priv_data.wtx_drop_oam++;
655 return -EIO;
656 }
657
658 conn = find_vcc(vcc);
659 if ( conn < 0 ) {
660 pr_err("FIND_VCC_FAIL\n");
661 g_atm_priv_data.wtx_drop_oam++;
662 return -EINVAL;
663 }
664
665 skb = alloc_skb_tx(CELL_SIZE);
666 if ( skb == NULL ) {
667 pr_err("ALLOC_SKB_TX_FAIL\n");
668 g_atm_priv_data.wtx_drop_oam++;
669 return -ENOMEM;
670 }
671 skb_put(skb, CELL_SIZE);
672 memcpy(skb->data, cell, CELL_SIZE);
673
674 reg_desc.dataptr = (unsigned int)skb->data >> 2;
675 reg_desc.datalen = CELL_SIZE;
676 reg_desc.byteoff = 0;
677 reg_desc.iscell = 1;
678
679 reg_desc.own = 1;
680 reg_desc.c = 1;
681 reg_desc.sop = reg_desc.eop = 1;
682
683 desc_base = get_tx_desc(conn);
684 if ( desc_base < 0 ) {
685 dev_kfree_skb_any(skb);
686 pr_err("ALLOC_TX_CONNECTION_FAIL\n");
687 g_atm_priv_data.wtx_drop_oam++;
688 return -EIO;
689 }
690
691 if ( vcc->stats )
692 atomic_inc(&vcc->stats->tx);
693
694 /* update descriptor send pointer */
695 if ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL )
696 dev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]);
697 g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb;
698
699 /* write discriptor to memory and write back cache */
700 g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc;
701 dma_cache_wback((unsigned long)skb->data, CELL_SIZE);
702
703 mailbox_signal(conn, 1);
704
705 g_atm_priv_data.wtx_oam++;
706 adsl_led_flash();
707
708 return 0;
709 }
710
711 static int ppe_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
712 {
713 int conn;
714
715 if ( vcc == NULL || qos == NULL )
716 return -EINVAL;
717
718 conn = find_vcc(vcc);
719 if ( conn < 0 )
720 return -EINVAL;
721
722 set_qsb(vcc, qos, conn);
723
724 return 0;
725 }
726
727 static inline void adsl_led_flash(void)
728 {
729 ifx_mei_atm_led_blink();
730 }
731
732 /*
733 * Description:
734 * Add a 32-bit value to 64-bit value, and put result in a 64-bit variable.
735 * Input:
736 * opt1 --- ppe_u64_t, first operand, a 64-bit unsigned integer value
737 * opt2 --- unsigned int, second operand, a 32-bit unsigned integer value
738 * ret --- ppe_u64_t, pointer to a variable to hold result
739 * Output:
740 * none
741 */
742 static inline void u64_add_u32(ppe_u64_t opt1, unsigned int opt2, ppe_u64_t *ret)
743 {
744 ret->l = opt1.l + opt2;
745 if ( ret->l < opt1.l || ret->l < opt2 )
746 ret->h++;
747 }
748
749 static inline struct sk_buff* alloc_skb_rx(void)
750 {
751 struct sk_buff *skb;
752
753 skb = dev_alloc_skb(RX_DMA_CH_AAL_BUF_SIZE + DATA_BUFFER_ALIGNMENT);
754 if ( skb != NULL ) {
755 /* must be burst length alignment */
756 if ( ((unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1)) != 0 )
757 skb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1));
758 /* pub skb in reserved area "skb->data - 4" */
759 *((struct sk_buff **)skb->data - 1) = skb;
760 /* write back and invalidate cache */
761 dma_cache_wback_inv((unsigned long)skb->data - sizeof(skb), sizeof(skb));
762 /* invalidate cache */
763 #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV
764 dma_cache_inv((unsigned long)skb->data, LESS_CACHE_INV_LEN);
765 #else
766 dma_cache_inv((unsigned long)skb->data, RX_DMA_CH_AAL_BUF_SIZE);
767 #endif
768 }
769 return skb;
770 }
771
772 static inline struct sk_buff* alloc_skb_tx(unsigned int size)
773 {
774 struct sk_buff *skb;
775
776 /* allocate memory including header and padding */
777 size += TX_INBAND_HEADER_LENGTH + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES;
778 size &= ~(DATA_BUFFER_ALIGNMENT - 1);
779 skb = dev_alloc_skb(size + DATA_BUFFER_ALIGNMENT);
780 /* must be burst length alignment */
781 if ( skb != NULL )
782 skb_reserve(skb, (~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1)) + TX_INBAND_HEADER_LENGTH);
783 return skb;
784 }
785
786 static inline void atm_free_tx_skb_vcc(struct sk_buff *skb, struct atm_vcc *vcc)
787 {
788 if ( vcc->pop != NULL )
789 vcc->pop(vcc, skb);
790 else
791 dev_kfree_skb_any(skb);
792 }
793
794 static inline struct sk_buff *get_skb_rx_pointer(unsigned int dataptr)
795 {
796 unsigned int skb_dataptr;
797 struct sk_buff *skb;
798
799 skb_dataptr = ((dataptr - 1) << 2) | KSEG1;
800 skb = *(struct sk_buff **)skb_dataptr;
801
802 ASSERT((unsigned int)skb >= KSEG0, "invalid skb - skb = %#08x, dataptr = %#08x", (unsigned int)skb, dataptr);
803 ASSERT(((unsigned int)skb->data | KSEG1) == ((dataptr << 2) | KSEG1), "invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x", (unsigned int)skb, (unsigned int)skb->data, dataptr);
804
805 return skb;
806 }
807
808 static inline int get_tx_desc(unsigned int conn)
809 {
810 int desc_base = -1;
811 struct connection *p_conn = &g_atm_priv_data.conn[conn];
812
813 if ( p_conn->tx_desc[p_conn->tx_desc_pos].own == 0 ) {
814 desc_base = p_conn->tx_desc_pos;
815 if ( ++(p_conn->tx_desc_pos) == dma_tx_descriptor_length )
816 p_conn->tx_desc_pos = 0;
817 }
818
819 return desc_base;
820 }
821
822 static void free_tx_ring(unsigned int queue)
823 {
824 unsigned long flags;
825 int i;
826 struct connection *conn = &g_atm_priv_data.conn[queue];
827 struct sk_buff *skb;
828
829 if (!conn)
830 return;
831
832 spin_lock_irqsave(&conn->lock, flags);
833
834 for (i = 0; i < dma_tx_descriptor_length; i++) {
835 if (conn->tx_desc[i].own == 0 && conn->tx_skb[i] != NULL) {
836 skb = conn->tx_skb[i];
837 conn->tx_skb[i] = NULL;
838 atm_free_tx_skb_vcc(skb, ATM_SKB(skb)->vcc);
839 }
840 }
841 spin_unlock_irqrestore(&conn->lock, flags);
842 }
843
844 static void mailbox_tx_handler(unsigned int queue_bitmap)
845 {
846 int i;
847 int bit;
848
849 /* only get valid queues */
850 queue_bitmap &= g_atm_priv_data.conn_table;
851
852 for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
853 if (queue_bitmap & bit)
854 free_tx_ring(i);
855 }
856 }
857
858 static inline void mailbox_oam_rx_handler(void)
859 {
860 unsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM)->vlddes;
861 struct rx_descriptor reg_desc;
862 struct uni_cell_header *header;
863 int conn;
864 struct atm_vcc *vcc;
865 unsigned int i;
866
867 for ( i = 0; i < vlddes; i++ ) {
868 unsigned int loop_count = 0;
869
870 do {
871 reg_desc = g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos];
872 if ( ++loop_count == 1000 )
873 break;
874 } while ( reg_desc.own || !reg_desc.c ); // keep test OWN and C bit until data is ready
875 ASSERT(loop_count == 1, "loop_count = %u, own = %d, c = %d, oam_desc_pos = %u", loop_count, (int)reg_desc.own, (int)reg_desc.c, g_atm_priv_data.oam_desc_pos);
876
877 header = (struct uni_cell_header *)&g_atm_priv_data.oam_buf[g_atm_priv_data.oam_desc_pos * RX_DMA_CH_OAM_BUF_SIZE];
878
879 if ( header->pti == ATM_PTI_SEGF5 || header->pti == ATM_PTI_E2EF5 )
880 conn = find_vpivci(header->vpi, header->vci);
881 else if ( header->vci == 0x03 || header->vci == 0x04 )
882 conn = find_vpi(header->vpi);
883 else
884 conn = -1;
885
886 if ( conn >= 0 && g_atm_priv_data.conn[conn].vcc != NULL ) {
887 vcc = g_atm_priv_data.conn[conn].vcc;
888
889 if ( vcc->push_oam != NULL )
890 vcc->push_oam(vcc, header);
891 else
892 ifx_push_oam((unsigned char *)header);
893
894 g_atm_priv_data.wrx_oam++;
895
896 adsl_led_flash();
897 } else
898 g_atm_priv_data.wrx_drop_oam++;
899
900 reg_desc.byteoff = 0;
901 reg_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE;
902 reg_desc.own = 1;
903 reg_desc.c = 0;
904
905 g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos] = reg_desc;
906 if ( ++g_atm_priv_data.oam_desc_pos == RX_DMA_CH_OAM_DESC_LEN )
907 g_atm_priv_data.oam_desc_pos = 0;
908
909 dma_cache_inv((unsigned long)header, CELL_SIZE);
910 mailbox_signal(RX_DMA_CH_OAM, 0);
911 }
912 }
913
914 static inline void mailbox_aal_rx_handler(void)
915 {
916 unsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL)->vlddes;
917 struct rx_descriptor reg_desc;
918 int conn;
919 struct atm_vcc *vcc;
920 struct sk_buff *skb, *new_skb;
921 struct rx_inband_trailer *trailer;
922 unsigned int i;
923
924 for ( i = 0; i < vlddes; i++ ) {
925 unsigned int loop_count = 0;
926
927 do {
928 reg_desc = g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos];
929 if ( ++loop_count == 1000 )
930 break;
931 } while ( reg_desc.own || !reg_desc.c ); // keep test OWN and C bit until data is ready
932 ASSERT(loop_count == 1, "loop_count = %u, own = %d, c = %d, aal_desc_pos = %u", loop_count, (int)reg_desc.own, (int)reg_desc.c, g_atm_priv_data.aal_desc_pos);
933
934 conn = reg_desc.id;
935
936 if ( g_atm_priv_data.conn[conn].vcc != NULL ) {
937 vcc = g_atm_priv_data.conn[conn].vcc;
938
939 skb = get_skb_rx_pointer(reg_desc.dataptr);
940
941 if ( reg_desc.err ) {
942 if ( vcc->qos.aal == ATM_AAL5 ) {
943 trailer = (struct rx_inband_trailer *)((unsigned int)skb->data + ((reg_desc.byteoff + reg_desc.datalen + MAX_RX_PACKET_PADDING_BYTES) & ~MAX_RX_PACKET_PADDING_BYTES));
944 if ( trailer->stw_crc )
945 g_atm_priv_data.conn[conn].aal5_vcc_crc_err++;
946 if ( trailer->stw_ovz )
947 g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu++;
948 g_atm_priv_data.wrx_drop_pdu++;
949 }
950 if ( vcc->stats ) {
951 atomic_inc(&vcc->stats->rx_drop);
952 atomic_inc(&vcc->stats->rx_err);
953 }
954 reg_desc.err = 0;
955 } else if ( atm_charge(vcc, skb->truesize) ) {
956 new_skb = alloc_skb_rx();
957 if ( new_skb != NULL ) {
958 #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV
959 if ( reg_desc.byteoff + reg_desc.datalen > LESS_CACHE_INV_LEN )
960 dma_cache_inv((unsigned long)skb->data + LESS_CACHE_INV_LEN, reg_desc.byteoff + reg_desc.datalen - LESS_CACHE_INV_LEN);
961 #endif
962
963 skb_reserve(skb, reg_desc.byteoff);
964 skb_put(skb, reg_desc.datalen);
965 ATM_SKB(skb)->vcc = vcc;
966
967 vcc->push(vcc, skb);
968
969 if ( vcc->qos.aal == ATM_AAL5 )
970 g_atm_priv_data.wrx_pdu++;
971 if ( vcc->stats )
972 atomic_inc(&vcc->stats->rx);
973 adsl_led_flash();
974
975 reg_desc.dataptr = (unsigned int)new_skb->data >> 2;
976 } else {
977 atm_return(vcc, skb->truesize);
978 if ( vcc->qos.aal == ATM_AAL5 )
979 g_atm_priv_data.wrx_drop_pdu++;
980 if ( vcc->stats )
981 atomic_inc(&vcc->stats->rx_drop);
982 }
983 } else {
984 if ( vcc->qos.aal == ATM_AAL5 )
985 g_atm_priv_data.wrx_drop_pdu++;
986 if ( vcc->stats )
987 atomic_inc(&vcc->stats->rx_drop);
988 }
989 } else {
990 g_atm_priv_data.wrx_drop_pdu++;
991 }
992
993 reg_desc.byteoff = 0;
994 reg_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE;
995 reg_desc.own = 1;
996 reg_desc.c = 0;
997
998 g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos] = reg_desc;
999 if ( ++g_atm_priv_data.aal_desc_pos == dma_rx_descriptor_length )
1000 g_atm_priv_data.aal_desc_pos = 0;
1001
1002 mailbox_signal(RX_DMA_CH_AAL, 0);
1003 }
1004 }
1005
1006 static void do_ppe_tasklet(unsigned long data)
1007 {
1008 unsigned int irqs = *MBOX_IGU1_ISR;
1009 *MBOX_IGU1_ISRC = *MBOX_IGU1_ISR;
1010
1011 if (irqs & (1 << RX_DMA_CH_AAL))
1012 mailbox_aal_rx_handler();
1013 if (irqs & (1 << RX_DMA_CH_OAM))
1014 mailbox_oam_rx_handler();
1015
1016 /* any valid tx irqs */
1017 if ((irqs >> (FIRST_QSB_QID + 16)) & g_atm_priv_data.conn_table)
1018 mailbox_tx_handler(irqs >> (FIRST_QSB_QID + 16));
1019
1020 if ((*MBOX_IGU1_ISR & ((1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM))) != 0)
1021 tasklet_schedule(&g_dma_tasklet);
1022 else if (*MBOX_IGU1_ISR >> (FIRST_QSB_QID + 16)) /* TX queue */
1023 tasklet_schedule(&g_dma_tasklet);
1024 else
1025 enable_irq(PPE_MAILBOX_IGU1_INT);
1026 }
1027
1028 static irqreturn_t mailbox_irq_handler(int irq, void *dev_id)
1029 {
1030 if ( !*MBOX_IGU1_ISR )
1031 return IRQ_HANDLED;
1032
1033 disable_irq_nosync(PPE_MAILBOX_IGU1_INT);
1034 tasklet_schedule(&g_dma_tasklet);
1035
1036 return IRQ_HANDLED;
1037 }
1038
1039 static inline void mailbox_signal(unsigned int queue, int is_tx)
1040 {
1041 int count = 1000;
1042
1043 if ( is_tx ) {
1044 while ( MBOX_IGU3_ISR_ISR(queue + FIRST_QSB_QID + 16) && count > 0 )
1045 count--;
1046 *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue + FIRST_QSB_QID + 16);
1047 } else {
1048 while ( MBOX_IGU3_ISR_ISR(queue) && count > 0 )
1049 count--;
1050 *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue);
1051 }
1052
1053 ASSERT(count > 0, "queue = %u, is_tx = %d, MBOX_IGU3_ISR = 0x%08x", queue, is_tx, IFX_REG_R32(MBOX_IGU3_ISR));
1054 }
1055
1056 static void set_qsb(struct atm_vcc *vcc, struct atm_qos *qos, unsigned int queue)
1057 {
1058 struct clk *fpi_clk = clk_get_fpi();
1059 unsigned int qsb_clk = clk_get_rate(fpi_clk);
1060 unsigned int qsb_qid = queue + FIRST_QSB_QID;
1061 union qsb_queue_parameter_table qsb_queue_parameter_table = {{0}};
1062 union qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table = {{0}};
1063 unsigned int tmp;
1064
1065
1066 /*
1067 * Peak Cell Rate (PCR) Limiter
1068 */
1069 if ( qos->txtp.max_pcr == 0 )
1070 qsb_queue_parameter_table.bit.tp = 0; /* disable PCR limiter */
1071 else {
1072 /* peak cell rate would be slightly lower than requested [maximum_rate / pcr = (qsb_clock / 8) * (time_step / 4) / pcr] */
1073 tmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.max_pcr + 1;
1074 /* check if overflow takes place */
1075 qsb_queue_parameter_table.bit.tp = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp;
1076 }
1077
1078 #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND
1079 // A funny issue. Create two PVCs, one UBR and one UBR with max_pcr.
1080 // Send packets to these two PVCs at same time, it trigger strange behavior.
1081 // In A1, RAM from 0x80000000 to 0x0x8007FFFF was corrupted with fixed pattern 0x00000000 0x40000000.
1082 // In A4, PPE firmware keep emiting unknown cell and do not respond to driver.
1083 // To work around, create UBR always with max_pcr.
1084 // If user want to create UBR without max_pcr, we give a default one larger than line-rate.
1085 if ( qos->txtp.traffic_class == ATM_UBR && qsb_queue_parameter_table.bit.tp == 0 ) {
1086 int port = g_atm_priv_data.conn[queue].port;
1087 unsigned int max_pcr = g_atm_priv_data.port[port].tx_max_cell_rate + 1000;
1088
1089 tmp = ((qsb_clk * qsb_tstep) >> 5) / max_pcr + 1;
1090 if ( tmp > QSB_TP_TS_MAX )
1091 tmp = QSB_TP_TS_MAX;
1092 else if ( tmp < 1 )
1093 tmp = 1;
1094 qsb_queue_parameter_table.bit.tp = tmp;
1095 }
1096 #endif
1097
1098 /*
1099 * Weighted Fair Queueing Factor (WFQF)
1100 */
1101 switch ( qos->txtp.traffic_class ) {
1102 case ATM_CBR:
1103 case ATM_VBR_RT:
1104 /* real time queue gets weighted fair queueing bypass */
1105 qsb_queue_parameter_table.bit.wfqf = 0;
1106 break;
1107 case ATM_VBR_NRT:
1108 case ATM_UBR_PLUS:
1109 /* WFQF calculation here is based on virtual cell rates, to reduce granularity for high rates */
1110 /* WFQF is maximum cell rate / garenteed cell rate */
1111 /* wfqf = qsb_minimum_cell_rate * QSB_WFQ_NONUBR_MAX / requested_minimum_peak_cell_rate */
1112 if ( qos->txtp.min_pcr == 0 )
1113 qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX;
1114 else {
1115 tmp = QSB_GCR_MIN * QSB_WFQ_NONUBR_MAX / qos->txtp.min_pcr;
1116 if ( tmp == 0 )
1117 qsb_queue_parameter_table.bit.wfqf = 1;
1118 else if ( tmp > QSB_WFQ_NONUBR_MAX )
1119 qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX;
1120 else
1121 qsb_queue_parameter_table.bit.wfqf = tmp;
1122 }
1123 break;
1124 default:
1125 case ATM_UBR:
1126 qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_UBR_BYPASS;
1127 }
1128
1129 /*
1130 * Sustained Cell Rate (SCR) Leaky Bucket Shaper VBR.0/VBR.1
1131 */
1132 if ( qos->txtp.traffic_class == ATM_VBR_RT || qos->txtp.traffic_class == ATM_VBR_NRT ) {
1133 #if 0
1134 if ( qos->txtp.scr == 0 ) {
1135 #endif
1136 /* disable shaper */
1137 qsb_queue_vbr_parameter_table.bit.taus = 0;
1138 qsb_queue_vbr_parameter_table.bit.ts = 0;
1139 #if 0
1140 } else {
1141 /* Cell Loss Priority (CLP) */
1142 if ( (vcc->atm_options & ATM_ATMOPT_CLP) )
1143 /* CLP1 */
1144 qsb_queue_parameter_table.bit.vbr = 1;
1145 else
1146 /* CLP0 */
1147 qsb_queue_parameter_table.bit.vbr = 0;
1148 /* Rate Shaper Parameter (TS) and Burst Tolerance Parameter for SCR (tauS) */
1149 tmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.scr + 1;
1150 qsb_queue_vbr_parameter_table.bit.ts = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp;
1151 tmp = (qos->txtp.mbs - 1) * (qsb_queue_vbr_parameter_table.bit.ts - qsb_queue_parameter_table.bit.tp) / 64;
1152 if ( tmp == 0 )
1153 qsb_queue_vbr_parameter_table.bit.taus = 1;
1154 else if ( tmp > QSB_TAUS_MAX )
1155 qsb_queue_vbr_parameter_table.bit.taus = QSB_TAUS_MAX;
1156 else
1157 qsb_queue_vbr_parameter_table.bit.taus = tmp;
1158 }
1159 #endif
1160 } else {
1161 qsb_queue_vbr_parameter_table.bit.taus = 0;
1162 qsb_queue_vbr_parameter_table.bit.ts = 0;
1163 }
1164
1165 /* Queue Parameter Table (QPT) */
1166 *QSB_RTM = QSB_RTM_DM_SET(QSB_QPT_SET_MASK);
1167 *QSB_RTD = QSB_RTD_TTV_SET(qsb_queue_parameter_table.dword);
1168 *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_QPT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid);
1169 /* Queue VBR Paramter Table (QVPT) */
1170 *QSB_RTM = QSB_RTM_DM_SET(QSB_QVPT_SET_MASK);
1171 *QSB_RTD = QSB_RTD_TTV_SET(qsb_queue_vbr_parameter_table.dword);
1172 *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_VBR) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid);
1173
1174 }
1175
1176 static void qsb_global_set(void)
1177 {
1178 struct clk *fpi_clk = clk_get_fpi();
1179 unsigned int qsb_clk = clk_get_rate(fpi_clk);
1180 int i;
1181 unsigned int tmp1, tmp2, tmp3;
1182
1183 *QSB_ICDV = QSB_ICDV_TAU_SET(qsb_tau);
1184 *QSB_SBL = QSB_SBL_SBL_SET(qsb_srvm);
1185 *QSB_CFG = QSB_CFG_TSTEPC_SET(qsb_tstep >> 1);
1186
1187 /*
1188 * set SCT and SPT per port
1189 */
1190 for ( i = 0; i < ATM_PORT_NUMBER; i++ ) {
1191 if ( g_atm_priv_data.port[i].tx_max_cell_rate != 0 ) {
1192 tmp1 = ((qsb_clk * qsb_tstep) >> 1) / g_atm_priv_data.port[i].tx_max_cell_rate;
1193 tmp2 = tmp1 >> 6; /* integer value of Tsb */
1194 tmp3 = (tmp1 & ((1 << 6) - 1)) + 1; /* fractional part of Tsb */
1195 /* carry over to integer part (?) */
1196 if ( tmp3 == (1 << 6) ) {
1197 tmp3 = 0;
1198 tmp2++;
1199 }
1200 if ( tmp2 == 0 )
1201 tmp2 = tmp3 = 1;
1202 /* 1. set mask */
1203 /* 2. write value to data transfer register */
1204 /* 3. start the tranfer */
1205 /* SCT (FracRate) */
1206 *QSB_RTM = QSB_RTM_DM_SET(QSB_SET_SCT_MASK);
1207 *QSB_RTD = QSB_RTD_TTV_SET(tmp3);
1208 *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) |
1209 QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SCT) |
1210 QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) |
1211 QSB_RAMAC_TESEL_SET(i & 0x01);
1212 /* SPT (SBV + PN + IntRage) */
1213 *QSB_RTM = QSB_RTM_DM_SET(QSB_SET_SPT_MASK);
1214 *QSB_RTD = QSB_RTD_TTV_SET(QSB_SPT_SBV_VALID | QSB_SPT_PN_SET(i & 0x01) | QSB_SPT_INTRATE_SET(tmp2));
1215 *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) |
1216 QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SPT) |
1217 QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) |
1218 QSB_RAMAC_TESEL_SET(i & 0x01);
1219 }
1220 }
1221 }
1222
1223 static inline void set_htu_entry(unsigned int vpi, unsigned int vci, unsigned int queue, int aal5, int is_retx)
1224 {
1225 struct htu_entry htu_entry = {
1226 res1: 0x00,
1227 clp: is_retx ? 0x01 : 0x00,
1228 pid: g_atm_priv_data.conn[queue].port & 0x01,
1229 vpi: vpi,
1230 vci: vci,
1231 pti: 0x00,
1232 vld: 0x01};
1233
1234 struct htu_mask htu_mask = {
1235 set: 0x01,
1236 clp: 0x01,
1237 pid_mask: 0x02,
1238 vpi_mask: 0x00,
1239 vci_mask: 0x0000,
1240 pti_mask: 0x03, // 0xx, user data
1241 clear: 0x00};
1242
1243 struct htu_result htu_result = {
1244 res1: 0x00,
1245 cellid: queue,
1246 res2: 0x00,
1247 type: aal5 ? 0x00 : 0x01,
1248 ven: 0x01,
1249 res3: 0x00,
1250 qid: queue};
1251
1252 *HTU_RESULT(queue + OAM_HTU_ENTRY_NUMBER) = htu_result;
1253 *HTU_MASK(queue + OAM_HTU_ENTRY_NUMBER) = htu_mask;
1254 *HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER) = htu_entry;
1255 }
1256
1257 static inline void clear_htu_entry(unsigned int queue)
1258 {
1259 HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER)->vld = 0;
1260 }
1261
1262 static void validate_oam_htu_entry(void)
1263 {
1264 HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 1;
1265 HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 1;
1266 HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 1;
1267 }
1268
1269 static void invalidate_oam_htu_entry(void)
1270 {
1271 HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 0;
1272 HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 0;
1273 HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 0;
1274 }
1275
1276 static inline int find_vpi(unsigned int vpi)
1277 {
1278 int i;
1279 unsigned int bit;
1280
1281 for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
1282 if ( (g_atm_priv_data.conn_table & bit) != 0
1283 && g_atm_priv_data.conn[i].vcc != NULL
1284 && vpi == g_atm_priv_data.conn[i].vcc->vpi )
1285 return i;
1286 }
1287
1288 return -1;
1289 }
1290
1291 static inline int find_vpivci(unsigned int vpi, unsigned int vci)
1292 {
1293 int i;
1294 unsigned int bit;
1295
1296 for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
1297 if ( (g_atm_priv_data.conn_table & bit) != 0
1298 && g_atm_priv_data.conn[i].vcc != NULL
1299 && vpi == g_atm_priv_data.conn[i].vcc->vpi
1300 && vci == g_atm_priv_data.conn[i].vcc->vci )
1301 return i;
1302 }
1303
1304 return -1;
1305 }
1306
1307 static inline int find_vcc(struct atm_vcc *vcc)
1308 {
1309 int i;
1310 unsigned int bit;
1311
1312 for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
1313 if ( (g_atm_priv_data.conn_table & bit) != 0
1314 && g_atm_priv_data.conn[i].vcc == vcc )
1315 return i;
1316 }
1317
1318 return -1;
1319 }
1320
1321 static inline int ifx_atm_version(const struct ltq_atm_ops *ops, char *buf)
1322 {
1323 int len = 0;
1324 unsigned int major, minor;
1325
1326 ops->fw_ver(&major, &minor);
1327
1328 len += sprintf(buf + len, "ATM%d.%d.%d", IFX_ATM_VER_MAJOR, IFX_ATM_VER_MID, IFX_ATM_VER_MINOR);
1329 len += sprintf(buf + len, " ATM (A1) firmware version %d.%d\n", major, minor);
1330
1331 return len;
1332 }
1333
1334 static inline void check_parameters(void)
1335 {
1336 /* Please refer to Amazon spec 15.4 for setting these values. */
1337 if ( qsb_tau < 1 )
1338 qsb_tau = 1;
1339 if ( qsb_tstep < 1 )
1340 qsb_tstep = 1;
1341 else if ( qsb_tstep > 4 )
1342 qsb_tstep = 4;
1343 else if ( qsb_tstep == 3 )
1344 qsb_tstep = 2;
1345
1346 /* There is a delay between PPE write descriptor and descriptor is */
1347 /* really stored in memory. Host also has this delay when writing */
1348 /* descriptor. So PPE will use this value to determine if the write */
1349 /* operation makes effect. */
1350 if ( write_descriptor_delay < 0 )
1351 write_descriptor_delay = 0;
1352
1353 if ( aal5_fill_pattern < 0 )
1354 aal5_fill_pattern = 0;
1355 else
1356 aal5_fill_pattern &= 0xFF;
1357
1358 /* Because of the limitation of length field in descriptors, the packet */
1359 /* size could not be larger than 64K minus overhead size. */
1360 if ( aal5r_max_packet_size < 0 )
1361 aal5r_max_packet_size = 0;
1362 else if ( aal5r_max_packet_size >= 65535 - MAX_RX_FRAME_EXTRA_BYTES )
1363 aal5r_max_packet_size = 65535 - MAX_RX_FRAME_EXTRA_BYTES;
1364 if ( aal5r_min_packet_size < 0 )
1365 aal5r_min_packet_size = 0;
1366 else if ( aal5r_min_packet_size > aal5r_max_packet_size )
1367 aal5r_min_packet_size = aal5r_max_packet_size;
1368 if ( aal5s_max_packet_size < 0 )
1369 aal5s_max_packet_size = 0;
1370 else if ( aal5s_max_packet_size >= 65535 - MAX_TX_FRAME_EXTRA_BYTES )
1371 aal5s_max_packet_size = 65535 - MAX_TX_FRAME_EXTRA_BYTES;
1372 if ( aal5s_min_packet_size < 0 )
1373 aal5s_min_packet_size = 0;
1374 else if ( aal5s_min_packet_size > aal5s_max_packet_size )
1375 aal5s_min_packet_size = aal5s_max_packet_size;
1376
1377 if ( dma_rx_descriptor_length < 2 )
1378 dma_rx_descriptor_length = 2;
1379 if ( dma_tx_descriptor_length < 2 )
1380 dma_tx_descriptor_length = 2;
1381 if ( dma_rx_clp1_descriptor_threshold < 0 )
1382 dma_rx_clp1_descriptor_threshold = 0;
1383 else if ( dma_rx_clp1_descriptor_threshold > dma_rx_descriptor_length )
1384 dma_rx_clp1_descriptor_threshold = dma_rx_descriptor_length;
1385
1386 if ( dma_tx_descriptor_length < 2 )
1387 dma_tx_descriptor_length = 2;
1388 }
1389
1390 static inline int init_priv_data(void)
1391 {
1392 void *p;
1393 int i;
1394 struct rx_descriptor rx_desc = {0};
1395 struct sk_buff *skb;
1396 volatile struct tx_descriptor *p_tx_desc;
1397 struct sk_buff **ppskb;
1398
1399 // clear atm private data structure
1400 memset(&g_atm_priv_data, 0, sizeof(g_atm_priv_data));
1401
1402 // allocate memory for RX (AAL) descriptors
1403 p = kzalloc(dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1404 if ( p == NULL )
1405 return -1;
1406 dma_cache_wback_inv((unsigned long)p, dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);
1407 g_atm_priv_data.aal_desc_base = p;
1408 p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1409 g_atm_priv_data.aal_desc = (volatile struct rx_descriptor *)p;
1410
1411 // allocate memory for RX (OAM) descriptors
1412 p = kzalloc(RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1413 if ( p == NULL )
1414 return -1;
1415 dma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);
1416 g_atm_priv_data.oam_desc_base = p;
1417 p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1418 g_atm_priv_data.oam_desc = (volatile struct rx_descriptor *)p;
1419
1420 // allocate memory for RX (OAM) buffer
1421 p = kzalloc(RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT, GFP_KERNEL);
1422 if ( p == NULL )
1423 return -1;
1424 dma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT);
1425 g_atm_priv_data.oam_buf_base = p;
1426 p = (void *)(((unsigned int)p + DATA_BUFFER_ALIGNMENT - 1) & ~(DATA_BUFFER_ALIGNMENT - 1));
1427 g_atm_priv_data.oam_buf = p;
1428
1429 // allocate memory for TX descriptors
1430 p = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1431 if ( p == NULL )
1432 return -1;
1433 dma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT);
1434 g_atm_priv_data.tx_desc_base = p;
1435
1436 // allocate memory for TX skb pointers
1437 p = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4, GFP_KERNEL);
1438 if ( p == NULL )
1439 return -1;
1440 dma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4);
1441 g_atm_priv_data.tx_skb_base = p;
1442
1443 // setup RX (AAL) descriptors
1444 rx_desc.own = 1;
1445 rx_desc.c = 0;
1446 rx_desc.sop = 1;
1447 rx_desc.eop = 1;
1448 rx_desc.byteoff = 0;
1449 rx_desc.id = 0;
1450 rx_desc.err = 0;
1451 rx_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE;
1452 for ( i = 0; i < dma_rx_descriptor_length; i++ ) {
1453 skb = alloc_skb_rx();
1454 if ( skb == NULL )
1455 return -1;
1456 rx_desc.dataptr = ((unsigned int)skb->data >> 2) & 0x0FFFFFFF;
1457 g_atm_priv_data.aal_desc[i] = rx_desc;
1458 }
1459
1460 // setup RX (OAM) descriptors
1461 p = (void *)((unsigned int)g_atm_priv_data.oam_buf | KSEG1);
1462 rx_desc.own = 1;
1463 rx_desc.c = 0;
1464 rx_desc.sop = 1;
1465 rx_desc.eop = 1;
1466 rx_desc.byteoff = 0;
1467 rx_desc.id = 0;
1468 rx_desc.err = 0;
1469 rx_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE;
1470 for ( i = 0; i < RX_DMA_CH_OAM_DESC_LEN; i++ ) {
1471 rx_desc.dataptr = ((unsigned int)p >> 2) & 0x0FFFFFFF;
1472 g_atm_priv_data.oam_desc[i] = rx_desc;
1473 p = (void *)((unsigned int)p + RX_DMA_CH_OAM_BUF_SIZE);
1474 }
1475
1476 // setup TX descriptors and skb pointers
1477 p_tx_desc = (volatile struct tx_descriptor *)((((unsigned int)g_atm_priv_data.tx_desc_base + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1478 ppskb = (struct sk_buff **)(((unsigned int)g_atm_priv_data.tx_skb_base + 3) & ~3);
1479 for ( i = 0; i < MAX_PVC_NUMBER; i++ ) {
1480 spin_lock_init(&g_atm_priv_data.conn[i].lock);
1481 g_atm_priv_data.conn[i].tx_desc = &p_tx_desc[i * dma_tx_descriptor_length];
1482 g_atm_priv_data.conn[i].tx_skb = &ppskb[i * dma_tx_descriptor_length];
1483 }
1484
1485 for ( i = 0; i < ATM_PORT_NUMBER; i++ )
1486 g_atm_priv_data.port[i].tx_max_cell_rate = DEFAULT_TX_LINK_RATE;
1487
1488 return 0;
1489 }
1490
1491 static inline void clear_priv_data(void)
1492 {
1493 int i, j;
1494 struct sk_buff *skb;
1495
1496 for ( i = 0; i < MAX_PVC_NUMBER; i++ ) {
1497 if ( g_atm_priv_data.conn[i].tx_skb != NULL ) {
1498 for ( j = 0; j < dma_tx_descriptor_length; j++ )
1499 if ( g_atm_priv_data.conn[i].tx_skb[j] != NULL )
1500 dev_kfree_skb_any(g_atm_priv_data.conn[i].tx_skb[j]);
1501 }
1502 }
1503
1504 if ( g_atm_priv_data.tx_skb_base != NULL )
1505 kfree(g_atm_priv_data.tx_skb_base);
1506
1507 if ( g_atm_priv_data.tx_desc_base != NULL )
1508 kfree(g_atm_priv_data.tx_desc_base);
1509
1510 if ( g_atm_priv_data.oam_buf_base != NULL )
1511 kfree(g_atm_priv_data.oam_buf_base);
1512
1513 if ( g_atm_priv_data.oam_desc_base != NULL )
1514 kfree(g_atm_priv_data.oam_desc_base);
1515
1516 if ( g_atm_priv_data.aal_desc_base != NULL ) {
1517 for ( i = 0; i < dma_rx_descriptor_length; i++ ) {
1518 if ( g_atm_priv_data.aal_desc[i].sop || g_atm_priv_data.aal_desc[i].eop ) { // descriptor initialized
1519 skb = get_skb_rx_pointer(g_atm_priv_data.aal_desc[i].dataptr);
1520 dev_kfree_skb_any(skb);
1521 }
1522 }
1523 kfree(g_atm_priv_data.aal_desc_base);
1524 }
1525 }
1526
1527 static inline void init_rx_tables(void)
1528 {
1529 int i;
1530 struct wrx_queue_config wrx_queue_config = {0};
1531 struct wrx_dma_channel_config wrx_dma_channel_config = {0};
1532 struct htu_entry htu_entry = {0};
1533 struct htu_result htu_result = {0};
1534 struct htu_mask htu_mask = {
1535 set: 0x01,
1536 clp: 0x01,
1537 pid_mask: 0x00,
1538 vpi_mask: 0x00,
1539 vci_mask: 0x00,
1540 pti_mask: 0x00,
1541 clear: 0x00
1542 };
1543
1544 /*
1545 * General Registers
1546 */
1547 *CFG_WRX_HTUTS = MAX_PVC_NUMBER + OAM_HTU_ENTRY_NUMBER;
1548 #ifndef CONFIG_AMAZON_SE
1549 *CFG_WRX_QNUM = MAX_QUEUE_NUMBER;
1550 #endif
1551 *CFG_WRX_DCHNUM = RX_DMA_CH_TOTAL;
1552 *WRX_DMACH_ON = (1 << RX_DMA_CH_TOTAL) - 1;
1553 *WRX_HUNT_BITTH = DEFAULT_RX_HUNT_BITTH;
1554
1555 /*
1556 * WRX Queue Configuration Table
1557 */
1558 wrx_queue_config.uumask = 0xFF;
1559 wrx_queue_config.cpimask = 0xFF;
1560 wrx_queue_config.uuexp = 0;
1561 wrx_queue_config.cpiexp = 0;
1562 wrx_queue_config.mfs = aal5r_max_packet_size;
1563 wrx_queue_config.oversize = aal5r_max_packet_size;
1564 wrx_queue_config.undersize = aal5r_min_packet_size;
1565 wrx_queue_config.errdp = aal5r_drop_error_packet;
1566 wrx_queue_config.dmach = RX_DMA_CH_AAL;
1567 for ( i = 0; i < MAX_QUEUE_NUMBER; i++ )
1568 *WRX_QUEUE_CONFIG(i) = wrx_queue_config;
1569 WRX_QUEUE_CONFIG(OAM_RX_QUEUE)->dmach = RX_DMA_CH_OAM;
1570
1571 /*
1572 * WRX DMA Channel Configuration Table
1573 */
1574 wrx_dma_channel_config.chrl = 0;
1575 wrx_dma_channel_config.clp1th = dma_rx_clp1_descriptor_threshold;
1576 wrx_dma_channel_config.mode = 0;
1577 wrx_dma_channel_config.rlcfg = 0;
1578
1579 wrx_dma_channel_config.deslen = RX_DMA_CH_OAM_DESC_LEN;
1580 wrx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.oam_desc >> 2) & 0x0FFFFFFF;
1581 *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM) = wrx_dma_channel_config;
1582
1583 wrx_dma_channel_config.deslen = dma_rx_descriptor_length;
1584 wrx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.aal_desc >> 2) & 0x0FFFFFFF;
1585 *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL) = wrx_dma_channel_config;
1586
1587 /*
1588 * HTU Tables
1589 */
1590 for (i = 0; i < MAX_PVC_NUMBER; i++) {
1591 htu_result.qid = (unsigned int)i;
1592
1593 *HTU_ENTRY(i + OAM_HTU_ENTRY_NUMBER) = htu_entry;
1594 *HTU_MASK(i + OAM_HTU_ENTRY_NUMBER) = htu_mask;
1595 *HTU_RESULT(i + OAM_HTU_ENTRY_NUMBER) = htu_result;
1596 }
1597
1598 /* OAM HTU Entry */
1599 htu_entry.vci = 0x03;
1600 htu_mask.pid_mask = 0x03;
1601 htu_mask.vpi_mask = 0xFF;
1602 htu_mask.vci_mask = 0x0000;
1603 htu_mask.pti_mask = 0x07;
1604 htu_result.cellid = OAM_RX_QUEUE;
1605 htu_result.type = 1;
1606 htu_result.ven = 1;
1607 htu_result.qid = OAM_RX_QUEUE;
1608 *HTU_RESULT(OAM_F4_SEG_HTU_ENTRY) = htu_result;
1609 *HTU_MASK(OAM_F4_SEG_HTU_ENTRY) = htu_mask;
1610 *HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY) = htu_entry;
1611 htu_entry.vci = 0x04;
1612 htu_result.cellid = OAM_RX_QUEUE;
1613 htu_result.type = 1;
1614 htu_result.ven = 1;
1615 htu_result.qid = OAM_RX_QUEUE;
1616 *HTU_RESULT(OAM_F4_TOT_HTU_ENTRY) = htu_result;
1617 *HTU_MASK(OAM_F4_TOT_HTU_ENTRY) = htu_mask;
1618 *HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY) = htu_entry;
1619 htu_entry.vci = 0x00;
1620 htu_entry.pti = 0x04;
1621 htu_mask.vci_mask = 0xFFFF;
1622 htu_mask.pti_mask = 0x01;
1623 htu_result.cellid = OAM_RX_QUEUE;
1624 htu_result.type = 1;
1625 htu_result.ven = 1;
1626 htu_result.qid = OAM_RX_QUEUE;
1627 *HTU_RESULT(OAM_F5_HTU_ENTRY) = htu_result;
1628 *HTU_MASK(OAM_F5_HTU_ENTRY) = htu_mask;
1629 *HTU_ENTRY(OAM_F5_HTU_ENTRY) = htu_entry;
1630 }
1631
1632 static inline void init_tx_tables(void)
1633 {
1634 int i;
1635 struct wtx_queue_config wtx_queue_config = {0};
1636 struct wtx_dma_channel_config wtx_dma_channel_config = {0};
1637 struct wtx_port_config wtx_port_config = {
1638 res1: 0,
1639 qid: 0,
1640 qsben: 1
1641 };
1642
1643 /*
1644 * General Registers
1645 */
1646 *CFG_WTX_DCHNUM = MAX_TX_DMA_CHANNEL_NUMBER;
1647 *WTX_DMACH_ON = ((1 << MAX_TX_DMA_CHANNEL_NUMBER) - 1) ^ ((1 << FIRST_QSB_QID) - 1);
1648 *CFG_WRDES_DELAY = write_descriptor_delay;
1649
1650 /*
1651 * WTX Port Configuration Table
1652 */
1653 for ( i = 0; i < ATM_PORT_NUMBER; i++ )
1654 *WTX_PORT_CONFIG(i) = wtx_port_config;
1655
1656 /*
1657 * WTX Queue Configuration Table
1658 */
1659 wtx_queue_config.qsben = 1;
1660 wtx_queue_config.sbid = 0;
1661 for ( i = 0; i < MAX_TX_DMA_CHANNEL_NUMBER; i++ ) {
1662 wtx_queue_config.qsb_vcid = i;
1663 *WTX_QUEUE_CONFIG(i) = wtx_queue_config;
1664 }
1665
1666 /*
1667 * WTX DMA Channel Configuration Table
1668 */
1669 wtx_dma_channel_config.mode = 0;
1670 wtx_dma_channel_config.deslen = 0;
1671 wtx_dma_channel_config.desba = 0;
1672 for ( i = 0; i < FIRST_QSB_QID; i++ )
1673 *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config;
1674 /* normal connection */
1675 wtx_dma_channel_config.deslen = dma_tx_descriptor_length;
1676 for ( ; i < MAX_TX_DMA_CHANNEL_NUMBER ; i++ ) {
1677 wtx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.conn[i - FIRST_QSB_QID].tx_desc >> 2) & 0x0FFFFFFF;
1678 *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config;
1679 }
1680 }
1681
1682 static int atm_showtime_enter(struct port_cell_info *port_cell, void *xdata_addr)
1683 {
1684 int i, j, port_num;
1685
1686 ASSERT(port_cell != NULL, "port_cell is NULL");
1687 ASSERT(xdata_addr != NULL, "xdata_addr is NULL");
1688
1689 for ( j = 0; j < ATM_PORT_NUMBER && j < port_cell->port_num; j++ )
1690 if ( port_cell->tx_link_rate[j] > 0 )
1691 break;
1692 for ( i = 0; i < ATM_PORT_NUMBER && i < port_cell->port_num; i++ )
1693 g_atm_priv_data.port[i].tx_max_cell_rate =
1694 port_cell->tx_link_rate[i] > 0 ? port_cell->tx_link_rate[i] : port_cell->tx_link_rate[j];
1695
1696 qsb_global_set();
1697
1698 for ( i = 0; i < MAX_PVC_NUMBER; i++ )
1699 if ( g_atm_priv_data.conn[i].vcc != NULL )
1700 set_qsb(g_atm_priv_data.conn[i].vcc, &g_atm_priv_data.conn[i].vcc->qos, i);
1701
1702 // TODO: ReTX set xdata_addr
1703 g_xdata_addr = xdata_addr;
1704
1705 g_showtime = 1;
1706
1707 for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
1708 atm_dev_signal_change(g_atm_priv_data.port[port_num].dev, ATM_PHY_SIG_FOUND);
1709
1710 #if defined(CONFIG_VR9)
1711 IFX_REG_W32(0x0F, UTP_CFG);
1712 #endif
1713
1714 printk("enter showtime, cell rate: 0 - %d, 1 - %d, xdata addr: 0x%08x\n",
1715 g_atm_priv_data.port[0].tx_max_cell_rate,
1716 g_atm_priv_data.port[1].tx_max_cell_rate,
1717 (unsigned int)g_xdata_addr);
1718
1719 return 0;
1720 }
1721
1722 static int atm_showtime_exit(void)
1723 {
1724 int port_num;
1725
1726 if ( !g_showtime )
1727 return -1;
1728
1729 #if defined(CONFIG_VR9)
1730 IFX_REG_W32(0x00, UTP_CFG);
1731 #endif
1732
1733 for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
1734 atm_dev_signal_change(g_atm_priv_data.port[port_num].dev, ATM_PHY_SIG_LOST);
1735
1736 g_showtime = 0;
1737 g_xdata_addr = NULL;
1738 printk("leave showtime\n");
1739 return 0;
1740 }
1741
1742 extern struct ltq_atm_ops ar9_ops;
1743 extern struct ltq_atm_ops vr9_ops;
1744 extern struct ltq_atm_ops danube_ops;
1745 extern struct ltq_atm_ops ase_ops;
1746
1747 static const struct of_device_id ltq_atm_match[] = {
1748 #ifdef CONFIG_DANUBE
1749 { .compatible = "lantiq,ppe-danube", .data = &danube_ops },
1750 #elif defined CONFIG_AMAZON_SE
1751 { .compatible = "lantiq,ppe-ase", .data = &ase_ops },
1752 #elif defined CONFIG_AR9
1753 { .compatible = "lantiq,ppe-arx100", .data = &ar9_ops },
1754 #elif defined CONFIG_VR9
1755 { .compatible = "lantiq,ppe-xrx200", .data = &vr9_ops },
1756 #endif
1757 {},
1758 };
1759 MODULE_DEVICE_TABLE(of, ltq_atm_match);
1760
1761 static int ltq_atm_probe(struct platform_device *pdev)
1762 {
1763 const struct of_device_id *match;
1764 struct ltq_atm_ops *ops = NULL;
1765 int ret;
1766 int port_num;
1767 struct port_cell_info port_cell = {0};
1768 char ver_str[256];
1769
1770 match = of_match_device(ltq_atm_match, &pdev->dev);
1771 if (!match) {
1772 dev_err(&pdev->dev, "failed to find matching device\n");
1773 return -ENOENT;
1774 }
1775 ops = (struct ltq_atm_ops *) match->data;
1776
1777 check_parameters();
1778
1779 ret = init_priv_data();
1780 if ( ret != 0 ) {
1781 pr_err("INIT_PRIV_DATA_FAIL\n");
1782 goto INIT_PRIV_DATA_FAIL;
1783 }
1784
1785 ops->init(pdev);
1786 init_rx_tables();
1787 init_tx_tables();
1788
1789 /* create devices */
1790 for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ ) {
1791 g_atm_priv_data.port[port_num].dev = atm_dev_register("ifxmips_atm", NULL, &g_ifx_atm_ops, -1, NULL);
1792 if ( !g_atm_priv_data.port[port_num].dev ) {
1793 pr_err("failed to register atm device %d!\n", port_num);
1794 ret = -EIO;
1795 goto ATM_DEV_REGISTER_FAIL;
1796 } else {
1797 g_atm_priv_data.port[port_num].dev->ci_range.vpi_bits = 8;
1798 g_atm_priv_data.port[port_num].dev->ci_range.vci_bits = 16;
1799 g_atm_priv_data.port[port_num].dev->link_rate = g_atm_priv_data.port[port_num].tx_max_cell_rate;
1800 g_atm_priv_data.port[port_num].dev->dev_data = (void*)port_num;
1801
1802 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
1803 atm_dev_signal_change(g_atm_priv_data.port[port_num].dev, ATM_PHY_SIG_LOST);
1804 #endif
1805 }
1806 }
1807
1808 /* register interrupt handler */
1809 ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, 0, "atm_mailbox_isr", &g_atm_priv_data);
1810 if ( ret ) {
1811 if ( ret == -EBUSY ) {
1812 pr_err("IRQ may be occupied by other driver, please reconfig to disable it.\n");
1813 } else {
1814 pr_err("request_irq fail irq:%d\n", PPE_MAILBOX_IGU1_INT);
1815 }
1816 goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
1817 }
1818 disable_irq(PPE_MAILBOX_IGU1_INT);
1819
1820
1821 ret = ops->start(0);
1822 if ( ret ) {
1823 pr_err("ifx_pp32_start fail!\n");
1824 goto PP32_START_FAIL;
1825 }
1826
1827 port_cell.port_num = ATM_PORT_NUMBER;
1828 ifx_mei_atm_showtime_check(&g_showtime, &port_cell, &g_xdata_addr);
1829 if ( g_showtime ) {
1830 atm_showtime_enter(&port_cell, &g_xdata_addr);
1831 } else {
1832 qsb_global_set();
1833 }
1834
1835 validate_oam_htu_entry();
1836
1837 ifx_mei_atm_showtime_enter = atm_showtime_enter;
1838 ifx_mei_atm_showtime_exit = atm_showtime_exit;
1839
1840 ifx_atm_version(ops, ver_str);
1841 printk(KERN_INFO "%s", ver_str);
1842 platform_set_drvdata(pdev, ops);
1843 printk("ifxmips_atm: ATM init succeed\n");
1844
1845 return 0;
1846
1847 PP32_START_FAIL:
1848 free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data);
1849 REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL:
1850 ATM_DEV_REGISTER_FAIL:
1851 while ( port_num-- > 0 )
1852 atm_dev_deregister(g_atm_priv_data.port[port_num].dev);
1853 INIT_PRIV_DATA_FAIL:
1854 clear_priv_data();
1855 printk("ifxmips_atm: ATM init failed\n");
1856 return ret;
1857 }
1858
1859 static int ltq_atm_remove(struct platform_device *pdev)
1860 {
1861 int port_num;
1862 struct ltq_atm_ops *ops = platform_get_drvdata(pdev);
1863
1864 ifx_mei_atm_showtime_enter = NULL;
1865 ifx_mei_atm_showtime_exit = NULL;
1866
1867 invalidate_oam_htu_entry();
1868
1869 ops->stop(0);
1870
1871 free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data);
1872
1873 for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
1874 atm_dev_deregister(g_atm_priv_data.port[port_num].dev);
1875
1876 ops->shutdown();
1877
1878 clear_priv_data();
1879
1880 return 0;
1881 }
1882
1883 static struct platform_driver ltq_atm_driver = {
1884 .probe = ltq_atm_probe,
1885 .remove = ltq_atm_remove,
1886 .driver = {
1887 .name = "atm",
1888 .owner = THIS_MODULE,
1889 .of_match_table = ltq_atm_match,
1890 },
1891 };
1892
1893 module_platform_driver(ltq_atm_driver);
1894
1895 MODULE_LICENSE("Dual BSD/GPL");
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