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base-files: fix uid/gid auto-enumeration to avoid 16-bit limit
[openwrt/openwrt.git] / package / kernel / lantiq / ltq-vmmc / patches / 400-falcon.patch
1 --- a/configure.in
2 +++ b/configure.in
3 @@ -956,14 +956,15 @@ AC_DEFINE([VMMC],[1],[enable VMMC suppor
4 AM_CONDITIONAL(DANUBE, false)
5 AM_CONDITIONAL(AR9, false)
6 AM_CONDITIONAL(VR9, false)
7 +AM_CONDITIONAL(FALCON, false)
8 AC_ARG_WITH(device,
9 AC_HELP_STRING(
10 - [--with-device=DANUBE|TWINPASS|AR9|VR9],
11 + [--with-device=DANUBE|TWINPASS|AR9|VR9|FALCON],
12 [Set device type, default is DANUBE]
13 ),
14 [
15 if test "$withval" = yes; then
16 - AC_MSG_ERROR([Set device type! Valid choices are DANUBE|TWINPASS|AR9|VR9]);
17 + AC_MSG_ERROR([Set device type! Valid choices are DANUBE|TWINPASS|AR9|VR9|FALCON]);
18 else
19 case $withval in
20 DANUBE)
21 @@ -986,8 +987,13 @@ AC_ARG_WITH(device,
22 AC_DEFINE([SYSTEM_VR9],[1],[enable VR9 specific code])
23 AM_CONDITIONAL(VR9, true)
24 ;;
25 + FALCON)
26 + AC_MSG_RESULT(FALCON device is used);
27 + AC_DEFINE([SYSTEM_FALCON],[1],[enable FALCON specific code])
28 + AM_CONDITIONAL(FALCON, true)
29 + ;;
30 *)
31 - AC_MSG_ERROR([Set device type! Valid choices are DANUBE|TWINPASS|AR9|VR9]);
32 + AC_MSG_ERROR([Set device type! Valid choices are DANUBE|TWINPASS|AR9|VR9|FALCON]);
33 ;;
34 esac
35 fi
36 --- a/src/Makefile.am
37 +++ b/src/Makefile.am
38 @@ -70,6 +70,11 @@ drv_vmmc_SOURCES +=\
39 mps/drv_mps_vmmc_ar9.c
40 endif
41
42 +if FALCON
43 +drv_vmmc_SOURCES +=\
44 + mps/drv_mps_vmmc_falcon.c
45 +endif
46 +
47 endif
48
49 if PMC_SUPPORT
50 --- a/drv_version.h
51 +++ b/drv_version.h
52 @@ -36,6 +36,10 @@
53 #define MIN_FW_MAJORSTEP 2
54 #define MIN_FW_MINORSTEP 1
55 #define MIN_FW_HOTFIXSTEP 0
56 +#elif defined(SYSTEM_FALCON)
57 +#define MIN_FW_MAJORSTEP 0
58 +#define MIN_FW_MINORSTEP 1
59 +#define MIN_FW_HOTFIXSTEP 0
60 #else
61 #error unknown system
62 #endif
63 --- a/src/drv_vmmc_bbd.c
64 +++ b/src/drv_vmmc_bbd.c
65 @@ -34,6 +34,7 @@
66 #define VMMC_WL_SDD_BASIC_CFG 0x04000400
67 #define VMMC_WL_SDD_RING_CFG 0x04000500
68 #define VMMC_WL_SDD_DCDC_CFG 0x04000C00
69 +#define VMMC_WL_SDD_MWI_CFG 0x04000600
70
71 #define IDLE_EXT_TOGGLE_SLEEP_MS 5
72
73 @@ -52,6 +53,8 @@
74 #define BBD_VMMC_MAGIC 0x41523921 /* "AR9" */
75 #elif defined(SYSTEM_VR9)
76 #define BBD_VMMC_MAGIC 0x56523921 /* "VR9" */
77 +#elif defined(SYSTEM_FALCON)
78 +#define BBD_VMMC_MAGIC 0x46414C43 /* "FALC" */
79 #else
80 #error system undefined
81 #endif
82 @@ -525,9 +528,6 @@ static IFX_int32_t VMMC_BBD_BlockHandler
83 IFX_uint16_t slic_val;
84 IFX_int32_t ret = IFX_SUCCESS;
85
86 - TRACE(VMMC, DBG_LEVEL_LOW,
87 - ("bbd block with tag 0x%04X passed\n", pBBDblock->tag));
88 -
89 /* for FXO line allowed blocks are FXO_CRAM and TRANSPARENT */
90 if (pCh->pALM->line_type_fxs != IFX_TRUE)
91 {
92 @@ -686,6 +686,7 @@ static IFX_int32_t VMMC_BBD_BlockHandler
93 break;
94 }
95 } /* if */
96 +
97 return ret;
98 }
99
100 @@ -1026,6 +1027,7 @@ static IFX_int32_t vmmc_BBD_WhiteListedC
101 }
102 case VMMC_WL_SDD_RING_CFG:
103 case VMMC_WL_SDD_DCDC_CFG:
104 + case VMMC_WL_SDD_MWI_CFG:
105 ret = CmdWrite (pCh->pParent, Msg.val, Msg.cmd.LENGTH);
106 break;
107
108 @@ -1068,7 +1070,7 @@ static IFX_int32_t vmmc_BBD_DownloadChCr
109 IFX_uint32_t countWords;
110 IFX_uint32_t posBytes = 0;
111 IFX_uint8_t lenBytes, *pByte;
112 -#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
113 +#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
114 IFX_uint8_t padBytes = 0;
115 #endif
116 IFX_uint16_t cram_offset, cram_crc,
117 @@ -1088,7 +1090,7 @@ static IFX_int32_t vmmc_BBD_DownloadChCr
118 #ifdef SYSTEM_DANUBE
119 /* CMD1 is a COP command */
120 pCmd[0] = (0x0200) | (pCh->nChannel - 1);
121 -#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
122 +#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
123 /* SDD_Coef command */
124 pCmd[0] = (0x0400) | (pCh->nChannel - 1);
125 pCmd[1] = (0x0D00);
126 @@ -1111,7 +1113,7 @@ static IFX_int32_t vmmc_BBD_DownloadChCr
127 pCmd[1] = ((cram_offset + (posBytes >> 1)) << 8);
128 /* set CRAM data while taking care of endianess */
129 cpb2w (&pCmd[2], &pByte[posBytes], lenBytes);
130 -#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
131 +#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
132 /* calculate length to download (in words = 16bit),
133 maximum allowed length for this message is 56 Bytes = 28 Words */
134 if (countWords > ((MAX_CMD_WORD - CMD_HDR_CNT - 1)))
135 @@ -1140,7 +1142,7 @@ static IFX_int32_t vmmc_BBD_DownloadChCr
136 /* write Data */
137 #if defined SYSTEM_DANUBE
138 ret = CmdWrite (pCh->pParent, (IFX_uint32_t *) pCmd, lenBytes);
139 -#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
140 +#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
141 #if 1
142 /* lenBytes + 2 bytes for block offset/length which are not calculated
143 in the download progress */
144 --- a/src/mps/drv_mps_version.h
145 +++ b/src/mps/drv_mps_version.h
146 @@ -17,7 +17,7 @@
147 #define VERSIONSTEP 2
148 #define VERS_TYPE 5
149
150 -#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
151 +#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
152 #define IFX_MPS_PLATFORM_NAME "MIPS34KEc"
153 #elif defined(SYSTEM_DANUBE)
154 #define IFX_MPS_PLATFORM_NAME "MIPS24KEc"
155 --- a/src/mps/drv_mps_vmmc_linux.c
156 +++ b/src/mps/drv_mps_vmmc_linux.c
157 @@ -2229,7 +2229,7 @@ IFX_int32_t __init ifx_mps_init_module (
158 #if defined(CONFIG_MIPS) && !defined(CONFIG_MIPS_UNCACHED)
159 #if defined(SYSTEM_DANUBE)
160 bDoCacheOps = IFX_TRUE; /* on Danube always perform cache ops */
161 -#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
162 +#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
163 /* on AR9/VR9 cache is configured by BSP;
164 here we check whether the D-cache is shared or partitioned;
165 1) in case of shared D-cache all cache operations are omitted;
166 @@ -2259,7 +2259,8 @@ IFX_int32_t __init ifx_mps_init_module (
167
168 /* reset the device before initializing the device driver */
169 ifx_mps_reset ();
170 - result = request_irq (INT_NUM_IM4_IRL18,
171 +
172 + result = request_irq (INT_NUM_IM4_IRL18,
173 #ifdef LINUX_2_6
174 ifx_mps_ad0_irq, 0x0
175 #else /* */
176 @@ -2400,7 +2401,7 @@ IFX_int32_t __init ifx_mps_init_module (
177 if (result = ifx_mps_init_gpt_danube ())
178 return result;
179 #endif /*DANUBE*/
180 - TRACE (MPS, DBG_LEVEL_HIGH, ("Downloading Firmware...\n"));
181 + TRACE (MPS, DBG_LEVEL_HIGH, ("Downloading Firmware...\n"));
182 ifx_mps_download_firmware (IFX_NULL, (mps_fw *) 0xa0a00000);
183 udelay (500);
184 TRACE (MPS, DBG_LEVEL_HIGH, ("Providing Buffers...\n"));
185 --- /dev/null
186 +++ b/src/mps/drv_mps_vmmc_falcon.c
187 @@ -0,0 +1,396 @@
188 +/******************************************************************************
189 +
190 + Copyright (c) 2009
191 + Lantiq Deutschland GmbH
192 + Am Campeon 3; 85579 Neubiberg, Germany
193 +
194 + For licensing information, see the file 'LICENSE' in the root folder of
195 + this software module.
196 +
197 +****************************************************************************
198 + Module : drv_mps_vmmc_falcon.c
199 + Description : This file contains the implementation of the FALC-ON specific
200 + driver functions.
201 +*******************************************************************************/
202 +
203 +/* ============================= */
204 +/* Includes */
205 +/* ============================= */
206 +#include "drv_config.h"
207 +
208 +#if defined(SYSTEM_FALCON) /* defined in drv_config.h */
209 +
210 +/* lib_ifxos headers */
211 +#include "ifx_types.h"
212 +#include "ifxos_linux_drv.h"
213 +#include "ifxos_copy_user_space.h"
214 +#include "ifxos_event.h"
215 +#include "ifxos_lock.h"
216 +#include "ifxos_select.h"
217 +#include "ifxos_interrupt.h"
218 +#include <linux/gpio.h>
219 +#include <sys1_reg.h>
220 +#include <falcon.h>
221 +#include <falcon_irq.h>
222 +#include <vpe.h>
223 +#include <sysctrl.h>
224 +void (*ifx_bsp_basic_mps_decrypt)(unsigned int addr, int n) = (void (*)(unsigned int, int))0xbf000290;
225 +
226 +#define IFX_MPS_SRAM IFXMIPS_MPS_SRAM
227 +
228 +/*#define USE_PLAIN_VOICE_FIRMWARE*/
229 +/* board specific headers */
230 +
231 +/* device specific headers */
232 +#include "drv_mps_vmmc.h"
233 +#include "drv_mps_vmmc_dbg.h"
234 +#include "drv_mps_vmmc_device.h"
235 +
236 +/* ============================= */
237 +/* Local Macros & Definitions */
238 +/* ============================= */
239 +/* Firmware watchdog timer counter address */
240 +#define VPE1_WDOG_CTR_ADDR ((IFX_uint32_t)((IFX_uint8_t* )IFX_MPS_SRAM + 432))
241 +
242 +/* Firmware watchdog timeout range, values in ms */
243 +#define VPE1_WDOG_TMOUT_MIN 20
244 +#define VPE1_WDOG_TMOUT_MAX 5000
245 +
246 +/* ============================= */
247 +/* Global variable definition */
248 +/* ============================= */
249 +extern mps_comm_dev *pMPSDev;
250 +
251 +/* ============================= */
252 +/* Global function declaration */
253 +/* ============================= */
254 +IFX_void_t ifx_mps_release (IFX_void_t);
255 +extern IFX_uint32_t ifx_mps_reset_structures (mps_comm_dev * pMPSDev);
256 +extern IFX_int32_t ifx_mps_bufman_close (IFX_void_t);
257 +extern IFXOS_event_t fw_ready_evt;
258 +
259 +/* ============================= */
260 +/* Local variable definition */
261 +/* ============================= */
262 +static IFX_int32_t vpe1_started = 0;
263 +/* VMMC watchdog timer callback */
264 +IFX_int32_t (*ifx_wdog_callback) (IFX_uint32_t flags) = IFX_NULL;
265 +
266 +/* ============================= */
267 +/* Local function definition */
268 +/* ============================= */
269 +
270 +/******************************************************************************
271 + * AR9 Specific Routines
272 + ******************************************************************************/
273 +
274 +/**
275 + * Firmware download to Voice CPU
276 + * This function performs a firmware download to the coprocessor.
277 + *
278 + * \param pMBDev Pointer to mailbox device structure
279 + * \param pFWDwnld Pointer to firmware structure
280 + * \return 0 IFX_SUCCESS, firmware ready
281 + * \return -1 IFX_ERROR, firmware not downloaded.
282 + * \ingroup Internal
283 + */
284 +IFX_int32_t ifx_mps_download_firmware (mps_mbx_dev *pMBDev, mps_fw *pFWDwnld)
285 +{
286 + IFX_uint32_t mem, cksum;
287 + IFX_uint8_t crc;
288 + IFX_boolean_t bMemReqNotPresent = IFX_FALSE;
289 +
290 + /* VCC register */
291 + /* dummy accesss on GTC for GPONC-55, otherwise upper bits are random on read */
292 + ltq_r32 ((u32 *)((KSEG1 | 0x1DC000B0)));
293 + /* NTR Frequency Select 1536 kHz per default or take existing,
294 + NTR Output Enable and NTR8K Output Enable */
295 + if ((ltq_r32 ((u32 *)(GPON_SYS_BASE + 0xBC)) & 7) == 0)
296 + ltq_w32_mask (0x10187, 0x183, (u32 *)(GPON_SYS_BASE + 0xBC));
297 + else
298 + ltq_w32_mask (0x10180, 0x180, (u32 *)(GPON_SYS_BASE + 0xBC));
299 +#if 0
300 + /* BIU-ICU1-IM1_ISR - IM1:FSCT_CMP1=1 and FSC_ROOT=1
301 + (0x1f880328 = 0x00002800) */
302 + ltq_w32 (0x00002800, (u32 *)(GPON_ICU1_BASE + 0x30));
303 +#endif
304 + /* copy FW footer from user space */
305 + if (IFX_NULL == IFXOS_CpyFromUser(pFW_img_data,
306 + pFWDwnld->data+pFWDwnld->length/4-sizeof(*pFW_img_data)/4,
307 + sizeof(*pFW_img_data)))
308 + {
309 + TRACE (MPS, DBG_LEVEL_HIGH,
310 + (KERN_ERR "[%s %s %d]: copy_from_user error\r\n",
311 + __FILE__, __func__, __LINE__));
312 + return IFX_ERROR;
313 + }
314 +
315 + mem = pFW_img_data->mem;
316 +
317 + /* memory requirement sanity check */
318 + if ((crc = ~((mem >> 16) + (mem >> 8) + mem)) != (mem >> 24))
319 + {
320 + TRACE (MPS, DBG_LEVEL_HIGH,
321 + ("[%s %s %d]: warning, image does not contain size - assuming 1MB!\n",
322 + __FILE__, __func__, __LINE__));
323 + mem = 1 * 1024 * 1024;
324 + bMemReqNotPresent = IFX_TRUE;
325 + }
326 + else
327 + {
328 + mem &= 0x00FFFFFF;
329 + }
330 +
331 + /* check if FW image fits in available memory space */
332 + if (mem > vpe1_get_max_mem(0))
333 + {
334 + TRACE (MPS, DBG_LEVEL_HIGH,
335 + ("[%s %s %d]: error, firmware memory exceeds reserved space (%i > %i)!\n",
336 + __FILE__, __func__, __LINE__, mem, vpe1_get_max_mem(0)));
337 + return IFX_ERROR;
338 + }
339 +
340 + /* reset the driver */
341 + ifx_mps_reset ();
342 +
343 + /* call BSP to get cpu1 base address */
344 + cpu1_base_addr = (IFX_uint32_t *)vpe1_get_load_addr(0);
345 +
346 + /* check if CPU1 base address is sane
347 + \todo: check if address is 1MB aligned,
348 + also make it visible in a /proc fs */
349 + if (!cpu1_base_addr)
350 + {
351 + TRACE (MPS, DBG_LEVEL_HIGH,
352 + (KERN_ERR "IFX_MPS: CPU1 base address is invalid!\r\n"));
353 + return IFX_ERROR;
354 + }
355 + /* further use uncached value */
356 + cpu1_base_addr = (IFX_uint32_t *)KSEG1ADDR(cpu1_base_addr);
357 +
358 + /* free all data buffers that might be currently used by FW */
359 + if (IFX_NULL != ifx_mps_bufman_freeall)
360 + {
361 + ifx_mps_bufman_freeall();
362 + }
363 +
364 + if(FW_FORMAT_NEW)
365 + {
366 + /* adjust download length */
367 + pFWDwnld->length -= (sizeof(*pFW_img_data)-sizeof(IFX_uint32_t));
368 + }
369 + else
370 + {
371 + pFWDwnld->length -= sizeof(IFX_uint32_t);
372 +
373 + /* handle unlikely case if FW image does not contain memory requirement -
374 + assumed for old format only */
375 + if (IFX_TRUE == bMemReqNotPresent)
376 + pFWDwnld->length += sizeof(IFX_uint32_t);
377 +
378 + /* in case of old FW format always assume that FW is encrypted;
379 + use compile switch USE_PLAIN_VOICE_FIRMWARE for plain FW */
380 +#ifndef USE_PLAIN_VOICE_FIRMWARE
381 + pFW_img_data->enc = 1;
382 +#else
383 +#warning Using unencrypted firmware!
384 + pFW_img_data->enc = 0;
385 +#endif /* USE_PLAIN_VOICE_FIRMWARE */
386 + /* initializations for the old format */
387 + pFW_img_data->st_addr_crc = 2*sizeof(IFX_uint32_t) +
388 + FW_AR9_OLD_FMT_XCPT_AREA_SZ;
389 + pFW_img_data->en_addr_crc = pFWDwnld->length;
390 + pFW_img_data->fw_vers = 0;
391 + pFW_img_data->magic = 0;
392 + }
393 +
394 + /* copy FW image to base address of CPU1 */
395 + if (IFX_NULL ==
396 + IFXOS_CpyFromUser ((IFX_void_t *)cpu1_base_addr,
397 + (IFX_void_t *)pFWDwnld->data, pFWDwnld->length))
398 + {
399 + TRACE (MPS, DBG_LEVEL_HIGH,
400 + (KERN_ERR "[%s %s %d]: copy_from_user error\r\n", __FILE__,
401 + __func__, __LINE__));
402 + return IFX_ERROR;
403 + }
404 +
405 + /* process firmware decryption */
406 + if (pFW_img_data->enc == 1)
407 + {
408 + if(FW_FORMAT_NEW)
409 + {
410 + /* adjust decryption length (avoid decrypting CRC32 checksum) */
411 + pFWDwnld->length -= sizeof(IFX_uint32_t);
412 + }
413 + /* BootROM actually decrypts n+4 bytes if n bytes were passed for
414 + decryption. Subtract sizeof(u32) from length to avoid decryption
415 + of data beyond the FW image code */
416 + pFWDwnld->length -= sizeof(IFX_uint32_t);
417 + ifx_bsp_basic_mps_decrypt((unsigned int)cpu1_base_addr, pFWDwnld->length);
418 + }
419 +
420 + /* calculate CRC32 checksum over downloaded image */
421 + cksum = ifx_mps_fw_crc32(cpu1_base_addr, pFW_img_data);
422 +
423 + /* verify the checksum */
424 + if(FW_FORMAT_NEW)
425 + {
426 + if (cksum != pFW_img_data->crc32)
427 + {
428 + TRACE (MPS, DBG_LEVEL_HIGH,
429 + ("MPS: FW checksum error: img=0x%08x calc=0x%08x\r\n",
430 + pFW_img_data->crc32, cksum));
431 + return IFX_ERROR;
432 + }
433 + }
434 + else
435 + {
436 + /* just store self-calculated checksum */
437 + pFW_img_data->crc32 = cksum;
438 + }
439 +
440 + /* start VPE1 */
441 + ifx_mps_release ();
442 +
443 + /* get FW version */
444 + return ifx_mps_get_fw_version (0);
445 +}
446 +
447 +
448 +/**
449 + * Restart CPU1
450 + * This function restarts CPU1 by accessing the reset request register and
451 + * reinitializes the mailbox.
452 + *
453 + * \return 0 IFX_SUCCESS, successful restart
454 + * \return -1 IFX_ERROR, if reset failed
455 + * \ingroup Internal
456 + */
457 +IFX_int32_t ifx_mps_restart (IFX_void_t)
458 +{
459 + /* raise reset request for CPU1 and reset driver structures */
460 + ifx_mps_reset ();
461 + /* Disable GPTC Interrupt to CPU1 */
462 + ifx_mps_shutdown_gpt ();
463 + /* re-configure GPTC */
464 + ifx_mps_init_gpt ();
465 + /* let CPU1 run */
466 + ifx_mps_release ();
467 + TRACE (MPS, DBG_LEVEL_HIGH, ("IFX_MPS: Restarting firmware..."));
468 + return ifx_mps_get_fw_version (0);
469 +}
470 +
471 +/**
472 + * Shutdown MPS - stop VPE1
473 + * This function stops VPE1
474 + *
475 + * \ingroup Internal
476 + */
477 +IFX_void_t ifx_mps_shutdown (IFX_void_t)
478 +{
479 + if (vpe1_started)
480 + {
481 + /* stop VPE1 */
482 + vpe1_sw_stop (0);
483 + vpe1_started = 0;
484 + }
485 + /* free GPTC */
486 + ifx_mps_shutdown_gpt ();
487 +}
488 +
489 +/**
490 + * Reset CPU1
491 + * This function causes a reset of CPU1 by clearing the CPU0 boot ready bit
492 + * in the reset request register RCU_RST_REQ.
493 + * It does not change the boot configuration registers for CPU0 or CPU1.
494 + *
495 + * \return 0 IFX_SUCCESS, cannot fail
496 + * \ingroup Internal
497 + */
498 +IFX_void_t ifx_mps_reset (IFX_void_t)
499 +{
500 + /* if VPE1 is already started, stop it */
501 + if (vpe1_started)
502 + {
503 + vpe1_sw_stop (0);
504 + vpe1_started = 0;
505 + }
506 +
507 + /* reset driver */
508 + ifx_mps_reset_structures (pMPSDev);
509 + ifx_mps_bufman_close ();
510 + return;
511 +}
512 +
513 +/**
514 + * Let CPU1 run
515 + * This function starts VPE1
516 + *
517 + * \return none
518 + * \ingroup Internal
519 + */
520 +IFX_void_t ifx_mps_release (IFX_void_t)
521 +{
522 + IFX_int_t ret;
523 + IFX_int32_t RetCode = 0;
524 +
525 + /* Start VPE1 */
526 + if (IFX_SUCCESS !=
527 + vpe1_sw_start ((IFX_void_t *)cpu1_base_addr, 0, 0))
528 + {
529 + TRACE (MPS, DBG_LEVEL_HIGH, (KERN_ERR "Error starting VPE1\r\n"));
530 + return;
531 + }
532 + vpe1_started = 1;
533 +
534 + /* sleep 3 seconds until FW is ready */
535 + ret = IFXOS_EventWait (&fw_ready_evt, 3000, &RetCode);
536 + if ((ret == IFX_ERROR) && (RetCode == 1))
537 + {
538 + /* timeout */
539 + TRACE (MPS, DBG_LEVEL_HIGH,
540 + (KERN_ERR "[%s %s %d]: Timeout waiting for firmware ready.\r\n",
541 + __FILE__, __func__, __LINE__));
542 + /* recalculate and compare the firmware checksum */
543 + ifx_mps_fw_crc_compare(cpu1_base_addr, pFW_img_data);
544 + /* dump exception area on a console */
545 + ifx_mps_dump_fw_xcpt(cpu1_base_addr, pFW_img_data);
546 + }
547 +}
548 +
549 +/**
550 + * Register WDT callback.
551 + * This function is called by VMMC driver to register its callback in
552 + * the MPS driver.
553 + *
554 + * \return 0 IFX_SUCCESS, cannot fail
555 + * \ingroup Internal
556 + */
557 +IFX_int32_t
558 +ifx_mps_register_wdog_callback (IFX_int32_t (*pfn) (IFX_uint32_t flags))
559 +{
560 + ifx_wdog_callback = pfn;
561 + return 0;
562 +}
563 +
564 +/**
565 + Hardware setup on FALC ON
566 +*/
567 +void sys_hw_setup (void)
568 +{
569 + /* Set INFRAC register bit 1: clock enable of the GPE primary clock. */
570 + sys_gpe_hw_activate (0);
571 + /* enable 1.5 V */
572 + ltq_w32_mask (0xf, 0x0b, (u32 *)(GPON_SYS1_BASE | 0xbc));
573 + /* SYS1-CLKEN:GPTC = 1 and MPS, no longer FSCT = 1 */
574 + sys1_hw_activate (ACTS_MPS | ACTS_GPTC);
575 + /* GPTC:CLC:RMC = 1 */
576 + ltq_w32 (0x00000100, (u32 *)(KSEG1 | 0x1E100E00));
577 +}
578 +
579 +#ifndef VMMC_WITH_MPS
580 +EXPORT_SYMBOL (ifx_mps_register_wdog_callback);
581 +#endif /* !VMMC_WITH_MPS */
582 +
583 +#endif /* SYSTEM_FALCON */
584 --- a/src/mps/drv_mps_vmmc_common.c
585 +++ b/src/mps/drv_mps_vmmc_common.c
586 @@ -66,6 +66,10 @@ static void inline bsp_mask_and_ack_irq(
587 # include <asm/ifx/ifx_regs.h>
588 # include <asm/ifx/ifx_gptu.h>
589 #endif
590 +#if defined(SYSTEM_FALCON)
591 +#include <sys1_reg.h>
592 +#include <sysctrl.h>
593 +#endif
594
595 #include "drv_mps_vmmc.h"
596 #include "drv_mps_vmmc_dbg.h"
597 @@ -1156,7 +1160,12 @@ IFX_uint32_t ifx_mps_init_structures (mp
598 mailbox, * upstream and downstream direction. */
599 memset (
600 /* avoid to overwrite CPU boot registers */
601 +#if defined(SYSTEM_FALCON)
602 + (IFX_void_t *) MBX_Memory +
603 + 2 * sizeof (mps_boot_cfg_reg),
604 +#else
605 (IFX_void_t *) MBX_Memory,
606 +#endif
607 0,
608 sizeof (mps_mbx_reg) - 2 * sizeof (mps_boot_cfg_reg));
609 MBX_Memory->MBX_UPSTR_CMD_BASE =
610 @@ -2651,7 +2660,6 @@ IFX_void_t ifx_mps_enable_mailbox_int ()
611 #endif
612
613 *IFX_MPS_AD0ENR = Ad0Reg.val;
614 -
615 }
616
617 /**
618 @@ -2669,6 +2677,7 @@ IFX_void_t ifx_mps_disable_mailbox_int (
619 Ad0Reg.fld.cu_mbx = 0;
620 Ad0Reg.fld.du_mbx = 0;
621 *IFX_MPS_AD0ENR = Ad0Reg.val;
622 +
623 }
624
625 /**
626 @@ -2766,11 +2775,13 @@ irqreturn_t ifx_mps_ad0_irq (IFX_int32_t
627 /* handle only enabled interrupts */
628 MPS_Ad0StatusReg.val &= *IFX_MPS_AD0ENR;
629
630 +#if !defined(SYSTEM_FALCON)
631 #ifdef LINUX_2_6
632 bsp_mask_and_ack_irq (irq);
633 #else /* */
634 mask_and_ack_danube_irq (irq);
635 #endif /* */
636 +#endif /* !defined(SYSTEM_FALCON) */
637 /* FW is up and ready to process commands */
638 if (MPS_Ad0StatusReg.fld.dl_end)
639 {
640 @@ -2919,11 +2930,13 @@ irqreturn_t ifx_mps_ad1_irq (IFX_int32_t
641 /* handle only enabled interrupts */
642 MPS_Ad1StatusReg.val &= *IFX_MPS_AD1ENR;
643
644 +#if !defined(SYSTEM_FALCON)
645 #ifdef LINUX_2_6
646 bsp_mask_and_ack_irq (irq);
647 #else /* */
648 mask_and_ack_danube_irq (irq);
649 #endif /* */
650 +#endif /* !defined(SYSTEM_FALCON) */
651 pMPSDev->event.MPS_Ad1Reg.val = MPS_Ad1StatusReg.val;
652
653 /* use callback function or queue wake up to notify about data reception */
654 @@ -2977,11 +2990,13 @@ irqreturn_t ifx_mps_vc_irq (IFX_int32_t
655 IFX_MPS_CVC0SR[chan] = MPS_VCStatusReg.val;
656 /* handle only enabled interrupts */
657 MPS_VCStatusReg.val &= IFX_MPS_VC0ENR[chan];
658 +#if !defined(SYSTEM_FALCON)
659 #ifdef LINUX_2_6
660 bsp_mask_and_ack_irq (irq);
661 #else /* */
662 mask_and_ack_danube_irq (irq);
663 #endif /* */
664 +#endif /* !defined(SYSTEM_FALCON) */
665
666 pMPSDev->event.MPS_VCStatReg[chan].val = MPS_VCStatusReg.val;
667 #ifdef PRINT_ON_ERR_INTERRUPT
668 @@ -3126,6 +3141,7 @@ IFX_int32_t ifx_mps_get_fw_version (IFX_
669 */
670 IFX_return_t ifx_mps_init_gpt ()
671 {
672 +#if !defined(SYSTEM_FALCON)
673 unsigned long flags;
674 IFX_uint32_t timer_flags, timer, loops = 0;
675 IFX_ulong_t count;
676 @@ -3134,7 +3150,11 @@ IFX_return_t ifx_mps_init_gpt ()
677 #else /* Danube */
678 timer = TIMER1B;
679 #endif /* SYSTEM_AR9 || SYSTEM_VR9 */
680 +#endif
681
682 +#if defined(SYSTEM_FALCON)
683 + sys_hw_setup ();
684 +#else
685 /* calibration loop - required to syncronize GPTC interrupt with falling
686 edge of FSC clock */
687 timer_flags =
688 @@ -3179,7 +3199,7 @@ Probably already in use.\r\n", __FILE__,
689 #endif /* DEBUG */
690
691 IFXOS_UNLOCKINT (flags);
692 -
693 +#endif
694 return IFX_SUCCESS;
695 }
696
697 @@ -3194,6 +3214,9 @@ Probably already in use.\r\n", __FILE__,
698 */
699 IFX_void_t ifx_mps_shutdown_gpt (IFX_void_t)
700 {
701 +#if defined(SYSTEM_FALCON)
702 + sys1_hw_deactivate (ACTS_MPS);
703 +#else
704 IFX_uint32_t timer;
705 #if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
706 timer = TIMER1A;
707 @@ -3202,6 +3225,7 @@ IFX_void_t ifx_mps_shutdown_gpt (IFX_voi
708 #endif /* SYSTEM_AR9 || SYSTEM_VR9 */
709
710 ifx_gptu_timer_free (timer);
711 +#endif
712 }
713
714 /**
715 --- a/src/mps/drv_mps_vmmc_device.h
716 +++ b/src/mps/drv_mps_vmmc_device.h
717 @@ -22,7 +22,12 @@
718 # include <lantiq_soc.h>
719 # include <linux/gpio.h>
720 #define IFXMIPS_MPS_SRAM ((u32 *)(KSEG1 + 0x1F200000))
721 +#if defined(SYSTEM_FALCON)
722 +#define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1D004000)
723 +#else
724 #define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
725 +#endif
726 +
727 #define IFXMIPS_MPS_CHIPID ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0344))
728 #define IFXMIPS_MPS_VC0ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0000))
729 #define IFXMIPS_MPS_RVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0010))
730 @@ -73,10 +78,11 @@
731 /* MPS Common defines */
732 /* ============================= */
733
734 -#define MPS_BASEADDRESS 0xBF107000
735 -#define MPS_RAD0SR MPS_BASEADDRESS + 0x0004
736 -
737 +#if defined(SYSTEM_FALCON)
738 +#define MBX_BASEADDRESS 0xBF200040
739 +#else
740 #define MBX_BASEADDRESS 0xBF200000
741 +#endif
742 #define VCPU_BASEADDRESS 0xBF208000 /* 0xBF108000 */
743 /*---------------------------------------------------------------------------*/
744 #if !defined(CONFIG_LANTIQ)
745 @@ -118,7 +124,6 @@
746 /*---------------------------------------------------------------------------*/
747
748 #ifdef CONFIG_MPS_EVENT_MBX
749 -
750 #define MBX_CMD_FIFO_SIZE 64 /**< Size of command FIFO in bytes */
751 #define MBX_DATA_UPSTRM_FIFO_SIZE 64
752 #define MBX_DATA_DNSTRM_FIFO_SIZE 128
753 @@ -294,6 +299,10 @@ typedef struct
754 #ifdef CONFIG_MPS_EVENT_MBX
755 typedef struct
756 {
757 +#if defined(SYSTEM_FALCON)
758 + mps_boot_cfg_reg MBX_CPU0_BOOT_CFG; /**< CPU0 Boot Configuration */
759 + mps_boot_cfg_reg MBX_CPU1_BOOT_CFG; /**< CPU1 Boot Configuration */
760 +#endif
761 volatile IFX_uint32_t *MBX_UPSTR_CMD_BASE; /**< Upstream Command FIFO Base Address */
762 volatile IFX_uint32_t MBX_UPSTR_CMD_SIZE; /**< Upstream Command FIFO size in byte */
763 volatile IFX_uint32_t *MBX_DNSTR_CMD_BASE; /**< Downstream Command FIFO Base Address */
764 @@ -317,13 +326,19 @@ typedef struct
765 volatile IFX_uint32_t MBX_UPSTR_EVENT_WRITE; /**< Upstream Event FIFO Write Index */
766 volatile IFX_uint32_t MBX_EVENT[MBX_EVENT_DATA_WORDS];
767 volatile IFX_uint32_t reserved[4];
768 +#if !defined(SYSTEM_FALCON)
769 mps_boot_cfg_reg MBX_CPU0_BOOT_CFG; /**< CPU0 Boot Configuration */
770 mps_boot_cfg_reg MBX_CPU1_BOOT_CFG; /**< CPU1 Boot Configuration */
771 +#endif
772 } mps_mbx_reg;
773
774 #else /* */
775 typedef struct
776 {
777 +#if defined(SYSTEM_FALCON)
778 + mps_boot_cfg_reg MBX_CPU0_BOOT_CFG; /**< CPU0 Boot Configuration */
779 + mps_boot_cfg_reg MBX_CPU1_BOOT_CFG; /**< CPU1 Boot Configuration */
780 +#endif
781 volatile IFX_uint32_t *MBX_UPSTR_CMD_BASE; /**< Upstream Command FIFO Base Address */
782 volatile IFX_uint32_t MBX_UPSTR_CMD_SIZE; /**< Upstream Command FIFO size in byte */
783 volatile IFX_uint32_t *MBX_DNSTR_CMD_BASE; /**< Downstream Command FIFO Base Address */
784 @@ -341,8 +356,10 @@ typedef struct
785 volatile IFX_uint32_t MBX_DNSTR_DATA_READ; /**< Downstream Data FIFO Read Index */
786 volatile IFX_uint32_t MBX_DNSTR_DATA_WRITE; /**< Downstream Data FIFO Write Index */
787 volatile IFX_uint32_t MBX_DATA[MBX_DATA_WORDS];
788 +#if !defined(SYSTEM_FALCON)
789 mps_boot_cfg_reg MBX_CPU0_BOOT_CFG; /**< CPU0 Boot Configuration */
790 mps_boot_cfg_reg MBX_CPU1_BOOT_CFG; /**< CPU1 Boot Configuration */
791 +#endif
792 } mps_mbx_reg;
793 #endif /* CONFIG_MPS_EVENT_MBX */
794
795 --- a/src/drv_api.h
796 +++ b/src/drv_api.h
797 @@ -183,7 +183,7 @@
798 #endif
799
800 /* TAPI FXS Phone Detection feature is not available for Danube platform */
801 -#if defined(TAPI_PHONE_DETECTION) && (defined(SYSTEM_AR9) || defined(SYSTEM_VR9))
802 +#if defined(TAPI_PHONE_DETECTION) && (defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON))
803 #define VMMC_CFG_ADD_FEAT_PHONE_DETECTION VMMC_FEAT_PHONE_DETECTION
804 #else
805 #define VMMC_CFG_ADD_FEAT_PHONE_DETECTION 0
806 --- a/src/drv_vmmc_alm.c
807 +++ b/src/drv_vmmc_alm.c
808 @@ -800,7 +800,7 @@ IFX_void_t VMMC_ALM_Free_Ch_Structures (
809 }
810
811
812 -#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
813 +#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
814 /**
815 Check whether SmartSLIC is connected
816
817 @@ -836,7 +836,7 @@ IFX_boolean_t VMMC_ALM_SmartSLIC_IsConne
818 #endif /*SYSTEM_AR9 || SYSTEM_VR9*/
819
820
821 -#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
822 +#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
823 /**
824 Read the number of channels on the SmartSLIC.
825
826 @@ -1876,7 +1876,7 @@ IFX_int32_t VMMC_TAPI_LL_ALM_VMMC_Test_L
827 /* write updated message contents */
828 ret = CmdWrite (pDev, (IFX_uint32_t *)((IFX_void_t *)&debugCfg),
829 DCCTL_CMD_LEN);
830 -#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
831 +#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
832 IFX_uint32_t dcctrlLoop[2];
833 IFX_uint32_t ch = (IFX_uint32_t)(pCh->nChannel - 1);
834
835 --- a/src/drv_vmmc_alm.h
836 +++ b/src/drv_vmmc_alm.h
837 @@ -65,7 +65,7 @@ extern IFX_void_t irq_VMMC_ALM_LineDisab
838 extern IFX_void_t VMMC_ALM_CorrectLinemodeCache (VMMC_CHANNEL *pCh,
839 IFX_uint16_t lm);
840
841 -#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
842 +#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
843 extern IFX_boolean_t VMMC_ALM_SmartSLIC_IsConnected (
844 VMMC_DEVICE *pDev);
845
846 --- a/src/drv_vmmc_init.c
847 +++ b/src/drv_vmmc_init.c
848 @@ -52,15 +52,6 @@
849 #include "ifx_pmu.h"
850 #endif /* PMU_SUPPORTED */
851
852 -#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
853 -# define IFX_MPS_CAD0SR IFXMIPS_MPS_CAD0SR
854 -# define IFX_MPS_CAD1SR IFXMIPS_MPS_CAD1SR
855 -# define IFX_MPS_CVC0SR IFXMIPS_MPS_CVC0SR
856 -# define IFX_MPS_CVC1SR IFXMIPS_MPS_CVC1SR
857 -# define IFX_MPS_CVC2SR IFXMIPS_MPS_CVC2SR
858 -# define IFX_MPS_CVC3SR IFXMIPS_MPS_CVC3SR
859 -#endif
860 -
861 /* ============================= */
862 /* Local Macros & Definitions */
863 /* ============================= */
864 @@ -820,7 +811,7 @@ static IFX_int32_t VMMC_TAPI_LL_FW_Init(
865 MIN_FW_HOTFIXSTEP};
866 IFX_uint8_t tmp1, tmp2;
867 IFX_TAPI_RESOURCE nResource;
868 -#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
869 +#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
870 IFX_uint8_t nChannels, nFXOChannels;
871 #endif /*SYSTEM_AR9 || SYSTEM_VR9*/
872 IFX_int32_t ret = VMMC_statusOk;
873 @@ -874,7 +865,7 @@ static IFX_int32_t VMMC_TAPI_LL_FW_Init(
874 pDev->bSmartSlic = IFX_FALSE;
875 pDev->bSlicSupportsIdleMode = IFX_FALSE;
876
877 -#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
878 +#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
879 if (VMMC_SUCCESS(ret))
880 {
881 /* Reduce the number of ALM channels in the capabilities if the SLIC
882 --- a/src/drv_vmmc_ioctl.c
883 +++ b/src/drv_vmmc_ioctl.c
884 @@ -273,7 +273,7 @@ IFX_int32_t VMMC_Dev_Spec_Ioctl (IFX_TAP
885 case FIO_GET_VERS:
886 {
887 VMMC_IO_VERSION *pVers;
888 -#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
889 +#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
890 VMMC_SDD_REVISION_READ_t *pSDDVersCmd = IFX_NULL;
891 #endif /*SYSTEM_AR9 || SYSTEM_VR9*/
892 SYS_VER_t *pCmd;
893 @@ -322,7 +322,7 @@ IFX_int32_t VMMC_Dev_Spec_Ioctl (IFX_TAP
894 pVers->nTapiVers = 3;
895 pVers->nDrvVers = MAJORSTEP << 24 | MINORSTEP << 16 |
896 VERSIONSTEP << 8 | VERS_TYPE;
897 -#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
898 +#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
899 /* in case of SmartSLIC based systems, we can give some more
900 versions.*/
901 if (VMMC_ALM_SmartSLIC_IsConnected(pDev))
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