target/linux/at91/patches-5.10/111-clk-at91-sama7g5-register-cpu-clock.patch

   1 From 36e97c421dd9f866e31fe14bcb7af01334791890 Mon Sep 17 00:00:00 2001
   2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
   3 Date: Thu, 19 Nov 2020 17:43:17 +0200
   4 Subject: [PATCH 111/247] clk: at91: sama7g5: register cpu clock
   5
   6 Register CPU clock as being the master clock prescaler. This would
   7 be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider
   8 between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the
   9 frequencies supported by SAMA7G5 could be directly received from
  10 CPUPLL + master clock prescaler and the extra divider would do no work in
  11 case it would be enabled.
  12
  13 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
  14 Link: https://lore.kernel.org/r/1605800597-16720-12-git-send-email-claudiu.beznea@microchip.com
  15 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  16 ---
  17  drivers/clk/at91/sama7g5.c       | 13 ++++++-------
  18  include/dt-bindings/clock/at91.h |  1 +
  19  2 files changed, 7 insertions(+), 7 deletions(-)
  20
  21 --- a/drivers/clk/at91/sama7g5.c
  22 +++ b/drivers/clk/at91/sama7g5.c
  23 @@ -904,7 +904,7 @@ static void __init sama7g5_pmc_setup(str
  24         if (IS_ERR(regmap))
  25                 return;
  26
  27 -       sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1,
  28 +       sama7g5_pmc = pmc_data_allocate(PMC_CPU + 1,
  29                                         nck(sama7g5_systemck),
  30                                         nck(sama7g5_periphck),
  31                                         nck(sama7g5_gck), 8);
  32 @@ -981,18 +981,17 @@ static void __init sama7g5_pmc_setup(str
  33                 }
  34         }
  35
  36 -       parent_names[0] = md_slck_name;
  37 -       parent_names[1] = "mainck";
  38 -       parent_names[2] = "cpupll_divpmcck";
  39 -       parent_names[3] = "syspll_divpmcck";
  40 -       hw = at91_clk_register_master_pres(regmap, "mck0_pres", 4, parent_names,
  41 +       parent_names[0] = "cpupll_divpmcck";
  42 +       hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names,
  43                                            &mck0_layout, &mck0_characteristics,
  44                                            &pmc_mck0_lock,
  45                                            CLK_SET_RATE_PARENT, 0);
  46         if (IS_ERR(hw))
  47                 goto err_free;
  48
  49 -       hw = at91_clk_register_master_div(regmap, "mck0_div", "mck0_pres",
  50 +       sama7g5_pmc->chws[PMC_CPU] = hw;
  51 +
  52 +       hw = at91_clk_register_master_div(regmap, "mck0", "cpuck",
  53                                           &mck0_layout, &mck0_characteristics,
  54                                           &pmc_mck0_lock, 0);
  55         if (IS_ERR(hw))
  56 --- a/include/dt-bindings/clock/at91.h
  57 +++ b/include/dt-bindings/clock/at91.h
  58 @@ -34,6 +34,7 @@
  59  #define PMC_AUDIOPMCPLL                (PMC_MAIN + 6)
  60  #define PMC_AUDIOIOPLL         (PMC_MAIN + 7)
  61  #define PMC_ETHPLL             (PMC_MAIN + 8)
  62 +#define PMC_CPU                        (PMC_MAIN + 9)
  63
  64  #ifndef AT91_PMC_MOSCS
  65  #define AT91_PMC_MOSCS         0               /* MOSCS Flag */