1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 compatible = "qca,qca9550";
17 bootargs = "console=ttyS0,115200n8";
26 compatible = "mips,mips74Kc";
27 clocks = <&pll ATH79_CLK_CPU>;
33 compatible = "fixed-clock";
35 clock-output-names = "ref";
36 clock-frequency = <40000000>;
41 ddr_ctrl: memory-controller@18000000 {
42 compatible = "qca,qca9550-ddr-controller",
43 "qca,ar7240-ddr-controller";
44 reg = <0x18000000 0x100>;
46 #qca,ddr-wb-channel-cells = <1>;
49 uart0: uart@18020000 {
50 compatible = "ns16550a";
51 reg = <0x18020000 0x20>;
55 clocks = <&pll ATH79_CLK_REF>;
63 usb_phy0: usb-phy0@18030000 {
64 compatible ="qca,qca9550-usb-phy", "qca,ar7200-usb-phy";
65 reg = <0x18030000 4>, <0x18030004 4>;
67 reset-names = "usb-phy", "usb-suspend-override";
68 resets = <&rst 4>, <&rst 3>;
75 usb_phy1: usb-phy1@18030010 {
76 compatible = "qca,qca9550-usb-phy", "qca,ar7200-usb-phy";
77 reg = <0x18030010 4>, <0x18030014 4>;
79 reset-names = "usb-phy", "usb-suspend-override";
80 resets = <&rst2 4>, <&rst2 3>;
88 compatible = "qca,qca9550-gpio",
90 reg = <0x18040000 0x28>;
99 #interrupt-cells = <2>;
102 pinmux: pinmux@1804002c {
103 compatible = "pinctrl-single";
105 reg = <0x1804002c 0x44>;
109 pinctrl-single,bit-per-mux;
110 pinctrl-single,register-width = <32>;
111 pinctrl-single,function-mask = <0x1>;
112 #pinctrl-cells = <2>;
114 jtag_disable_pins: pinmux_jtag_disable_pins {
115 pinctrl-single,bits = <0x40 0x2 0x2>;
119 pll: pll-controller@18050000 {
120 compatible = "qca,qca9550-pll", "syscon";
121 reg = <0x18050000 0x50>;
124 clock-output-names = "cpu", "ddr", "ahb";
131 compatible = "qca,ar7130-wdt";
132 reg = <0x18060008 0x8>;
136 clocks = <&pll ATH79_CLK_AHB>;
140 rst: reset-controller@1806001c {
141 compatible = "qca,qca9550-reset",
143 reg = <0x1806001c 0x4>;
146 interrupt-parent = <&cpuintc>;
148 intc2: interrupt-controller2 {
149 compatible = "qca,ar9340-intc";
151 interrupt-parent = <&cpuintc>;
154 interrupt-controller;
155 #interrupt-cells = <1>;
157 qca,int-status-addr = <0xac>;
158 qca,pending-bits = <0xf>, /* wmac */
159 <0x1f0>; /* pcie rc 0 */
162 intc3: interrupt-controller3 {
163 compatible = "qca,ar9340-intc";
165 interrupt-parent = <&cpuintc>;
168 interrupt-controller;
169 #interrupt-cells = <1>;
171 qca,int-status-addr = <0xac>;
172 qca,pending-bits = <0x1f000>, /* pcie rc 1 */
173 <0x1000000>, /* usb1 */
174 <0x10000000>; /* usb2 */
178 rst2: reset-controller@180600c0 {
179 compatible = "qca,qca9550-reset",
182 reg = <0x180600c0 0x4>;
187 uart1: uart@18500000 {
188 compatible = "qca,ar9330-uart";
189 reg = <0x18500000 0x14>;
193 clocks = <&pll ATH79_CLK_REF>;
194 clock-names = "uart";
200 gmac: gmac@18070000 {
201 compatible = "qca,qca9550-gmac";
202 reg = <0x18070000 0x58>;
205 pcie0: pcie@180c0000 {
206 compatible = "qcom,qca9550-pci", "qcom,ar7240-pci";
207 #address-cells = <3>;
209 bus-range = <0x0 0x0>;
210 reg = <0x180c0000 0x1000>, /* CRP */
211 <0x180f0000 0x100>, /* CTRL */
212 <0x14000000 0x1000>; /* CFG */
213 reg-names = "crp_base", "ctrl_base", "cfg_base";
214 ranges = <0x2000000 0 0x10000000 0x10000000 0 0x02000000 /* pci memory */
215 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
216 interrupt-parent = <&intc2>;
221 resets = <&rst 6>, <&rst 7>;
222 reset-names = "hc", "phy";
224 interrupt-controller;
225 #interrupt-cells = <1>;
227 interrupt-map-mask = <0 0 0 1>;
228 interrupt-map = <0 0 0 0 &pcie0 0>;
232 wmac: wmac@18100000 {
233 compatible = "qca,qca9550-wmac";
234 reg = <0x18100000 0x10000>;
236 interrupt-parent = <&intc2>;
242 pcie1: pcie@18250000 {
243 compatible = "qcom,qca9550-pci", "qcom,ar7240-pci";
244 #address-cells = <3>;
246 bus-range = <0x0 0x0>;
247 reg = <0x18250000 0x1000>, /* CRP */
248 <0x18280000 0x100>, /* CTRL */
249 <0x16000000 0x1000>; /* CFG */
250 reg-names = "crp_base", "ctrl_base", "cfg_base";
251 ranges = <0x2000000 0 0x12000000 0x12000000 0 0x02000000 /* pci memory */
252 0x1000000 0 0x00000000 0x0000001 0 0x000001>; /* io space */
253 interrupt-parent = <&intc3>;
258 resets = <&rst2 6>, <&rst2 7>;
259 reset-names = "hc", "phy";
261 interrupt-controller;
262 #interrupt-cells = <1>;
264 interrupt-map-mask = <0 0 0 1>;
265 interrupt-map = <0 0 0 0 &pcie1 0>;
270 compatible = "generic-ehci";
271 reg = <0x1b000000 0x1fc>;
273 interrupt-parent = <&intc3>;
276 reset-names = "usb-host";
278 has-transaction-translator;
279 caps-offset = <0x100>;
281 phy-names = "usb-phy0";
286 #address-cells = <1>;
291 #trigger-source-cells = <0>;
296 compatible = "generic-ehci";
297 reg = <0x1b400000 0x1fc>;
299 interrupt-parent = <&intc3>;
302 reset-names = "usb-host";
304 has-transaction-translator;
305 caps-offset = <0x100>;
307 phy-names = "usb-phy1";
312 #address-cells = <1>;
317 #trigger-source-cells = <0>;
321 nand: nand@1b800200 {
322 compatible = "qca,ar934x-nand";
323 reg = <0x1b800200 0xb8>;
326 interrupt-parent = <&miscintc>;
329 reset-names = "nand";
331 nand-ecc-mode = "hw";
337 compatible = "qca,ar934x-spi";
338 reg = <0x1f000000 0x1c>;
340 clocks = <&pll ATH79_CLK_AHB>;
344 #address-cells = <1>;
351 compatible = "qca,ar9340-mdio";
355 compatible = "qca,qca9550-eth", "syscon";
357 pll-reg = <0 0x28 0>;
360 pll-data = <0x16000000 0x00000101 0x00001616>;
363 resets = <&rst 9>, <&rst 22>;
364 reset-names = "mac", "mdio";
368 compatible = "qca,ar9340-mdio";
372 compatible = "qca,qca9550-eth", "syscon";
374 pll-reg = <0 0x48 0>;
377 pll-data = <0x16000000 0x00000101 0x00001616>;
380 resets = <&rst 13>, <&rst 23>;
381 reset-names = "mac", "mdio";