target/linux/ath79/patches-5.10/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch

   1 From 60efe35257b063ce584968f9f80b437030ce6ba6 Mon Sep 17 00:00:00 2001
   2 From: David Bauer <mail@david-bauer.net>
   3 Date: Mon, 18 Mar 2019 00:54:06 +0100
   4 Subject: [PATCH] MIPS: ath79: add missing QCA955x GMAC registers
   5
   6 This adds missing GMAC register definitions for the Qualcomm Atheros
   7 QCA955X series MIPS SoCs.
   8
   9 They originate from the platforms U-Boot code and the AVM FRITZ!WLAN
  10 Repeater 450E's GPL tarball.
  11
  12 Signed-off-by: David Bauer <mail@david-bauer.net>
  13 ---
  14  .../mips/include/asm/mach-ath79/ar71xx_regs.h | 54 +++++++++++++++++++
  15  1 file changed, 54 insertions(+)
  16
  17 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  18 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  19 @@ -1246,7 +1246,12 @@
  20   */
  21
  22  #define QCA955X_GMAC_REG_ETH_CFG       0x00
  23 +#define QCA955X_GMAC_REG_SGMII_RESET   0x14
  24  #define QCA955X_GMAC_REG_SGMII_SERDES  0x18
  25 +#define QCA955X_GMAC_REG_MR_AN_CONTROL 0x1c
  26 +#define QCA955X_GMAC_REG_MR_AN_STATUS  0x20
  27 +#define QCA955X_GMAC_REG_SGMII_CONFIG  0x34
  28 +#define QCA955X_GMAC_REG_SGMII_DEBUG   0x58
  29
  30  #define QCA955X_ETH_CFG_RGMII_EN       BIT(0)
  31  #define QCA955X_ETH_CFG_MII_GE0                BIT(1)
  32 @@ -1268,9 +1273,58 @@
  33  #define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
  34  #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT        20
  35
  36 +#define QCA955X_SGMII_RESET_RX_CLK_N_RESET     0
  37 +#define QCA955X_SGMII_RESET_RX_CLK_N           BIT(0)
  38 +#define QCA955X_SGMII_RESET_TX_CLK_N           BIT(1)
  39 +#define QCA955X_SGMII_RESET_RX_125M_N          BIT(2)
  40 +#define QCA955X_SGMII_RESET_TX_125M_N          BIT(3)
  41 +#define QCA955X_SGMII_RESET_HW_RX_125M_N       BIT(4)
  42 +
  43  #define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS        BIT(15)
  44  #define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
  45  #define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
  46 +
  47 +#define QCA955X_MR_AN_CONTROL_SPEED_SEL1       BIT(6)
  48 +#define QCA955X_MR_AN_CONTROL_DUPLEX_MODE      BIT(8)
  49 +#define QCA955X_MR_AN_CONTROL_RESTART_AN       BIT(9)
  50 +#define QCA955X_MR_AN_CONTROL_POWER_DOWN       BIT(11)
  51 +#define QCA955X_MR_AN_CONTROL_AN_ENABLE                BIT(12)
  52 +#define QCA955X_MR_AN_CONTROL_SPEED_SEL0       BIT(13)
  53 +#define QCA955X_MR_AN_CONTROL_LOOPBACK         BIT(14)
  54 +#define QCA955X_MR_AN_CONTROL_PHY_RESET                BIT(15)
  55 +
  56 +#define QCA955X_MR_AN_STATUS_EXT_CAP           BIT(0)
  57 +#define QCA955X_MR_AN_STATUS_LINK_UP           BIT(2)
  58 +#define QCA955X_MR_AN_STATUS_AN_ABILITY                BIT(3)
  59 +#define QCA955X_MR_AN_STATUS_REMOTE_FAULT      BIT(4)
  60 +#define QCA955X_MR_AN_STATUS_AN_COMPLETE       BIT(5)
  61 +#define QCA955X_MR_AN_STATUS_NO_PREAMBLE       BIT(6)
  62 +#define QCA955X_MR_AN_STATUS_BASE_PAGE         BIT(7)
  63 +
  64 +#define QCA955X_SGMII_CONFIG_MODE_CTRL_SHIFT           0
  65 +#define QCA955X_SGMII_CONFIG_MODE_CTRL_MASK            0x7
  66 +#define QCA955X_SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE     BIT(3)
  67 +#define QCA955X_SGMII_CONFIG_MR_REG4_CHANGED           BIT(4)
  68 +#define QCA955X_SGMII_CONFIG_FORCE_SPEED               BIT(5)
  69 +#define QCA955X_SGMII_CONFIG_SPEED_SHIFT               6
  70 +#define QCA955X_SGMII_CONFIG_SPEED_MASK                        0xc0
  71 +#define QCA955X_SGMII_CONFIG_REMOTE_PHY_LOOPBACK       BIT(8)
  72 +#define QCA955X_SGMII_CONFIG_NEXT_PAGE_LOADED          BIT(9)
  73 +#define QCA955X_SGMII_CONFIG_MDIO_ENABLE               BIT(10)
  74 +#define QCA955X_SGMII_CONFIG_MDIO_PULSE                        BIT(11)
  75 +#define QCA955X_SGMII_CONFIG_MDIO_COMPLETE             BIT(12)
  76 +#define QCA955X_SGMII_CONFIG_PRBS_ENABLE               BIT(13)
  77 +#define QCA955X_SGMII_CONFIG_BERT_ENABLE               BIT(14)
  78 +
  79 +#define QCA955X_SGMII_DEBUG_TX_STATE_MASK      0xff
  80 +#define QCA955X_SGMII_DEBUG_TX_STATE_SHIFT     0
  81 +#define QCA955X_SGMII_DEBUG_RX_STATE_MASK      0xff00
  82 +#define QCA955X_SGMII_DEBUG_RX_STATE_SHIFT     8
  83 +#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_MASK 0xff0000
  84 +#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_SHIFT        16
  85 +#define QCA955X_SGMII_DEBUG_ARB_STATE_MASK     0xf000000
  86 +#define QCA955X_SGMII_DEBUG_ARB_STATE_SHIFT    24
  87 +
  88  /*
  89   * QCA956X GMAC Interface
  90   */