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generic: 6.1, 6.6: remove patch which breaks WAN on MT7621
[openwrt/openwrt.git] / target / linux / bcm63xx / patches-5.4 / 341-MIPS-BCM63XX-add-support-for-BCM6318.patch
1 From 60c29522a8c77d96145d965589c56befda7d4c3d Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jogo@openwrt.org>
3 Date: Sun, 8 Dec 2013 01:24:09 +0100
4 Subject: [PATCH 51/53] MIPS: BCM63XX: add support for BCM6318
5
6 ---
7 arch/mips/bcm63xx/Kconfig | 5 +
8 arch/mips/bcm63xx/boards/board_bcm963xx.c | 2 +-
9 arch/mips/bcm63xx/clk.c | 8 +-
10 arch/mips/bcm63xx/cpu.c | 53 +++++++++++
11 arch/mips/bcm63xx/dev-flash.c | 3 +
12 arch/mips/bcm63xx/dev-spi.c | 2 +-
13 arch/mips/bcm63xx/irq.c | 10 ++
14 arch/mips/bcm63xx/prom.c | 2 +-
15 arch/mips/bcm63xx/reset.c | 24 +++++
16 arch/mips/bcm63xx/setup.c | 5 +-
17 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 107 ++++++++++++++++++++++
18 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 75 ++++++++++++++-
19 arch/mips/include/asm/mach-bcm63xx/ioremap.h | 1 +
20 13 files changed, 291 insertions(+), 6 deletions(-)
21
22 --- a/arch/mips/bcm63xx/Kconfig
23 +++ b/arch/mips/bcm63xx/Kconfig
24 @@ -19,6 +19,11 @@ config BCM63XX_EHCI
25 select USB_EHCI_BIG_ENDIAN_DESC if USB_EHCI_HCD
26 select USB_EHCI_BIG_ENDIAN_MMIO if USB_EHCI_HCD
27
28 +config BCM63XX_CPU_6318
29 + bool "support 6318 CPU"
30 + select SYS_HAS_CPU_BMIPS32_3300
31 + select HAVE_PCI
32 +
33 config BCM63XX_CPU_6328
34 bool "support 6328 CPU"
35 select SYS_HAS_CPU_BMIPS4350
36 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
37 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
38 @@ -697,7 +697,7 @@ void __init board_prom_init(void)
39 /* read base address of boot chip select (0)
40 * 6328/6362 do not have MPI but boot from a fixed address
41 */
42 - if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) {
43 + if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) {
44 val = 0x18000000;
45 } else {
46 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
47 --- a/arch/mips/bcm63xx/clk.c
48 +++ b/arch/mips/bcm63xx/clk.c
49 @@ -289,7 +289,9 @@ static void hsspi_set(struct clk *clk, i
50 {
51 u32 mask;
52
53 - if (BCMCPU_IS_6328())
54 + if (BCMCPU_IS_6318())
55 + mask = CKCTL_6318_HSSPI_EN;
56 + else if (BCMCPU_IS_6328())
57 mask = CKCTL_6328_HSSPI_EN;
58 else if (BCMCPU_IS_6362())
59 mask = CKCTL_6362_HSSPI_EN;
60 @@ -444,6 +446,19 @@ static struct clk_lookup bcm3368_clks[]
61 CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1),
62 };
63
64 +static struct clk_lookup bcm6318_clks[] = {
65 + /* fixed rate clocks */
66 + CLKDEV_INIT(NULL, "periph", &clk_periph),
67 + CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
68 + CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
69 + /* gated clocks */
70 + CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
71 + CLKDEV_INIT(NULL, "usbh", &clk_usbh),
72 + CLKDEV_INIT(NULL, "usbd", &clk_usbh),
73 + CLKDEV_INIT(NULL, "hsspi", &clk_hsspi),
74 + CLKDEV_INIT(NULL, "pcie", &clk_pcie),
75 +};
76 +
77 static struct clk_lookup bcm6328_clks[] = {
78 /* fixed rate clocks */
79 CLKDEV_INIT(NULL, "periph", &clk_periph),
80 @@ -565,6 +580,7 @@ static struct clk_lookup bcm63268_clks[]
81 CLKDEV_INIT(NULL, "pcie", &clk_pcie),
82 };
83
84 +#define HSSPI_PLL_HZ_6318 250000000
85 #define HSSPI_PLL_HZ_6328 133333333
86 #define HSSPI_PLL_HZ_6362 400000000
87
88 @@ -574,6 +590,10 @@ static int __init bcm63xx_clk_init(void)
89 case BCM3368_CPU_ID:
90 clkdev_add_table(bcm3368_clks, ARRAY_SIZE(bcm3368_clks));
91 break;
92 + case BCM6318_CPU_ID:
93 + clk_hsspi_pll.rate = HSSPI_PLL_HZ_6318;
94 + clkdev_add_table(bcm6318_clks, ARRAY_SIZE(bcm6318_clks));
95 + break;
96 case BCM6328_CPU_ID:
97 clk_hsspi_pll.rate = HSSPI_PLL_HZ_6328;
98 clkdev_add_table(bcm6328_clks, ARRAY_SIZE(bcm6328_clks));
99 --- a/arch/mips/bcm63xx/cpu.c
100 +++ b/arch/mips/bcm63xx/cpu.c
101 @@ -41,6 +41,14 @@ static const int bcm3368_irqs[] = {
102 __GEN_CPU_IRQ_TABLE(3368)
103 };
104
105 +static const unsigned long bcm6318_regs_base[] = {
106 + __GEN_CPU_REGS_TABLE(6318)
107 +};
108 +
109 +static const int bcm6318_irqs[] = {
110 + __GEN_CPU_IRQ_TABLE(6318)
111 +};
112 +
113 static const unsigned long bcm6328_regs_base[] = {
114 __GEN_CPU_REGS_TABLE(6328)
115 };
116 @@ -134,6 +142,10 @@ unsigned int bcm63xx_get_memory_size(voi
117 return bcm63xx_memory_size;
118 }
119
120 +#define STRAP_OVERRIDE_BUS_REG 0x0
121 +#define OVERRIDE_BUS_MIPS_FREQ_SHIFT 23
122 +#define OVERRIDE_BUS_MIPS_FREQ_MASK (0x3 << OVERRIDE_BUS_MIPS_FREQ_SHIFT)
123 +
124 static unsigned int detect_cpu_clock(void)
125 {
126 u32 cpu_id = bcm63xx_get_cpu_id();
127 @@ -142,6 +154,30 @@ static unsigned int detect_cpu_clock(voi
128 case BCM3368_CPU_ID:
129 return 300000000;
130
131 + case BCM6318_CPU_ID:
132 + {
133 + unsigned int tmp, mips_pll_fcvo;
134 +
135 + tmp = bcm_readl(BCM_6318_STRAP_BASE + STRAP_OVERRIDE_BUS_REG);
136 +
137 + pr_info("strap_override_bus = %08x\n", tmp);
138 +
139 + mips_pll_fcvo = (tmp & OVERRIDE_BUS_MIPS_FREQ_MASK)
140 + >> OVERRIDE_BUS_MIPS_FREQ_SHIFT;
141 +
142 + switch (mips_pll_fcvo) {
143 + case 0:
144 + return 166000000;
145 + case 1:
146 + return 400000000;
147 + case 2:
148 + return 250000000;
149 + case 3:
150 + return 333000000;
151 + default:
152 + return 320000000;
153 + }
154 + }
155 case BCM6328_CPU_ID:
156 {
157 unsigned int tmp, mips_pll_fcvo;
158 @@ -297,6 +333,13 @@ static unsigned int detect_memory_size(v
159 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
160 u32 val;
161
162 + if (BCMCPU_IS_6318()) {
163 + val = bcm_sdram_readl(SDRAM_CFG_REG);
164 + val = val & SDRAM_CFG_6318_SPACE_MASK;
165 + val >>= SDRAM_CFG_6318_SPACE_SHIFT;
166 + return 1 << (val + 20);
167 + }
168 +
169 if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268())
170 return bcm_ddr_readl(DDR_CSEND_REG) << 24;
171
172 @@ -343,6 +386,12 @@ void __init bcm63xx_cpu_init(void)
173
174 switch (current_cpu_type()) {
175 case CPU_BMIPS3300:
176 + if ((read_c0_prid() & 0xff) >= 0x33) {
177 + /* BCM6318 */
178 + chipid_reg = BCM_6368_PERF_BASE;
179 + break;
180 + }
181 +
182 if ((read_c0_prid() & PRID_IMP_MASK) != PRID_IMP_BMIPS3300_ALT)
183 __cpu_name[cpu] = "Broadcom BCM6338";
184 /* fall-through */
185 @@ -390,6 +439,10 @@ void __init bcm63xx_cpu_init(void)
186 bcm63xx_cpu_variant = bcm63xx_cpu_id;
187
188 switch (bcm63xx_cpu_id) {
189 + case BCM6318_CPU_ID:
190 + bcm63xx_regs_base = bcm6318_regs_base;
191 + bcm63xx_irqs = bcm6318_irqs;
192 + break;
193 case BCM3368_CPU_ID:
194 bcm63xx_regs_base = bcm3368_regs_base;
195 bcm63xx_irqs = bcm3368_irqs;
196 --- a/arch/mips/bcm63xx/dev-flash.c
197 +++ b/arch/mips/bcm63xx/dev-flash.c
198 @@ -60,6 +60,9 @@ static int __init bcm63xx_detect_flash_t
199 u32 val;
200
201 switch (bcm63xx_get_cpu_id()) {
202 + case BCM6318_CPU_ID:
203 + /* only support serial flash */
204 + return BCM63XX_FLASH_TYPE_SERIAL;
205 case BCM6328_CPU_ID:
206 val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
207 if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
208 --- a/arch/mips/bcm63xx/dev-spi.c
209 +++ b/arch/mips/bcm63xx/dev-spi.c
210 @@ -38,7 +38,7 @@ static struct platform_device bcm63xx_sp
211
212 int __init bcm63xx_spi_register(void)
213 {
214 - if (BCMCPU_IS_6328() || BCMCPU_IS_6345())
215 + if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6345())
216 return -ENODEV;
217
218 spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
219 --- a/arch/mips/bcm63xx/irq.c
220 +++ b/arch/mips/bcm63xx/irq.c
221 @@ -48,6 +48,19 @@ void __init arch_init_irq(void)
222 ext_irqs[3] = BCM_3368_EXT_IRQ3;
223 ext_shift = 4;
224 break;
225 + case BCM6318_CPU_ID:
226 + periph_bases[0] += PERF_IRQMASK_6318_REG;
227 + periph_irq_count = 1;
228 + periph_width = 4;
229 +
230 + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6318;
231 + ext_irq_count = 4;
232 + ext_irqs[0] = BCM_6318_EXT_IRQ0;
233 + ext_irqs[1] = BCM_6318_EXT_IRQ0;
234 + ext_irqs[2] = BCM_6318_EXT_IRQ0;
235 + ext_irqs[3] = BCM_6318_EXT_IRQ0;
236 + ext_shift = 4;
237 + break;
238 case BCM6328_CPU_ID:
239 periph_bases[0] += PERF_IRQMASK_6328_REG(0);
240 periph_bases[1] += PERF_IRQMASK_6328_REG(1);
241 --- a/arch/mips/bcm63xx/prom.c
242 +++ b/arch/mips/bcm63xx/prom.c
243 @@ -68,7 +68,7 @@ void __init prom_init(void)
244
245 if (reg & OTP_6328_REG3_TP1_DISABLED)
246 bmips_smp_enabled = 0;
247 - } else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
248 + } else if (BCMCPU_IS_6318() || BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
249 bmips_smp_enabled = 0;
250 }
251
252 --- a/arch/mips/bcm63xx/reset.c
253 +++ b/arch/mips/bcm63xx/reset.c
254 @@ -44,6 +44,23 @@
255 #define BCM3368_RESET_PCIE 0
256 #define BCM3368_RESET_PCIE_EXT 0
257
258 +
259 +#define BCM6318_RESET_SPI SOFTRESET_6318_SPI_MASK
260 +#define BCM6318_RESET_ENET 0
261 +#define BCM6318_RESET_USBH SOFTRESET_6318_USBH_MASK
262 +#define BCM6318_RESET_USBD SOFTRESET_6318_USBS_MASK
263 +#define BCM6318_RESET_DSL 0
264 +#define BCM6318_RESET_SAR SOFTRESET_6318_SAR_MASK
265 +#define BCM6318_RESET_EPHY SOFTRESET_6318_EPHY_MASK
266 +#define BCM6318_RESET_ENETSW SOFTRESET_6318_ENETSW_MASK
267 +#define BCM6318_RESET_PCM 0
268 +#define BCM6318_RESET_MPI 0
269 +#define BCM6318_RESET_PCIE \
270 + (SOFTRESET_6318_PCIE_MASK | \
271 + SOFTRESET_6318_PCIE_CORE_MASK | \
272 + SOFTRESET_6318_PCIE_HARD_MASK)
273 +#define BCM6318_RESET_PCIE_EXT SOFTRESET_6318_PCIE_EXT_MASK
274 +
275 #define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK
276 #define BCM6328_RESET_ENET 0
277 #define BCM6328_RESET_USBH SOFTRESET_6328_USBH_MASK
278 @@ -148,6 +165,10 @@ static const u32 bcm3368_reset_bits[] =
279 __GEN_RESET_BITS_TABLE(3368)
280 };
281
282 +static const u32 bcm6318_reset_bits[] = {
283 + __GEN_RESET_BITS_TABLE(6318)
284 +};
285 +
286 static const u32 bcm6328_reset_bits[] = {
287 __GEN_RESET_BITS_TABLE(6328)
288 };
289 @@ -184,6 +205,9 @@ static int __init bcm63xx_reset_bits_ini
290 if (BCMCPU_IS_3368()) {
291 reset_reg = PERF_SOFTRESET_6358_REG;
292 bcm63xx_reset_bits = bcm3368_reset_bits;
293 + } else if (BCMCPU_IS_6318()) {
294 + reset_reg = PERF_SOFTRESET_6318_REG;
295 + bcm63xx_reset_bits = bcm6318_reset_bits;
296 } else if (BCMCPU_IS_6328()) {
297 reset_reg = PERF_SOFTRESET_6328_REG;
298 bcm63xx_reset_bits = bcm6328_reset_bits;
299 --- a/arch/mips/bcm63xx/setup.c
300 +++ b/arch/mips/bcm63xx/setup.c
301 @@ -72,6 +72,9 @@ void bcm63xx_machine_reboot(void)
302 case BCM3368_CPU_ID:
303 perf_regs[0] = PERF_EXTIRQ_CFG_REG_3368;
304 break;
305 + case BCM6318_CPU_ID:
306 + perf_regs[0] = PERF_EXTIRQ_CFG_REG_6318;
307 + break;
308 case BCM6328_CPU_ID:
309 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328;
310 break;
311 @@ -111,7 +114,7 @@ void bcm63xx_machine_reboot(void)
312 bcm6348_a1_reboot();
313
314 pr_info("triggering watchdog soft-reset...\n");
315 - if (BCMCPU_IS_6328()) {
316 + if (BCMCPU_IS_6318() || BCMCPU_IS_6328()) {
317 bcm_wdt_writel(1, WDT_SOFTRESET_REG);
318 } else {
319 reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
320 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
321 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
322 @@ -11,6 +11,7 @@
323 * arm mach-types)
324 */
325 #define BCM3368_CPU_ID 0x3368
326 +#define BCM6318_CPU_ID 0x6318
327 #define BCM6328_CPU_ID 0x6328
328 #define BCM63281_CPU_ID 0x63281
329 #define BCM63283_CPU_ID 0x63283
330 @@ -40,6 +41,10 @@ static inline u32 __pure __bcm63xx_get_c
331 case BCM3368_CPU_ID:
332 #endif
333
334 +#ifdef CONFIG_BCM63XX_CPU_6318
335 + case BCM6318_CPU_ID:
336 +#endif
337 +
338 #ifdef CONFIG_BCM63XX_CPU_6328
339 case BCM6328_CPU_ID:
340 #endif
341 @@ -89,6 +94,7 @@ static inline u32 __pure bcm63xx_get_cpu
342 }
343
344 #define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
345 +#define BCMCPU_IS_6318() (bcm63xx_get_cpu_id() == BCM6318_CPU_ID)
346 #define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
347 #define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
348 #define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
349 @@ -100,6 +106,8 @@ static inline u32 __pure bcm63xx_get_cpu
350
351 #define BCMCPU_VARIANT_IS_3368() \
352 (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID)
353 +#define BCMCPU_VARIANT_IS_6318() \
354 + (bcm63xx_get_cpu_variant() == BCM6318_CPU_ID)
355 #define BCMCPU_VARIANT_IS_63281() \
356 (bcm63xx_get_cpu_variant() == BCM63281_CPU_ID)
357 #define BCMCPU_VARIANT_IS_63283() \
358 @@ -256,6 +264,56 @@ enum bcm63xx_regs_set {
359 #define BCM_3368_MISC_BASE (0xdeadbeef)
360
361 /*
362 + * 6318 register sets base address
363 + */
364 +#define BCM_6318_DSL_LMEM_BASE (0xdeadbeef)
365 +#define BCM_6318_PERF_BASE (0xb0000000)
366 +#define BCM_6318_TIMER_BASE (0xb0000040)
367 +#define BCM_6318_WDT_BASE (0xb0000068)
368 +#define BCM_6318_UART0_BASE (0xb0000100)
369 +#define BCM_6318_UART1_BASE (0xdeadbeef)
370 +#define BCM_6318_GPIO_BASE (0xb0000080)
371 +#define BCM_6318_SPI_BASE (0xdeadbeef)
372 +#define BCM_6318_HSSPI_BASE (0xb0003000)
373 +#define BCM_6318_UDC0_BASE (0xdeadbeef)
374 +#define BCM_6318_USBDMA_BASE (0xb0006800)
375 +#define BCM_6318_OHCI0_BASE (0xb0005100)
376 +#define BCM_6318_OHCI_PRIV_BASE (0xdeadbeef)
377 +#define BCM_6318_USBH_PRIV_BASE (0xb0005200)
378 +#define BCM_6318_USBD_BASE (0xb0006000)
379 +#define BCM_6318_MPI_BASE (0xdeadbeef)
380 +#define BCM_6318_PCMCIA_BASE (0xdeadbeef)
381 +#define BCM_6318_PCIE_BASE (0xb0010000)
382 +#define BCM_6318_SDRAM_REGS_BASE (0xdeadbeef)
383 +#define BCM_6318_DSL_BASE (0xdeadbeef)
384 +#define BCM_6318_UBUS_BASE (0xdeadbeef)
385 +#define BCM_6318_ENET0_BASE (0xdeadbeef)
386 +#define BCM_6318_ENET1_BASE (0xdeadbeef)
387 +#define BCM_6318_ENETDMA_BASE (0xb0088000)
388 +#define BCM_6318_ENETDMAC_BASE (0xb0088200)
389 +#define BCM_6318_ENETDMAS_BASE (0xb0088400)
390 +#define BCM_6318_ENETSW_BASE (0xb0080000)
391 +#define BCM_6318_EHCI0_BASE (0xb0005000)
392 +#define BCM_6318_SDRAM_BASE (0xb0004000)
393 +#define BCM_6318_MEMC_BASE (0xdeadbeef)
394 +#define BCM_6318_DDR_BASE (0xdeadbeef)
395 +#define BCM_6318_M2M_BASE (0xdeadbeef)
396 +#define BCM_6318_ATM_BASE (0xdeadbeef)
397 +#define BCM_6318_XTM_BASE (0xdeadbeef)
398 +#define BCM_6318_XTMDMA_BASE (0xb000c000)
399 +#define BCM_6318_XTMDMAC_BASE (0xdeadbeef)
400 +#define BCM_6318_XTMDMAS_BASE (0xdeadbeef)
401 +#define BCM_6318_PCM_BASE (0xdeadbeef)
402 +#define BCM_6318_PCMDMA_BASE (0xdeadbeef)
403 +#define BCM_6318_PCMDMAC_BASE (0xdeadbeef)
404 +#define BCM_6318_PCMDMAS_BASE (0xdeadbeef)
405 +#define BCM_6318_RNG_BASE (0xdeadbeef)
406 +#define BCM_6318_MISC_BASE (0xb0000280)
407 +#define BCM_6318_OTP_BASE (0xdeadbeef)
408 +
409 +#define BCM_6318_STRAP_BASE (0xb0000900)
410 +
411 +/*
412 * 6328 register sets base address
413 */
414 #define BCM_6328_DSL_LMEM_BASE (0xdeadbeef)
415 @@ -778,6 +836,55 @@ enum bcm63xx_irq {
416 #define BCM_3368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
417 #define BCM_3368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
418
419 +/*
420 + * 6318 irqs
421 + */
422 +#define BCM_6318_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
423 +#define BCM_6318_VERY_HIGH_IRQ_BASE (BCM_6318_HIGH_IRQ_BASE + 32)
424 +
425 +#define BCM_6318_TIMER_IRQ (IRQ_INTERNAL_BASE + 31)
426 +#define BCM_6318_SPI_IRQ 0
427 +#define BCM_6318_UART0_IRQ (IRQ_INTERNAL_BASE + 28)
428 +#define BCM_6318_UART1_IRQ 0
429 +#define BCM_6318_DSL_IRQ (IRQ_INTERNAL_BASE + 21)
430 +#define BCM_6318_UDC0_IRQ 0
431 +#define BCM_6318_ENET0_IRQ 0
432 +#define BCM_6318_ENET1_IRQ 0
433 +#define BCM_6318_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
434 +#define BCM_6318_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29)
435 +#define BCM_6318_OHCI0_IRQ (BCM_6318_HIGH_IRQ_BASE + 9)
436 +#define BCM_6318_EHCI0_IRQ (BCM_6318_HIGH_IRQ_BASE + 10)
437 +#define BCM_6318_USBD_IRQ (IRQ_INTERNAL_BASE + 4)
438 +#define BCM_6318_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 5)
439 +#define BCM_6318_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 6)
440 +#define BCM_6318_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 7)
441 +#define BCM_6318_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 8)
442 +#define BCM_6318_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 9)
443 +#define BCM_6318_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 10)
444 +#define BCM_6318_PCMCIA_IRQ 0
445 +#define BCM_6318_ENET0_RXDMA_IRQ 0
446 +#define BCM_6318_ENET0_TXDMA_IRQ 0
447 +#define BCM_6318_ENET1_RXDMA_IRQ 0
448 +#define BCM_6318_ENET1_TXDMA_IRQ 0
449 +#define BCM_6318_PCI_IRQ (IRQ_INTERNAL_BASE + 23)
450 +#define BCM_6318_ATM_IRQ 0
451 +#define BCM_6318_ENETSW_RXDMA0_IRQ (BCM_6318_HIGH_IRQ_BASE + 0)
452 +#define BCM_6318_ENETSW_RXDMA1_IRQ (BCM_6318_HIGH_IRQ_BASE + 1)
453 +#define BCM_6318_ENETSW_RXDMA2_IRQ (BCM_6318_HIGH_IRQ_BASE + 2)
454 +#define BCM_6318_ENETSW_RXDMA3_IRQ (BCM_6318_HIGH_IRQ_BASE + 3)
455 +#define BCM_6318_ENETSW_TXDMA0_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 10)
456 +#define BCM_6318_ENETSW_TXDMA1_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 11)
457 +#define BCM_6318_ENETSW_TXDMA2_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 12)
458 +#define BCM_6318_ENETSW_TXDMA3_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 13)
459 +#define BCM_6318_XTM_IRQ (BCM_6318_HIGH_IRQ_BASE + 31)
460 +#define BCM_6318_XTM_DMA0_IRQ (BCM_6318_HIGH_IRQ_BASE + 11)
461 +
462 +#define BCM_6318_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2)
463 +#define BCM_6318_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3)
464 +#define BCM_6318_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24)
465 +#define BCM_6318_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25)
466 +#define BCM_6318_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26)
467 +#define BCM_6318_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27)
468
469 /*
470 * 6328 irqs
471 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
472 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
473 @@ -53,6 +53,39 @@
474 CKCTL_3368_EMUSB_EN | \
475 CKCTL_3368_USBU_EN)
476
477 +#define CKCTL_6318_ADSL_ASB_EN (1 << 0)
478 +#define CKCTL_6318_USB_ASB_EN (1 << 1)
479 +#define CKCTL_6318_MIPS_ASB_EN (1 << 2)
480 +#define CKCTL_6318_PCIE_ASB_EN (1 << 3)
481 +#define CKCTL_6318_PHYMIPS_ASB_EN (1 << 4)
482 +#define CKCTL_6318_ROBOSW_ASB_EN (1 << 5)
483 +#define CKCTL_6318_SAR_ASB_EN (1 << 6)
484 +#define CKCTL_6318_SDR_ASB_EN (1 << 7)
485 +#define CKCTL_6318_SWREG_ASB_EN (1 << 8)
486 +#define CKCTL_6318_PERIPH_ASB_EN (1 << 9)
487 +#define CKCTL_6318_CPUBUS160_EN (1 << 10)
488 +#define CKCTL_6318_ADSL_EN (1 << 11)
489 +#define CKCTL_6318_SAR125_EN (1 << 12)
490 +#define CKCTL_6318_MIPS_EN (1 << 13)
491 +#define CKCTL_6318_PCIE_EN (1 << 14)
492 +#define CKCTL_6318_ROBOSW250_EN (1 << 16)
493 +#define CKCTL_6318_ROBOSW025_EN (1 << 17)
494 +#define CKCTL_6318_SDR_EN (1 << 19)
495 +#define CKCTL_6318_USB_EN (1 << 20) /* both device and host */
496 +#define CKCTL_6318_HSSPI_EN (1 << 25)
497 +#define CKCTL_6318_PCIE25_EN (1 << 27)
498 +#define CKCTL_6318_PHYMIPS_EN (1 << 28)
499 +#define CKCTL_6318_ADSL_AFE_EN (1 << 29)
500 +#define CKCTL_6318_ADSL_QPROC_EN (1 << 30)
501 +
502 +#define CKCTL_6318_ALL_SAFE_EN (CKCTL_6318_PHYMIPS_EN | \
503 + CKCTL_6318_ADSL_QPROC_EN | \
504 + CKCTL_6318_ADSL_AFE_EN | \
505 + CKCTL_6318_ADSL_EN | \
506 + CKCTL_6318_SAR_EN | \
507 + CKCTL_6318_USB_EN | \
508 + CKCTL_6318_PCIE_EN)
509 +
510 #define CKCTL_6328_PHYMIPS_EN (1 << 0)
511 #define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
512 #define CKCTL_6328_ADSL_AFE_EN (1 << 2)
513 @@ -260,12 +293,27 @@
514 CKCTL_63268_TBUS_EN | \
515 CKCTL_63268_ROBOSW250_EN)
516
517 +/* UBUS Clock Control register */
518 +#define PERF_UB_CKCTL_REG 0x10
519 +
520 +#define UB_CKCTL_6318_ADSL_EN (1 << 0)
521 +#define UB_CKCTL_6318_ARB_EN (1 << 1)
522 +#define UB_CKCTL_6318_MIPS_EN (1 << 2)
523 +#define UB_CKCTL_6318_PCIE_EN (1 << 3)
524 +#define UB_CKCTL_6318_PERIPH_EN (1 << 4)
525 +#define UB_CKCTL_6318_PHYMIPS_EN (1 << 5)
526 +#define UB_CKCTL_6318_ROBOSW_EN (1 << 6)
527 +#define UB_CKCTL_6318_SAR_EN (1 << 7)
528 +#define UB_CKCTL_6318_SDR_EN (1 << 8)
529 +#define UB_CKCTL_6318_USB_EN (1 << 9)
530 +
531 /* System PLL Control register */
532 #define PERF_SYS_PLL_CTL_REG 0x8
533 #define SYS_PLL_SOFT_RESET 0x1
534
535 /* Interrupt Mask register */
536 #define PERF_IRQMASK_3368_REG 0xc
537 +#define PERF_IRQMASK_6318_REG 0x20
538 #define PERF_IRQMASK_6328_REG(x) (0x20 + (x) * 0x10)
539 #define PERF_IRQMASK_6338_REG 0xc
540 #define PERF_IRQMASK_6345_REG 0xc
541 @@ -277,6 +325,7 @@
542
543 /* Interrupt Status register */
544 #define PERF_IRQSTAT_3368_REG 0x10
545 +#define PERF_IRQSTAT_6318_REG 0x30
546 #define PERF_IRQSTAT_6328_REG(x) (0x28 + (x) * 0x10)
547 #define PERF_IRQSTAT_6338_REG 0x10
548 #define PERF_IRQSTAT_6345_REG 0x10
549 @@ -288,6 +337,7 @@
550
551 /* External Interrupt Configuration register */
552 #define PERF_EXTIRQ_CFG_REG_3368 0x14
553 +#define PERF_EXTIRQ_CFG_REG_6318 0x18
554 #define PERF_EXTIRQ_CFG_REG_6328 0x18
555 #define PERF_EXTIRQ_CFG_REG_6338 0x14
556 #define PERF_EXTIRQ_CFG_REG_6345 0x14
557 @@ -322,6 +372,7 @@
558
559 /* Soft Reset register */
560 #define PERF_SOFTRESET_REG 0x28
561 +#define PERF_SOFTRESET_6318_REG 0x10
562 #define PERF_SOFTRESET_6328_REG 0x10
563 #define PERF_SOFTRESET_6358_REG 0x34
564 #define PERF_SOFTRESET_6362_REG 0x10
565 @@ -335,6 +386,18 @@
566 #define SOFTRESET_3368_USBS_MASK (1 << 11)
567 #define SOFTRESET_3368_PCM_MASK (1 << 13)
568
569 +#define SOFTRESET_6318_SPI_MASK (1 << 0)
570 +#define SOFTRESET_6318_EPHY_MASK (1 << 1)
571 +#define SOFTRESET_6318_SAR_MASK (1 << 2)
572 +#define SOFTRESET_6318_ENETSW_MASK (1 << 3)
573 +#define SOFTRESET_6318_USBS_MASK (1 << 4)
574 +#define SOFTRESET_6318_USBH_MASK (1 << 5)
575 +#define SOFTRESET_6318_PCIE_CORE_MASK (1 << 6)
576 +#define SOFTRESET_6318_PCIE_MASK (1 << 7)
577 +#define SOFTRESET_6318_PCIE_EXT_MASK (1 << 8)
578 +#define SOFTRESET_6318_PCIE_HARD_MASK (1 << 9)
579 +#define SOFTRESET_6318_ADSL_MASK (1 << 10)
580 +
581 #define SOFTRESET_6328_SPI_MASK (1 << 0)
582 #define SOFTRESET_6328_EPHY_MASK (1 << 1)
583 #define SOFTRESET_6328_SAR_MASK (1 << 2)
584 @@ -506,8 +569,17 @@
585 #define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9)
586 #define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10)
587
588 +#define TIMER_IRQMASK_6318_REG 0x0
589 +#define TIMER_IRQSTAT_6318_REG 0x4
590 +#define IRQSTATMASK_TIMER0 (1 << 0)
591 +#define IRQSTATMASK_TIMER1 (1 << 1)
592 +#define IRQSTATMASK_TIMER2 (1 << 2)
593 +#define IRQSTATMASK_TIMER3 (1 << 3)
594 +#define IRQSTATMASK_WDT (1 << 4)
595 +
596 /* Timer control register */
597 #define TIMER_CTLx_REG(x) (0x4 + (x * 4))
598 +#define TIMER_CTRx_6318_REG(x) (0x8 + (x * 4))
599 #define TIMER_CTL0_REG 0x4
600 #define TIMER_CTL1_REG 0x8
601 #define TIMER_CTL2_REG 0xC
602 @@ -1254,6 +1326,8 @@
603 #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
604 #define SDRAM_CFG_BANK_SHIFT 13
605 #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
606 +#define SDRAM_CFG_6318_SPACE_SHIFT 4
607 +#define SDRAM_CFG_6318_SPACE_MASK (0xf << SDRAM_CFG_6318_SPACE_SHIFT)
608
609 #define SDRAM_MBASE_REG 0xc
610
611 --- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
612 +++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
613 @@ -23,6 +23,7 @@ static inline int is_bcm63xx_internal_re
614 if (offset >= 0xfff00000)
615 return 1;
616 break;
617 + case BCM6318_CPU_ID:
618 case BCM6328_CPU_ID:
619 case BCM6362_CPU_ID:
620 case BCM6368_CPU_ID:
621 --- a/arch/mips/bcm63xx/dev-hsspi.c
622 +++ b/arch/mips/bcm63xx/dev-hsspi.c
623 @@ -35,7 +35,8 @@ static struct platform_device bcm63xx_hs
624
625 int __init bcm63xx_hsspi_register(void)
626 {
627 - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_63268())
628 + if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6362() &&
629 + !BCMCPU_IS_63268())
630 return -ENODEV;
631
632 spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI);
633 --- a/arch/mips/bcm63xx/dev-usb-usbd.c
634 +++ b/arch/mips/bcm63xx/dev-usb-usbd.c
635 @@ -41,7 +41,7 @@ int __init bcm63xx_usbd_register(const s
636 IRQ_USBD_RXDMA2, IRQ_USBD_TXDMA2 };
637 int i;
638
639 - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6368())
640 + if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6368())
641 return 0;
642
643 usbd_resources[0].start = bcm63xx_regset_address(RSET_USBD);
644 --- a/arch/mips/bcm63xx/dev-enet.c
645 +++ b/arch/mips/bcm63xx/dev-enet.c
646 @@ -184,8 +184,8 @@ static int __init register_shared(void)
647 else
648 shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
649
650 - if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368() ||
651 - BCMCPU_IS_63268())
652 + if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() ||
653 + BCMCPU_IS_6368() || BCMCPU_IS_63268())
654 chan_count = 32;
655 else if (BCMCPU_IS_6345())
656 chan_count = 8;
657 @@ -293,8 +293,8 @@ bcm63xx_enetsw_register(const struct bcm
658 {
659 int ret;
660
661 - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368() &&
662 - !BCMCPU_IS_63268())
663 + if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6362() &&
664 + !BCMCPU_IS_6368() && !BCMCPU_IS_63268())
665 return -ENODEV;
666
667 ret = register_shared();
668 @@ -311,7 +311,7 @@ bcm63xx_enetsw_register(const struct bcm
669
670 memcpy(bcm63xx_enetsw_device.dev.platform_data, pd, sizeof(*pd));
671
672 - if (BCMCPU_IS_6328())
673 + if (BCMCPU_IS_6318() || BCMCPU_IS_6328())
674 enetsw_pd.num_ports = ENETSW_PORTS_6328;
675 else if (BCMCPU_IS_6362() || BCMCPU_IS_6368())
676 enetsw_pd.num_ports = ENETSW_PORTS_6368;
677 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
678 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
679 @@ -10,6 +10,8 @@ int __init bcm63xx_gpio_init(void);
680 static inline unsigned long bcm63xx_gpio_count(void)
681 {
682 switch (bcm63xx_get_cpu_id()) {
683 + case BCM6318_CPU_ID:
684 + return 50;
685 case BCM6328_CPU_ID:
686 return 32;
687 case BCM3368_CPU_ID:
688 --- a/arch/mips/bcm63xx/dev-usb-ehci.c
689 +++ b/arch/mips/bcm63xx/dev-usb-ehci.c
690 @@ -81,7 +81,8 @@ static struct platform_device bcm63xx_eh
691
692 int __init bcm63xx_ehci_register(void)
693 {
694 - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6358() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368())
695 + if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() &&
696 + !BCMCPU_IS_6362() && !BCMCPU_IS_6368())
697 return 0;
698
699 ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0);
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