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bmips: Build U-Boot into the XG6846 target
[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / b53 / b53_common.c
1 /*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
21 #include <linux/delay.h>
22 #include <linux/export.h>
23 #include <linux/gpio.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/switch.h>
27 #include <linux/phy.h>
28 #include <linux/of.h>
29 #include <linux/of_net.h>
30 #include <linux/platform_data/b53.h>
31
32 #include "b53_regs.h"
33 #include "b53_priv.h"
34
35 /* buffer size needed for displaying all MIBs with max'd values */
36 #define B53_BUF_SIZE 1188
37
38 struct b53_mib_desc {
39 u8 size;
40 u8 offset;
41 const char *name;
42 };
43
44 /* BCM5365 MIB counters */
45 static const struct b53_mib_desc b53_mibs_65[] = {
46 { 8, 0x00, "TxOctets" },
47 { 4, 0x08, "TxDropPkts" },
48 { 4, 0x10, "TxBroadcastPkts" },
49 { 4, 0x14, "TxMulticastPkts" },
50 { 4, 0x18, "TxUnicastPkts" },
51 { 4, 0x1c, "TxCollisions" },
52 { 4, 0x20, "TxSingleCollision" },
53 { 4, 0x24, "TxMultipleCollision" },
54 { 4, 0x28, "TxDeferredTransmit" },
55 { 4, 0x2c, "TxLateCollision" },
56 { 4, 0x30, "TxExcessiveCollision" },
57 { 4, 0x38, "TxPausePkts" },
58 { 8, 0x44, "RxOctets" },
59 { 4, 0x4c, "RxUndersizePkts" },
60 { 4, 0x50, "RxPausePkts" },
61 { 4, 0x54, "Pkts64Octets" },
62 { 4, 0x58, "Pkts65to127Octets" },
63 { 4, 0x5c, "Pkts128to255Octets" },
64 { 4, 0x60, "Pkts256to511Octets" },
65 { 4, 0x64, "Pkts512to1023Octets" },
66 { 4, 0x68, "Pkts1024to1522Octets" },
67 { 4, 0x6c, "RxOversizePkts" },
68 { 4, 0x70, "RxJabbers" },
69 { 4, 0x74, "RxAlignmentErrors" },
70 { 4, 0x78, "RxFCSErrors" },
71 { 8, 0x7c, "RxGoodOctets" },
72 { 4, 0x84, "RxDropPkts" },
73 { 4, 0x88, "RxUnicastPkts" },
74 { 4, 0x8c, "RxMulticastPkts" },
75 { 4, 0x90, "RxBroadcastPkts" },
76 { 4, 0x94, "RxSAChanges" },
77 { 4, 0x98, "RxFragments" },
78 { },
79 };
80
81 #define B63XX_MIB_TXB_ID 0 /* TxOctets */
82 #define B63XX_MIB_RXB_ID 14 /* RxOctets */
83
84 /* BCM63xx MIB counters */
85 static const struct b53_mib_desc b53_mibs_63xx[] = {
86 { 8, 0x00, "TxOctets" },
87 { 4, 0x08, "TxDropPkts" },
88 { 4, 0x0c, "TxQoSPkts" },
89 { 4, 0x10, "TxBroadcastPkts" },
90 { 4, 0x14, "TxMulticastPkts" },
91 { 4, 0x18, "TxUnicastPkts" },
92 { 4, 0x1c, "TxCollisions" },
93 { 4, 0x20, "TxSingleCollision" },
94 { 4, 0x24, "TxMultipleCollision" },
95 { 4, 0x28, "TxDeferredTransmit" },
96 { 4, 0x2c, "TxLateCollision" },
97 { 4, 0x30, "TxExcessiveCollision" },
98 { 4, 0x38, "TxPausePkts" },
99 { 8, 0x3c, "TxQoSOctets" },
100 { 8, 0x44, "RxOctets" },
101 { 4, 0x4c, "RxUndersizePkts" },
102 { 4, 0x50, "RxPausePkts" },
103 { 4, 0x54, "Pkts64Octets" },
104 { 4, 0x58, "Pkts65to127Octets" },
105 { 4, 0x5c, "Pkts128to255Octets" },
106 { 4, 0x60, "Pkts256to511Octets" },
107 { 4, 0x64, "Pkts512to1023Octets" },
108 { 4, 0x68, "Pkts1024to1522Octets" },
109 { 4, 0x6c, "RxOversizePkts" },
110 { 4, 0x70, "RxJabbers" },
111 { 4, 0x74, "RxAlignmentErrors" },
112 { 4, 0x78, "RxFCSErrors" },
113 { 8, 0x7c, "RxGoodOctets" },
114 { 4, 0x84, "RxDropPkts" },
115 { 4, 0x88, "RxUnicastPkts" },
116 { 4, 0x8c, "RxMulticastPkts" },
117 { 4, 0x90, "RxBroadcastPkts" },
118 { 4, 0x94, "RxSAChanges" },
119 { 4, 0x98, "RxFragments" },
120 { 4, 0xa0, "RxSymbolErrors" },
121 { 4, 0xa4, "RxQoSPkts" },
122 { 8, 0xa8, "RxQoSOctets" },
123 { 4, 0xb0, "Pkts1523to2047Octets" },
124 { 4, 0xb4, "Pkts2048to4095Octets" },
125 { 4, 0xb8, "Pkts4096to8191Octets" },
126 { 4, 0xbc, "Pkts8192to9728Octets" },
127 { 4, 0xc0, "RxDiscarded" },
128 { }
129 };
130
131 #define B53XX_MIB_TXB_ID 0 /* TxOctets */
132 #define B53XX_MIB_RXB_ID 12 /* RxOctets */
133
134 /* MIB counters */
135 static const struct b53_mib_desc b53_mibs[] = {
136 { 8, 0x00, "TxOctets" },
137 { 4, 0x08, "TxDropPkts" },
138 { 4, 0x10, "TxBroadcastPkts" },
139 { 4, 0x14, "TxMulticastPkts" },
140 { 4, 0x18, "TxUnicastPkts" },
141 { 4, 0x1c, "TxCollisions" },
142 { 4, 0x20, "TxSingleCollision" },
143 { 4, 0x24, "TxMultipleCollision" },
144 { 4, 0x28, "TxDeferredTransmit" },
145 { 4, 0x2c, "TxLateCollision" },
146 { 4, 0x30, "TxExcessiveCollision" },
147 { 4, 0x38, "TxPausePkts" },
148 { 8, 0x50, "RxOctets" },
149 { 4, 0x58, "RxUndersizePkts" },
150 { 4, 0x5c, "RxPausePkts" },
151 { 4, 0x60, "Pkts64Octets" },
152 { 4, 0x64, "Pkts65to127Octets" },
153 { 4, 0x68, "Pkts128to255Octets" },
154 { 4, 0x6c, "Pkts256to511Octets" },
155 { 4, 0x70, "Pkts512to1023Octets" },
156 { 4, 0x74, "Pkts1024to1522Octets" },
157 { 4, 0x78, "RxOversizePkts" },
158 { 4, 0x7c, "RxJabbers" },
159 { 4, 0x80, "RxAlignmentErrors" },
160 { 4, 0x84, "RxFCSErrors" },
161 { 8, 0x88, "RxGoodOctets" },
162 { 4, 0x90, "RxDropPkts" },
163 { 4, 0x94, "RxUnicastPkts" },
164 { 4, 0x98, "RxMulticastPkts" },
165 { 4, 0x9c, "RxBroadcastPkts" },
166 { 4, 0xa0, "RxSAChanges" },
167 { 4, 0xa4, "RxFragments" },
168 { 4, 0xa8, "RxJumboPkts" },
169 { 4, 0xac, "RxSymbolErrors" },
170 { 4, 0xc0, "RxDiscarded" },
171 { }
172 };
173
174 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
175 {
176 unsigned int i;
177
178 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
179
180 for (i = 0; i < 10; i++) {
181 u8 vta;
182
183 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
184 if (!(vta & VTA_START_CMD))
185 return 0;
186
187 usleep_range(100, 200);
188 }
189
190 return -EIO;
191 }
192
193 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, u16 members,
194 u16 untag)
195 {
196 if (is5325(dev)) {
197 u32 entry = 0;
198
199 if (members) {
200 entry = ((untag & VA_UNTAG_MASK_25) << VA_UNTAG_S_25) |
201 members;
202 if (dev->core_rev >= 3)
203 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
204 else
205 entry |= VA_VALID_25;
206 }
207
208 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
209 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
210 VTA_RW_STATE_WR | VTA_RW_OP_EN);
211 } else if (is5365(dev)) {
212 u16 entry = 0;
213
214 if (members)
215 entry = ((untag & VA_UNTAG_MASK_65) << VA_UNTAG_S_65) |
216 members | VA_VALID_65;
217
218 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
219 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
220 VTA_RW_STATE_WR | VTA_RW_OP_EN);
221 } else {
222 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
223 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
224 (untag << VTE_UNTAG_S) | members);
225
226 b53_do_vlan_op(dev, VTA_CMD_WRITE);
227 }
228 }
229
230 void b53_set_forwarding(struct b53_device *dev, int enable)
231 {
232 u8 mgmt;
233
234 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
235
236 if (enable)
237 mgmt |= SM_SW_FWD_EN;
238 else
239 mgmt &= ~SM_SW_FWD_EN;
240
241 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
242 }
243
244 static void b53_enable_vlan(struct b53_device *dev, int enable)
245 {
246 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
247
248 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
249 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
250 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
251
252 if (is5325(dev) || is5365(dev)) {
253 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
254 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
255 } else if (is63xx(dev)) {
256 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
257 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
258 } else {
259 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
260 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
261 }
262
263 mgmt &= ~SM_SW_FWD_MODE;
264
265 if (enable) {
266 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
267 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
268 vc4 &= ~VC4_ING_VID_CHECK_MASK;
269 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
270 vc5 |= VC5_DROP_VTABLE_MISS;
271
272 if (is5325(dev))
273 vc0 &= ~VC0_RESERVED_1;
274
275 if (is5325(dev) || is5365(dev))
276 vc1 |= VC1_RX_MCST_TAG_EN;
277
278 if (!is5325(dev) && !is5365(dev)) {
279 if (dev->allow_vid_4095)
280 vc5 |= VC5_VID_FFF_EN;
281 else
282 vc5 &= ~VC5_VID_FFF_EN;
283 }
284 } else {
285 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
286 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
287 vc4 &= ~VC4_ING_VID_CHECK_MASK;
288 vc5 &= ~VC5_DROP_VTABLE_MISS;
289
290 if (is5325(dev) || is5365(dev))
291 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
292 else
293 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
294
295 if (is5325(dev) || is5365(dev))
296 vc1 &= ~VC1_RX_MCST_TAG_EN;
297
298 if (!is5325(dev) && !is5365(dev))
299 vc5 &= ~VC5_VID_FFF_EN;
300 }
301
302 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
303 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
304
305 if (is5325(dev) || is5365(dev)) {
306 /* enable the high 8 bit vid check on 5325 */
307 if (is5325(dev) && enable)
308 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
309 VC3_HIGH_8BIT_EN);
310 else
311 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
312
313 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
314 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
315 } else if (is63xx(dev)) {
316 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
317 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
318 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
319 } else {
320 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
321 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
322 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
323 }
324
325 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
326 }
327
328 static int b53_set_jumbo(struct b53_device *dev, int enable, int allow_10_100)
329 {
330 u32 port_mask = 0;
331 u16 max_size = JMS_MIN_SIZE;
332
333 if (is5325(dev) || is5365(dev))
334 return -EINVAL;
335
336 if (enable) {
337 port_mask = dev->enabled_ports;
338 max_size = JMS_MAX_SIZE;
339 if (allow_10_100)
340 port_mask |= JPM_10_100_JUMBO_EN;
341 }
342
343 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
344 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
345 }
346
347 static int b53_flush_arl(struct b53_device *dev)
348 {
349 unsigned int i;
350
351 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
352 FAST_AGE_DONE | FAST_AGE_DYNAMIC | FAST_AGE_STATIC);
353
354 for (i = 0; i < 10; i++) {
355 u8 fast_age_ctrl;
356
357 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
358 &fast_age_ctrl);
359
360 if (!(fast_age_ctrl & FAST_AGE_DONE))
361 return 0;
362
363 mdelay(1);
364 }
365
366 pr_warn("time out while flushing ARL\n");
367
368 return -EINVAL;
369 }
370
371 static void b53_enable_ports(struct b53_device *dev)
372 {
373 unsigned i;
374
375 b53_for_each_port(dev, i) {
376 u8 port_ctrl;
377 u16 pvlan_mask;
378
379 /*
380 * prevent leaking packets between wan and lan in unmanaged
381 * mode through port vlans.
382 */
383 if (dev->enable_vlan || is_cpu_port(dev, i))
384 pvlan_mask = 0x1ff;
385 else if (is531x5(dev) || is5301x(dev))
386 /* BCM53115 may use a different port as cpu port */
387 pvlan_mask = BIT(dev->sw_dev.cpu_port);
388 else
389 pvlan_mask = BIT(B53_CPU_PORT);
390
391 /* BCM5325 CPU port is at 8 */
392 if ((is5325(dev) || is5365(dev)) && i == B53_CPU_PORT_25)
393 i = B53_CPU_PORT;
394
395 if (dev->chip_id == BCM5398_DEVICE_ID && (i == 6 || i == 7))
396 /* disable unused ports 6 & 7 */
397 port_ctrl = PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
398 else if (i == B53_CPU_PORT)
399 port_ctrl = PORT_CTRL_RX_BCST_EN |
400 PORT_CTRL_RX_MCST_EN |
401 PORT_CTRL_RX_UCST_EN;
402 else
403 port_ctrl = 0;
404
405 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i),
406 pvlan_mask);
407
408 /* port state is handled by bcm63xx_enet driver */
409 if (!is63xx(dev) && !(is5301x(dev) && i == 6))
410 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(i),
411 port_ctrl);
412 }
413 }
414
415 static void b53_enable_mib(struct b53_device *dev)
416 {
417 u8 gc;
418
419 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
420
421 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
422
423 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
424 }
425
426 static int b53_apply(struct b53_device *dev)
427 {
428 int i;
429
430 /* clear all vlan entries */
431 if (is5325(dev) || is5365(dev)) {
432 for (i = 1; i < dev->sw_dev.vlans; i++)
433 b53_set_vlan_entry(dev, i, 0, 0);
434 } else {
435 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
436 }
437
438 b53_enable_vlan(dev, dev->enable_vlan);
439
440 /* fill VLAN table */
441 if (dev->enable_vlan) {
442 for (i = 0; i < dev->sw_dev.vlans; i++) {
443 struct b53_vlan *vlan = &dev->vlans[i];
444
445 if (!vlan->members)
446 continue;
447
448 b53_set_vlan_entry(dev, i, vlan->members, vlan->untag);
449 }
450
451 b53_for_each_port(dev, i)
452 b53_write16(dev, B53_VLAN_PAGE,
453 B53_VLAN_PORT_DEF_TAG(i),
454 dev->ports[i].pvid);
455 } else {
456 b53_for_each_port(dev, i)
457 b53_write16(dev, B53_VLAN_PAGE,
458 B53_VLAN_PORT_DEF_TAG(i), 1);
459
460 }
461
462 b53_enable_ports(dev);
463
464 if (!is5325(dev) && !is5365(dev))
465 b53_set_jumbo(dev, dev->enable_jumbo, 1);
466
467 return 0;
468 }
469
470 static void b53_switch_reset_gpio(struct b53_device *dev)
471 {
472 int gpio = dev->reset_gpio;
473
474 if (gpio < 0)
475 return;
476
477 /*
478 * Reset sequence: RESET low(50ms)->high(20ms)
479 */
480 gpio_set_value(gpio, 0);
481 mdelay(50);
482
483 gpio_set_value(gpio, 1);
484 mdelay(20);
485
486 dev->current_page = 0xff;
487 }
488
489 static int b53_configure_ports_of(struct b53_device *dev)
490 {
491 struct device_node *dn, *pn;
492 u32 port_num;
493
494 dn = of_get_child_by_name(dev_of_node(dev->dev), "ports");
495
496 for_each_available_child_of_node(dn, pn) {
497 struct device_node *fixed_link;
498
499 if (of_property_read_u32(pn, "reg", &port_num))
500 continue;
501
502 if (port_num > B53_CPU_PORT)
503 continue;
504
505 fixed_link = of_get_child_by_name(pn, "fixed-link");
506 if (fixed_link) {
507 u32 spd;
508 u8 po = GMII_PO_LINK;
509 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 5, 0)
510 phy_interface_t mode;
511 #else
512 int mode = of_get_phy_mode(pn);
513 #endif
514
515 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 5, 0)
516 of_get_phy_mode(pn, &mode);
517 #endif
518
519 if (!of_property_read_u32(fixed_link, "speed", &spd)) {
520 switch (spd) {
521 case 10:
522 po |= GMII_PO_SPEED_10M;
523 break;
524 case 100:
525 po |= GMII_PO_SPEED_100M;
526 break;
527 case 2000:
528 if (is_imp_port(dev, port_num))
529 po |= PORT_OVERRIDE_SPEED_2000M;
530 else
531 po |= GMII_PO_SPEED_2000M;
532 fallthrough;
533 case 1000:
534 po |= GMII_PO_SPEED_1000M;
535 break;
536 }
537 }
538
539 if (of_property_read_bool(fixed_link, "full-duplex"))
540 po |= PORT_OVERRIDE_FULL_DUPLEX;
541 if (of_property_read_bool(fixed_link, "pause"))
542 po |= GMII_PO_RX_FLOW;
543 if (of_property_read_bool(fixed_link, "asym-pause"))
544 po |= GMII_PO_TX_FLOW;
545
546 if (is_imp_port(dev, port_num)) {
547 po |= PORT_OVERRIDE_EN;
548
549 if (is5325(dev) &&
550 mode == PHY_INTERFACE_MODE_REVMII)
551 po |= PORT_OVERRIDE_RV_MII_25;
552
553 b53_write8(dev, B53_CTRL_PAGE,
554 B53_PORT_OVERRIDE_CTRL, po);
555
556 if (is5325(dev) &&
557 mode == PHY_INTERFACE_MODE_REVMII) {
558 b53_read8(dev, B53_CTRL_PAGE,
559 B53_PORT_OVERRIDE_CTRL, &po);
560 if (!(po & PORT_OVERRIDE_RV_MII_25))
561 pr_err("Failed to enable reverse MII mode\n");
562 return -EINVAL;
563 }
564 } else {
565 po |= GMII_PO_EN;
566 b53_write8(dev, B53_CTRL_PAGE,
567 B53_GMII_PORT_OVERRIDE_CTRL(port_num),
568 po);
569 }
570 }
571 }
572
573 return 0;
574 }
575
576 static int b53_configure_ports(struct b53_device *dev)
577 {
578 u8 cpu_port = dev->sw_dev.cpu_port;
579
580 /* configure MII port if necessary */
581 if (is5325(dev)) {
582 u8 mii_port_override;
583
584 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
585 &mii_port_override);
586 /* reverse mii needs to be enabled */
587 if (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) {
588 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
589 mii_port_override | PORT_OVERRIDE_RV_MII_25);
590 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
591 &mii_port_override);
592
593 if (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) {
594 pr_err("Failed to enable reverse MII mode\n");
595 return -EINVAL;
596 }
597 }
598 } else if (is531x5(dev) && cpu_port == B53_CPU_PORT) {
599 u8 mii_port_override;
600
601 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
602 &mii_port_override);
603 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
604 mii_port_override | PORT_OVERRIDE_EN |
605 PORT_OVERRIDE_LINK);
606
607 /* BCM47189 has another interface connected to the port 5 */
608 if (dev->enabled_ports & BIT(5)) {
609 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(5);
610 u8 gmii_po;
611
612 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
613 gmii_po |= GMII_PO_LINK |
614 GMII_PO_RX_FLOW |
615 GMII_PO_TX_FLOW |
616 GMII_PO_EN;
617 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
618 }
619 } else if (is5301x(dev)) {
620 if (cpu_port == 8) {
621 u8 mii_port_override;
622
623 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
624 &mii_port_override);
625 mii_port_override |= PORT_OVERRIDE_LINK |
626 PORT_OVERRIDE_RX_FLOW |
627 PORT_OVERRIDE_TX_FLOW |
628 PORT_OVERRIDE_SPEED_2000M |
629 PORT_OVERRIDE_EN;
630 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
631 mii_port_override);
632
633 /* TODO: Ports 5 & 7 require some extra handling */
634 } else {
635 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(cpu_port);
636 u8 gmii_po;
637
638 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
639 gmii_po |= GMII_PO_LINK |
640 GMII_PO_RX_FLOW |
641 GMII_PO_TX_FLOW |
642 GMII_PO_EN |
643 GMII_PO_SPEED_2000M;
644 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
645 }
646 }
647
648 return 0;
649 }
650
651 static int b53_switch_reset(struct b53_device *dev)
652 {
653 int ret = 0;
654 u8 mgmt;
655
656 b53_switch_reset_gpio(dev);
657
658 if (is539x(dev)) {
659 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
660 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
661 }
662
663 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
664
665 if (!(mgmt & SM_SW_FWD_EN)) {
666 mgmt &= ~SM_SW_FWD_MODE;
667 mgmt |= SM_SW_FWD_EN;
668
669 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
670 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
671
672 if (!(mgmt & SM_SW_FWD_EN)) {
673 pr_err("Failed to enable switch!\n");
674 return -EINVAL;
675 }
676 }
677
678 /* enable all ports */
679 b53_enable_ports(dev);
680
681 if (dev->dev->of_node)
682 ret = b53_configure_ports_of(dev);
683 else
684 ret = b53_configure_ports(dev);
685
686 if (ret)
687 return ret;
688
689 b53_enable_mib(dev);
690
691 return b53_flush_arl(dev);
692 }
693
694 /*
695 * Swconfig glue functions
696 */
697
698 static int b53_global_get_vlan_enable(struct switch_dev *dev,
699 const struct switch_attr *attr,
700 struct switch_val *val)
701 {
702 struct b53_device *priv = sw_to_b53(dev);
703
704 val->value.i = priv->enable_vlan;
705
706 return 0;
707 }
708
709 static int b53_global_set_vlan_enable(struct switch_dev *dev,
710 const struct switch_attr *attr,
711 struct switch_val *val)
712 {
713 struct b53_device *priv = sw_to_b53(dev);
714
715 priv->enable_vlan = val->value.i;
716
717 return 0;
718 }
719
720 static int b53_global_get_jumbo_enable(struct switch_dev *dev,
721 const struct switch_attr *attr,
722 struct switch_val *val)
723 {
724 struct b53_device *priv = sw_to_b53(dev);
725
726 val->value.i = priv->enable_jumbo;
727
728 return 0;
729 }
730
731 static int b53_global_set_jumbo_enable(struct switch_dev *dev,
732 const struct switch_attr *attr,
733 struct switch_val *val)
734 {
735 struct b53_device *priv = sw_to_b53(dev);
736
737 priv->enable_jumbo = val->value.i;
738
739 return 0;
740 }
741
742 static int b53_global_get_4095_enable(struct switch_dev *dev,
743 const struct switch_attr *attr,
744 struct switch_val *val)
745 {
746 struct b53_device *priv = sw_to_b53(dev);
747
748 val->value.i = priv->allow_vid_4095;
749
750 return 0;
751 }
752
753 static int b53_global_set_4095_enable(struct switch_dev *dev,
754 const struct switch_attr *attr,
755 struct switch_val *val)
756 {
757 struct b53_device *priv = sw_to_b53(dev);
758
759 priv->allow_vid_4095 = val->value.i;
760
761 return 0;
762 }
763
764 static int b53_global_get_ports(struct switch_dev *dev,
765 const struct switch_attr *attr,
766 struct switch_val *val)
767 {
768 struct b53_device *priv = sw_to_b53(dev);
769
770 val->len = snprintf(priv->buf, B53_BUF_SIZE, "0x%04x",
771 priv->enabled_ports);
772 val->value.s = priv->buf;
773
774 return 0;
775 }
776
777 static int b53_port_get_pvid(struct switch_dev *dev, int port, int *val)
778 {
779 struct b53_device *priv = sw_to_b53(dev);
780
781 *val = priv->ports[port].pvid;
782
783 return 0;
784 }
785
786 static int b53_port_set_pvid(struct switch_dev *dev, int port, int val)
787 {
788 struct b53_device *priv = sw_to_b53(dev);
789
790 if (val > 15 && is5325(priv))
791 return -EINVAL;
792 if (val == 4095 && !priv->allow_vid_4095)
793 return -EINVAL;
794
795 priv->ports[port].pvid = val;
796
797 return 0;
798 }
799
800 static int b53_vlan_get_ports(struct switch_dev *dev, struct switch_val *val)
801 {
802 struct b53_device *priv = sw_to_b53(dev);
803 struct switch_port *port = &val->value.ports[0];
804 struct b53_vlan *vlan = &priv->vlans[val->port_vlan];
805 int i;
806
807 val->len = 0;
808
809 if (!vlan->members)
810 return 0;
811
812 for (i = 0; i < dev->ports; i++) {
813 if (!(vlan->members & BIT(i)))
814 continue;
815
816
817 if (!(vlan->untag & BIT(i)))
818 port->flags = BIT(SWITCH_PORT_FLAG_TAGGED);
819 else
820 port->flags = 0;
821
822 port->id = i;
823 val->len++;
824 port++;
825 }
826
827 return 0;
828 }
829
830 static int b53_vlan_set_ports(struct switch_dev *dev, struct switch_val *val)
831 {
832 struct b53_device *priv = sw_to_b53(dev);
833 struct switch_port *port;
834 struct b53_vlan *vlan = &priv->vlans[val->port_vlan];
835 int i;
836
837 /* only BCM5325 and BCM5365 supports VID 0 */
838 if (val->port_vlan == 0 && !is5325(priv) && !is5365(priv))
839 return -EINVAL;
840
841 /* VLAN 4095 needs special handling */
842 if (val->port_vlan == 4095 && !priv->allow_vid_4095)
843 return -EINVAL;
844
845 port = &val->value.ports[0];
846 vlan->members = 0;
847 vlan->untag = 0;
848 for (i = 0; i < val->len; i++, port++) {
849 vlan->members |= BIT(port->id);
850
851 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED))) {
852 vlan->untag |= BIT(port->id);
853 priv->ports[port->id].pvid = val->port_vlan;
854 };
855 }
856
857 /* ignore disabled ports */
858 vlan->members &= priv->enabled_ports;
859 vlan->untag &= priv->enabled_ports;
860
861 return 0;
862 }
863
864 static int b53_port_get_link(struct switch_dev *dev, int port,
865 struct switch_port_link *link)
866 {
867 struct b53_device *priv = sw_to_b53(dev);
868
869 if (is_cpu_port(priv, port)) {
870 link->link = 1;
871 link->duplex = 1;
872 link->speed = is5325(priv) || is5365(priv) ?
873 SWITCH_PORT_SPEED_100 : SWITCH_PORT_SPEED_1000;
874 link->aneg = 0;
875 } else if (priv->enabled_ports & BIT(port)) {
876 u32 speed;
877 u16 lnk, duplex;
878
879 b53_read16(priv, B53_STAT_PAGE, B53_LINK_STAT, &lnk);
880 b53_read16(priv, B53_STAT_PAGE, priv->duplex_reg, &duplex);
881
882 lnk = (lnk >> port) & 1;
883 duplex = (duplex >> port) & 1;
884
885 if (is5325(priv) || is5365(priv)) {
886 u16 tmp;
887
888 b53_read16(priv, B53_STAT_PAGE, B53_SPEED_STAT, &tmp);
889 speed = SPEED_PORT_FE(tmp, port);
890 } else {
891 b53_read32(priv, B53_STAT_PAGE, B53_SPEED_STAT, &speed);
892 speed = SPEED_PORT_GE(speed, port);
893 }
894
895 link->link = lnk;
896 if (lnk) {
897 link->duplex = duplex;
898 switch (speed) {
899 case SPEED_STAT_10M:
900 link->speed = SWITCH_PORT_SPEED_10;
901 break;
902 case SPEED_STAT_100M:
903 link->speed = SWITCH_PORT_SPEED_100;
904 break;
905 case SPEED_STAT_1000M:
906 link->speed = SWITCH_PORT_SPEED_1000;
907 break;
908 }
909 }
910
911 link->aneg = 1;
912 } else {
913 link->link = 0;
914 }
915
916 return 0;
917
918 }
919
920 static int b53_port_set_link(struct switch_dev *sw_dev, int port,
921 struct switch_port_link *link)
922 {
923 struct b53_device *dev = sw_to_b53(sw_dev);
924
925 /*
926 * TODO: BCM63XX requires special handling as it can have external phys
927 * and ports might be GE or only FE
928 */
929 if (is63xx(dev))
930 return -ENOTSUPP;
931
932 if (port == sw_dev->cpu_port)
933 return -EINVAL;
934
935 if (!(BIT(port) & dev->enabled_ports))
936 return -EINVAL;
937
938 if (link->speed == SWITCH_PORT_SPEED_1000 &&
939 (is5325(dev) || is5365(dev)))
940 return -EINVAL;
941
942 if (link->speed == SWITCH_PORT_SPEED_1000 && !link->duplex)
943 return -EINVAL;
944
945 return switch_generic_set_link(sw_dev, port, link);
946 }
947
948 static int b53_phy_read16(struct switch_dev *dev, int addr, u8 reg, u16 *value)
949 {
950 struct b53_device *priv = sw_to_b53(dev);
951
952 if (priv->ops->phy_read16)
953 return priv->ops->phy_read16(priv, addr, reg, value);
954
955 return b53_read16(priv, B53_PORT_MII_PAGE(addr), reg, value);
956 }
957
958 static int b53_phy_write16(struct switch_dev *dev, int addr, u8 reg, u16 value)
959 {
960 struct b53_device *priv = sw_to_b53(dev);
961
962 if (priv->ops->phy_write16)
963 return priv->ops->phy_write16(priv, addr, reg, value);
964
965 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg, value);
966 }
967
968 static int b53_global_reset_switch(struct switch_dev *dev)
969 {
970 struct b53_device *priv = sw_to_b53(dev);
971
972 /* reset vlans */
973 priv->enable_vlan = 0;
974 priv->enable_jumbo = 0;
975 priv->allow_vid_4095 = 0;
976
977 memset(priv->vlans, 0, sizeof(*priv->vlans) * dev->vlans);
978 memset(priv->ports, 0, sizeof(*priv->ports) * dev->ports);
979
980 return b53_switch_reset(priv);
981 }
982
983 static int b53_global_apply_config(struct switch_dev *dev)
984 {
985 struct b53_device *priv = sw_to_b53(dev);
986
987 /* disable switching */
988 b53_set_forwarding(priv, 0);
989
990 b53_apply(priv);
991
992 /* enable switching */
993 b53_set_forwarding(priv, 1);
994
995 return 0;
996 }
997
998
999 static int b53_global_reset_mib(struct switch_dev *dev,
1000 const struct switch_attr *attr,
1001 struct switch_val *val)
1002 {
1003 struct b53_device *priv = sw_to_b53(dev);
1004 u8 gc;
1005
1006 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
1007
1008 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
1009 mdelay(1);
1010 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
1011 mdelay(1);
1012
1013 return 0;
1014 }
1015
1016 static int b53_port_get_mib(struct switch_dev *sw_dev,
1017 const struct switch_attr *attr,
1018 struct switch_val *val)
1019 {
1020 struct b53_device *dev = sw_to_b53(sw_dev);
1021 const struct b53_mib_desc *mibs;
1022 int port = val->port_vlan;
1023 int len = 0;
1024
1025 if (!(BIT(port) & dev->enabled_ports))
1026 return -1;
1027
1028 if (is5365(dev)) {
1029 if (port == 5)
1030 port = 8;
1031
1032 mibs = b53_mibs_65;
1033 } else if (is63xx(dev)) {
1034 mibs = b53_mibs_63xx;
1035 } else {
1036 mibs = b53_mibs;
1037 }
1038
1039 dev->buf[0] = 0;
1040
1041 for (; mibs->size > 0; mibs++) {
1042 u64 val;
1043
1044 if (mibs->size == 8) {
1045 b53_read64(dev, B53_MIB_PAGE(port), mibs->offset, &val);
1046 } else {
1047 u32 val32;
1048
1049 b53_read32(dev, B53_MIB_PAGE(port), mibs->offset,
1050 &val32);
1051 val = val32;
1052 }
1053
1054 len += snprintf(dev->buf + len, B53_BUF_SIZE - len,
1055 "%-20s: %llu\n", mibs->name, val);
1056 }
1057
1058 val->len = len;
1059 val->value.s = dev->buf;
1060
1061 return 0;
1062 }
1063
1064 static int b53_port_get_stats(struct switch_dev *sw_dev, int port,
1065 struct switch_port_stats *stats)
1066 {
1067 struct b53_device *dev = sw_to_b53(sw_dev);
1068 const struct b53_mib_desc *mibs;
1069 int txb_id, rxb_id;
1070 u64 rxb, txb;
1071
1072 if (!(BIT(port) & dev->enabled_ports))
1073 return -EINVAL;
1074
1075 txb_id = B53XX_MIB_TXB_ID;
1076 rxb_id = B53XX_MIB_RXB_ID;
1077
1078 if (is5365(dev)) {
1079 if (port == 5)
1080 port = 8;
1081
1082 mibs = b53_mibs_65;
1083 } else if (is63xx(dev)) {
1084 mibs = b53_mibs_63xx;
1085 txb_id = B63XX_MIB_TXB_ID;
1086 rxb_id = B63XX_MIB_RXB_ID;
1087 } else {
1088 mibs = b53_mibs;
1089 }
1090
1091 dev->buf[0] = 0;
1092
1093 if (mibs->size == 8) {
1094 b53_read64(dev, B53_MIB_PAGE(port), mibs[txb_id].offset, &txb);
1095 b53_read64(dev, B53_MIB_PAGE(port), mibs[rxb_id].offset, &rxb);
1096 } else {
1097 u32 val32;
1098
1099 b53_read32(dev, B53_MIB_PAGE(port), mibs[txb_id].offset, &val32);
1100 txb = val32;
1101
1102 b53_read32(dev, B53_MIB_PAGE(port), mibs[rxb_id].offset, &val32);
1103 rxb = val32;
1104 }
1105
1106 stats->tx_bytes = txb;
1107 stats->rx_bytes = rxb;
1108
1109 return 0;
1110 }
1111
1112 static struct switch_attr b53_global_ops_25[] = {
1113 {
1114 .type = SWITCH_TYPE_INT,
1115 .name = "enable_vlan",
1116 .description = "Enable VLAN mode",
1117 .set = b53_global_set_vlan_enable,
1118 .get = b53_global_get_vlan_enable,
1119 .max = 1,
1120 },
1121 {
1122 .type = SWITCH_TYPE_STRING,
1123 .name = "ports",
1124 .description = "Available ports (as bitmask)",
1125 .get = b53_global_get_ports,
1126 },
1127 };
1128
1129 static struct switch_attr b53_global_ops_65[] = {
1130 {
1131 .type = SWITCH_TYPE_INT,
1132 .name = "enable_vlan",
1133 .description = "Enable VLAN mode",
1134 .set = b53_global_set_vlan_enable,
1135 .get = b53_global_get_vlan_enable,
1136 .max = 1,
1137 },
1138 {
1139 .type = SWITCH_TYPE_STRING,
1140 .name = "ports",
1141 .description = "Available ports (as bitmask)",
1142 .get = b53_global_get_ports,
1143 },
1144 {
1145 .type = SWITCH_TYPE_INT,
1146 .name = "reset_mib",
1147 .description = "Reset MIB counters",
1148 .set = b53_global_reset_mib,
1149 },
1150 };
1151
1152 static struct switch_attr b53_global_ops[] = {
1153 {
1154 .type = SWITCH_TYPE_INT,
1155 .name = "enable_vlan",
1156 .description = "Enable VLAN mode",
1157 .set = b53_global_set_vlan_enable,
1158 .get = b53_global_get_vlan_enable,
1159 .max = 1,
1160 },
1161 {
1162 .type = SWITCH_TYPE_STRING,
1163 .name = "ports",
1164 .description = "Available Ports (as bitmask)",
1165 .get = b53_global_get_ports,
1166 },
1167 {
1168 .type = SWITCH_TYPE_INT,
1169 .name = "reset_mib",
1170 .description = "Reset MIB counters",
1171 .set = b53_global_reset_mib,
1172 },
1173 {
1174 .type = SWITCH_TYPE_INT,
1175 .name = "enable_jumbo",
1176 .description = "Enable Jumbo Frames",
1177 .set = b53_global_set_jumbo_enable,
1178 .get = b53_global_get_jumbo_enable,
1179 .max = 1,
1180 },
1181 {
1182 .type = SWITCH_TYPE_INT,
1183 .name = "allow_vid_4095",
1184 .description = "Allow VID 4095",
1185 .set = b53_global_set_4095_enable,
1186 .get = b53_global_get_4095_enable,
1187 .max = 1,
1188 },
1189 };
1190
1191 static struct switch_attr b53_port_ops[] = {
1192 {
1193 .type = SWITCH_TYPE_STRING,
1194 .name = "mib",
1195 .description = "Get port's MIB counters",
1196 .get = b53_port_get_mib,
1197 },
1198 };
1199
1200 static struct switch_attr b53_no_ops[] = {
1201 };
1202
1203 static const struct switch_dev_ops b53_switch_ops_25 = {
1204 .attr_global = {
1205 .attr = b53_global_ops_25,
1206 .n_attr = ARRAY_SIZE(b53_global_ops_25),
1207 },
1208 .attr_port = {
1209 .attr = b53_no_ops,
1210 .n_attr = ARRAY_SIZE(b53_no_ops),
1211 },
1212 .attr_vlan = {
1213 .attr = b53_no_ops,
1214 .n_attr = ARRAY_SIZE(b53_no_ops),
1215 },
1216
1217 .get_vlan_ports = b53_vlan_get_ports,
1218 .set_vlan_ports = b53_vlan_set_ports,
1219 .get_port_pvid = b53_port_get_pvid,
1220 .set_port_pvid = b53_port_set_pvid,
1221 .apply_config = b53_global_apply_config,
1222 .reset_switch = b53_global_reset_switch,
1223 .get_port_link = b53_port_get_link,
1224 .set_port_link = b53_port_set_link,
1225 .get_port_stats = b53_port_get_stats,
1226 .phy_read16 = b53_phy_read16,
1227 .phy_write16 = b53_phy_write16,
1228 };
1229
1230 static const struct switch_dev_ops b53_switch_ops_65 = {
1231 .attr_global = {
1232 .attr = b53_global_ops_65,
1233 .n_attr = ARRAY_SIZE(b53_global_ops_65),
1234 },
1235 .attr_port = {
1236 .attr = b53_port_ops,
1237 .n_attr = ARRAY_SIZE(b53_port_ops),
1238 },
1239 .attr_vlan = {
1240 .attr = b53_no_ops,
1241 .n_attr = ARRAY_SIZE(b53_no_ops),
1242 },
1243
1244 .get_vlan_ports = b53_vlan_get_ports,
1245 .set_vlan_ports = b53_vlan_set_ports,
1246 .get_port_pvid = b53_port_get_pvid,
1247 .set_port_pvid = b53_port_set_pvid,
1248 .apply_config = b53_global_apply_config,
1249 .reset_switch = b53_global_reset_switch,
1250 .get_port_link = b53_port_get_link,
1251 .set_port_link = b53_port_set_link,
1252 .get_port_stats = b53_port_get_stats,
1253 .phy_read16 = b53_phy_read16,
1254 .phy_write16 = b53_phy_write16,
1255 };
1256
1257 static const struct switch_dev_ops b53_switch_ops = {
1258 .attr_global = {
1259 .attr = b53_global_ops,
1260 .n_attr = ARRAY_SIZE(b53_global_ops),
1261 },
1262 .attr_port = {
1263 .attr = b53_port_ops,
1264 .n_attr = ARRAY_SIZE(b53_port_ops),
1265 },
1266 .attr_vlan = {
1267 .attr = b53_no_ops,
1268 .n_attr = ARRAY_SIZE(b53_no_ops),
1269 },
1270
1271 .get_vlan_ports = b53_vlan_get_ports,
1272 .set_vlan_ports = b53_vlan_set_ports,
1273 .get_port_pvid = b53_port_get_pvid,
1274 .set_port_pvid = b53_port_set_pvid,
1275 .apply_config = b53_global_apply_config,
1276 .reset_switch = b53_global_reset_switch,
1277 .get_port_link = b53_port_get_link,
1278 .set_port_link = b53_port_set_link,
1279 .get_port_stats = b53_port_get_stats,
1280 .phy_read16 = b53_phy_read16,
1281 .phy_write16 = b53_phy_write16,
1282 };
1283
1284 struct b53_chip_data {
1285 u32 chip_id;
1286 const char *dev_name;
1287 const char *alias;
1288 u16 vlans;
1289 u16 enabled_ports;
1290 u8 cpu_port;
1291 u8 vta_regs[3];
1292 u8 duplex_reg;
1293 u8 jumbo_pm_reg;
1294 u8 jumbo_size_reg;
1295 const struct switch_dev_ops *sw_ops;
1296 };
1297
1298 #define B53_VTA_REGS \
1299 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1300 #define B53_VTA_REGS_9798 \
1301 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1302 #define B53_VTA_REGS_63XX \
1303 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1304
1305 static const struct b53_chip_data b53_switch_chips[] = {
1306 {
1307 .chip_id = BCM5325_DEVICE_ID,
1308 .dev_name = "BCM5325",
1309 .alias = "bcm5325",
1310 .vlans = 16,
1311 .enabled_ports = 0x1f,
1312 .cpu_port = B53_CPU_PORT_25,
1313 .duplex_reg = B53_DUPLEX_STAT_FE,
1314 .sw_ops = &b53_switch_ops_25,
1315 },
1316 {
1317 .chip_id = BCM5365_DEVICE_ID,
1318 .dev_name = "BCM5365",
1319 .alias = "bcm5365",
1320 .vlans = 256,
1321 .enabled_ports = 0x1f,
1322 .cpu_port = B53_CPU_PORT_25,
1323 .duplex_reg = B53_DUPLEX_STAT_FE,
1324 .sw_ops = &b53_switch_ops_65,
1325 },
1326 {
1327 .chip_id = BCM5395_DEVICE_ID,
1328 .dev_name = "BCM5395",
1329 .alias = "bcm5395",
1330 .vlans = 4096,
1331 .enabled_ports = 0x1f,
1332 .cpu_port = B53_CPU_PORT,
1333 .vta_regs = B53_VTA_REGS,
1334 .duplex_reg = B53_DUPLEX_STAT_GE,
1335 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1336 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1337 .sw_ops = &b53_switch_ops,
1338 },
1339 {
1340 .chip_id = BCM5397_DEVICE_ID,
1341 .dev_name = "BCM5397",
1342 .alias = "bcm5397",
1343 .vlans = 4096,
1344 .enabled_ports = 0x1f,
1345 .cpu_port = B53_CPU_PORT,
1346 .vta_regs = B53_VTA_REGS_9798,
1347 .duplex_reg = B53_DUPLEX_STAT_GE,
1348 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1349 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1350 .sw_ops = &b53_switch_ops,
1351 },
1352 {
1353 .chip_id = BCM5398_DEVICE_ID,
1354 .dev_name = "BCM5398",
1355 .alias = "bcm5398",
1356 .vlans = 4096,
1357 .enabled_ports = 0x7f,
1358 .cpu_port = B53_CPU_PORT,
1359 .vta_regs = B53_VTA_REGS_9798,
1360 .duplex_reg = B53_DUPLEX_STAT_GE,
1361 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1362 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1363 .sw_ops = &b53_switch_ops,
1364 },
1365 {
1366 .chip_id = BCM53115_DEVICE_ID,
1367 .dev_name = "BCM53115",
1368 .alias = "bcm53115",
1369 .vlans = 4096,
1370 .enabled_ports = 0x1f,
1371 .vta_regs = B53_VTA_REGS,
1372 .cpu_port = B53_CPU_PORT,
1373 .duplex_reg = B53_DUPLEX_STAT_GE,
1374 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1375 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1376 .sw_ops = &b53_switch_ops,
1377 },
1378 {
1379 .chip_id = BCM53125_DEVICE_ID,
1380 .dev_name = "BCM53125",
1381 .alias = "bcm53125",
1382 .vlans = 4096,
1383 .enabled_ports = 0x1f,
1384 .cpu_port = B53_CPU_PORT,
1385 .vta_regs = B53_VTA_REGS,
1386 .duplex_reg = B53_DUPLEX_STAT_GE,
1387 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1388 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1389 .sw_ops = &b53_switch_ops,
1390 },
1391 {
1392 .chip_id = BCM53128_DEVICE_ID,
1393 .dev_name = "BCM53128",
1394 .alias = "bcm53128",
1395 .vlans = 4096,
1396 .enabled_ports = 0x1ff,
1397 .cpu_port = B53_CPU_PORT,
1398 .vta_regs = B53_VTA_REGS,
1399 .duplex_reg = B53_DUPLEX_STAT_GE,
1400 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1401 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1402 .sw_ops = &b53_switch_ops,
1403 },
1404 {
1405 .chip_id = BCM63XX_DEVICE_ID,
1406 .dev_name = "BCM63xx",
1407 .alias = "bcm63xx",
1408 .vlans = 4096,
1409 .enabled_ports = 0, /* pdata must provide them */
1410 .cpu_port = B53_CPU_PORT,
1411 .vta_regs = B53_VTA_REGS_63XX,
1412 .duplex_reg = B53_DUPLEX_STAT_63XX,
1413 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1414 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1415 .sw_ops = &b53_switch_ops,
1416 },
1417 {
1418 .chip_id = BCM53010_DEVICE_ID,
1419 .dev_name = "BCM53010",
1420 .alias = "bcm53011",
1421 .vlans = 4096,
1422 .enabled_ports = 0x1f,
1423 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1424 .vta_regs = B53_VTA_REGS,
1425 .duplex_reg = B53_DUPLEX_STAT_GE,
1426 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1427 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1428 .sw_ops = &b53_switch_ops,
1429 },
1430 {
1431 .chip_id = BCM53011_DEVICE_ID,
1432 .dev_name = "BCM53011",
1433 .alias = "bcm53011",
1434 .vlans = 4096,
1435 .enabled_ports = 0x1bf,
1436 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1437 .vta_regs = B53_VTA_REGS,
1438 .duplex_reg = B53_DUPLEX_STAT_GE,
1439 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1440 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1441 .sw_ops = &b53_switch_ops,
1442 },
1443 {
1444 .chip_id = BCM53012_DEVICE_ID,
1445 .dev_name = "BCM53012",
1446 .alias = "bcm53011",
1447 .vlans = 4096,
1448 .enabled_ports = 0x1bf,
1449 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1450 .vta_regs = B53_VTA_REGS,
1451 .duplex_reg = B53_DUPLEX_STAT_GE,
1452 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1453 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1454 .sw_ops = &b53_switch_ops,
1455 },
1456 {
1457 .chip_id = BCM53018_DEVICE_ID,
1458 .dev_name = "BCM53018",
1459 .alias = "bcm53018",
1460 .vlans = 4096,
1461 .enabled_ports = 0x1f,
1462 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1463 .vta_regs = B53_VTA_REGS,
1464 .duplex_reg = B53_DUPLEX_STAT_GE,
1465 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1466 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1467 .sw_ops = &b53_switch_ops,
1468 },
1469 {
1470 .chip_id = BCM53019_DEVICE_ID,
1471 .dev_name = "BCM53019",
1472 .alias = "bcm53019",
1473 .vlans = 4096,
1474 .enabled_ports = 0x1f,
1475 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1476 .vta_regs = B53_VTA_REGS,
1477 .duplex_reg = B53_DUPLEX_STAT_GE,
1478 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1479 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1480 .sw_ops = &b53_switch_ops,
1481 },
1482 };
1483
1484 static int b53_switch_init_of(struct b53_device *dev)
1485 {
1486 struct device_node *dn, *pn;
1487 const char *alias;
1488 u32 port_num;
1489 u16 ports = 0;
1490
1491 dn = of_get_child_by_name(dev_of_node(dev->dev), "ports");
1492 if (!dn)
1493 return -EINVAL;
1494
1495 for_each_available_child_of_node(dn, pn) {
1496 const char *label;
1497 int len;
1498
1499 if (of_property_read_u32(pn, "reg", &port_num))
1500 continue;
1501
1502 if (port_num > B53_CPU_PORT)
1503 continue;
1504
1505 ports |= BIT(port_num);
1506
1507 label = of_get_property(pn, "label", &len);
1508 if (label && !strcmp(label, "cpu"))
1509 dev->sw_dev.cpu_port = port_num;
1510 }
1511
1512 dev->enabled_ports = ports;
1513
1514 if (!of_property_read_string(dev_of_node(dev->dev), "lede,alias",
1515 &alias))
1516 dev->sw_dev.alias = devm_kstrdup(dev->dev, alias, GFP_KERNEL);
1517
1518 return 0;
1519 }
1520
1521 static int b53_switch_init(struct b53_device *dev)
1522 {
1523 struct switch_dev *sw_dev = &dev->sw_dev;
1524 unsigned i;
1525 int ret;
1526
1527 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1528 const struct b53_chip_data *chip = &b53_switch_chips[i];
1529
1530 if (chip->chip_id == dev->chip_id) {
1531 sw_dev->name = chip->dev_name;
1532 if (!sw_dev->alias)
1533 sw_dev->alias = chip->alias;
1534 if (!dev->enabled_ports)
1535 dev->enabled_ports = chip->enabled_ports;
1536 dev->duplex_reg = chip->duplex_reg;
1537 dev->vta_regs[0] = chip->vta_regs[0];
1538 dev->vta_regs[1] = chip->vta_regs[1];
1539 dev->vta_regs[2] = chip->vta_regs[2];
1540 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1541 sw_dev->ops = chip->sw_ops;
1542 sw_dev->cpu_port = chip->cpu_port;
1543 sw_dev->vlans = chip->vlans;
1544 break;
1545 }
1546 }
1547
1548 if (!sw_dev->name)
1549 return -EINVAL;
1550
1551 /* check which BCM5325x version we have */
1552 if (is5325(dev)) {
1553 u8 vc4;
1554
1555 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1556
1557 /* check reserved bits */
1558 switch (vc4 & 3) {
1559 case 1:
1560 /* BCM5325E */
1561 break;
1562 case 3:
1563 /* BCM5325F - do not use port 4 */
1564 dev->enabled_ports &= ~BIT(4);
1565 break;
1566 default:
1567 /* On the BCM47XX SoCs this is the supported internal switch.*/
1568 #ifndef CONFIG_BCM47XX
1569 /* BCM5325M */
1570 return -EINVAL;
1571 #else
1572 break;
1573 #endif
1574 }
1575 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1576 u64 strap_value;
1577
1578 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1579 /* use second IMP port if GMII is enabled */
1580 if (strap_value & SV_GMII_CTRL_115)
1581 sw_dev->cpu_port = 5;
1582 }
1583
1584 if (dev_of_node(dev->dev)) {
1585 ret = b53_switch_init_of(dev);
1586 if (ret)
1587 return ret;
1588 }
1589
1590 dev->enabled_ports |= BIT(sw_dev->cpu_port);
1591 sw_dev->ports = fls(dev->enabled_ports);
1592
1593 dev->ports = devm_kzalloc(dev->dev,
1594 sizeof(struct b53_port) * sw_dev->ports,
1595 GFP_KERNEL);
1596 if (!dev->ports)
1597 return -ENOMEM;
1598
1599 dev->vlans = devm_kzalloc(dev->dev,
1600 sizeof(struct b53_vlan) * sw_dev->vlans,
1601 GFP_KERNEL);
1602 if (!dev->vlans)
1603 return -ENOMEM;
1604
1605 dev->buf = devm_kzalloc(dev->dev, B53_BUF_SIZE, GFP_KERNEL);
1606 if (!dev->buf)
1607 return -ENOMEM;
1608
1609 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1610 if (dev->reset_gpio >= 0) {
1611 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1612 GPIOF_OUT_INIT_HIGH, "robo_reset");
1613 if (ret)
1614 return ret;
1615 }
1616
1617 return b53_switch_reset(dev);
1618 }
1619
1620 struct b53_device *b53_switch_alloc(struct device *base, struct b53_io_ops *ops,
1621 void *priv)
1622 {
1623 struct b53_device *dev;
1624
1625 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
1626 if (!dev)
1627 return NULL;
1628
1629 dev->dev = base;
1630 dev->ops = ops;
1631 dev->priv = priv;
1632 mutex_init(&dev->reg_mutex);
1633
1634 return dev;
1635 }
1636 EXPORT_SYMBOL(b53_switch_alloc);
1637
1638 int b53_switch_detect(struct b53_device *dev)
1639 {
1640 u32 id32;
1641 u16 tmp;
1642 u8 id8;
1643 int ret;
1644
1645 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1646 if (ret)
1647 return ret;
1648
1649 switch (id8) {
1650 case 0:
1651 /*
1652 * BCM5325 and BCM5365 do not have this register so reads
1653 * return 0. But the read operation did succeed, so assume
1654 * this is one of them.
1655 *
1656 * Next check if we can write to the 5325's VTA register; for
1657 * 5365 it is read only.
1658 */
1659
1660 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1661 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1662
1663 if (tmp == 0xf)
1664 dev->chip_id = BCM5325_DEVICE_ID;
1665 else
1666 dev->chip_id = BCM5365_DEVICE_ID;
1667 break;
1668 case BCM5395_DEVICE_ID:
1669 case BCM5397_DEVICE_ID:
1670 case BCM5398_DEVICE_ID:
1671 dev->chip_id = id8;
1672 break;
1673 default:
1674 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
1675 if (ret)
1676 return ret;
1677
1678 switch (id32) {
1679 case BCM53115_DEVICE_ID:
1680 case BCM53125_DEVICE_ID:
1681 case BCM53128_DEVICE_ID:
1682 case BCM53010_DEVICE_ID:
1683 case BCM53011_DEVICE_ID:
1684 case BCM53012_DEVICE_ID:
1685 case BCM53018_DEVICE_ID:
1686 case BCM53019_DEVICE_ID:
1687 dev->chip_id = id32;
1688 break;
1689 default:
1690 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1691 id8, id32);
1692 return -ENODEV;
1693 }
1694 }
1695
1696 if (dev->chip_id == BCM5325_DEVICE_ID)
1697 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
1698 &dev->core_rev);
1699 else
1700 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
1701 &dev->core_rev);
1702 }
1703 EXPORT_SYMBOL(b53_switch_detect);
1704
1705 int b53_switch_register(struct b53_device *dev)
1706 {
1707 int ret;
1708
1709 if (dev->pdata) {
1710 dev->chip_id = dev->pdata->chip_id;
1711 dev->enabled_ports = dev->pdata->enabled_ports;
1712 dev->sw_dev.alias = dev->pdata->alias;
1713 }
1714
1715 if (!dev->chip_id && b53_switch_detect(dev))
1716 return -EINVAL;
1717
1718 ret = b53_switch_init(dev);
1719 if (ret)
1720 return ret;
1721
1722 pr_info("found switch: %s, rev %i\n", dev->sw_dev.name, dev->core_rev);
1723
1724 return register_switch(&dev->sw_dev, NULL);
1725 }
1726 EXPORT_SYMBOL(b53_switch_register);
1727
1728 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1729 MODULE_DESCRIPTION("B53 switch library");
1730 MODULE_LICENSE("Dual BSD/GPL");
OpenWrt Source Repository