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Revert "mediatek: backport mt7622 dts fix for mt7531 switch id to 6.1"
[openwrt/openwrt.git] / target / linux / mediatek / patches-4.14 / 0186-ASoC-mediatek-update-MT2701-AFE-documentation-to-ada.patch
1 From 018219d340c0f7a10098683b8a4733618ea76ba3 Mon Sep 17 00:00:00 2001
2 From: Ryder Lee <ryder.lee@mediatek.com>
3 Date: Thu, 4 Jan 2018 15:44:09 +0800
4 Subject: [PATCH 186/224] ASoC: mediatek: update MT2701 AFE documentation to
5 adapt mfd device
6
7 As the new MFD parent is in place, modify MT2701 AFE documentation to
8 adapt it. Also add three core clocks in example.
9
10 Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
11 Signed-off-by: Mark Brown <broonie@kernel.org>
12 ---
13 .../devicetree/bindings/sound/mt2701-afe-pcm.txt | 171 +++++++++++----------
14 1 file changed, 93 insertions(+), 78 deletions(-)
15
16 --- a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
17 +++ b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
18 @@ -2,15 +2,17 @@ Mediatek AFE PCM controller for mt2701
19
20 Required properties:
21 - compatible = "mediatek,mt2701-audio";
22 -- reg: register location and size
23 - interrupts: should contain AFE and ASYS interrupts
24 - interrupt-names: should be "afe" and "asys"
25 - power-domains: should define the power domain
26 - clocks: Must contain an entry for each entry in clock-names
27 See ../clocks/clock-bindings.txt for details
28 - clock-names: should have these clock names:
29 + "infra_sys_audio_clk",
30 "top_audio_mux1_sel",
31 "top_audio_mux2_sel",
32 + "top_audio_a1sys_hp",
33 + "top_audio_a2sys_hp",
34 "i2s0_src_sel",
35 "i2s1_src_sel",
36 "i2s2_src_sel",
37 @@ -45,85 +47,98 @@ Required properties:
38 - assigned-clocks-parents: parent of input clocks of assigned clocks.
39 - assigned-clock-rates: list of clock frequencies of assigned clocks.
40
41 +Must be a subnode of MediaTek audsys device tree node.
42 +See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.
43 +
44 Example:
45
46 - afe: mt2701-afe-pcm@11220000 {
47 - compatible = "mediatek,mt2701-audio";
48 - reg = <0 0x11220000 0 0x2000>,
49 - <0 0x112A0000 0 0x20000>;
50 - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
51 - <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
52 - interrupt-names = "afe", "asys";
53 - power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
54 - clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
55 - <&topckgen CLK_TOP_AUD_MUX2_SEL>,
56 - <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
57 - <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
58 - <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
59 - <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
60 - <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
61 - <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
62 - <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
63 - <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
64 - <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
65 - <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
66 - <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
67 - <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
68 - <&audiosys CLK_AUD_I2SO1>,
69 - <&audiosys CLK_AUD_I2SO2>,
70 - <&audiosys CLK_AUD_I2SO3>,
71 - <&audiosys CLK_AUD_I2SO4>,
72 - <&audiosys CLK_AUD_I2SIN1>,
73 - <&audiosys CLK_AUD_I2SIN2>,
74 - <&audiosys CLK_AUD_I2SIN3>,
75 - <&audiosys CLK_AUD_I2SIN4>,
76 - <&audiosys CLK_AUD_ASRCO1>,
77 - <&audiosys CLK_AUD_ASRCO2>,
78 - <&audiosys CLK_AUD_ASRCO3>,
79 - <&audiosys CLK_AUD_ASRCO4>,
80 - <&audiosys CLK_AUD_AFE>,
81 - <&audiosys CLK_AUD_AFE_CONN>,
82 - <&audiosys CLK_AUD_A1SYS>,
83 - <&audiosys CLK_AUD_A2SYS>,
84 - <&audiosys CLK_AUD_AFE_MRGIF>;
85 -
86 - clock-names = "top_audio_mux1_sel",
87 - "top_audio_mux2_sel",
88 - "i2s0_src_sel",
89 - "i2s1_src_sel",
90 - "i2s2_src_sel",
91 - "i2s3_src_sel",
92 - "i2s0_src_div",
93 - "i2s1_src_div",
94 - "i2s2_src_div",
95 - "i2s3_src_div",
96 - "i2s0_mclk_en",
97 - "i2s1_mclk_en",
98 - "i2s2_mclk_en",
99 - "i2s3_mclk_en",
100 - "i2so0_hop_ck",
101 - "i2so1_hop_ck",
102 - "i2so2_hop_ck",
103 - "i2so3_hop_ck",
104 - "i2si0_hop_ck",
105 - "i2si1_hop_ck",
106 - "i2si2_hop_ck",
107 - "i2si3_hop_ck",
108 - "asrc0_out_ck",
109 - "asrc1_out_ck",
110 - "asrc2_out_ck",
111 - "asrc3_out_ck",
112 - "audio_afe_pd",
113 - "audio_afe_conn_pd",
114 - "audio_a1sys_pd",
115 - "audio_a2sys_pd",
116 - "audio_mrgif_pd";
117 -
118 - assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
119 - <&topckgen CLK_TOP_AUD_MUX2_SEL>,
120 - <&topckgen CLK_TOP_AUD_MUX1_DIV>,
121 - <&topckgen CLK_TOP_AUD_MUX2_DIV>;
122 - assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
123 - <&topckgen CLK_TOP_AUD2PLL_90M>;
124 - assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
125 + audsys: audio-subsystem@11220000 {
126 + compatible = "mediatek,mt2701-audsys", "syscon", "simple-mfd";
127 + ...
128 +
129 + afe: audio-controller {
130 + compatible = "mediatek,mt2701-audio";
131 + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
132 + <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
133 + interrupt-names = "afe", "asys";
134 + power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
135 +
136 + clocks = <&infracfg CLK_INFRA_AUDIO>,
137 + <&topckgen CLK_TOP_AUD_MUX1_SEL>,
138 + <&topckgen CLK_TOP_AUD_MUX2_SEL>,
139 + <&topckgen CLK_TOP_AUD_48K_TIMING>,
140 + <&topckgen CLK_TOP_AUD_44K_TIMING>,
141 + <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
142 + <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
143 + <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
144 + <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
145 + <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
146 + <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
147 + <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
148 + <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
149 + <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
150 + <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
151 + <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
152 + <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
153 + <&audsys CLK_AUD_I2SO1>,
154 + <&audsys CLK_AUD_I2SO2>,
155 + <&audsys CLK_AUD_I2SO3>,
156 + <&audsys CLK_AUD_I2SO4>,
157 + <&audsys CLK_AUD_I2SIN1>,
158 + <&audsys CLK_AUD_I2SIN2>,
159 + <&audsys CLK_AUD_I2SIN3>,
160 + <&audsys CLK_AUD_I2SIN4>,
161 + <&audsys CLK_AUD_ASRCO1>,
162 + <&audsys CLK_AUD_ASRCO2>,
163 + <&audsys CLK_AUD_ASRCO3>,
164 + <&audsys CLK_AUD_ASRCO4>,
165 + <&audsys CLK_AUD_AFE>,
166 + <&audsys CLK_AUD_AFE_CONN>,
167 + <&audsys CLK_AUD_A1SYS>,
168 + <&audsys CLK_AUD_A2SYS>,
169 + <&audsys CLK_AUD_AFE_MRGIF>;
170 +
171 + clock-names = "infra_sys_audio_clk",
172 + "top_audio_mux1_sel",
173 + "top_audio_mux2_sel",
174 + "top_audio_a1sys_hp",
175 + "top_audio_a2sys_hp",
176 + "i2s0_src_sel",
177 + "i2s1_src_sel",
178 + "i2s2_src_sel",
179 + "i2s3_src_sel",
180 + "i2s0_src_div",
181 + "i2s1_src_div",
182 + "i2s2_src_div",
183 + "i2s3_src_div",
184 + "i2s0_mclk_en",
185 + "i2s1_mclk_en",
186 + "i2s2_mclk_en",
187 + "i2s3_mclk_en",
188 + "i2so0_hop_ck",
189 + "i2so1_hop_ck",
190 + "i2so2_hop_ck",
191 + "i2so3_hop_ck",
192 + "i2si0_hop_ck",
193 + "i2si1_hop_ck",
194 + "i2si2_hop_ck",
195 + "i2si3_hop_ck",
196 + "asrc0_out_ck",
197 + "asrc1_out_ck",
198 + "asrc2_out_ck",
199 + "asrc3_out_ck",
200 + "audio_afe_pd",
201 + "audio_afe_conn_pd",
202 + "audio_a1sys_pd",
203 + "audio_a2sys_pd",
204 + "audio_mrgif_pd";
205 +
206 + assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
207 + <&topckgen CLK_TOP_AUD_MUX2_SEL>,
208 + <&topckgen CLK_TOP_AUD_MUX1_DIV>,
209 + <&topckgen CLK_TOP_AUD_MUX2_DIV>;
210 + assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
211 + <&topckgen CLK_TOP_AUD2PLL_90M>;
212 + assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
213 + };
214 };
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