1 From 4fbacf244953285ac58cb833060076fafd990588 Mon Sep 17 00:00:00 2001
2 From: Sean Wang <sean.wang@mediatek.com>
3 Date: Fri, 29 Dec 2017 10:45:07 +0800
4 Subject: [PATCH 218/224] arm64: dts: mt7622: add ethernet device nodes
6 add ethernet device nodes which enable GMAC1 with SGMII interface
8 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
10 arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 22 ++++++++++++++++++++
11 arch/arm64/boot/dts/mediatek/mt7622.dtsi | 31 ++++++++++++++++++++++++++++
12 2 files changed, 53 insertions(+)
14 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
15 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
21 + pinctrl-names = "default";
22 + pinctrl-0 = <ð_pins>;
26 + compatible = "mediatek,eth-mac";
28 + phy-handle = <&phy5>;
32 + #address-cells = <1>;
35 + phy5: ethernet-phy@5 {
43 pinctrl-names = "default";
44 pinctrl-0 = <&i2c1_pins>;
45 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
46 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
51 + eth: ethernet@1b100000 {
52 + compatible = "mediatek,mt7622-eth",
53 + "mediatek,mt2701-eth",
55 + reg = <0 0x1b100000 0 0x20000>;
56 + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
57 + <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
58 + <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
59 + clocks = <&topckgen CLK_TOP_ETH_SEL>,
60 + <ðsys CLK_ETH_ESW_EN>,
61 + <ðsys CLK_ETH_GP0_EN>,
62 + <ðsys CLK_ETH_GP1_EN>,
63 + <ðsys CLK_ETH_GP2_EN>,
64 + <&sgmiisys CLK_SGMII_TX250M_EN>,
65 + <&sgmiisys CLK_SGMII_RX250M_EN>,
66 + <&sgmiisys CLK_SGMII_CDR_REF>,
67 + <&sgmiisys CLK_SGMII_CDR_FB>,
68 + <&topckgen CLK_TOP_SGMIIPLL>,
69 + <&apmixedsys CLK_APMIXED_ETH2PLL>;
70 + clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
71 + "sgmii_tx250m", "sgmii_rx250m",
72 + "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
74 + power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
75 + mediatek,ethsys = <ðsys>;
76 + mediatek,sgmiisys = <&sgmiisys>;
77 + #address-cells = <1>;
79 + status = "disabled";
82 sgmiisys: sgmiisys@1b128000 {
83 compatible = "mediatek,mt7622-sgmiisys",