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tools/elfutils: refresh portability patch for macOS
[openwrt/openwrt.git] / target / linux / mediatek / patches-5.4 / 0600-4-6-net-dsa-mt7530-Add-the-support-of-MT7531-switch.patch
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5 X-Patchwork-Submitter: Landen Chao <landen.chao@mediatek.com>
6 X-Patchwork-Id: 1206959
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50 From: Landen Chao <landen.chao@mediatek.com>
51 To: <andrew@lunn.ch>, <f.fainelli@gmail.com>,
52 <vivien.didelot@savoirfairelinux.com>, <matthias.bgg@gmail.com>,
53 <robh+dt@kernel.org>, <mark.rutland@arm.com>
54 CC: <devicetree@vger.kernel.org>, <netdev@vger.kernel.org>,
55 <linux-kernel@vger.kernel.org>,
56 <linux-mediatek@lists.infradead.org>, <davem@davemloft.net>,
57 <sean.wang@mediatek.com>, <opensource@vdorst.com>,
58 <frank-w@public-files.de>, Landen Chao <landen.chao@mediatek.com>
59 Subject: [PATCH net-next 4/6] net: dsa: mt7530: Add the support of MT7531
60 switch
61 Date: Tue, 10 Dec 2019 16:14:40 +0800
62 Message-ID: <6d608dd024edc90b09ba4fe35417b693847f973c.1575914275.git.landen.chao@mediatek.com>
63 X-Mailer: git-send-email 2.18.0
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65 References: <cover.1575914275.git.landen.chao@mediatek.com>
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72
73 Add new support for MT7531:
74
75 MT7531 is the next generation of MT7530. It is also a 7-ports switch with
76 5 giga embedded phys, 2 cpu ports, and the same MAC logic of MT7530. Cpu
77 port 6 only supports HSGMII interface. Cpu port 5 supports either RGMII
78 or HSGMII in different HW sku. Due to HSGMII interface support, pll, and
79 pad setting are different from MT7530. This patch adds different initial
80 setting of MT7531.
81
82 Signed-off-by: Landen Chao <landen.chao@mediatek.com>
83 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
84 ---
85 drivers/net/dsa/Kconfig | 6 +-
86 drivers/net/dsa/mt7530.c | 643 ++++++++++++++++++++++++++++++++++++++-
87 drivers/net/dsa/mt7530.h | 144 +++++++++
88 3 files changed, 784 insertions(+), 9 deletions(-)
89
90 --- a/drivers/net/dsa/Kconfig
91 +++ b/drivers/net/dsa/Kconfig
92 @@ -33,12 +33,12 @@ config NET_DSA_LANTIQ_GSWIP
93 the xrx200 / VR9 SoC.
94
95 config NET_DSA_MT7530
96 - tristate "MediaTek MT7530 and MT7621 Ethernet switch support"
97 + tristate "MediaTek MT753x and MT7621 Ethernet switch support"
98 depends on NET_DSA
99 select NET_DSA_TAG_MTK
100 ---help---
101 - This enables support for the MediaTek MT7530 and MT7621 Ethernet
102 - switch chip.
103 + This enables support for the MediaTek MT7530, MT7531 and MT7621
104 + Ethernet switch chip.
105
106 config NET_DSA_MV88E6060
107 tristate "Marvell 88E6060 ethernet switch chip support"
108 --- a/drivers/net/dsa/mt7530.c
109 +++ b/drivers/net/dsa/mt7530.c
110 @@ -234,6 +234,12 @@ mt7530_write(struct mt7530_priv *priv, u
111 }
112
113 static u32
114 +_mt7530_unlocked_read(struct mt7530_dummy_poll *p)
115 +{
116 + return mt7530_mii_read(p->priv, p->reg);
117 +}
118 +
119 +static u32
120 _mt7530_read(struct mt7530_dummy_poll *p)
121 {
122 struct mii_bus *bus = p->priv->bus;
123 @@ -287,6 +293,102 @@ mt7530_clear(struct mt7530_priv *priv, u
124 }
125
126 static int
127 +mt7531_ind_mmd_phy_read(struct mt7530_priv *priv, int port, int devad,
128 + int regnum)
129 +{
130 + struct mii_bus *bus = priv->bus;
131 + struct mt7530_dummy_poll p;
132 + u32 reg, val;
133 + int ret;
134 +
135 + INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
136 +
137 + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
138 +
139 + ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
140 + !(val & PHY_ACS_ST), 20, 100000);
141 + if (ret < 0) {
142 + dev_err(priv->dev, "poll timeout\n");
143 + goto out;
144 + }
145 +
146 + reg = MDIO_CL45_ADDR | MDIO_PHY_ADDR(port) | MDIO_DEV_ADDR(devad) |
147 + regnum;
148 + mt7530_mii_write(priv, MT7531_PHY_IAC, reg | PHY_ACS_ST);
149 +
150 + ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
151 + !(val & PHY_ACS_ST), 20, 100000);
152 + if (ret < 0) {
153 + dev_err(priv->dev, "poll timeout\n");
154 + goto out;
155 + }
156 +
157 + reg = MDIO_CL45_READ | MDIO_PHY_ADDR(port) | MDIO_DEV_ADDR(devad);
158 + mt7530_mii_write(priv, MT7531_PHY_IAC, reg | PHY_ACS_ST);
159 +
160 + ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
161 + !(val & PHY_ACS_ST), 20, 100000);
162 + if (ret < 0) {
163 + dev_err(priv->dev, "poll timeout\n");
164 + goto out;
165 + }
166 +
167 + ret = val & MDIO_RW_DATA_MASK;
168 +out:
169 + mutex_unlock(&bus->mdio_lock);
170 +
171 + return ret;
172 +}
173 +
174 +static int
175 +mt7531_ind_mmd_phy_write(struct mt7530_priv *priv, int port, int devad,
176 + int regnum, u32 data)
177 +{
178 + struct mii_bus *bus = priv->bus;
179 + struct mt7530_dummy_poll p;
180 + u32 val, reg;
181 + int ret;
182 +
183 + INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
184 +
185 + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
186 +
187 + ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
188 + !(val & PHY_ACS_ST), 20, 100000);
189 + if (ret < 0) {
190 + dev_err(priv->dev, "poll timeout\n");
191 + goto out;
192 + }
193 +
194 + reg = MDIO_CL45_ADDR | MDIO_PHY_ADDR(port) | MDIO_DEV_ADDR(devad) |
195 + regnum;
196 + mt7530_mii_write(priv, MT7531_PHY_IAC, reg | PHY_ACS_ST);
197 +
198 + ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
199 + !(val & PHY_ACS_ST), 20, 100000);
200 + if (ret < 0) {
201 + dev_err(priv->dev, "poll timeout\n");
202 + goto out;
203 + }
204 +
205 + reg = MDIO_CL45_WRITE | MDIO_PHY_ADDR(port) | MDIO_DEV_ADDR(devad) |
206 + data;
207 + mt7530_mii_write(priv, MT7531_PHY_IAC, reg | PHY_ACS_ST);
208 +
209 + ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
210 + !(val & PHY_ACS_ST), 20, 100000);
211 + if (ret < 0) {
212 + dev_err(priv->dev, "poll timeout\n");
213 + goto out;
214 + }
215 +
216 +out:
217 + mutex_unlock(&bus->mdio_lock);
218 +
219 + return ret;
220 +}
221 +
222 +static int
223 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
224 {
225 u32 val;
226 @@ -516,6 +618,83 @@ static int mt7530_phy_write(struct dsa_s
227 return mdiobus_write_nested(priv->bus, port, regnum, val);
228 }
229
230 +static int
231 +mt7531_ind_phy_read(struct dsa_switch *ds, int port, int regnum)
232 +{
233 + struct mt7530_priv *priv = ds->priv;
234 + struct mii_bus *bus = priv->bus;
235 + struct mt7530_dummy_poll p;
236 + int ret;
237 + u32 val;
238 +
239 + INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
240 +
241 + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
242 +
243 + ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
244 + !(val & PHY_ACS_ST), 20, 100000);
245 + if (ret < 0) {
246 + dev_err(priv->dev, "poll timeout\n");
247 + goto out;
248 + }
249 +
250 + val = MDIO_CL22_READ | MDIO_PHY_ADDR(port) | MDIO_REG_ADDR(regnum);
251 +
252 + mt7530_mii_write(priv, MT7531_PHY_IAC, val | PHY_ACS_ST);
253 +
254 + ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
255 + !(val & PHY_ACS_ST), 20, 100000);
256 + if (ret < 0) {
257 + dev_err(priv->dev, "poll timeout\n");
258 + goto out;
259 + }
260 +
261 + ret = val & MDIO_RW_DATA_MASK;
262 +out:
263 + mutex_unlock(&bus->mdio_lock);
264 +
265 + return ret;
266 +}
267 +
268 +static int
269 +mt7531_ind_phy_write(struct dsa_switch *ds, int port, int regnum,
270 + u16 data)
271 +{
272 + struct mt7530_priv *priv = ds->priv;
273 + struct mii_bus *bus = priv->bus;
274 + struct mt7530_dummy_poll p;
275 + int ret;
276 + u32 reg;
277 +
278 + INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
279 +
280 + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
281 +
282 + ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
283 + !(reg & PHY_ACS_ST), 20, 100000);
284 + if (ret < 0) {
285 + dev_err(priv->dev, "poll timeout\n");
286 + goto out;
287 + }
288 +
289 + reg = MDIO_CL22_WRITE | MDIO_PHY_ADDR(port) | MDIO_REG_ADDR(regnum) |
290 + data;
291 +
292 + mt7530_mii_write(priv, MT7531_PHY_IAC, reg | PHY_ACS_ST);
293 +
294 + ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
295 + !(reg & PHY_ACS_ST), 20, 100000);
296 + if (ret < 0) {
297 + dev_err(priv->dev, "poll timeout\n");
298 + goto out;
299 + }
300 +
301 +out:
302 + mutex_unlock(&bus->mdio_lock);
303 +
304 + return ret;
305 +}
306 +
307 static void
308 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
309 uint8_t *data)
310 @@ -1355,6 +1534,86 @@ mt7530_setup(struct dsa_switch *ds)
311 return 0;
312 }
313
314 +static int mt7531_setup(struct dsa_switch *ds)
315 +{
316 + struct mt7530_priv *priv = ds->priv;
317 + struct mt7530_dummy_poll p;
318 + u32 val, id;
319 + int ret, i;
320 +
321 + /* Reset whole chip through gpio pin or memory-mapped registers for
322 + * different type of hardware
323 + */
324 + if (priv->mcm) {
325 + reset_control_assert(priv->rstc);
326 + usleep_range(1000, 1100);
327 + reset_control_deassert(priv->rstc);
328 + } else {
329 + gpiod_set_value_cansleep(priv->reset, 0);
330 + usleep_range(1000, 1100);
331 + gpiod_set_value_cansleep(priv->reset, 1);
332 + }
333 +
334 + /* Waiting for MT7530 got to stable */
335 + INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
336 + ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
337 + 20, 1000000);
338 + if (ret < 0) {
339 + dev_err(priv->dev, "reset timeout\n");
340 + return ret;
341 + }
342 +
343 + id = mt7530_read(priv, MT7531_CREV);
344 + id >>= CHIP_NAME_SHIFT;
345 +
346 + if (id != MT7531_ID) {
347 + dev_err(priv->dev, "chip %x can't be supported\n", id);
348 + return -ENODEV;
349 + }
350 +
351 + /* Reset the switch through internal reset */
352 + mt7530_write(priv, MT7530_SYS_CTRL,
353 + SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
354 + SYS_CTRL_REG_RST);
355 +
356 + priv->p6_interface = PHY_INTERFACE_MODE_NA;
357 +
358 + /* Enable PHY power, since phy_device has not yet been created
359 + * provided for phy_[read,write]_mmd_indirect is called, we provide
360 + * our own mt7531_ind_mmd_phy_[read,write] to complete this
361 + * function.
362 + */
363 + val = mt7531_ind_mmd_phy_read(priv, 0, PHY_DEV1F,
364 + MT7531_PHY_DEV1F_REG_403);
365 + val |= MT7531_PHY_EN_BYPASS_MODE;
366 + val &= ~MT7531_PHY_POWER_OFF;
367 + mt7531_ind_mmd_phy_write(priv, 0, PHY_DEV1F,
368 + MT7531_PHY_DEV1F_REG_403, val);
369 +
370 + /* Enable and reset MIB counters */
371 + mt7530_mib_reset(ds);
372 +
373 + mt7530_clear(priv, MT7530_MFC, UNU_FFP_MASK);
374 +
375 + for (i = 0; i < MT7530_NUM_PORTS; i++) {
376 + /* Disable forwarding by default on all ports */
377 + mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
378 + PCR_MATRIX_CLR);
379 +
380 + if (dsa_is_cpu_port(ds, i))
381 + mt7530_cpu_port_enable(priv, i);
382 + else
383 + mt7530_port_disable(ds, i);
384 + }
385 +
386 + /* Flush the FDB table */
387 + ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
388 + if (ret < 0)
389 + return ret;
390 +
391 + return 0;
392 +}
393 +
394 static bool mt7530_phy_supported(struct dsa_switch *ds, int port,
395 const struct phylink_link_state *state)
396 {
397 @@ -1392,6 +1651,49 @@ unsupported:
398 return false;
399 }
400
401 +static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv)
402 +{
403 + u32 val;
404 +
405 + val = mt7530_read(priv, MT7531_TOP_SIG_SR);
406 + return ((val & PAD_DUAL_SGMII_EN) != 0);
407 +}
408 +
409 +static bool mt7531_phy_supported(struct dsa_switch *ds, int port,
410 + const struct phylink_link_state *state)
411 +{
412 + struct mt7530_priv *priv = ds->priv;
413 +
414 + switch (port) {
415 + case 0: /* Internal phy */
416 + case 1:
417 + case 2:
418 + case 3:
419 + case 4:
420 + if (state->interface != PHY_INTERFACE_MODE_GMII)
421 + goto unsupported;
422 + break;
423 + case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
424 + if (!mt7531_dual_sgmii_supported(priv))
425 + return phy_interface_mode_is_rgmii(state->interface);
426 + /* fall through */
427 + case 6: /* 1st cpu port supports sgmii/8023z only */
428 + if (state->interface != PHY_INTERFACE_MODE_SGMII &&
429 + !phy_interface_mode_is_8023z(state->interface))
430 + goto unsupported;
431 + break;
432 + default:
433 + dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
434 + port);
435 + goto unsupported;
436 + }
437 +
438 + return true;
439 +
440 +unsupported:
441 + return false;
442 +}
443 +
444 static bool mt753x_phy_supported(struct dsa_switch *ds, int port,
445 const struct phylink_link_state *state)
446 {
447 @@ -1413,7 +1715,144 @@ mt7530_pad_setup(struct dsa_switch *ds,
448 * host which must be placed after the setup on the
449 * device side is all finished.
450 */
451 - mt7623_pad_clk_setup(ds);
452 + //mt7623_pad_clk_setup(ds);
453 + }
454 +
455 + return 0;
456 +}
457 +
458 +static int
459 +mt7531_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
460 +{
461 + struct mt7530_priv *priv = ds->priv;
462 + u32 xtal, val;
463 +
464 + if (mt7531_dual_sgmii_supported(priv))
465 + return 0;
466 +
467 + xtal = mt7530_read(priv, MT7531_HWTRAP) & HWTRAP_XTAL_FSEL_MASK;
468 +
469 + switch (xtal) {
470 + case HWTRAP_XTAL_FSEL_25MHZ:
471 + /* Step 1 : Disable MT7531 COREPLL */
472 + val = mt7530_read(priv, MT7531_PLLGP_EN);
473 + val &= ~EN_COREPLL;
474 + mt7530_write(priv, MT7531_PLLGP_EN, val);
475 +
476 + /* Step 2: switch to XTAL output */
477 + val = mt7530_read(priv, MT7531_PLLGP_EN);
478 + val |= SW_CLKSW;
479 + mt7530_write(priv, MT7531_PLLGP_EN, val);
480 +
481 + val = mt7530_read(priv, MT7531_PLLGP_CR0);
482 + val &= ~RG_COREPLL_EN;
483 + mt7530_write(priv, MT7531_PLLGP_CR0, val);
484 +
485 + /* Step 3: disable PLLGP and enable program PLLGP */
486 + val = mt7530_read(priv, MT7531_PLLGP_EN);
487 + val |= SW_PLLGP;
488 + mt7530_write(priv, MT7531_PLLGP_EN, val);
489 +
490 + /* Step 4: program COREPLL output frequency to 500MHz */
491 + val = mt7530_read(priv, MT7531_PLLGP_CR0);
492 + val &= ~RG_COREPLL_POSDIV_M;
493 + val |= 2 << RG_COREPLL_POSDIV_S;
494 + mt7530_write(priv, MT7531_PLLGP_CR0, val);
495 + usleep_range(25, 35);
496 +
497 + val = mt7530_read(priv, MT7531_PLLGP_CR0);
498 + val &= ~RG_COREPLL_SDM_PCW_M;
499 + val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
500 + mt7530_write(priv, MT7531_PLLGP_CR0, val);
501 +
502 + /* Set feedback divide ratio update signal to high */
503 + val = mt7530_read(priv, MT7531_PLLGP_CR0);
504 + val |= RG_COREPLL_SDM_PCW_CHG;
505 + mt7530_write(priv, MT7531_PLLGP_CR0, val);
506 + /* Wait for at least 16 XTAL clocks */
507 + usleep_range(10, 20);
508 +
509 + /* Step 5: set feedback divide ratio update signal to low */
510 + val = mt7530_read(priv, MT7531_PLLGP_CR0);
511 + val &= ~RG_COREPLL_SDM_PCW_CHG;
512 + mt7530_write(priv, MT7531_PLLGP_CR0, val);
513 +
514 + /* Enable 325M clock for SGMII */
515 + mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
516 +
517 + /* Enable 250SSC clock for RGMII */
518 + mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
519 +
520 + /* Step 6: Enable MT7531 PLL */
521 + val = mt7530_read(priv, MT7531_PLLGP_CR0);
522 + val |= RG_COREPLL_EN;
523 + mt7530_write(priv, MT7531_PLLGP_CR0, val);
524 +
525 + val = mt7530_read(priv, MT7531_PLLGP_EN);
526 + val |= EN_COREPLL;
527 + mt7530_write(priv, MT7531_PLLGP_EN, val);
528 + usleep_range(25, 35);
529 + break;
530 + case HWTRAP_XTAL_FSEL_40MHZ:
531 + /* Step 1 : Disable MT7531 COREPLL */
532 + val = mt7530_read(priv, MT7531_PLLGP_EN);
533 + val &= ~EN_COREPLL;
534 + mt7530_write(priv, MT7531_PLLGP_EN, val);
535 +
536 + /* Step 2: switch to XTAL output */
537 + val = mt7530_read(priv, MT7531_PLLGP_EN);
538 + val |= SW_CLKSW;
539 + mt7530_write(priv, MT7531_PLLGP_EN, val);
540 +
541 + val = mt7530_read(priv, MT7531_PLLGP_CR0);
542 + val &= ~RG_COREPLL_EN;
543 + mt7530_write(priv, MT7531_PLLGP_CR0, val);
544 +
545 + /* Step 3: disable PLLGP and enable program PLLGP */
546 + val = mt7530_read(priv, MT7531_PLLGP_EN);
547 + val |= SW_PLLGP;
548 + mt7530_write(priv, MT7531_PLLGP_EN, val);
549 +
550 + /* Step 4: program COREPLL output frequency to 500MHz */
551 + val = mt7530_read(priv, MT7531_PLLGP_CR0);
552 + val &= ~RG_COREPLL_POSDIV_M;
553 + val |= 2 << RG_COREPLL_POSDIV_S;
554 + mt7530_write(priv, MT7531_PLLGP_CR0, val);
555 + usleep_range(25, 35);
556 +
557 + val = mt7530_read(priv, MT7531_PLLGP_CR0);
558 + val &= ~RG_COREPLL_SDM_PCW_M;
559 + val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
560 + mt7530_write(priv, MT7531_PLLGP_CR0, val);
561 +
562 + /* Set feedback divide ratio update signal to high */
563 + val = mt7530_read(priv, MT7531_PLLGP_CR0);
564 + val |= RG_COREPLL_SDM_PCW_CHG;
565 + mt7530_write(priv, MT7531_PLLGP_CR0, val);
566 + /* Wait for at least 16 XTAL clocks */
567 + usleep_range(10, 20);
568 +
569 + /* Step 5: set feedback divide ratio update signal to low */
570 + val = mt7530_read(priv, MT7531_PLLGP_CR0);
571 + val &= ~RG_COREPLL_SDM_PCW_CHG;
572 + mt7530_write(priv, MT7531_PLLGP_CR0, val);
573 +
574 + /* Enable 325M clock for SGMII */
575 + mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
576 +
577 + /* Enable 250SSC clock for RGMII */
578 + mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
579 +
580 + /* Step 6: Enable MT7531 PLL */
581 + val = mt7530_read(priv, MT7531_PLLGP_CR0);
582 + val |= RG_COREPLL_EN;
583 + mt7530_write(priv, MT7531_PLLGP_CR0, val);
584 +
585 + val = mt7530_read(priv, MT7531_PLLGP_EN);
586 + val |= EN_COREPLL;
587 + mt7530_write(priv, MT7531_PLLGP_EN, val);
588 + usleep_range(25, 35);
589 + break;
590 }
591
592 return 0;
593 @@ -1442,6 +1881,149 @@ mt7530_mac_setup(struct dsa_switch *ds,
594 return 0;
595 }
596
597 +static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port)
598 +{
599 + u32 val;
600 +
601 + if (port != 5) {
602 + dev_err(priv->dev, "RGMII mode is not available for port %d\n",
603 + port);
604 + return -EINVAL;
605 + }
606 +
607 + val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
608 + val |= GP_CLK_EN;
609 + val &= ~GP_MODE_MASK;
610 + val |= GP_MODE(MT7531_GP_MODE_RGMII);
611 + val |= TXCLK_NO_REVERSE;
612 + val |= RXCLK_NO_DELAY;
613 + val &= ~CLK_SKEW_IN_MASK;
614 + val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG);
615 + val &= ~CLK_SKEW_OUT_MASK;
616 + val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG);
617 + mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
618 +
619 + return 0;
620 +}
621 +
622 +static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port,
623 + const struct phylink_link_state *state)
624 +{
625 + u32 val;
626 +
627 + if (port != 5 && port != 6)
628 + return -EINVAL;
629 +
630 + val = mt7530_read(priv, MT7531_QPHY_PWR_STATE_CTRL(port));
631 + val |= MT7531_SGMII_PHYA_PWD;
632 + mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), val);
633 +
634 + val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port));
635 + val &= ~MT7531_RG_TPHY_SPEED_MASK;
636 + if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
637 + val |= MT7531_RG_TPHY_SPEED_3_125G;
638 + mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val);
639 +
640 + val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
641 + val &= ~MT7531_SGMII_AN_ENABLE;
642 + mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
643 +
644 + val = mt7530_read(priv, MT7531_SGMII_MODE(port));
645 + val &= ~MT7531_SGMII_IF_MODE_MASK;
646 +
647 + switch (state->speed) {
648 + case SPEED_10:
649 + val |= MT7531_SGMII_FORCE_SPEED_10;
650 + break;
651 + case SPEED_100:
652 + val |= MT7531_SGMII_FORCE_SPEED_100;
653 + break;
654 + case SPEED_2500:
655 + case SPEED_1000:
656 + val |= MT7531_SGMII_FORCE_SPEED_1000;
657 + break;
658 + };
659 +
660 + val &= ~MT7531_SGMII_FORCE_DUPLEX;
661 + /* For sgmii force mode, 0 is full duplex and 1 is half duplex */
662 + if (state->duplex == DUPLEX_HALF)
663 + val |= MT7531_SGMII_FORCE_DUPLEX;
664 +
665 + mt7530_write(priv, MT7531_SGMII_MODE(port), val);
666 +
667 + val = mt7530_read(priv, MT7531_QPHY_PWR_STATE_CTRL(port));
668 + val &= ~MT7531_SGMII_PHYA_PWD;
669 + mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), val);
670 +
671 + return 0;
672 +}
673 +
674 +static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port,
675 + const struct phylink_link_state *state)
676 +{
677 + u32 val;
678 +
679 + if (port != 5 && port != 6)
680 + return -EINVAL;
681 +
682 + val = mt7530_read(priv, MT7531_QPHY_PWR_STATE_CTRL(port));
683 + val |= MT7531_SGMII_PHYA_PWD;
684 + mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), val);
685 +
686 + switch (state->speed) {
687 + case SPEED_10:
688 + case SPEED_100:
689 + case SPEED_1000:
690 + val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port));
691 + val &= ~MT7531_RG_TPHY_SPEED_MASK;
692 + mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val);
693 + break;
694 + default:
695 + dev_info(priv->dev, "invalid SGMII speed idx %d for port %d\n",
696 + state->speed, port);
697 +
698 + return -EINVAL;
699 + }
700 +
701 + val = mt7530_read(priv, MT7531_SGMII_MODE(port));
702 + val |= MT7531_SGMII_REMOTE_FAULT_DIS;
703 + mt7530_write(priv, MT7531_SGMII_MODE(port), val);
704 +
705 + val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
706 + val |= MT7531_SGMII_AN_RESTART;
707 + mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
708 +
709 + val = mt7530_read(priv, MT7531_QPHY_PWR_STATE_CTRL(port));
710 + val &= ~MT7531_SGMII_PHYA_PWD;
711 + mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), val);
712 +
713 + return 0;
714 +}
715 +
716 +static int
717 +mt7531_mac_setup(struct dsa_switch *ds, int port, unsigned int mode,
718 + const struct phylink_link_state *state)
719 +{
720 + struct mt7530_priv *priv = ds->priv;
721 +
722 + if (port < 5 || port >= MT7530_NUM_PORTS) {
723 + dev_err(priv->dev, "port %d is not a MAC port\n", port);
724 + return -EINVAL;
725 + }
726 +
727 + switch (state->interface) {
728 + case PHY_INTERFACE_MODE_RGMII:
729 + return mt7531_rgmii_setup(priv, port);
730 + case PHY_INTERFACE_MODE_1000BASEX:
731 + case PHY_INTERFACE_MODE_2500BASEX:
732 + return mt7531_sgmii_setup_mode_force(priv, port, state);
733 + case PHY_INTERFACE_MODE_SGMII:
734 + return mt7531_sgmii_setup_mode_an(priv, port, state);
735 + default:
736 + return -EINVAL;
737 + }
738 +}
739 +
740 static int mt753x_mac_setup(struct dsa_switch *ds, int port, unsigned int mode,
741 const struct phylink_link_state *state)
742 {
743 @@ -1473,22 +2055,23 @@ static void mt753x_phylink_mac_config(st
744 if (priv->p5_interface == state->interface)
745 break;
746 if (mt753x_mac_setup(ds, port, mode, state) < 0)
747 - goto unsupported;
748 + break;
749 + priv->p5_interface = state->interface;
750 break;
751 case 6: /* 1st cpu port */
752 if (priv->p6_interface == state->interface)
753 break;
754 mt753x_pad_setup(ds, state);
755 if (mt753x_mac_setup(ds, port, mode, state) < 0)
756 - goto unsupported;
757 + break;
758 priv->p6_interface = state->interface;
759 break;
760 default:
761 - dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
762 return;
763 }
764
765 - if (phylink_autoneg_inband(mode)) {
766 + if (phylink_autoneg_inband(mode) &&
767 + state->interface != PHY_INTERFACE_MODE_SGMII) {
768 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
769 __func__);
770 return;
771 @@ -1499,13 +2082,15 @@ static void mt753x_phylink_mac_config(st
772 mcr_new &= ~(PMCR_FORCE_SPEED_1000 | PMCR_FORCE_SPEED_100 |
773 PMCR_FORCE_FDX | PMCR_TX_FC_EN | PMCR_RX_FC_EN);
774 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
775 - PMCR_BACKPR_EN | PMCR_FORCE_MODE;
776 + PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id) |
777 + PMCR_FORCE_LNK;
778
779 /* Are we connected to external phy */
780 if (port == 5 && dsa_is_user_port(ds, 5))
781 mcr_new |= PMCR_EXT_PHY;
782
783 switch (state->speed) {
784 + case SPEED_2500:
785 case SPEED_1000:
786 mcr_new |= PMCR_FORCE_SPEED_1000;
787 if (priv->eee_enable & BIT(port))
788 @@ -1529,6 +2114,27 @@ static void mt753x_phylink_mac_config(st
789 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
790 }
791
792 +void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port)
793 +{
794 + struct mt7530_priv *priv = ds->priv;
795 + u32 val;
796 +
797 + val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
798 + val |= MT7531_SGMII_AN_RESTART;
799 + mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
800 +}
801 +
802 +static void
803 +mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port)
804 +{
805 + struct mt7530_priv *priv = ds->priv;
806 +
807 + if (!priv->info->port_an_restart)
808 + return;
809 +
810 + priv->info->port_an_restart(ds, port);
811 +}
812 +
813 static void mt7530_phylink_mac_link_down(struct dsa_switch *ds, int port,
814 unsigned int mode,
815 phy_interface_t interface)
816 @@ -1563,9 +2169,20 @@ static void mt753x_phylink_validate(stru
817 phylink_set_port_modes(mask);
818 phylink_set(mask, Autoneg);
819
820 - if (state->interface == PHY_INTERFACE_MODE_TRGMII) {
821 + switch (state->interface) {
822 + case PHY_INTERFACE_MODE_TRGMII:
823 phylink_set(mask, 1000baseT_Full);
824 - } else {
825 + break;
826 + case PHY_INTERFACE_MODE_1000BASEX:
827 + case PHY_INTERFACE_MODE_2500BASEX:
828 + phylink_set(mask, 1000baseX_Full);
829 + phylink_set(mask, 2500baseX_Full);
830 + break;
831 + case PHY_INTERFACE_MODE_SGMII:
832 + phylink_set(mask, 1000baseT_Full);
833 + phylink_set(mask, 1000baseX_Full);
834 + /* fall through */
835 + default:
836 phylink_set(mask, 10baseT_Half);
837 phylink_set(mask, 10baseT_Full);
838 phylink_set(mask, 100baseT_Half);
839 @@ -1577,6 +2194,7 @@ static void mt753x_phylink_validate(stru
840 if (port == 5)
841 phylink_set(mask, 1000baseX_Full);
842 }
843 + break;
844 }
845
846 phylink_set(mask, Pause);
847 @@ -1721,8 +2339,9 @@ static const struct dsa_switch_ops mt753
848 .port_mirror_add = mt7530_port_mirror_add,
849 .port_mirror_del = mt7530_port_mirror_del,
850 .phylink_validate = mt753x_phylink_validate,
851 - .phylink_mac_link_state = mt7530_phylink_mac_link_state,
852 + .phylink_mac_link_state = mt7530_phylink_mac_link_state,
853 .phylink_mac_config = mt753x_phylink_mac_config,
854 + .phylink_mac_an_restart = mt753x_phylink_mac_an_restart,
855 .phylink_mac_link_down = mt7530_phylink_mac_link_down,
856 .phylink_mac_link_up = mt7530_phylink_mac_link_up,
857 .get_mac_eee = mt7530_get_mac_eee,
858 @@ -1748,11 +2367,22 @@ static const struct mt753x_info mt753x_t
859 .pad_setup = mt7530_pad_setup,
860 .mac_setup = mt7530_mac_setup,
861 },
862 + [ID_MT7531] = {
863 + .id = ID_MT7531,
864 + .setup = mt7531_setup,
865 + .phy_read = mt7531_ind_phy_read,
866 + .phy_write = mt7531_ind_phy_write,
867 + .phy_supported = mt7531_phy_supported,
868 + .pad_setup = mt7531_pad_setup,
869 + .mac_setup = mt7531_mac_setup,
870 + .port_an_restart = mt7531_sgmii_restart_an,
871 + },
872 };
873
874 static const struct of_device_id mt7530_of_match[] = {
875 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
876 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
877 + { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
878 { /* sentinel */ },
879 };
880 MODULE_DEVICE_TABLE(of, mt7530_of_match);
881 --- a/drivers/net/dsa/mt7530.h
882 +++ b/drivers/net/dsa/mt7530.h
883 @@ -14,6 +14,7 @@
884 enum mt753x_id {
885 ID_MT7530 = 0,
886 ID_MT7621 = 1,
887 + ID_MT7531 = 2,
888 };
889
890 #define NUM_TRGMII_CTRL 5
891 @@ -222,6 +223,19 @@ enum mt7530_vlan_port_attr {
892 #define PMCR_FORCE_LNK BIT(0)
893 #define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \
894 PMCR_FORCE_SPEED_1000)
895 +#define MT7531_FORCE_LNK BIT(31)
896 +#define MT7531_FORCE_SPD BIT(30)
897 +#define MT7531_FORCE_DPX BIT(29)
898 +#define MT7531_FORCE_RX_FC BIT(28)
899 +#define MT7531_FORCE_TX_FC BIT(27)
900 +#define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \
901 + MT7531_FORCE_SPD | \
902 + MT7531_FORCE_DPX | \
903 + MT7531_FORCE_RX_FC | \
904 + MT7531_FORCE_TX_FC)
905 +#define PMCR_FORCE_MODE_ID(id) (((id) == ID_MT7531) ? \
906 + MT7531_FORCE_MODE : \
907 + PMCR_FORCE_MODE)
908
909 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
910 #define PMSR_EEE1G BIT(7)
911 @@ -258,12 +272,111 @@ enum mt7530_vlan_port_attr {
912 CCR_RX_OCT_CNT_BAD | \
913 CCR_TX_OCT_CNT_GOOD | \
914 CCR_TX_OCT_CNT_BAD)
915 +
916 +/* SGMII registers */
917 +#define MT7531_SGMII_REG_BASE 0x5000
918 +#define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \
919 + ((p) - 5) * 0x1000 + (r))
920 +
921 +/* SGMII PCS_CONTROL_1 */
922 +#define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(p, 0x00)
923 +#define MT7531_SGMII_LINK_STATUS BIT(18)
924 +#define MT7531_SGMII_AN_ENABLE BIT(12)
925 +#define MT7531_SGMII_AN_RESTART BIT(9)
926 +
927 +/* Fields of SGMII_MODE */
928 +#define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(p, 0x20)
929 +#define MT7531_SGMII_REMOTE_FAULT_DIS BIT(8)
930 +#define MT7531_SGMII_FORCE_DUPLEX BIT(4)
931 +#define MT7531_SGMII_IF_MODE_MASK GENMASK(5, 1)
932 +#define MT7531_SGMII_FORCE_SPEED_10 0x0
933 +#define MT7531_SGMII_FORCE_SPEED_100 BIT(2)
934 +#define MT7531_SGMII_FORCE_SPEED_1000 BIT(3)
935 +
936 +/* Fields of QPHY_PWR_STATE_CTRL */
937 +#define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(p, 0xe8)
938 +#define MT7531_SGMII_PHYA_PWD BIT(4)
939 +
940 +/* Values of SGMII SPEED */
941 +#define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(p, 0x128)
942 +#define MT7531_RG_TPHY_SPEED_MASK (BIT(2) | BIT(3))
943 +#define MT7531_RG_TPHY_SPEED_1_25G 0x0
944 +#define MT7531_RG_TPHY_SPEED_3_125G BIT(2)
945 +
946 /* Register for system reset */
947 #define MT7530_SYS_CTRL 0x7000
948 #define SYS_CTRL_PHY_RST BIT(2)
949 #define SYS_CTRL_SW_RST BIT(1)
950 #define SYS_CTRL_REG_RST BIT(0)
951
952 +/* Register for PHY Indirect Access Control */
953 +#define MT7531_PHY_IAC 0x701C
954 +#define PHY_ACS_ST BIT(31)
955 +#define MDIO_REG_ADDR_MASK (0x1f << 25)
956 +#define MDIO_PHY_ADDR_MASK (0x1f << 20)
957 +#define MDIO_CMD_MASK (0x3 << 18)
958 +#define MDIO_ST_MASK (0x3 << 16)
959 +#define MDIO_RW_DATA_MASK (0xffff)
960 +#define MDIO_REG_ADDR(x) (((x) & 0x1f) << 25)
961 +#define MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25)
962 +#define MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20)
963 +#define MDIO_CMD(x) (((x) & 0x3) << 18)
964 +#define MDIO_ST(x) (((x) & 0x3) << 16)
965 +
966 +enum mt7531_phy_iac_cmd {
967 + MT7531_MDIO_ADDR = 0,
968 + MT7531_MDIO_WRITE = 1,
969 + MT7531_MDIO_READ = 2,
970 + MT7531_MDIO_READ_CL45 = 3,
971 +};
972 +
973 +/* MDIO_ST: MDIO start field */
974 +enum mt7531_mdio_st {
975 + MT7531_MDIO_ST_CL45 = 0,
976 + MT7531_MDIO_ST_CL22 = 1,
977 +};
978 +
979 +#define MDIO_CL22_READ (MDIO_ST(MT7531_MDIO_ST_CL22) | \
980 + MDIO_CMD(MT7531_MDIO_READ))
981 +#define MDIO_CL22_WRITE (MDIO_ST(MT7531_MDIO_ST_CL22) | \
982 + MDIO_CMD(MT7531_MDIO_WRITE))
983 +#define MDIO_CL45_ADDR (MDIO_ST(MT7531_MDIO_ST_CL45) | \
984 + MDIO_CMD(MT7531_MDIO_ADDR))
985 +#define MDIO_CL45_READ (MDIO_ST(MT7531_MDIO_ST_CL45) | \
986 + MDIO_CMD(MT7531_MDIO_READ))
987 +#define MDIO_CL45_WRITE (MDIO_ST(MT7531_MDIO_ST_CL45) | \
988 + MDIO_CMD(MT7531_MDIO_WRITE))
989 +
990 +#define MT7531_CLKGEN_CTRL 0x7500
991 +#define CLK_SKEW_OUT(x) (((x) & 0x3) << 8)
992 +#define CLK_SKEW_OUT_MASK (0x3 << 8)
993 +#define CLK_SKEW_IN(x) (((x) & 0x3) << 6)
994 +#define CLK_SKEW_IN_MASK (0x3 << 6)
995 +#define RXCLK_NO_DELAY BIT(5)
996 +#define TXCLK_NO_REVERSE BIT(4)
997 +#define GP_MODE(x) (((x) & 0x3) << 1)
998 +#define GP_MODE_MASK (0x3 << 1)
999 +#define GP_CLK_EN BIT(0)
1000 +
1001 +#define PHY_DEV1F 0x1f
1002 +#define MT7531_PHY_DEV1F_REG_403 0x403
1003 +
1004 +#define MT7531_PHY_EN_BYPASS_MODE BIT(4)
1005 +#define MT7531_PHY_POWER_OFF BIT(5)
1006 +
1007 +enum mt7531_gp_mode {
1008 + MT7531_GP_MODE_RGMII = 0,
1009 + MT7531_GP_MODE_MII = 1,
1010 + MT7531_GP_MODE_REV_MII = 2
1011 +};
1012 +
1013 +enum mt7531_clk_skew {
1014 + MT7531_CLK_SKEW_NO_CHG = 0,
1015 + MT7531_CLK_SKEW_DLY_100PPS = 1,
1016 + MT7531_CLK_SKEW_DLY_200PPS = 2,
1017 + MT7531_CLK_SKEW_REVERSE = 3,
1018 +};
1019 +
1020 /* Register for hw trap status */
1021 #define MT7530_HWTRAP 0x7800
1022 #define HWTRAP_XTAL_MASK (BIT(10) | BIT(9))
1023 @@ -271,6 +384,11 @@ enum mt7530_vlan_port_attr {
1024 #define HWTRAP_XTAL_40MHZ (BIT(10))
1025 #define HWTRAP_XTAL_20MHZ (BIT(9))
1026
1027 +#define MT7531_HWTRAP 0x7800
1028 +#define HWTRAP_XTAL_FSEL_MASK BIT(7)
1029 +#define HWTRAP_XTAL_FSEL_25MHZ BIT(7)
1030 +#define HWTRAP_XTAL_FSEL_40MHZ 0
1031 +
1032 /* Register for hw trap modification */
1033 #define MT7530_MHWTRAP 0x7804
1034 #define MHWTRAP_PHY0_SEL BIT(20)
1035 @@ -285,14 +403,34 @@ enum mt7530_vlan_port_attr {
1036 #define MT7530_TOP_SIG_CTRL 0x7808
1037 #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16))
1038
1039 +#define MT7531_TOP_SIG_SR 0x780c
1040 +#define PAD_DUAL_SGMII_EN BIT(1)
1041 +
1042 #define MT7530_IO_DRV_CR 0x7810
1043 #define P5_IO_CLK_DRV(x) ((x) & 0x3)
1044 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4)
1045
1046 +#define MT7531_PLLGP_EN 0x7820
1047 +#define EN_COREPLL BIT(2)
1048 +#define SW_CLKSW BIT(1)
1049 +#define SW_PLLGP BIT(0)
1050 +
1051 +#define MT7531_PLLGP_CR0 0x78a8
1052 +#define RG_COREPLL_EN BIT(22)
1053 +#define RG_COREPLL_POSDIV_S 23
1054 +#define RG_COREPLL_POSDIV_M 0x3800000
1055 +#define RG_COREPLL_SDM_PCW_S 1
1056 +#define RG_COREPLL_SDM_PCW_M 0x3ffffe
1057 +#define RG_COREPLL_SDM_PCW_CHG BIT(0)
1058 +
1059 #define MT7530_P6ECR 0x7830
1060 #define P6_INTF_MODE_MASK 0x3
1061 #define P6_INTF_MODE(x) ((x) & 0x3)
1062
1063 +/* RGMII and SGMII PLL clock */
1064 +#define MT7531_ANA_PLLGP_CR2 0x78b0
1065 +#define MT7531_ANA_PLLGP_CR5 0x78bc
1066 +
1067 /* Registers for TRGMII on the both side */
1068 #define MT7530_TRGMII_RCK_CTRL 0x7a00
1069 #define RX_RST BIT(31)
1070 @@ -335,6 +473,9 @@ enum mt7530_vlan_port_attr {
1071 #define CHIP_NAME_SHIFT 16
1072 #define MT7530_ID 0x7530
1073
1074 +#define MT7531_CREV 0x781C
1075 +#define MT7531_ID 0x7531
1076 +
1077 /* Registers for core PLL access through mmd indirect */
1078 #define CORE_PLL_GROUP2 0x401
1079 #define RG_SYSPLL_EN_NORMAL BIT(15)
1080 @@ -458,6 +599,8 @@ static const char *p5_intf_modes(unsigne
1081 * port
1082 * @mac_setup: Holding the way setting up the PHY attribute for a
1083 * certain MAC port
1084 + * @port_an_restart Holding the way restarting 802.3z BaseX autonegotiation
1085 + * for a certain MAC port
1086 */
1087 struct mt753x_info {
1088 enum mt753x_id id;
1089 @@ -471,6 +614,7 @@ struct mt753x_info {
1090 const struct phylink_link_state *state);
1091 int (*mac_setup)(struct dsa_switch *ds, int port, unsigned int mode,
1092 const struct phylink_link_state *state);
1093 + void (*port_an_restart)(struct dsa_switch *ds, int port);
1094 };
1095
1096 /* struct mt7530_priv - This is the main data structure for holding the state
OpenWrt Source Repository