Revert "mediatek: backport mt7622 dts fix for mt7531 switch id to 6.1"
[openwrt/openwrt.git] / target / linux / realtek / dts-5.15 / rtl8382_panasonic_m16eg-pn28160k.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "rtl838x.dtsi"
4 #include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi"
5
6 #include <dt-bindings/interrupt-controller/irq.h>
7
8 / {
9 compatible = "panasonic,m16eg-pn28160k", "realtek,rtl8382-soc";
10 model = "Panasonic Switch-M16eG PN28160K";
11
12 aliases {
13 led-boot = &led_status_eco_green;
14 led-failsafe = &led_status_eco_amber;
15 led-running = &led_status_eco_green;
16 led-upgrade = &led_status_eco_green;
17 };
18
19 /*
20 * sfp0/1 are "combo" port with each TP port (23/24), and they are
21 * connected to the RTL8218FB. Currently, there is no support for
22 * the chip and only TP ports work by the RTL8218D support.
23 */
24 sfp0: sfp-p23 {
25 compatible = "sff,sfp";
26 i2c-bus = <&i2c0>;
27 tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
28 tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
29 mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
30 los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
31 };
32
33 sfp1: sfp-p24 {
34 compatible = "sff,sfp";
35 i2c-bus = <&i2c1>;
36 tx-fault-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
37 tx-disable-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
38 mod-def0-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
39 los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
40 };
41 };
42
43 &leds {
44 led_status_eco_amber: led-5 {
45 gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
46 color = <LED_COLOR_ID_AMBER>;
47 function = LED_FUNCTION_STATUS;
48 function-enumerator = <1>;
49 };
50
51 led_status_eco_green: led-6 {
52 gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
53 color = <LED_COLOR_ID_GREEN>;
54 function = LED_FUNCTION_STATUS;
55 function-enumerator = <2>;
56 };
57 };
58
59 &i2c_gpio_0 {
60 scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
61 sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
62 };
63
64 &i2c_gpio_1 {
65 scl-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
66 sda-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
67 };
68
69 &gpio2 {
70 interrupt-controller;
71 #interrupt-cells = <2>;
72 interrupt-parent = <&gpio0>;
73 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
74
75 /*
76 * GPIO12 (IO1_4): RTL8218FB
77 *
78 * This GPIO pin should be specified as "reset-gpio" in mdio node, but
79 * RTL8218FB phy won't be configured on RTL8218D support in the current
80 * phy driver. So, ethernet ports on the phy will be broken after hard-
81 * resetting.
82 * (RTL8218FB phy will be detected as RTL8218D by the phy driver)
83 * At the moment, configure this GPIO pin as gpio-hog to avoid breaking
84 * by resetting.
85 */
86 ext_switch_reset {
87 gpio-hog;
88 gpios = <12 GPIO_ACTIVE_HIGH>;
89 output-high;
90 line-name = "ext-switch-reset";
91 };
92 };
93
94 &i2c_switch {
95 i2c0: i2c@0 {
96 #address-cells = <1>;
97 #size-cells = <0>;
98 reg = <0>;
99 };
100
101 i2c1: i2c@1 {
102 #address-cells = <1>;
103 #size-cells = <0>;
104 reg = <1>;
105 };
106 };
107
108 &ethernet0 {
109 mdio-bus {
110 compatible = "realtek,rtl838x-mdio";
111 #address-cells = <1>;
112 #size-cells = <0>;
113
114 INTERNAL_PHY(8)
115 INTERNAL_PHY(9)
116 INTERNAL_PHY(10)
117 INTERNAL_PHY(11)
118 INTERNAL_PHY(12)
119 INTERNAL_PHY(13)
120 INTERNAL_PHY(14)
121 INTERNAL_PHY(15)
122
123 /* RTL8218FB */
124 EXTERNAL_PHY(16)
125 EXTERNAL_PHY(17)
126 EXTERNAL_PHY(18)
127 EXTERNAL_PHY(19)
128 EXTERNAL_PHY(20)
129 EXTERNAL_PHY(21)
130 EXTERNAL_PHY(22)
131 EXTERNAL_PHY(23)
132 };
133 };
134
135 &switch0 {
136 ports {
137 #address-cells = <1>;
138 #size-cells = <0>;
139
140 SWITCH_PORT(8, 1, internal)
141 SWITCH_PORT(9, 2, internal)
142 SWITCH_PORT(10, 3, internal)
143 SWITCH_PORT(11, 4, internal)
144 SWITCH_PORT(12, 5, internal)
145 SWITCH_PORT(13, 6, internal)
146 SWITCH_PORT(14, 7, internal)
147 SWITCH_PORT(15, 8, internal)
148
149 SWITCH_PORT(16, 9, qsgmii)
150 SWITCH_PORT(17, 10, qsgmii)
151 SWITCH_PORT(18, 11, qsgmii)
152 SWITCH_PORT(19, 12, qsgmii)
153 SWITCH_PORT(20, 13, qsgmii)
154 SWITCH_PORT(21, 14, qsgmii)
155 SWITCH_PORT(22, 15, qsgmii)
156 SWITCH_PORT(23, 16, qsgmii)
157
158 port@28 {
159 ethernet = <&ethernet0>;
160 reg = <28>;
161 phy-mode = "internal";
162
163 fixed-link {
164 speed = <1000>;
165 full-duplex;
166 };
167 };
168 };
169 };