target/linux/realtek/dts-5.15/rtl8393_tplink_sg2452p-v4.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "rtl839x.dtsi"
   4
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/leds/common.h>
   8
   9 / {
  10         compatible = "tplink,sg2452p-v4", "realtek,rtl8393-soc";
  11         model = "TP-Link SG2452P v4";
  12
  13         memory@0 {
  14                 device_type = "memory";
  15                 reg = <0x0 0x10000000>;
  16         };
  17
  18         aliases {
  19                 led-boot = &led_sys;
  20                 led-failsafe = &led_sys;
  21                 led-running = &led_sys;
  22                 led-upgrade = &led_sys;
  23                 label-mac-device = &ethernet0;
  24         };
  25
  26         chosen {
  27                 stdout-path = "serial0:38400n8";
  28         };
  29
  30         keys {
  31                 compatible = "gpio-keys";
  32
  33                 reset {
  34                         label = "reset";
  35                         gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
  36                         linux,code = <KEY_RESTART>;
  37                 };
  38
  39                 speed {
  40                         label = "speed";
  41                         gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
  42                         linux,code = <BTN_0>;
  43                 };
  44         };
  45
  46         gpio_fan_sys {
  47                 compatible = "gpio-fan";
  48                 alarm-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
  49         };
  50
  51         gpio_fan_psu_1 {
  52                 pinctrl-names = "default";
  53                 pinctrl-0 = <&disable_jtag>;
  54                 compatible = "gpio-fan";
  55
  56                 alarm-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
  57                 gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
  58                 /* the actual speeds (rpm) are unknown, just use dummy values */
  59                 gpio-fan,speed-map = <1 0>, <2 1>;
  60                 #cooling-cells = <2>;
  61         };
  62
  63         gpio_fan_psu_2 {
  64                 /* This fan runs in parallel to PSU1 fan, but has a separate
  65                  * alarm GPIO. This is not (yet) supported by the gpio-fan driver,
  66                  * so a separate instance is added
  67                  */
  68                 compatible = "gpio-fan";
  69                 alarm-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
  70         };
  71
  72         leds {
  73                 pinctrl-names = "default";
  74                 compatible = "gpio-leds";
  75
  76                 led-0 {
  77                         gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
  78                         color = <LED_COLOR_ID_GREEN>;
  79                         function = LED_FUNCTION_INDICATOR;
  80                 };
  81
  82                 led-1 {
  83                         gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
  84                         color = <LED_COLOR_ID_GREEN>;
  85                         function = LED_FUNCTION_INDICATOR;
  86                 };
  87
  88                 led_sys: led-2 {
  89                         gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
  90                         color = <LED_COLOR_ID_GREEN>;
  91                         function = LED_FUNCTION_STATUS;
  92                 };
  93
  94                 led-3 {
  95                         gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
  96                         color = <LED_COLOR_ID_GREEN>;
  97                         function = LED_FUNCTION_STATUS;
  98                 };
  99
 100                 led-4 {
 101                         gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
 102                         color = <LED_COLOR_ID_AMBER>;
 103                         function = "fault-fan";
 104                 };
 105
 106                 led-5 {
 107                         gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
 108                         color = <LED_COLOR_ID_GREEN>;
 109                         function = "alarm-poe";
 110                 };
 111         };
 112
 113         i2c-gpio-0 {
 114                 compatible = "i2c-gpio";
 115                 sda-gpios = <&gpio0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 116                 scl-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 117                 i2c-gpio,delay-us = <2>;
 118                 #address-cells = <1>;
 119                 #size-cells = <0>;
 120
 121                 /* LAN9 - LAN12 */
 122                 tps23861@5 {
 123                         compatible = "ti,tps23861";
 124                         reg = <0x05>;
 125                 };
 126
 127                 /* LAN17 - LAN20 */
 128                 tps23861@6 {
 129                         compatible = "ti,tps23861";
 130                         reg = <0x06>;
 131                 };
 132
 133                 /* LAN45 - LAN48 */
 134                 tps23861@9 {
 135                         compatible = "ti,tps23861";
 136                         reg = <0x09>;
 137                 };
 138
 139                 /* LAN37 - LAN40 */
 140                 tps23861@a {
 141                         compatible = "ti,tps23861";
 142                         reg = <0x0a>;
 143                 };
 144
 145                 /* LAN1 - LAN4 */
 146                 tps23861@14 {
 147                         compatible = "ti,tps23861";
 148                         reg = <0x14>;
 149                 };
 150
 151                 /* LAN25 - LAN28 */
 152                 tps23861@24 {
 153                         compatible = "ti,tps23861";
 154                         reg = <0x24>;
 155                 };
 156
 157                 /* LAN33 - LAN 36 */
 158                 tps23861@25 {
 159                         compatible = "ti,tps23861";
 160                         reg = <0x25>;
 161                 };
 162
 163                 /* LAN41 - LAN44 */
 164                 tps23861@26 {
 165                         compatible = "ti,tps23861";
 166                         reg = <0x26>;
 167                 };
 168
 169                 /* LAN13 - LAN16 */
 170                 tps23861@29 {
 171                         compatible = "ti,tps23861";
 172                         reg = <0x29>;
 173                 };
 174
 175                 /* LAN29 - LAN32 */
 176                 tps23861@2c {
 177                         compatible = "ti,tps23861";
 178                         reg = <0x2c>;
 179                 };
 180
 181                 /* LAN5 - LAN8 */
 182                 tps23861@48 {
 183                         compatible = "ti,tps23861";
 184                         reg = <0x48>;
 185                 };
 186
 187                 /* LAN21 - LAN24 */
 188                 tps23861@49 {
 189                         compatible = "ti,tps23861";
 190                         reg = <0x49>;
 191                 };
 192         };
 193
 194         gpio-restart {
 195                 compatible = "gpio-restart";
 196                 gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
 197         };
 198 };
 199
 200 &gpio0 {
 201         poe-enable {
 202                 gpio-hog;
 203                 gpios = <23 GPIO_ACTIVE_HIGH>;
 204                 output-high;
 205                 line-name = "poe-enable";
 206         };
 207 };
 208
 209 &spi0 {
 210         status = "okay";
 211         flash@0 {
 212                 compatible = "jedec,spi-nor";
 213                 reg = <0>;
 214                 spi-max-frequency = <10000000>;
 215
 216                 partitions {
 217                         compatible = "fixed-partitions";
 218                         #address-cells = <1>;
 219                         #size-cells = <1>;
 220
 221                         partition@0 {
 222                                 label = "u-boot";
 223                                 reg = <0x0 0xe0000>;
 224                                 read-only;
 225                         };
 226                         partition@e0000 {
 227                                 label = "u-boot-env";
 228                                 reg = <0xe0000 0x20000>;
 229                         };
 230
 231                         /* We use the "sys", "usrimg1" and "usrimg2" partitions
 232                          *  as firmware since the kernel needs to be in "sys", but the
 233                          *  partition is too small to hold the "rootfs" as well.
 234                          *  The original partition map contains:
 235                          *
 236                          *   partition@100000 {
 237                          *       label = "sys";
 238                          *       reg = <0x100000 0x600000>;
 239                          *   };
 240                          *   partition@700000 {
 241                          *       label = "usrimg1";
 242                          *       reg = <0x700000 0xa00000>;
 243                          *   };
 244                          *   partition@1100000 {
 245                          *       label = "usrimg2";
 246                          *       reg = <0x1100000 0xa00000>;
 247                          *   };
 248                          */
 249
 250                         partition@100000 {
 251                                 label = "firmware";
 252                                 reg = <0x100000 0x1a00000>;
 253                         };
 254                         partition@1b00000 {
 255                                 label = "usrappfs";
 256                                 reg = <0x1b00000 0x400000>;
 257                         };
 258                         partition@1f00000 {
 259                                 label = "para";
 260                                 reg = <0x1f00000 0x100000>;
 261                                 read-only;
 262
 263                                 nvmem-layout {
 264                                         compatible = "fixed-layout";
 265                                         #address-cells = <1>;
 266                                         #size-cells = <1>;
 267
 268                                         factory_macaddr: macaddr@fdff4 {
 269                                                 reg = <0xfdff4 0x6>;
 270                                         };
 271                                 };
 272                         };
 273                 };
 274         };
 275 };
 276
 277 &ethernet0 {
 278         nvmem-cells = <&factory_macaddr>;
 279         nvmem-cell-names = "mac-address";
 280
 281         mdio: mdio-bus {
 282                 compatible = "realtek,rtl838x-mdio";
 283                 #address-cells = <1>;
 284                 #size-cells = <0>;
 285
 286                 /* External phy RTL8218B #1 */
 287                 EXTERNAL_PHY(0)
 288                 EXTERNAL_PHY(1)
 289                 EXTERNAL_PHY(2)
 290                 EXTERNAL_PHY(3)
 291                 EXTERNAL_PHY(4)
 292                 EXTERNAL_PHY(5)
 293                 EXTERNAL_PHY(6)
 294                 EXTERNAL_PHY(7)
 295
 296                 /* External phy RTL8218B #2 */
 297                 EXTERNAL_PHY(8)
 298                 EXTERNAL_PHY(9)
 299                 EXTERNAL_PHY(10)
 300                 EXTERNAL_PHY(11)
 301                 EXTERNAL_PHY(12)
 302                 EXTERNAL_PHY(13)
 303                 EXTERNAL_PHY(14)
 304                 EXTERNAL_PHY(15)
 305
 306                 /* External phy RTL8218B #3 */
 307                 EXTERNAL_PHY(16)
 308                 EXTERNAL_PHY(17)
 309                 EXTERNAL_PHY(18)
 310                 EXTERNAL_PHY(19)
 311                 EXTERNAL_PHY(20)
 312                 EXTERNAL_PHY(21)
 313                 EXTERNAL_PHY(22)
 314                 EXTERNAL_PHY(23)
 315
 316                 /* External phy RTL8218B #4 */
 317                 EXTERNAL_PHY(24)
 318                 EXTERNAL_PHY(25)
 319                 EXTERNAL_PHY(26)
 320                 EXTERNAL_PHY(27)
 321                 EXTERNAL_PHY(28)
 322                 EXTERNAL_PHY(29)
 323                 EXTERNAL_PHY(30)
 324                 EXTERNAL_PHY(31)
 325
 326                 /* External phy RTL8218B #5 */
 327                 EXTERNAL_PHY(32)
 328                 EXTERNAL_PHY(33)
 329                 EXTERNAL_PHY(34)
 330                 EXTERNAL_PHY(35)
 331                 EXTERNAL_PHY(36)
 332                 EXTERNAL_PHY(37)
 333                 EXTERNAL_PHY(38)
 334                 EXTERNAL_PHY(39)
 335
 336                 /* External phy RTL8218B #6 */
 337                 EXTERNAL_PHY(40)
 338                 EXTERNAL_PHY(41)
 339                 EXTERNAL_PHY(42)
 340                 EXTERNAL_PHY(43)
 341                 EXTERNAL_PHY(44)
 342                 EXTERNAL_PHY(45)
 343                 EXTERNAL_PHY(46)
 344                 EXTERNAL_PHY(47)
 345         };
 346 };
 347
 348 &switch0 {
 349         ports {
 350                 #address-cells = <1>;
 351                 #size-cells = <0>;
 352
 353                 SWITCH_PORT(0, 01, qsgmii)
 354                 SWITCH_PORT(1, 02, qsgmii)
 355                 SWITCH_PORT(2, 03, qsgmii)
 356                 SWITCH_PORT(3, 04, qsgmii)
 357                 SWITCH_PORT(4, 05, qsgmii)
 358                 SWITCH_PORT(5, 06, qsgmii)
 359                 SWITCH_PORT(6, 07, qsgmii)
 360                 SWITCH_PORT(7, 08, qsgmii)
 361
 362                 SWITCH_PORT(8, 09, qsgmii)
 363                 SWITCH_PORT(9, 10, qsgmii)
 364                 SWITCH_PORT(10, 11, qsgmii)
 365                 SWITCH_PORT(11, 12, qsgmii)
 366                 SWITCH_PORT(12, 13, qsgmii)
 367                 SWITCH_PORT(13, 14, qsgmii)
 368                 SWITCH_PORT(14, 15, qsgmii)
 369                 SWITCH_PORT(15, 16, qsgmii)
 370
 371                 SWITCH_PORT(16, 17, qsgmii)
 372                 SWITCH_PORT(17, 18, qsgmii)
 373                 SWITCH_PORT(18, 19, qsgmii)
 374                 SWITCH_PORT(19, 20, qsgmii)
 375                 SWITCH_PORT(20, 21, qsgmii)
 376                 SWITCH_PORT(21, 22, qsgmii)
 377                 SWITCH_PORT(22, 23, qsgmii)
 378                 SWITCH_PORT(23, 24, qsgmii)
 379
 380                 SWITCH_PORT(24, 25, qsgmii)
 381                 SWITCH_PORT(25, 26, qsgmii)
 382                 SWITCH_PORT(26, 27, qsgmii)
 383                 SWITCH_PORT(27, 28, qsgmii)
 384                 SWITCH_PORT(28, 29, qsgmii)
 385                 SWITCH_PORT(29, 30, qsgmii)
 386                 SWITCH_PORT(30, 31, qsgmii)
 387                 SWITCH_PORT(31, 32, qsgmii)
 388
 389                 SWITCH_PORT(32, 33, qsgmii)
 390                 SWITCH_PORT(33, 34, qsgmii)
 391                 SWITCH_PORT(34, 35, qsgmii)
 392                 SWITCH_PORT(35, 36, qsgmii)
 393                 SWITCH_PORT(36, 37, qsgmii)
 394                 SWITCH_PORT(37, 38, qsgmii)
 395                 SWITCH_PORT(38, 39, qsgmii)
 396                 SWITCH_PORT(39, 40, qsgmii)
 397
 398                 SWITCH_PORT(40, 41, qsgmii)
 399                 SWITCH_PORT(41, 42, qsgmii)
 400                 SWITCH_PORT(42, 43, qsgmii)
 401                 SWITCH_PORT(43, 44, qsgmii)
 402                 SWITCH_PORT(44, 45, qsgmii)
 403                 SWITCH_PORT(45, 46, qsgmii)
 404                 SWITCH_PORT(46, 47, qsgmii)
 405                 SWITCH_PORT(47, 48, qsgmii)
 406
 407                 /* CPU-Port */
 408                 port@52 {
 409                         ethernet = <&ethernet0>;
 410                         reg = <52>;
 411                         phy-mode = "internal";
 412
 413                         fixed-link {
 414                                 speed = <1000>;
 415                                 full-duplex;
 416                         };
 417                 };
 418         };
 419 };