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kernel: bump 6.1 to 6.1.89
[openwrt/openwrt.git] / target / linux / realtek / files-5.10 / drivers / net / dsa / rtl83xx / common.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/of_mdio.h>
4 #include <linux/of_platform.h>
5 #include <net/arp.h>
6 #include <net/nexthop.h>
7 #include <net/neighbour.h>
8 #include <net/netevent.h>
9 #include <linux/inetdevice.h>
10 #include <linux/rhashtable.h>
11 #include <linux/of_net.h>
12
13 #include <asm/mach-rtl838x/mach-rtl83xx.h>
14 #include "rtl83xx.h"
15
16 extern struct rtl83xx_soc_info soc_info;
17
18 extern const struct rtl838x_reg rtl838x_reg;
19 extern const struct rtl838x_reg rtl839x_reg;
20 extern const struct rtl838x_reg rtl930x_reg;
21 extern const struct rtl838x_reg rtl931x_reg;
22
23 extern const struct dsa_switch_ops rtl83xx_switch_ops;
24 extern const struct dsa_switch_ops rtl930x_switch_ops;
25
26 DEFINE_MUTEX(smi_lock);
27
28 int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port)
29 {
30 u32 msti = 0;
31 u32 port_state[4];
32 int index, bit;
33 int pos = port;
34 int n = priv->port_width << 1;
35
36 /* Ports above or equal CPU port can never be configured */
37 if (port >= priv->cpu_port)
38 return -1;
39
40 mutex_lock(&priv->reg_mutex);
41
42 /* For the RTL839x and following, the bits are left-aligned in the 64/128 bit field */
43 if (priv->family_id == RTL8390_FAMILY_ID)
44 pos += 12;
45 if (priv->family_id == RTL9300_FAMILY_ID)
46 pos += 3;
47 if (priv->family_id == RTL9310_FAMILY_ID)
48 pos += 8;
49
50 index = n - (pos >> 4) - 1;
51 bit = (pos << 1) % 32;
52
53 priv->r->stp_get(priv, msti, port_state);
54
55 mutex_unlock(&priv->reg_mutex);
56
57 return (port_state[index] >> bit) & 3;
58 }
59
60 static struct table_reg rtl838x_tbl_regs[] = {
61 TBL_DESC(0x6900, 0x6908, 3, 15, 13, 1), // RTL8380_TBL_L2
62 TBL_DESC(0x6914, 0x6918, 18, 14, 12, 1), // RTL8380_TBL_0
63 TBL_DESC(0xA4C8, 0xA4CC, 6, 14, 12, 1), // RTL8380_TBL_1
64
65 TBL_DESC(0x1180, 0x1184, 3, 16, 14, 0), // RTL8390_TBL_L2
66 TBL_DESC(0x1190, 0x1194, 17, 15, 12, 0), // RTL8390_TBL_0
67 TBL_DESC(0x6B80, 0x6B84, 4, 14, 12, 0), // RTL8390_TBL_1
68 TBL_DESC(0x611C, 0x6120, 9, 8, 6, 0), // RTL8390_TBL_2
69
70 TBL_DESC(0xB320, 0xB334, 3, 18, 16, 0), // RTL9300_TBL_L2
71 TBL_DESC(0xB340, 0xB344, 19, 16, 12, 0), // RTL9300_TBL_0
72 TBL_DESC(0xB3A0, 0xB3A4, 20, 16, 13, 0), // RTL9300_TBL_1
73 TBL_DESC(0xCE04, 0xCE08, 6, 14, 12, 0), // RTL9300_TBL_2
74 TBL_DESC(0xD600, 0xD604, 30, 7, 6, 0), // RTL9300_TBL_HSB
75 TBL_DESC(0x7880, 0x7884, 22, 9, 8, 0), // RTL9300_TBL_HSA
76
77 TBL_DESC(0x8500, 0x8508, 8, 19, 15, 0), // RTL9310_TBL_0
78 TBL_DESC(0x40C0, 0x40C4, 22, 16, 14, 0), // RTL9310_TBL_1
79 TBL_DESC(0x8528, 0x852C, 6, 18, 14, 0), // RTL9310_TBL_2
80 TBL_DESC(0x0200, 0x0204, 9, 15, 12, 0), // RTL9310_TBL_3
81 TBL_DESC(0x20dc, 0x20e0, 29, 7, 6, 0), // RTL9310_TBL_4
82 TBL_DESC(0x7e1c, 0x7e20, 53, 8, 6, 0), // RTL9310_TBL_5
83 };
84
85 void rtl_table_init(void)
86 {
87 int i;
88
89 for (i = 0; i < RTL_TBL_END; i++)
90 mutex_init(&rtl838x_tbl_regs[i].lock);
91 }
92
93 /*
94 * Request access to table t in table access register r
95 * Returns a handle to a lock for that table
96 */
97 struct table_reg *rtl_table_get(rtl838x_tbl_reg_t r, int t)
98 {
99 if (r >= RTL_TBL_END)
100 return NULL;
101
102 if (t >= BIT(rtl838x_tbl_regs[r].c_bit-rtl838x_tbl_regs[r].t_bit))
103 return NULL;
104
105 mutex_lock(&rtl838x_tbl_regs[r].lock);
106 rtl838x_tbl_regs[r].tbl = t;
107
108 return &rtl838x_tbl_regs[r];
109 }
110
111 /*
112 * Release a table r, unlock the corresponding lock
113 */
114 void rtl_table_release(struct table_reg *r)
115 {
116 if (!r)
117 return;
118
119 // pr_info("Unlocking %08x\n", (u32)r);
120 mutex_unlock(&r->lock);
121 // pr_info("Unlock done\n");
122 }
123
124 /*
125 * Reads table index idx into the data registers of the table
126 */
127 void rtl_table_read(struct table_reg *r, int idx)
128 {
129 u32 cmd = r->rmode ? BIT(r->c_bit) : 0;
130
131 cmd |= BIT(r->c_bit + 1) | (r->tbl << r->t_bit) | (idx & (BIT(r->t_bit) - 1));
132 sw_w32(cmd, r->addr);
133 do { } while (sw_r32(r->addr) & BIT(r->c_bit + 1));
134 }
135
136 /*
137 * Writes the content of the table data registers into the table at index idx
138 */
139 void rtl_table_write(struct table_reg *r, int idx)
140 {
141 u32 cmd = r->rmode ? 0 : BIT(r->c_bit);
142
143 cmd |= BIT(r->c_bit + 1) | (r->tbl << r->t_bit) | (idx & (BIT(r->t_bit) - 1));
144 sw_w32(cmd, r->addr);
145 do { } while (sw_r32(r->addr) & BIT(r->c_bit + 1));
146 }
147
148 /*
149 * Returns the address of the ith data register of table register r
150 * the address is relative to the beginning of the Switch-IO block at 0xbb000000
151 */
152 inline u16 rtl_table_data(struct table_reg *r, int i)
153 {
154 if (i >= r->max_data)
155 i = r->max_data - 1;
156 return r->data + i * 4;
157 }
158
159 inline u32 rtl_table_data_r(struct table_reg *r, int i)
160 {
161 return sw_r32(rtl_table_data(r, i));
162 }
163
164 inline void rtl_table_data_w(struct table_reg *r, u32 v, int i)
165 {
166 sw_w32(v, rtl_table_data(r, i));
167 }
168
169 /* Port register accessor functions for the RTL838x and RTL930X SoCs */
170 void rtl838x_mask_port_reg(u64 clear, u64 set, int reg)
171 {
172 sw_w32_mask((u32)clear, (u32)set, reg);
173 }
174
175 void rtl838x_set_port_reg(u64 set, int reg)
176 {
177 sw_w32((u32)set, reg);
178 }
179
180 u64 rtl838x_get_port_reg(int reg)
181 {
182 return ((u64) sw_r32(reg));
183 }
184
185 /* Port register accessor functions for the RTL839x and RTL931X SoCs */
186 void rtl839x_mask_port_reg_be(u64 clear, u64 set, int reg)
187 {
188 sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg);
189 sw_w32_mask((u32)(clear & 0xffffffff), (u32)(set & 0xffffffff), reg + 4);
190 }
191
192 u64 rtl839x_get_port_reg_be(int reg)
193 {
194 u64 v = sw_r32(reg);
195
196 v <<= 32;
197 v |= sw_r32(reg + 4);
198 return v;
199 }
200
201 void rtl839x_set_port_reg_be(u64 set, int reg)
202 {
203 sw_w32(set >> 32, reg);
204 sw_w32(set & 0xffffffff, reg + 4);
205 }
206
207 void rtl839x_mask_port_reg_le(u64 clear, u64 set, int reg)
208 {
209 sw_w32_mask((u32)clear, (u32)set, reg);
210 sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg + 4);
211 }
212
213 void rtl839x_set_port_reg_le(u64 set, int reg)
214 {
215 sw_w32(set, reg);
216 sw_w32(set >> 32, reg + 4);
217 }
218
219 u64 rtl839x_get_port_reg_le(int reg)
220 {
221 u64 v = sw_r32(reg + 4);
222
223 v <<= 32;
224 v |= sw_r32(reg);
225 return v;
226 }
227
228 int read_phy(u32 port, u32 page, u32 reg, u32 *val)
229 {
230 switch (soc_info.family) {
231 case RTL8380_FAMILY_ID:
232 return rtl838x_read_phy(port, page, reg, val);
233 case RTL8390_FAMILY_ID:
234 return rtl839x_read_phy(port, page, reg, val);
235 case RTL9300_FAMILY_ID:
236 return rtl930x_read_phy(port, page, reg, val);
237 case RTL9310_FAMILY_ID:
238 return rtl931x_read_phy(port, page, reg, val);
239 }
240 return -1;
241 }
242
243 int write_phy(u32 port, u32 page, u32 reg, u32 val)
244 {
245 switch (soc_info.family) {
246 case RTL8380_FAMILY_ID:
247 return rtl838x_write_phy(port, page, reg, val);
248 case RTL8390_FAMILY_ID:
249 return rtl839x_write_phy(port, page, reg, val);
250 case RTL9300_FAMILY_ID:
251 return rtl930x_write_phy(port, page, reg, val);
252 case RTL9310_FAMILY_ID:
253 return rtl931x_write_phy(port, page, reg, val);
254 }
255 return -1;
256 }
257
258 static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
259 {
260 struct device *dev = priv->dev;
261 struct device_node *dn, *phy_node, *mii_np = dev->of_node;
262 struct mii_bus *bus;
263 int ret;
264 u32 pn;
265
266 pr_debug("In %s\n", __func__);
267 mii_np = of_find_compatible_node(NULL, NULL, "realtek,rtl838x-mdio");
268 if (mii_np) {
269 pr_debug("Found compatible MDIO node!\n");
270 } else {
271 dev_err(priv->dev, "no %s child node found", "mdio-bus");
272 return -ENODEV;
273 }
274
275 priv->mii_bus = of_mdio_find_bus(mii_np);
276 if (!priv->mii_bus) {
277 pr_debug("Deferring probe of mdio bus\n");
278 return -EPROBE_DEFER;
279 }
280 if (!of_device_is_available(mii_np))
281 ret = -ENODEV;
282
283 bus = devm_mdiobus_alloc(priv->ds->dev);
284 if (!bus)
285 return -ENOMEM;
286
287 bus->name = "rtl838x slave mii";
288
289 /*
290 * Since the NIC driver is loaded first, we can use the mdio rw functions
291 * assigned there.
292 */
293 bus->read = priv->mii_bus->read;
294 bus->write = priv->mii_bus->write;
295 bus->read_paged = priv->mii_bus->read_paged;
296 bus->write_paged = priv->mii_bus->write_paged;
297 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", bus->name, dev->id);
298
299 bus->parent = dev;
300 priv->ds->slave_mii_bus = bus;
301 priv->ds->slave_mii_bus->priv = priv->mii_bus->priv;
302 priv->ds->slave_mii_bus->access_capabilities = priv->mii_bus->access_capabilities;
303
304 ret = mdiobus_register(priv->ds->slave_mii_bus);
305 if (ret && mii_np) {
306 of_node_put(dn);
307 return ret;
308 }
309
310 dn = of_find_compatible_node(NULL, NULL, "realtek,rtl83xx-switch");
311 if (!dn) {
312 dev_err(priv->dev, "No RTL switch node in DTS\n");
313 return -ENODEV;
314 }
315
316 for_each_node_by_name(dn, "port") {
317 phy_interface_t interface;
318 u32 led_set;
319
320 if (of_property_read_u32(dn, "reg", &pn))
321 continue;
322
323 pr_info("%s found port %d\n", __func__, pn);
324 phy_node = of_parse_phandle(dn, "phy-handle", 0);
325 if (!phy_node) {
326 if (pn != priv->cpu_port)
327 dev_err(priv->dev, "Port node %d misses phy-handle\n", pn);
328 continue;
329 }
330
331 pr_info("%s port %d has phandle\n", __func__, pn);
332 if (of_property_read_u32(phy_node, "sds", &priv->ports[pn].sds_num))
333 priv->ports[pn].sds_num = -1;
334 else {
335 pr_info("%s sds port %d is %d\n", __func__, pn,
336 priv->ports[pn].sds_num);
337 }
338 pr_info("%s port %d has SDS\n", __func__, priv->ports[pn].sds_num);
339
340 if (of_get_phy_mode(dn, &interface))
341 interface = PHY_INTERFACE_MODE_NA;
342 if (interface == PHY_INTERFACE_MODE_HSGMII)
343 priv->ports[pn].is2G5 = true;
344 if (interface == PHY_INTERFACE_MODE_USXGMII)
345 priv->ports[pn].is2G5 = priv->ports[pn].is10G = true;
346 if (interface == PHY_INTERFACE_MODE_10GBASER)
347 priv->ports[pn].is10G = true;
348
349 if (of_property_read_u32(dn, "led-set", &led_set))
350 led_set = 0;
351 priv->ports[pn].led_set = led_set;
352
353 // Check for the integrated SerDes of the RTL8380M first
354 if (of_property_read_bool(phy_node, "phy-is-integrated")
355 && priv->id == 0x8380 && pn >= 24) {
356 pr_debug("----> FÓUND A SERDES\n");
357 priv->ports[pn].phy = PHY_RTL838X_SDS;
358 continue;
359 }
360
361 if (priv->id >= 0x9300) {
362 priv->ports[pn].phy_is_integrated = false;
363 if (of_property_read_bool(phy_node, "phy-is-integrated")) {
364 priv->ports[pn].phy_is_integrated = true;
365 priv->ports[pn].phy = PHY_RTL930X_SDS;
366 }
367 } else {
368 if (of_property_read_bool(phy_node, "phy-is-integrated")
369 && !of_property_read_bool(phy_node, "sfp")) {
370 priv->ports[pn].phy = PHY_RTL8218B_INT;
371 continue;
372 }
373 }
374
375 if (!of_property_read_bool(phy_node, "phy-is-integrated")
376 && of_property_read_bool(phy_node, "sfp")) {
377 priv->ports[pn].phy = PHY_RTL8214FC;
378 continue;
379 }
380
381 if (!of_property_read_bool(phy_node, "phy-is-integrated")
382 && !of_property_read_bool(phy_node, "sfp")) {
383 priv->ports[pn].phy = PHY_RTL8218B_EXT;
384 continue;
385 }
386 }
387
388 /* Disable MAC polling the PHY so that we can start configuration */
389 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
390
391 /* Enable PHY control via SoC */
392 if (priv->family_id == RTL8380_FAMILY_ID) {
393 /* Enable SerDes NWAY and PHY control via SoC */
394 sw_w32_mask(BIT(7), BIT(15), RTL838X_SMI_GLB_CTRL);
395 } else if (priv->family_id == RTL8390_FAMILY_ID) {
396 /* Disable PHY polling via SoC */
397 sw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL);
398 }
399
400 /* Power on fibre ports and reset them if necessary */
401 if (priv->ports[24].phy == PHY_RTL838X_SDS) {
402 pr_debug("Powering on fibre ports & reset\n");
403 rtl8380_sds_power(24, 1);
404 rtl8380_sds_power(26, 1);
405 }
406
407 pr_debug("%s done\n", __func__);
408 return 0;
409 }
410
411 static int __init rtl83xx_get_l2aging(struct rtl838x_switch_priv *priv)
412 {
413 int t = sw_r32(priv->r->l2_ctrl_1);
414
415 t &= priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
416
417 if (priv->family_id == RTL8380_FAMILY_ID)
418 t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */
419 else
420 t = (t * 3) / 5;
421
422 pr_debug("L2 AGING time: %d sec\n", t);
423 pr_debug("Dynamic aging for ports: %x\n", sw_r32(priv->r->l2_port_aging_out));
424 return t;
425 }
426
427 /* Caller must hold priv->reg_mutex */
428 int rtl83xx_lag_add(struct dsa_switch *ds, int group, int port, struct netdev_lag_upper_info *info)
429 {
430 struct rtl838x_switch_priv *priv = ds->priv;
431 int i;
432 u32 algomsk = 0;
433 u32 algoidx = 0;
434
435 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
436 pr_err("%s: Only mode LACP 802.3ad (4) allowed.\n", __func__);
437 return -EINVAL;
438 }
439
440 if (group >= priv->n_lags) {
441 pr_err("%s: LAG %d invalid.\n", __func__, group);
442 return -EINVAL;
443 }
444
445 if (port >= priv->cpu_port) {
446 pr_err("%s: Port %d invalid.\n", __func__, port);
447 return -EINVAL;
448 }
449
450 for (i = 0; i < priv->n_lags; i++) {
451 if (priv->lags_port_members[i] & BIT_ULL(port))
452 break;
453 }
454 if (i != priv->n_lags) {
455 pr_err("%s: Port %d already member of LAG %d.\n", __func__, port, i);
456 return -ENOSPC;
457 }
458 switch(info->hash_type) {
459 case NETDEV_LAG_HASH_L2:
460 algomsk |= TRUNK_DISTRIBUTION_ALGO_DMAC_BIT;
461 algomsk |= TRUNK_DISTRIBUTION_ALGO_SMAC_BIT;
462 break;
463 case NETDEV_LAG_HASH_L23:
464 algomsk |= TRUNK_DISTRIBUTION_ALGO_DMAC_BIT;
465 algomsk |= TRUNK_DISTRIBUTION_ALGO_SMAC_BIT;
466 algomsk |= TRUNK_DISTRIBUTION_ALGO_SIP_BIT; //source ip
467 algomsk |= TRUNK_DISTRIBUTION_ALGO_DIP_BIT; //dest ip
468 algoidx = 1;
469 break;
470 case NETDEV_LAG_HASH_L34:
471 algomsk |= TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT; //sport
472 algomsk |= TRUNK_DISTRIBUTION_ALGO_DST_L4PORT_BIT; //dport
473 algomsk |= TRUNK_DISTRIBUTION_ALGO_SIP_BIT; //source ip
474 algomsk |= TRUNK_DISTRIBUTION_ALGO_DIP_BIT; //dest ip
475 algoidx = 2;
476 break;
477 default:
478 algomsk |= 0x7f;
479 }
480 priv->r->set_distribution_algorithm(group, algoidx, algomsk);
481 priv->r->mask_port_reg_be(0, BIT_ULL(port), priv->r->trk_mbr_ctr(group));
482 priv->lags_port_members[group] |= BIT_ULL(port);
483
484 pr_info("%s: Added port %d to LAG %d. Members now %016llx.\n",
485 __func__, port, group, priv->lags_port_members[group]);
486 return 0;
487 }
488
489 /* Caller must hold priv->reg_mutex */
490 int rtl83xx_lag_del(struct dsa_switch *ds, int group, int port)
491 {
492 struct rtl838x_switch_priv *priv = ds->priv;
493
494 if (group >= priv->n_lags) {
495 pr_err("%s: LAG %d invalid.\n", __func__, group);
496 return -EINVAL;
497 }
498
499 if (port >= priv->cpu_port) {
500 pr_err("%s: Port %d invalid.\n", __func__, port);
501 return -EINVAL;
502 }
503
504 if (!(priv->lags_port_members[group] & BIT_ULL(port))) {
505 pr_err("%s: Port %d not member of LAG %d.\n", __func__, port, group);
506 return -ENOSPC;
507 }
508
509 // 0x7f algo mask all
510 priv->r->mask_port_reg_be(BIT_ULL(port), 0, priv->r->trk_mbr_ctr(group));
511 priv->lags_port_members[group] &= ~BIT_ULL(port);
512
513 pr_info("%s: Removed port %d from LAG %d. Members now %016llx.\n",
514 __func__, port, group, priv->lags_port_members[group]);
515 return 0;
516 }
517
518 /*
519 * Allocate a 64 bit octet counter located in the LOG HW table
520 */
521 static int rtl83xx_octet_cntr_alloc(struct rtl838x_switch_priv *priv)
522 {
523 int idx;
524
525 mutex_lock(&priv->reg_mutex);
526
527 idx = find_first_zero_bit(priv->octet_cntr_use_bm, MAX_COUNTERS);
528 if (idx >= priv->n_counters) {
529 mutex_unlock(&priv->reg_mutex);
530 return -1;
531 }
532
533 set_bit(idx, priv->octet_cntr_use_bm);
534 mutex_unlock(&priv->reg_mutex);
535
536 return idx;
537 }
538
539 /*
540 * Allocate a 32-bit packet counter
541 * 2 32-bit packet counters share the location of a 64-bit octet counter
542 * Initially there are no free packet counters and 2 new ones need to be freed
543 * by allocating the corresponding octet counter
544 */
545 int rtl83xx_packet_cntr_alloc(struct rtl838x_switch_priv *priv)
546 {
547 int idx, j;
548
549 mutex_lock(&priv->reg_mutex);
550
551 /* Because initially no packet counters are free, the logic is reversed:
552 * a 0-bit means the counter is already allocated (for octets)
553 */
554 idx = find_first_bit(priv->packet_cntr_use_bm, MAX_COUNTERS * 2);
555 if (idx >= priv->n_counters * 2) {
556 j = find_first_zero_bit(priv->octet_cntr_use_bm, MAX_COUNTERS);
557 if (j >= priv->n_counters) {
558 mutex_unlock(&priv->reg_mutex);
559 return -1;
560 }
561 set_bit(j, priv->octet_cntr_use_bm);
562 idx = j * 2;
563 set_bit(j * 2 + 1, priv->packet_cntr_use_bm);
564
565 } else {
566 clear_bit(idx, priv->packet_cntr_use_bm);
567 }
568
569 mutex_unlock(&priv->reg_mutex);
570
571 return idx;
572 }
573
574 /*
575 * Add an L2 nexthop entry for the L3 routing system / PIE forwarding in the SoC
576 * Use VID and MAC in rtl838x_l2_entry to identify either a free slot in the L2 hash table
577 * or mark an existing entry as a nexthop by setting it's nexthop bit
578 * Called from the L3 layer
579 * The index in the L2 hash table is filled into nh->l2_id;
580 */
581 int rtl83xx_l2_nexthop_add(struct rtl838x_switch_priv *priv, struct rtl83xx_nexthop *nh)
582 {
583 struct rtl838x_l2_entry e;
584 u64 seed = priv->r->l2_hash_seed(nh->mac, nh->rvid);
585 u32 key = priv->r->l2_hash_key(priv, seed);
586 int i, idx = -1;
587 u64 entry;
588
589 pr_debug("%s searching for %08llx vid %d with key %d, seed: %016llx\n",
590 __func__, nh->mac, nh->rvid, key, seed);
591
592 e.type = L2_UNICAST;
593 u64_to_ether_addr(nh->mac, &e.mac[0]);
594 e.port = nh->port;
595
596 // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs
597 for (i = 0; i < priv->l2_bucket_size; i++) {
598 entry = priv->r->read_l2_entry_using_hash(key, i, &e);
599
600 if (!e.valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
601 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1
602 : ((key << 2) | i) & 0xffff;
603 break;
604 }
605 }
606
607 if (idx < 0) {
608 pr_err("%s: No more L2 forwarding entries available\n", __func__);
609 return -1;
610 }
611
612 // Found an existing (e->valid is true) or empty entry, make it a nexthop entry
613 nh->l2_id = idx;
614 if (e.valid) {
615 nh->port = e.port;
616 nh->vid = e.vid; // Save VID
617 nh->rvid = e.rvid;
618 nh->dev_id = e.stack_dev;
619 // If the entry is already a valid next hop entry, don't change it
620 if (e.next_hop)
621 return 0;
622 } else {
623 e.valid = true;
624 e.is_static = true;
625 e.rvid = nh->rvid;
626 e.is_ip_mc = false;
627 e.is_ipv6_mc = false;
628 e.block_da = false;
629 e.block_sa = false;
630 e.suspended = false;
631 e.age = 0; // With port-ignore
632 e.port = priv->port_ignore;
633 u64_to_ether_addr(nh->mac, &e.mac[0]);
634 }
635 e.next_hop = true;
636 e.nh_route_id = nh->id; // NH route ID takes place of VID
637 e.nh_vlan_target = false;
638
639 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
640
641 return 0;
642 }
643
644 /*
645 * Removes a Layer 2 next hop entry in the forwarding database
646 * If it was static, the entire entry is removed, otherwise the nexthop bit is cleared
647 * and we wait until the entry ages out
648 */
649 int rtl83xx_l2_nexthop_rm(struct rtl838x_switch_priv *priv, struct rtl83xx_nexthop *nh)
650 {
651 struct rtl838x_l2_entry e;
652 u32 key = nh->l2_id >> 2;
653 int i = nh->l2_id & 0x3;
654 u64 entry = entry = priv->r->read_l2_entry_using_hash(key, i, &e);
655
656 pr_debug("%s: id %d, key %d, index %d\n", __func__, nh->l2_id, key, i);
657 if (!e.valid) {
658 dev_err(priv->dev, "unknown nexthop, id %x\n", nh->l2_id);
659 return -1;
660 }
661
662 if (e.is_static)
663 e.valid = false;
664 e.next_hop = false;
665 e.vid = nh->vid; // Restore VID
666 e.rvid = nh->rvid;
667
668 priv->r->write_l2_entry_using_hash(key, i, &e);
669
670 return 0;
671 }
672
673 static int rtl83xx_handle_changeupper(struct rtl838x_switch_priv *priv,
674 struct net_device *ndev,
675 struct netdev_notifier_changeupper_info *info)
676 {
677 struct net_device *upper = info->upper_dev;
678 struct netdev_lag_upper_info *lag_upper_info = NULL;
679 int i, j, err;
680
681 if (!netif_is_lag_master(upper))
682 return 0;
683
684 mutex_lock(&priv->reg_mutex);
685
686 for (i = 0; i < priv->n_lags; i++) {
687 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == upper))
688 break;
689 }
690 for (j = 0; j < priv->cpu_port; j++) {
691 if (priv->ports[j].dp->slave == ndev)
692 break;
693 }
694 if (j >= priv->cpu_port) {
695 err = -EINVAL;
696 goto out;
697 }
698
699 if (info->linking) {
700 lag_upper_info = info->upper_info;
701 if (!priv->lag_devs[i])
702 priv->lag_devs[i] = upper;
703 err = rtl83xx_lag_add(priv->ds, i, priv->ports[j].dp->index, lag_upper_info);
704 if (err) {
705 err = -EINVAL;
706 goto out;
707 }
708 } else {
709 if (!priv->lag_devs[i])
710 err = -EINVAL;
711 err = rtl83xx_lag_del(priv->ds, i, priv->ports[j].dp->index);
712 if (err) {
713 err = -EINVAL;
714 goto out;
715 }
716 if (!priv->lags_port_members[i])
717 priv->lag_devs[i] = NULL;
718 }
719
720 out:
721 mutex_unlock(&priv->reg_mutex);
722 return 0;
723 }
724
725 /*
726 * Is the lower network device a DSA slave network device of our RTL930X-switch?
727 * Unfortunately we cannot just follow dev->dsa_prt as this is only set for the
728 * DSA master device.
729 */
730 int rtl83xx_port_is_under(const struct net_device * dev, struct rtl838x_switch_priv *priv)
731 {
732 int i;
733
734 // TODO: On 5.12:
735 // if(!dsa_slave_dev_check(dev)) {
736 // netdev_info(dev, "%s: not a DSA device.\n", __func__);
737 // return -EINVAL;
738 // }
739
740 for (i = 0; i < priv->cpu_port; i++) {
741 if (!priv->ports[i].dp)
742 continue;
743 if (priv->ports[i].dp->slave == dev)
744 return i;
745 }
746 return -EINVAL;
747 }
748
749 static int rtl83xx_netdevice_event(struct notifier_block *this,
750 unsigned long event, void *ptr)
751 {
752 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
753 struct rtl838x_switch_priv *priv;
754 int err;
755
756 pr_debug("In: %s, event: %lu\n", __func__, event);
757
758 if ((event != NETDEV_CHANGEUPPER) && (event != NETDEV_CHANGELOWERSTATE))
759 return NOTIFY_DONE;
760
761 priv = container_of(this, struct rtl838x_switch_priv, nb);
762 switch (event) {
763 case NETDEV_CHANGEUPPER:
764 err = rtl83xx_handle_changeupper(priv, ndev, ptr);
765 break;
766 }
767
768 if (err)
769 return err;
770
771 return NOTIFY_DONE;
772 }
773
774 const static struct rhashtable_params route_ht_params = {
775 .key_len = sizeof(u32),
776 .key_offset = offsetof(struct rtl83xx_route, gw_ip),
777 .head_offset = offsetof(struct rtl83xx_route, linkage),
778 };
779
780 /*
781 * Updates an L3 next hop entry in the ROUTING table
782 */
783 static int rtl83xx_l3_nexthop_update(struct rtl838x_switch_priv *priv, __be32 ip_addr, u64 mac)
784 {
785 struct rtl83xx_route *r;
786 struct rhlist_head *tmp, *list;
787
788 rcu_read_lock();
789 list = rhltable_lookup(&priv->routes, &ip_addr, route_ht_params);
790 if (!list) {
791 rcu_read_unlock();
792 return -ENOENT;
793 }
794
795 rhl_for_each_entry_rcu(r, tmp, list, linkage) {
796 pr_info("%s: Setting up fwding: ip %pI4, GW mac %016llx\n",
797 __func__, &ip_addr, mac);
798
799 // Reads the ROUTING table entry associated with the route
800 priv->r->route_read(r->id, r);
801 pr_info("Route with id %d to %pI4 / %d\n", r->id, &r->dst_ip, r->prefix_len);
802
803 r->nh.mac = r->nh.gw = mac;
804 r->nh.port = priv->port_ignore;
805 r->nh.id = r->id;
806
807 // Do we need to explicitly add a DMAC entry with the route's nh index?
808 if (priv->r->set_l3_egress_mac)
809 priv->r->set_l3_egress_mac(r->id, mac);
810
811 // Update ROUTING table: map gateway-mac and switch-mac id to route id
812 rtl83xx_l2_nexthop_add(priv, &r->nh);
813
814 r->attr.valid = true;
815 r->attr.action = ROUTE_ACT_FORWARD;
816 r->attr.type = 0;
817 r->attr.hit = false; // Reset route-used indicator
818
819 // Add PIE entry with dst_ip and prefix_len
820 r->pr.dip = r->dst_ip;
821 r->pr.dip_m = inet_make_mask(r->prefix_len);
822
823 if (r->is_host_route) {
824 int slot = priv->r->find_l3_slot(r, false);
825
826 pr_info("%s: Got slot for route: %d\n", __func__, slot);
827 priv->r->host_route_write(slot, r);
828 } else {
829 priv->r->route_write(r->id, r);
830 r->pr.fwd_sel = true;
831 r->pr.fwd_data = r->nh.l2_id;
832 r->pr.fwd_act = PIE_ACT_ROUTE_UC;
833 }
834
835 if (priv->r->set_l3_nexthop)
836 priv->r->set_l3_nexthop(r->nh.id, r->nh.l2_id, r->nh.if_id);
837
838 if (r->pr.id < 0) {
839 r->pr.packet_cntr = rtl83xx_packet_cntr_alloc(priv);
840 if (r->pr.packet_cntr >= 0) {
841 pr_info("Using packet counter %d\n", r->pr.packet_cntr);
842 r->pr.log_sel = true;
843 r->pr.log_data = r->pr.packet_cntr;
844 }
845 priv->r->pie_rule_add(priv, &r->pr);
846 } else {
847 int pkts = priv->r->packet_cntr_read(r->pr.packet_cntr);
848 pr_info("%s: total packets: %d\n", __func__, pkts);
849
850 priv->r->pie_rule_write(priv, r->pr.id, &r->pr);
851 }
852 }
853 rcu_read_unlock();
854 return 0;
855 }
856
857 static int rtl83xx_port_ipv4_resolve(struct rtl838x_switch_priv *priv,
858 struct net_device *dev, __be32 ip_addr)
859 {
860 struct neighbour *n = neigh_lookup(&arp_tbl, &ip_addr, dev);
861 int err = 0;
862 u64 mac;
863
864 if (!n) {
865 n = neigh_create(&arp_tbl, &ip_addr, dev);
866 if (IS_ERR(n))
867 return PTR_ERR(n);
868 }
869
870 /* If the neigh is already resolved, then go ahead and
871 * install the entry, otherwise start the ARP process to
872 * resolve the neigh.
873 */
874 if (n->nud_state & NUD_VALID) {
875 mac = ether_addr_to_u64(n->ha);
876 pr_info("%s: resolved mac: %016llx\n", __func__, mac);
877 rtl83xx_l3_nexthop_update(priv, ip_addr, mac);
878 } else {
879 pr_info("%s: need to wait\n", __func__);
880 neigh_event_send(n, NULL);
881 }
882
883 neigh_release(n);
884 return err;
885 }
886
887 struct rtl83xx_walk_data {
888 struct rtl838x_switch_priv *priv;
889 int port;
890 };
891
892 static int rtl83xx_port_lower_walk(struct net_device *lower, struct netdev_nested_priv *_priv)
893 {
894 struct rtl83xx_walk_data *data = (struct rtl83xx_walk_data *)_priv->data;
895 struct rtl838x_switch_priv *priv = data->priv;
896 int ret = 0;
897 int index;
898
899 index = rtl83xx_port_is_under(lower, priv);
900 data->port = index;
901 if (index >= 0) {
902 pr_debug("Found DSA-port, index %d\n", index);
903 ret = 1;
904 }
905
906 return ret;
907 }
908
909 int rtl83xx_port_dev_lower_find(struct net_device *dev, struct rtl838x_switch_priv *priv)
910 {
911 struct rtl83xx_walk_data data;
912 struct netdev_nested_priv _priv;
913
914 data.priv = priv;
915 data.port = 0;
916 _priv.data = (void *)&data;
917
918 netdev_walk_all_lower_dev(dev, rtl83xx_port_lower_walk, &_priv);
919
920 return data.port;
921 }
922
923 static struct rtl83xx_route *rtl83xx_route_alloc(struct rtl838x_switch_priv *priv, u32 ip)
924 {
925 struct rtl83xx_route *r;
926 int idx = 0, err;
927
928 mutex_lock(&priv->reg_mutex);
929
930 idx = find_first_zero_bit(priv->route_use_bm, MAX_ROUTES);
931 pr_debug("%s id: %d, ip %pI4\n", __func__, idx, &ip);
932
933 r = kzalloc(sizeof(*r), GFP_KERNEL);
934 if (!r) {
935 mutex_unlock(&priv->reg_mutex);
936 return r;
937 }
938
939 r->id = idx;
940 r->gw_ip = ip;
941 r->pr.id = -1; // We still need to allocate a rule in HW
942 r->is_host_route = false;
943
944 err = rhltable_insert(&priv->routes, &r->linkage, route_ht_params);
945 if (err) {
946 pr_err("Could not insert new rule\n");
947 mutex_unlock(&priv->reg_mutex);
948 goto out_free;
949 }
950
951 set_bit(idx, priv->route_use_bm);
952
953 mutex_unlock(&priv->reg_mutex);
954
955 return r;
956
957 out_free:
958 kfree(r);
959 return NULL;
960 }
961
962
963 static struct rtl83xx_route *rtl83xx_host_route_alloc(struct rtl838x_switch_priv *priv, u32 ip)
964 {
965 struct rtl83xx_route *r;
966 int idx = 0, err;
967
968 mutex_lock(&priv->reg_mutex);
969
970 idx = find_first_zero_bit(priv->host_route_use_bm, MAX_HOST_ROUTES);
971 pr_debug("%s id: %d, ip %pI4\n", __func__, idx, &ip);
972
973 r = kzalloc(sizeof(*r), GFP_KERNEL);
974 if (!r) {
975 mutex_unlock(&priv->reg_mutex);
976 return r;
977 }
978
979 /* We require a unique route ID irrespective of whether it is a prefix or host
980 * route (on RTL93xx) as we use this ID to associate a DMAC and next-hop entry */
981 r->id = idx + MAX_ROUTES;
982
983 r->gw_ip = ip;
984 r->pr.id = -1; // We still need to allocate a rule in HW
985 r->is_host_route = true;
986
987 err = rhltable_insert(&priv->routes, &r->linkage, route_ht_params);
988 if (err) {
989 pr_err("Could not insert new rule\n");
990 mutex_unlock(&priv->reg_mutex);
991 goto out_free;
992 }
993
994 set_bit(idx, priv->host_route_use_bm);
995
996 mutex_unlock(&priv->reg_mutex);
997
998 return r;
999
1000 out_free:
1001 kfree(r);
1002 return NULL;
1003 }
1004
1005
1006
1007 static void rtl83xx_route_rm(struct rtl838x_switch_priv *priv, struct rtl83xx_route *r)
1008 {
1009 int id;
1010
1011 if (rhltable_remove(&priv->routes, &r->linkage, route_ht_params))
1012 dev_warn(priv->dev, "Could not remove route\n");
1013
1014 if (r->is_host_route) {
1015 id = priv->r->find_l3_slot(r, false);
1016 pr_debug("%s: Got id for host route: %d\n", __func__, id);
1017 r->attr.valid = false;
1018 priv->r->host_route_write(id, r);
1019 clear_bit(r->id - MAX_ROUTES, priv->host_route_use_bm);
1020 } else {
1021 // If there is a HW representation of the route, delete it
1022 if (priv->r->route_lookup_hw) {
1023 id = priv->r->route_lookup_hw(r);
1024 pr_info("%s: Got id for prefix route: %d\n", __func__, id);
1025 r->attr.valid = false;
1026 priv->r->route_write(id, r);
1027 }
1028 clear_bit(r->id, priv->route_use_bm);
1029 }
1030
1031 kfree(r);
1032 }
1033
1034 static int rtl83xx_fib4_del(struct rtl838x_switch_priv *priv,
1035 struct fib_entry_notifier_info *info)
1036 {
1037 struct fib_nh *nh = fib_info_nh(info->fi, 0);
1038 struct rtl83xx_route *r;
1039 struct rhlist_head *tmp, *list;
1040
1041 pr_debug("In %s, ip %pI4, len %d\n", __func__, &info->dst, info->dst_len);
1042 rcu_read_lock();
1043 list = rhltable_lookup(&priv->routes, &nh->fib_nh_gw4, route_ht_params);
1044 if (!list) {
1045 rcu_read_unlock();
1046 pr_err("%s: no such gateway: %pI4\n", __func__, &nh->fib_nh_gw4);
1047 return -ENOENT;
1048 }
1049 rhl_for_each_entry_rcu(r, tmp, list, linkage) {
1050 if (r->dst_ip == info->dst && r->prefix_len == info->dst_len) {
1051 pr_info("%s: found a route with id %d, nh-id %d\n",
1052 __func__, r->id, r->nh.id);
1053 break;
1054 }
1055 }
1056 rcu_read_unlock();
1057
1058 rtl83xx_l2_nexthop_rm(priv, &r->nh);
1059
1060 pr_debug("%s: Releasing packet counter %d\n", __func__, r->pr.packet_cntr);
1061 set_bit(r->pr.packet_cntr, priv->packet_cntr_use_bm);
1062 priv->r->pie_rule_rm(priv, &r->pr);
1063
1064 rtl83xx_route_rm(priv, r);
1065
1066 nh->fib_nh_flags &= ~RTNH_F_OFFLOAD;
1067
1068 return 0;
1069 }
1070
1071 /*
1072 * On the RTL93xx, an L3 termination endpoint MAC address on which the router waits
1073 * for packets to be routed needs to be allocated.
1074 */
1075 static int rtl83xx_alloc_router_mac(struct rtl838x_switch_priv *priv, u64 mac)
1076 {
1077 int i, free_mac = -1;
1078 struct rtl93xx_rt_mac m;
1079
1080 mutex_lock(&priv->reg_mutex);
1081 for (i = 0; i < MAX_ROUTER_MACS; i++) {
1082 priv->r->get_l3_router_mac(i, &m);
1083 if (free_mac < 0 && !m.valid) {
1084 free_mac = i;
1085 continue;
1086 }
1087 if (m.valid && m.mac == mac) {
1088 free_mac = i;
1089 break;
1090 }
1091 }
1092
1093 if (free_mac < 0) {
1094 pr_err("No free router MACs, cannot offload\n");
1095 mutex_unlock(&priv->reg_mutex);
1096 return -1;
1097 }
1098
1099 m.valid = true;
1100 m.mac = mac;
1101 m.p_type = 0; // An individual port, not a trunk port
1102 m.p_id = 0x3f; // Listen on any port
1103 m.p_id_mask = 0;
1104 m.vid = 0; // Listen on any VLAN...
1105 m.vid_mask = 0; // ... so mask needs to be 0
1106 m.mac_mask = 0xffffffffffffULL; // We want an exact match of the interface MAC
1107 m.action = L3_FORWARD; // Route the packet
1108 priv->r->set_l3_router_mac(free_mac, &m);
1109
1110 mutex_unlock(&priv->reg_mutex);
1111
1112 return 0;
1113 }
1114
1115 static int rtl83xx_alloc_egress_intf(struct rtl838x_switch_priv *priv, u64 mac, int vlan)
1116 {
1117 int i, free_mac = -1;
1118 struct rtl838x_l3_intf intf;
1119 u64 m;
1120
1121 mutex_lock(&priv->reg_mutex);
1122 for (i = 0; i < MAX_SMACS; i++) {
1123 m = priv->r->get_l3_egress_mac(L3_EGRESS_DMACS + i);
1124 if (free_mac < 0 && !m) {
1125 free_mac = i;
1126 continue;
1127 }
1128 if (m == mac) {
1129 mutex_unlock(&priv->reg_mutex);
1130 return i;
1131 }
1132 }
1133
1134 if (free_mac < 0) {
1135 pr_err("No free egress interface, cannot offload\n");
1136 return -1;
1137 }
1138
1139 // Set up default egress interface 1
1140 intf.vid = vlan;
1141 intf.smac_idx = free_mac;
1142 intf.ip4_mtu_id = 1;
1143 intf.ip6_mtu_id = 1;
1144 intf.ttl_scope = 1; // TTL
1145 intf.hl_scope = 1; // Hop Limit
1146 intf.ip4_icmp_redirect = intf.ip6_icmp_redirect = 2; // FORWARD
1147 intf.ip4_pbr_icmp_redirect = intf.ip6_pbr_icmp_redirect = 2; // FORWARD;
1148 priv->r->set_l3_egress_intf(free_mac, &intf);
1149
1150 priv->r->set_l3_egress_mac(L3_EGRESS_DMACS + free_mac, mac);
1151
1152 mutex_unlock(&priv->reg_mutex);
1153
1154 return free_mac;
1155 }
1156
1157 static int rtl83xx_fib4_add(struct rtl838x_switch_priv *priv,
1158 struct fib_entry_notifier_info *info)
1159 {
1160 struct fib_nh *nh = fib_info_nh(info->fi, 0);
1161 struct net_device *dev = fib_info_nh(info->fi, 0)->fib_nh_dev;
1162 int port;
1163 struct rtl83xx_route *r;
1164 bool to_localhost;
1165 int vlan = is_vlan_dev(dev) ? vlan_dev_vlan_id(dev) : 0;
1166
1167 pr_debug("In %s, ip %pI4, len %d\n", __func__, &info->dst, info->dst_len);
1168 if (!info->dst) {
1169 pr_info("Not offloading default route for now\n");
1170 return 0;
1171 }
1172
1173 pr_debug("GW: %pI4, interface name %s, mac %016llx, vlan %d\n", &nh->fib_nh_gw4, dev->name,
1174 ether_addr_to_u64(dev->dev_addr), vlan
1175 );
1176
1177 port = rtl83xx_port_dev_lower_find(dev, priv);
1178 if (port < 0)
1179 return -1;
1180
1181 // For now we only work with routes that have a gateway and are not ourself
1182 // if ((!nh->fib_nh_gw4) && (info->dst_len != 32))
1183 // return 0;
1184
1185 if ((info->dst & 0xff) == 0xff)
1186 return 0;
1187
1188 // Do not offload routes to 192.168.100.x
1189 if ((info->dst & 0xffffff00) == 0xc0a86400)
1190 return 0;
1191
1192 // Do not offload routes to 127.x.x.x
1193 if ((info->dst & 0xff000000) == 0x7f000000)
1194 return 0;
1195
1196 // Allocate route or host-route (entry if hardware supports this)
1197 if (info->dst_len == 32 && priv->r->host_route_write)
1198 r = rtl83xx_host_route_alloc(priv, nh->fib_nh_gw4);
1199 else
1200 r = rtl83xx_route_alloc(priv, nh->fib_nh_gw4);
1201
1202 if (!r) {
1203 pr_err("%s: No more free route entries\n", __func__);
1204 return -1;
1205 }
1206
1207 r->dst_ip = info->dst;
1208 r->prefix_len = info->dst_len;
1209 r->nh.rvid = vlan;
1210 to_localhost = !nh->fib_nh_gw4;
1211
1212 if (priv->r->set_l3_router_mac) {
1213 u64 mac = ether_addr_to_u64(dev->dev_addr);
1214
1215 pr_debug("Local route and router mac %016llx\n", mac);
1216
1217 if (rtl83xx_alloc_router_mac(priv, mac))
1218 goto out_free_rt;
1219
1220 // vid = 0: Do not care about VID
1221 r->nh.if_id = rtl83xx_alloc_egress_intf(priv, mac, vlan);
1222 if (r->nh.if_id < 0)
1223 goto out_free_rmac;
1224
1225 if (to_localhost) {
1226 int slot;
1227
1228 r->nh.mac = mac;
1229 r->nh.port = priv->port_ignore;
1230 r->attr.valid = true;
1231 r->attr.action = ROUTE_ACT_TRAP2CPU;
1232 r->attr.type = 0;
1233
1234 slot = priv->r->find_l3_slot(r, false);
1235 pr_debug("%s: Got slot for route: %d\n", __func__, slot);
1236 priv->r->host_route_write(slot, r);
1237 }
1238 }
1239
1240 // We need to resolve the mac address of the GW
1241 if (!to_localhost)
1242 rtl83xx_port_ipv4_resolve(priv, dev, nh->fib_nh_gw4);
1243
1244 nh->fib_nh_flags |= RTNH_F_OFFLOAD;
1245
1246 return 0;
1247
1248 out_free_rmac:
1249 out_free_rt:
1250 return 0;
1251 }
1252
1253 static int rtl83xx_fib6_add(struct rtl838x_switch_priv *priv,
1254 struct fib6_entry_notifier_info *info)
1255 {
1256 pr_debug("In %s\n", __func__);
1257 // nh->fib_nh_flags |= RTNH_F_OFFLOAD;
1258 return 0;
1259 }
1260
1261 struct net_event_work {
1262 struct work_struct work;
1263 struct rtl838x_switch_priv *priv;
1264 u64 mac;
1265 u32 gw_addr;
1266 };
1267
1268 static void rtl83xx_net_event_work_do(struct work_struct *work)
1269 {
1270 struct net_event_work *net_work =
1271 container_of(work, struct net_event_work, work);
1272 struct rtl838x_switch_priv *priv = net_work->priv;
1273
1274 rtl83xx_l3_nexthop_update(priv, net_work->gw_addr, net_work->mac);
1275 }
1276
1277 static int rtl83xx_netevent_event(struct notifier_block *this,
1278 unsigned long event, void *ptr)
1279 {
1280 struct rtl838x_switch_priv *priv;
1281 struct net_device *dev;
1282 struct neighbour *n = ptr;
1283 int err, port;
1284 struct net_event_work *net_work;
1285
1286 priv = container_of(this, struct rtl838x_switch_priv, ne_nb);
1287
1288 net_work = kzalloc(sizeof(*net_work), GFP_ATOMIC);
1289 if (!net_work)
1290 return NOTIFY_BAD;
1291
1292 INIT_WORK(&net_work->work, rtl83xx_net_event_work_do);
1293 net_work->priv = priv;
1294
1295 switch (event) {
1296 case NETEVENT_NEIGH_UPDATE:
1297 if (n->tbl != &arp_tbl)
1298 return NOTIFY_DONE;
1299 dev = n->dev;
1300 port = rtl83xx_port_dev_lower_find(dev, priv);
1301 if (port < 0 || !(n->nud_state & NUD_VALID)) {
1302 pr_debug("%s: Neigbour invalid, not updating\n", __func__);
1303 kfree(net_work);
1304 return NOTIFY_DONE;
1305 }
1306
1307 net_work->mac = ether_addr_to_u64(n->ha);
1308 net_work->gw_addr = *(__be32 *) n->primary_key;
1309
1310 pr_debug("%s: updating neighbour on port %d, mac %016llx\n",
1311 __func__, port, net_work->mac);
1312 schedule_work(&net_work->work);
1313 if (err)
1314 netdev_warn(dev, "failed to handle neigh update (err %d)\n", err);
1315 break;
1316 }
1317
1318 return NOTIFY_DONE;
1319 }
1320
1321 struct rtl83xx_fib_event_work {
1322 struct work_struct work;
1323 union {
1324 struct fib_entry_notifier_info fen_info;
1325 struct fib6_entry_notifier_info fen6_info;
1326 struct fib_rule_notifier_info fr_info;
1327 };
1328 struct rtl838x_switch_priv *priv;
1329 bool is_fib6;
1330 unsigned long event;
1331 };
1332
1333 static void rtl83xx_fib_event_work_do(struct work_struct *work)
1334 {
1335 struct rtl83xx_fib_event_work *fib_work =
1336 container_of(work, struct rtl83xx_fib_event_work, work);
1337 struct rtl838x_switch_priv *priv = fib_work->priv;
1338 struct fib_rule *rule;
1339 int err;
1340
1341 /* Protect internal structures from changes */
1342 rtnl_lock();
1343 pr_debug("%s: doing work, event %ld\n", __func__, fib_work->event);
1344 switch (fib_work->event) {
1345 case FIB_EVENT_ENTRY_ADD:
1346 case FIB_EVENT_ENTRY_REPLACE:
1347 case FIB_EVENT_ENTRY_APPEND:
1348 if (fib_work->is_fib6) {
1349 err = rtl83xx_fib6_add(priv, &fib_work->fen6_info);
1350 } else {
1351 err = rtl83xx_fib4_add(priv, &fib_work->fen_info);
1352 fib_info_put(fib_work->fen_info.fi);
1353 }
1354 if (err)
1355 pr_err("%s: FIB4 failed\n", __func__);
1356 break;
1357 case FIB_EVENT_ENTRY_DEL:
1358 rtl83xx_fib4_del(priv, &fib_work->fen_info);
1359 fib_info_put(fib_work->fen_info.fi);
1360 break;
1361 case FIB_EVENT_RULE_ADD:
1362 case FIB_EVENT_RULE_DEL:
1363 rule = fib_work->fr_info.rule;
1364 if (!fib4_rule_default(rule))
1365 pr_err("%s: FIB4 default rule failed\n", __func__);
1366 fib_rule_put(rule);
1367 break;
1368 }
1369 rtnl_unlock();
1370 kfree(fib_work);
1371 }
1372
1373 /* Called with rcu_read_lock() */
1374 static int rtl83xx_fib_event(struct notifier_block *this, unsigned long event, void *ptr)
1375 {
1376 struct fib_notifier_info *info = ptr;
1377 struct rtl838x_switch_priv *priv;
1378 struct rtl83xx_fib_event_work *fib_work;
1379
1380 if ((info->family != AF_INET && info->family != AF_INET6 &&
1381 info->family != RTNL_FAMILY_IPMR &&
1382 info->family != RTNL_FAMILY_IP6MR))
1383 return NOTIFY_DONE;
1384
1385 priv = container_of(this, struct rtl838x_switch_priv, fib_nb);
1386
1387 fib_work = kzalloc(sizeof(*fib_work), GFP_ATOMIC);
1388 if (!fib_work)
1389 return NOTIFY_BAD;
1390
1391 INIT_WORK(&fib_work->work, rtl83xx_fib_event_work_do);
1392 fib_work->priv = priv;
1393 fib_work->event = event;
1394 fib_work->is_fib6 = false;
1395
1396 switch (event) {
1397 case FIB_EVENT_ENTRY_ADD:
1398 case FIB_EVENT_ENTRY_REPLACE:
1399 case FIB_EVENT_ENTRY_APPEND:
1400 case FIB_EVENT_ENTRY_DEL:
1401 pr_debug("%s: FIB_ENTRY ADD/DELL, event %ld\n", __func__, event);
1402 if (info->family == AF_INET) {
1403 struct fib_entry_notifier_info *fen_info = ptr;
1404
1405 if (fen_info->fi->fib_nh_is_v6) {
1406 NL_SET_ERR_MSG_MOD(info->extack,
1407 "IPv6 gateway with IPv4 route is not supported");
1408 kfree(fib_work);
1409 return notifier_from_errno(-EINVAL);
1410 }
1411
1412 memcpy(&fib_work->fen_info, ptr, sizeof(fib_work->fen_info));
1413 /* Take referece on fib_info to prevent it from being
1414 * freed while work is queued. Release it afterwards.
1415 */
1416 fib_info_hold(fib_work->fen_info.fi);
1417
1418 } else if (info->family == AF_INET6) {
1419 struct fib6_entry_notifier_info *fen6_info = ptr;
1420 pr_warn("%s: FIB_RULE ADD/DELL for IPv6 not supported\n", __func__);
1421 kfree(fib_work);
1422 return NOTIFY_DONE;
1423 }
1424 break;
1425
1426 case FIB_EVENT_RULE_ADD:
1427 case FIB_EVENT_RULE_DEL:
1428 pr_debug("%s: FIB_RULE ADD/DELL, event: %ld\n", __func__, event);
1429 memcpy(&fib_work->fr_info, ptr, sizeof(fib_work->fr_info));
1430 fib_rule_get(fib_work->fr_info.rule);
1431 break;
1432 }
1433
1434 schedule_work(&fib_work->work);
1435
1436 return NOTIFY_DONE;
1437 }
1438
1439 static int __init rtl83xx_sw_probe(struct platform_device *pdev)
1440 {
1441 int err = 0, i;
1442 struct rtl838x_switch_priv *priv;
1443 struct device *dev = &pdev->dev;
1444 u64 bpdu_mask;
1445
1446 pr_debug("Probing RTL838X switch device\n");
1447 if (!pdev->dev.of_node) {
1448 dev_err(dev, "No DT found\n");
1449 return -EINVAL;
1450 }
1451
1452 // Initialize access to RTL switch tables
1453 rtl_table_init();
1454
1455 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1456 if (!priv)
1457 return -ENOMEM;
1458
1459 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
1460
1461 if (!priv->ds)
1462 return -ENOMEM;
1463 priv->ds->dev = dev;
1464 priv->ds->priv = priv;
1465 priv->ds->ops = &rtl83xx_switch_ops;
1466 priv->dev = dev;
1467
1468 mutex_init(&priv->reg_mutex);
1469
1470 priv->family_id = soc_info.family;
1471 priv->id = soc_info.id;
1472 switch(soc_info.family) {
1473 case RTL8380_FAMILY_ID:
1474 priv->ds->ops = &rtl83xx_switch_ops;
1475 priv->cpu_port = RTL838X_CPU_PORT;
1476 priv->port_mask = 0x1f;
1477 priv->port_width = 1;
1478 priv->irq_mask = 0x0FFFFFFF;
1479 priv->r = &rtl838x_reg;
1480 priv->ds->num_ports = 29;
1481 priv->fib_entries = 8192;
1482 rtl8380_get_version(priv);
1483 priv->n_lags = 8;
1484 priv->l2_bucket_size = 4;
1485 priv->n_pie_blocks = 12;
1486 priv->port_ignore = 0x1f;
1487 priv->n_counters = 128;
1488 break;
1489 case RTL8390_FAMILY_ID:
1490 priv->ds->ops = &rtl83xx_switch_ops;
1491 priv->cpu_port = RTL839X_CPU_PORT;
1492 priv->port_mask = 0x3f;
1493 priv->port_width = 2;
1494 priv->irq_mask = 0xFFFFFFFFFFFFFULL;
1495 priv->r = &rtl839x_reg;
1496 priv->ds->num_ports = 53;
1497 priv->fib_entries = 16384;
1498 rtl8390_get_version(priv);
1499 priv->n_lags = 16;
1500 priv->l2_bucket_size = 4;
1501 priv->n_pie_blocks = 18;
1502 priv->port_ignore = 0x3f;
1503 priv->n_counters = 1024;
1504 break;
1505 case RTL9300_FAMILY_ID:
1506 priv->ds->ops = &rtl930x_switch_ops;
1507 priv->cpu_port = RTL930X_CPU_PORT;
1508 priv->port_mask = 0x1f;
1509 priv->port_width = 1;
1510 priv->irq_mask = 0x0FFFFFFF;
1511 priv->r = &rtl930x_reg;
1512 priv->ds->num_ports = 29;
1513 priv->fib_entries = 16384;
1514 priv->version = RTL8390_VERSION_A;
1515 priv->n_lags = 16;
1516 sw_w32(1, RTL930X_ST_CTRL);
1517 priv->l2_bucket_size = 8;
1518 priv->n_pie_blocks = 16;
1519 priv->port_ignore = 0x3f;
1520 priv->n_counters = 2048;
1521 break;
1522 case RTL9310_FAMILY_ID:
1523 priv->ds->ops = &rtl930x_switch_ops;
1524 priv->cpu_port = RTL931X_CPU_PORT;
1525 priv->port_mask = 0x3f;
1526 priv->port_width = 2;
1527 priv->irq_mask = 0xFFFFFFFFFFFFFULL;
1528 priv->r = &rtl931x_reg;
1529 priv->ds->num_ports = 57;
1530 priv->fib_entries = 16384;
1531 priv->version = RTL8390_VERSION_A;
1532 priv->n_lags = 16;
1533 priv->l2_bucket_size = 8;
1534 break;
1535 }
1536 pr_debug("Chip version %c\n", priv->version);
1537
1538 err = rtl83xx_mdio_probe(priv);
1539 if (err) {
1540 /* Probing fails the 1st time because of missing ethernet driver
1541 * initialization. Use this to disable traffic in case the bootloader left if on
1542 */
1543 return err;
1544 }
1545 err = dsa_register_switch(priv->ds);
1546 if (err) {
1547 dev_err(dev, "Error registering switch: %d\n", err);
1548 return err;
1549 }
1550
1551 /*
1552 * dsa_to_port returns dsa_port from the port list in
1553 * dsa_switch_tree, the tree is built when the switch
1554 * is registered by dsa_register_switch
1555 */
1556 for (i = 0; i <= priv->cpu_port; i++)
1557 priv->ports[i].dp = dsa_to_port(priv->ds, i);
1558
1559 /* Enable link and media change interrupts. Are the SERDES masks needed? */
1560 sw_w32_mask(0, 3, priv->r->isr_glb_src);
1561
1562 priv->r->set_port_reg_le(priv->irq_mask, priv->r->isr_port_link_sts_chg);
1563 priv->r->set_port_reg_le(priv->irq_mask, priv->r->imr_port_link_sts_chg);
1564
1565 priv->link_state_irq = platform_get_irq(pdev, 0);
1566 pr_info("LINK state irq: %d\n", priv->link_state_irq);
1567 switch (priv->family_id) {
1568 case RTL8380_FAMILY_ID:
1569 err = request_irq(priv->link_state_irq, rtl838x_switch_irq,
1570 IRQF_SHARED, "rtl838x-link-state", priv->ds);
1571 break;
1572 case RTL8390_FAMILY_ID:
1573 err = request_irq(priv->link_state_irq, rtl839x_switch_irq,
1574 IRQF_SHARED, "rtl839x-link-state", priv->ds);
1575 break;
1576 case RTL9300_FAMILY_ID:
1577 err = request_irq(priv->link_state_irq, rtl930x_switch_irq,
1578 IRQF_SHARED, "rtl930x-link-state", priv->ds);
1579 break;
1580 case RTL9310_FAMILY_ID:
1581 err = request_irq(priv->link_state_irq, rtl931x_switch_irq,
1582 IRQF_SHARED, "rtl931x-link-state", priv->ds);
1583 break;
1584 }
1585 if (err) {
1586 dev_err(dev, "Error setting up switch interrupt.\n");
1587 /* Need to free allocated switch here */
1588 }
1589
1590 /* Enable interrupts for switch, on RTL931x, the IRQ is always on globally */
1591 if (soc_info.family != RTL9310_FAMILY_ID)
1592 sw_w32(0x1, priv->r->imr_glb);
1593
1594 rtl83xx_get_l2aging(priv);
1595
1596 rtl83xx_setup_qos(priv);
1597
1598 priv->r->l3_setup(priv);
1599
1600 /* Clear all destination ports for mirror groups */
1601 for (i = 0; i < 4; i++)
1602 priv->mirror_group_ports[i] = -1;
1603
1604 /*
1605 * Register netdevice event callback to catch changes in link aggregation groups
1606 */
1607 priv->nb.notifier_call = rtl83xx_netdevice_event;
1608 if (register_netdevice_notifier(&priv->nb)) {
1609 priv->nb.notifier_call = NULL;
1610 dev_err(dev, "Failed to register LAG netdev notifier\n");
1611 goto err_register_nb;
1612 }
1613
1614 // Initialize hash table for L3 routing
1615 rhltable_init(&priv->routes, &route_ht_params);
1616
1617 /*
1618 * Register netevent notifier callback to catch notifications about neighboring
1619 * changes to update nexthop entries for L3 routing.
1620 */
1621 priv->ne_nb.notifier_call = rtl83xx_netevent_event;
1622 if (register_netevent_notifier(&priv->ne_nb)) {
1623 priv->ne_nb.notifier_call = NULL;
1624 dev_err(dev, "Failed to register netevent notifier\n");
1625 goto err_register_ne_nb;
1626 }
1627
1628 priv->fib_nb.notifier_call = rtl83xx_fib_event;
1629
1630 /*
1631 * Register Forwarding Information Base notifier to offload routes where
1632 * where possible
1633 * Only FIBs pointing to our own netdevs are programmed into
1634 * the device, so no need to pass a callback.
1635 */
1636 err = register_fib_notifier(&init_net, &priv->fib_nb, NULL, NULL);
1637 if (err)
1638 goto err_register_fib_nb;
1639
1640 // TODO: put this into l2_setup()
1641 // Flood BPDUs to all ports including cpu-port
1642 if (soc_info.family != RTL9300_FAMILY_ID) {
1643 bpdu_mask = soc_info.family == RTL8380_FAMILY_ID ? 0x1FFFFFFF : 0x1FFFFFFFFFFFFF;
1644 priv->r->set_port_reg_be(bpdu_mask, priv->r->rma_bpdu_fld_pmask);
1645
1646 // TRAP 802.1X frames (EAPOL) to the CPU-Port, bypass STP and VLANs
1647 sw_w32(7, priv->r->spcl_trap_eapol_ctrl);
1648
1649 rtl838x_dbgfs_init(priv);
1650 } else {
1651 rtl930x_dbgfs_init(priv);
1652 }
1653
1654 return 0;
1655
1656 err_register_fib_nb:
1657 unregister_netevent_notifier(&priv->ne_nb);
1658 err_register_ne_nb:
1659 unregister_netdevice_notifier(&priv->nb);
1660 err_register_nb:
1661 return err;
1662 }
1663
1664 static int rtl83xx_sw_remove(struct platform_device *pdev)
1665 {
1666 // TODO:
1667 pr_debug("Removing platform driver for rtl83xx-sw\n");
1668 return 0;
1669 }
1670
1671 static const struct of_device_id rtl83xx_switch_of_ids[] = {
1672 { .compatible = "realtek,rtl83xx-switch"},
1673 { /* sentinel */ }
1674 };
1675
1676
1677 MODULE_DEVICE_TABLE(of, rtl83xx_switch_of_ids);
1678
1679 static struct platform_driver rtl83xx_switch_driver = {
1680 .probe = rtl83xx_sw_probe,
1681 .remove = rtl83xx_sw_remove,
1682 .driver = {
1683 .name = "rtl83xx-switch",
1684 .pm = NULL,
1685 .of_match_table = rtl83xx_switch_of_ids,
1686 },
1687 };
1688
1689 module_platform_driver(rtl83xx_switch_driver);
1690
1691 MODULE_AUTHOR("B. Koblitz");
1692 MODULE_DESCRIPTION("RTL83XX SoC Switch Driver");
1693 MODULE_LICENSE("GPL");
OpenWrt Source Repository