mvebu: remove linux 4.4 support
authorFelix Fietkau <nbd@nbd.name>
Mon, 13 Feb 2017 10:02:06 +0000 (11:02 +0100)
committerFelix Fietkau <nbd@nbd.name>
Wed, 12 Apr 2017 07:51:34 +0000 (09:51 +0200)
Signed-off-by: Felix Fietkau <nbd@nbd.name>
79 files changed:
target/linux/mvebu/config-4.4 [deleted file]
target/linux/mvebu/patches-4.4/002-add_powertables.patch [deleted file]
target/linux/mvebu/patches-4.4/003-add_switch_nodes.patch [deleted file]
target/linux/mvebu/patches-4.4/010-build_new_dtbs.patch [deleted file]
target/linux/mvebu/patches-4.4/020-mtd-nand-pxa3xx_nand-add-support-for-partial-chunks.patch [deleted file]
target/linux/mvebu/patches-4.4/021-mtd-pxa3xx_nand-Increase-the-initial-chunk-size.patch [deleted file]
target/linux/mvebu/patches-4.4/022-mtd-pxa3xx_nand-Fix-initial-controller-configuration.patch [deleted file]
target/linux/mvebu/patches-4.4/023-bus-mvebu-mbus-provide-api-for-obtaining-IO-and-DRAM.patch [deleted file]
target/linux/mvebu/patches-4.4/030-mvneta-consolidate-autoneg-enabling.patch [deleted file]
target/linux/mvebu/patches-4.4/031-mvneta-implement-ethtool-autonegotiation-control.patch [deleted file]
target/linux/mvebu/patches-4.4/032-net-mvneta-Make-the-default-queue-related-for-each-p.patch [deleted file]
target/linux/mvebu/patches-4.4/033-net-mvneta-Associate-RX-queues-with-each-CPU.patch [deleted file]
target/linux/mvebu/patches-4.4/034-net-mvneta-Add-naive-RSS-support.patch [deleted file]
target/linux/mvebu/patches-4.4/035-net-mvneta-Configure-XPS-support.patch [deleted file]
target/linux/mvebu/patches-4.4/036-net-mvneta-fix-trivial-cut-off-issue-in-mvneta_ethto.patch [deleted file]
target/linux/mvebu/patches-4.4/037-net-mvneta-Fix-for_each_present_cpu-usage.patch [deleted file]
target/linux/mvebu/patches-4.4/038-net-mvneta-Fix-the-CPU-choice-in-mvneta_percpu_elect.patch [deleted file]
target/linux/mvebu/patches-4.4/039-net-mvneta-Use-on_each_cpu-when-possible.patch [deleted file]
target/linux/mvebu/patches-4.4/040-net-mvneta-Modify-the-queue-related-fields-from-each.patch [deleted file]
target/linux/mvebu/patches-4.4/041-net-mvneta-The-mvneta_percpu_elect-function-should-b.patch [deleted file]
target/linux/mvebu/patches-4.4/042-net-mvneta-Fix-race-condition-during-stopping.patch [deleted file]
target/linux/mvebu/patches-4.4/043-net-mvneta-sort-the-headers-in-alphabetic-order.patch [deleted file]
target/linux/mvebu/patches-4.4/044-net-add-a-hardware-buffer-management-helper-API.patch [deleted file]
target/linux/mvebu/patches-4.4/045-net-mvneta-bm-add-support-for-hardware-buffer-manage.patch [deleted file]
target/linux/mvebu/patches-4.4/046-net-mvneta-Use-the-new-hwbm-framework.patch [deleted file]
target/linux/mvebu/patches-4.4/047-net-mvneta-Fix-spinlock-usage.patch [deleted file]
target/linux/mvebu/patches-4.4/048-net-mvneta-fix-error-messages-in-mvneta_port_down-fu.patch [deleted file]
target/linux/mvebu/patches-4.4/049-net-mvneta-replace-MVNETA_CPU_D_CACHE_LINE_SIZE-with.patch [deleted file]
target/linux/mvebu/patches-4.4/050-net-mvneta-fix-changing-MTU-when-using-per-cpu-proce.patch [deleted file]
target/linux/mvebu/patches-4.4/051-ARM-dts-armada-38x-add-buffer-manager-nodes.patch [deleted file]
target/linux/mvebu/patches-4.4/052-ARM-dts-armada-xp-add-buffer-manager-nodes.patch [deleted file]
target/linux/mvebu/patches-4.4/053-ARM-dts-Add-SolidRun-Armada-388-Clearfog-A1-DT-file.patch [deleted file]
target/linux/mvebu/patches-4.4/054-ARM-dts-armada-38x-enable-buffer-manager-support-on-.patch [deleted file]
target/linux/mvebu/patches-4.4/055-ARM-dts-armada-388-clearfog-remove-duplicate-mdio-en.patch [deleted file]
target/linux/mvebu/patches-4.4/100-find_active_root.patch [deleted file]
target/linux/mvebu/patches-4.4/102-revert_i2c_delay.patch [deleted file]
target/linux/mvebu/patches-4.4/103-remove-nand-driver-bug.patch [deleted file]
target/linux/mvebu/patches-4.4/104-linksys_mamba_disable_keep_config.patch [deleted file]
target/linux/mvebu/patches-4.4/106-enable-bm-on-linksys-devices.patch [deleted file]
target/linux/mvebu/patches-4.4/110-pxa3xxx_revert_irq_thread.patch [deleted file]
target/linux/mvebu/patches-4.4/120-phy-move-fixed_phy-MII-register-generation-to-a-libr.patch [deleted file]
target/linux/mvebu/patches-4.4/121-phy-convert-swphy-register-generation-to-tabular-for.patch [deleted file]
target/linux/mvebu/patches-4.4/122-phy-separate-swphy-state-validation-from-register-ge.patch [deleted file]
target/linux/mvebu/patches-4.4/123-phy-generate-swphy-registers-on-the-fly.patch [deleted file]
target/linux/mvebu/patches-4.4/124-phy-improve-safety-of-fixed-phy-MII-register-reading.patch [deleted file]
target/linux/mvebu/patches-4.4/125-phy-provide-a-hook-for-link-up-link-down-events.patch [deleted file]
target/linux/mvebu/patches-4.4/126-phy-marvell-88E1512-add-flow-control-support.patch [deleted file]
target/linux/mvebu/patches-4.4/127-phy-export-phy_start_machine-for-phylink.patch [deleted file]
target/linux/mvebu/patches-4.4/128-phy-export-phy_speed_to_str-for-phylink.patch [deleted file]
target/linux/mvebu/patches-4.4/129-phy-add-I2C-mdio-bus.patch [deleted file]
target/linux/mvebu/patches-4.4/130-phylink-add-phylink-infrastructure.patch [deleted file]
target/linux/mvebu/patches-4.4/131-phylink-add-hooks-for-SFP-support.patch [deleted file]
target/linux/mvebu/patches-4.4/132-sfp-add-phylink-based-SFP-module-support.patch [deleted file]
target/linux/mvebu/patches-4.4/133-sfp-display-SFP-module-information.patch [deleted file]
target/linux/mvebu/patches-4.4/134-net-mvneta-convert-to-phylink.patch [deleted file]
target/linux/mvebu/patches-4.4/135-phy-fixed-phy-remove-fixed_phy_update_state.patch [deleted file]
target/linux/mvebu/patches-4.4/136-phylink-add-ethtool-nway_reset-support.patch [deleted file]
target/linux/mvebu/patches-4.4/137-net-mvneta-add-nway_reset-support.patch [deleted file]
target/linux/mvebu/patches-4.4/138-phylink-add-flow-control-support.patch [deleted file]
target/linux/mvebu/patches-4.4/139-net-mvneta-add-flow-control-support-via-phylink.patch [deleted file]
target/linux/mvebu/patches-4.4/140-net-mvneta-enable-flow-control-for-PHY-connections.patch [deleted file]
target/linux/mvebu/patches-4.4/141-net-mvneta-enable-flow-control-for-fixed-connections.patch [deleted file]
target/linux/mvebu/patches-4.4/142-phylink-add-EEE-support.patch [deleted file]
target/linux/mvebu/patches-4.4/143-net-mvneta-add-EEE-support.patch [deleted file]
target/linux/mvebu/patches-4.4/144-phylink-add-module-EEPROM-support.patch [deleted file]
target/linux/mvebu/patches-4.4/145-net-mvneta-add-module-EEPROM-reading-support.patch [deleted file]
target/linux/mvebu/patches-4.4/146-sfp-phylink-hook-up-eeprom-functions.patch [deleted file]
target/linux/mvebu/patches-4.4/147-net-mvneta-add-BQL-support.patch [deleted file]
target/linux/mvebu/patches-4.4/202-gpio_mvebu_add_limited_pwm_support.patch [deleted file]
target/linux/mvebu/patches-4.4/203-dt_bindings_extend_mvebu_gpio_documentation_with_pwm.patch [deleted file]
target/linux/mvebu/patches-4.4/204-mvebu_xp_add_pwm_properties_to_dtsi_files.patch [deleted file]
target/linux/mvebu/patches-4.4/205-arm_mvebu_enable_pwm_in_defconfig.patch [deleted file]
target/linux/mvebu/patches-4.4/206-mvebu_wrt1900ac_use_pwm-fan_rather_than_gpio-fan.patch [deleted file]
target/linux/mvebu/patches-4.4/207-armada-385-rd-mtd-partitions.patch [deleted file]
target/linux/mvebu/patches-4.4/208-ARM-mvebu-385-ap-Add-partitions.patch [deleted file]
target/linux/mvebu/patches-4.4/209-clearfog_switch_node.patch [deleted file]
target/linux/mvebu/patches-4.4/210-ARM-dts-armada388-clearfog-add-SFP-module-support.patch [deleted file]
target/linux/mvebu/patches-4.4/300-reprobe_sfp_phy.patch [deleted file]
target/linux/mvebu/patches-4.4/400-mvneta-tx-queue-workaround.patch [deleted file]

diff --git a/target/linux/mvebu/config-4.4 b/target/linux/mvebu/config-4.4
deleted file mode 100644 (file)
index d819970..0000000
+++ /dev/null
@@ -1,437 +0,0 @@
-CONFIG_AHCI_MVEBU=y
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
-CONFIG_ARCH_HAS_SG_CHAIN=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-# CONFIG_ARCH_MULTI_CPU_AUTO is not set
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_MVEBU=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
-CONFIG_ARM=y
-CONFIG_ARMADA_370_CLK=y
-CONFIG_ARMADA_370_XP_TIMER=y
-CONFIG_ARMADA_38X_CLK=y
-CONFIG_ARMADA_THERMAL=y
-CONFIG_ARMADA_XP_CLK=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_ERRATA_720789=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-# CONFIG_ARM_LPAE is not set
-CONFIG_ARM_MVEBU_V7_CPUIDLE=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-# CONFIG_ARM_THUMBEE is not set
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
-CONFIG_ATA=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BOUNCE=y
-# CONFIG_CACHE_FEROCEON_L2 is not set
-CONFIG_CACHE_L2X0=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_OF=y
-CONFIG_CLKSRC_PROBE=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-# CONFIG_CPU_BIG_ENDIAN is not set
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_GOV_COMMON=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PJ4B=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_ABLK_HELPER=y
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_AES_ARM=y
-CONFIG_CRYPTO_AES_ARM_BS=y
-# CONFIG_CRYPTO_AES_ARM_CE is not set
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_DEV_MARVELL_CESA=y
-# CONFIG_CRYPTO_GHASH_ARM_CE is not set
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_NULL2=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA1_ARM=y
-# CONFIG_CRYPTO_SHA1_ARM_CE is not set
-CONFIG_CRYPTO_SHA1_ARM_NEON=y
-CONFIG_CRYPTO_SHA256_ARM=y
-# CONFIG_CRYPTO_SHA2_ARM_CE is not set
-CONFIG_CRYPTO_SHA512_ARM=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
-CONFIG_DEBUG_MVEBU_UART0=y
-# CONFIG_DEBUG_MVEBU_UART0_ALTERNATE is not set
-# CONFIG_DEBUG_MVEBU_UART1_ALTERNATE is not set
-CONFIG_DEBUG_UART_8250=y
-# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set
-CONFIG_DEBUG_UART_8250_SHIFT=2
-# CONFIG_DEBUG_UART_8250_WORD is not set
-CONFIG_DEBUG_UART_PHYS=0xd0012000
-CONFIG_DEBUG_UART_VIRT=0xfec12000
-CONFIG_DEBUG_UNCOMPRESS=y
-CONFIG_DEBUG_USER=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_ENGINE_RAID=y
-CONFIG_DMA_OF=y
-CONFIG_DTC=y
-# CONFIG_DW_DMAC_PCI is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EXT4_FS=y
-# CONFIG_F2FS_CHECK_FS is not set
-CONFIG_F2FS_FS=y
-# CONFIG_F2FS_FS_SECURITY is not set
-CONFIG_F2FS_FS_XATTR=y
-CONFIG_F2FS_STAT_FS=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FS_MBCACHE=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_MVEBU=y
-CONFIG_GPIO_MVEBU_PWM=y
-CONFIG_GPIO_PCA953X=y
-# CONFIG_GPIO_PCA953X_IRQ is not set
-CONFIG_GPIO_SYSFS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_AUDITSYSCALL=y
-CONFIG_HAVE_ARCH_BITREVERSE=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_ARM_SCU=y
-CONFIG_HAVE_ARM_TWD=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_OPTPROBES=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SMP=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HIGHMEM=y
-# CONFIG_HIGHPTE is not set
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HWBM=y
-CONFIG_HWMON=y
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MV64XXX=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IOMMU_HELPER=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_DEBUG=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_IWMMXT is not set
-CONFIG_JBD2=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_PCA963X=y
-CONFIG_LEDS_TLC591XX=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MACH_ARMADA_370=y
-# CONFIG_MACH_ARMADA_375 is not set
-CONFIG_MACH_ARMADA_38X=y
-# CONFIG_MACH_ARMADA_39X is not set
-CONFIG_MACH_ARMADA_XP=y
-# CONFIG_MACH_DOVE is not set
-CONFIG_MACH_MVEBU_ANY=y
-CONFIG_MACH_MVEBU_V7=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MANGLE_BOOTARGS=y
-CONFIG_MARVELL_PHY=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MDIO_I2C=y
-CONFIG_MEMORY=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGHT_HAVE_PCI=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_MVSDIO=y
-CONFIG_MMC_SDHCI=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_SDHCI_PXAV3=y
-# CONFIG_MMC_TIFM_SD is not set
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_PXA3xx=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-# CONFIG_MTD_UBI_FASTMAP is not set
-# CONFIG_MTD_UBI_GLUEBI is not set
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_MVEBU_CLK_COMMON=y
-CONFIG_MVEBU_CLK_COREDIV=y
-CONFIG_MVEBU_CLK_CPU=y
-CONFIG_MVEBU_DEVBUS=y
-CONFIG_MVEBU_MBUS=y
-CONFIG_MVMDIO=y
-CONFIG_MVNETA=y
-CONFIG_MVNETA_BM=y
-CONFIG_MVSW61XX_PHY=y
-CONFIG_MV_XOR=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NLS=y
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_NO_BOOTMEM=y
-CONFIG_NR_CPUS=4
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_ADDRESS_PCI=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_OF_RESERVED_MEM=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_ORION_WATCHDOG=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PCI=y
-# CONFIG_PCI_DOMAINS_GENERIC is not set
-CONFIG_PCI_MVEBU=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_ARMADA_370=y
-CONFIG_PINCTRL_ARMADA_38X=y
-CONFIG_PINCTRL_ARMADA_XP=y
-CONFIG_PINCTRL_MVEBU=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PJ4B_ERRATA_4742=y
-# CONFIG_PL310_ERRATA_588369 is not set
-# CONFIG_PL310_ERRATA_727915 is not set
-# CONFIG_PL310_ERRATA_753970 is not set
-# CONFIG_PL310_ERRATA_769419 is not set
-CONFIG_PLAT_ORION=y
-CONFIG_PM_OPP=y
-CONFIG_PWM=y
-CONFIG_PWM_SYSFS=y
-CONFIG_RATIONAL=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_ARMADA38X=y
-CONFIG_RTC_DRV_MV=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-CONFIG_SATA_AHCI_PLATFORM=y
-CONFIG_SATA_MV=y
-CONFIG_SCHED_HRTICK=y
-# CONFIG_SCHED_INFO is not set
-CONFIG_SCSI=y
-CONFIG_SENSORS_PWM_FAN=y
-CONFIG_SENSORS_TMP421=y
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SFP=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SOC_BUS=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_ORION=y
-CONFIG_SRAM=y
-CONFIG_SRCU=y
-CONFIG_SWCONFIG=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_STATS=y
-CONFIG_TREE_RCU=y
-CONFIG_UBIFS_FS=y
-# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-CONFIG_UBIFS_FS_LZO=y
-CONFIG_UBIFS_FS_ZLIB=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_ORION=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_LEDS_TRIGGER_USBPORT=y
-CONFIG_USB_PHY=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_MVEBU=y
-CONFIG_USB_XHCI_PCI=y
-CONFIG_USB_XHCI_PLATFORM=y
-CONFIG_USE_OF=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA_FLAG=0
diff --git a/target/linux/mvebu/patches-4.4/002-add_powertables.patch b/target/linux/mvebu/patches-4.4/002-add_powertables.patch
deleted file mode 100644 (file)
index a5a47e4..0000000
+++ /dev/null
@@ -1,748 +0,0 @@
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -86,12 +86,100 @@
-                       pcie@2,0 {
-                               /* Port 0, Lane 1 */
-                               status = "okay";
-+
-+                              mwlwifi {
-+                                      marvell,5ghz = <0>;
-+                                      marvell,chainmask = <4 4>;
-+                                      marvell,powertable {
-+                                              FCC =
-+                                                      <1 0 0x17 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <2 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <3 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <4 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <5 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <6 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <7 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <8 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <9 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <10 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <11 0 0x17 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>;
-+
-+                                              ETSI =
-+                                                      <1 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <2 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <3 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <4 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <5 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <6 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <7 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <8 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <9 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <10 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <11 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <12 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <13 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>;
-+                                      };
-+                              };
-                       };
-                       /* Second mini-PCIe port */
-                       pcie@3,0 {
-                               /* Port 0, Lane 3 */
-                               status = "okay";
-+
-+                              mwlwifi {
-+                                      marvell,2ghz = <0>;
-+                                      marvell,chainmask = <4 4>;
-+                                      marvell,powertable {
-+                                              FCC =
-+                                                      <36 0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+                                                      <40 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+                                                      <44 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+                                                      <48 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+                                                      <52 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
-+                                                      <56 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
-+                                                      <60 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
-+                                                      <64 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
-+                                                      <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <149 0 0x16 0x16 0x16 0x16 0x14 0x14 0x14 0x14 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <153 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <157 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <161 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <165 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>;
-+
-+                                              ETSI =
-+                                                      <36 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+                                                      <40 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+                                                      <44 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+                                                      <48 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+                                                      <52 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+                                                      <56 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+                                                      <60 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+                                                      <64 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+                                                      <100 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+                                                      <104 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+                                                      <108 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+                                                      <112 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+                                                      <116 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+                                                      <120 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+                                                      <124 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+                                                      <128 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+                                                      <132 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+                                                      <136 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+                                                      <140 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+                                                      <149 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>;
-+                                      };
-+                              };
-                       };
-               };
---- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
-@@ -100,6 +100,212 @@
-                               };
-                       };
-               };
-+
-+              pcie-controller {
-+                      pcie@1,0 {
-+                              mwlwifi {
-+                                      marvell,2ghz = <0>;
-+                                      marvell,chainmask = <4 4>;
-+                                      marvell,powertable {
-+                                              AU =
-+                                                      <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+                                                      <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+                                                      <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+                                                      <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+                                                      <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>;
-+                                              CA =
-+                                                      <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
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-+                                                      <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+                                                      <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
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-+                                                      <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
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-+                                                      <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
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-+                                                      <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+                                                      <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
-+                                              CN =
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-+                                                      <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
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-+                                                      <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>;
-+                                              ETSI =
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-+                                                      <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
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-+                                                      <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>;
-+                                              FCC =
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-+                                                      <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
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-+                                                      <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
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-+                                                      <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
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-+                                                      <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
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-+                                                      <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
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-+                                                      <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+                                                      <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+                                                      <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+                                                      <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+                                                      <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
-+                                      };
-+                              };
-+                      };
-+
-+                      pcie@2,0 {
-+                              mwlwifi {
-+                                      marvell,5ghz = <0>;
-+                                      marvell,chainmask = <4 4>;
-+                                      marvell,powertable {
-+                                              AU =
-+                                                      <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+                                              CA =
-+                                                      <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
-+                                              CN =
-+                                                      <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+                                              ETSI =
-+                                                      <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+                                              FCC =
-+                                                      <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
-+                                      };
-+                              };
-+                      };
-+              };
-       };
-       gpio-leds {
---- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
-@@ -100,6 +100,212 @@
-                               };
-                       };
-               };
-+
-+              pcie-controller {
-+                      pcie@1,0 {
-+                              mwlwifi {
-+                                      marvell,2ghz = <0>;
-+                                      marvell,chainmask = <2 2>;
-+                                      marvell,powertable {
-+                                              AU =
-+                                                      <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <100 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+                                                      <104 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+                                                      <108 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+                                                      <112 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+                                                      <116 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+                                                      <120 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+                                                      <124 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+                                                      <128 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+                                                      <132 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+                                                      <136 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+                                                      <140 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+                                                      <149 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
-+                                                      <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
-+                                                      <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
-+                                                      <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
-+                                                      <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>;
-+                                              CA =
-+                                                      <36 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
-+                                                      <40 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
-+                                                      <44 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
-+                                                      <48 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
-+                                                      <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+                                                      <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+                                                      <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+                                                      <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+                                                      <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>;
-+                                              CN =
-+                                                      <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <149 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <165 0 0x15 0x15 0x15 0x15 0x16 0x16 0x16 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>;
-+                                              ETSI =
-+                                                      <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+                                                      <149 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>;
-+                                              FCC =
-+                                                      <36 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <40 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <44 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <48 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+                                                      <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+                                                      <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+                                                      <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+                                                      <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>;
-+                                      };
-+                              };
-+                      };
-+
-+                      pcie@2,0 {
-+                              mwlwifi {
-+                                      marvell,5ghz = <0>;
-+                                      marvell,chainmask = <2 2>;
-+                                      marvell,powertable {
-+                                              AU =
-+                                                      <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
-+                                              CA =
-+                                                      <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x00 0x00 0x00 0x00 0 0xf>,
-+                                                      <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+                                                      <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+                                                      <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+                                                      <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+                                                      <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+                                                      <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+                                                      <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+                                                      <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+                                                      <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+                                                      <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x00 0x00 0x00 0x00 0 0xf>;
-+                                              CN =
-+                                                      <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <14 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
-+                                              ETSI =
-+                                                      <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
-+                                              FCC =
-+                                                      <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x0 0x0 0x0 0x0 0 0xf>;
-+                                      };
-+                              };
-+                      };
-+              };
-       };
-       gpio-leds {
---- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
-@@ -100,6 +100,212 @@
-                               };
-                       };
-               };
-+
-+              pcie-controller {
-+                      pcie@1,0 {
-+                              mwlwifi {
-+                                      marvell,2ghz = <0>;
-+                                      marvell,chainmask = <4 4>;
-+                                      marvell,powertable {
-+                                              AU =
-+                                                      <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+                                                      <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+                                                      <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+                                                      <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+                                                      <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+                                                      <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>;
-+                                              CA =
-+                                                      <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+                                                      <40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+                                                      <44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+                                                      <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+                                                      <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+                                                      <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+                                                      <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+                                                      <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+                                                      <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
-+                                              CN =
-+                                                      <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>;
-+                                              ETSI =
-+                                                      <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+                                                      <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>;
-+                                              FCC =
-+                                                      <36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>,
-+                                                      <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+                                                      <44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+                                                      <48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+                                                      <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+                                                      <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+                                                      <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+                                                      <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+                                                      <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+                                                      <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
-+                                      };
-+                              };
-+                      };
-+
-+                      pcie@2,0 {
-+                              mwlwifi {
-+                                      marvell,5ghz = <0>;
-+                                      marvell,chainmask = <4 4>;
-+                                      marvell,powertable {
-+                                              AU =
-+                                                      <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+                                              CA =
-+                                                      <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
-+                                              CN =
-+                                                      <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+                                              ETSI =
-+                                                      <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+                                              FCC =
-+                                                      <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+                                                      <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
-+                                      };
-+                              };
-+                      };
-+              };
-       };
-       gpio-leds {
diff --git a/target/linux/mvebu/patches-4.4/003-add_switch_nodes.patch b/target/linux/mvebu/patches-4.4/003-add_switch_nodes.patch
deleted file mode 100644 (file)
index 1502b6b..0000000
+++ /dev/null
@@ -1,40 +0,0 @@
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -467,6 +467,16 @@
-                       };
-               };
-       };
-+
-+      mvsw61xx {
-+              compatible = "marvell,88e6172";
-+              status = "okay";
-+              reg = <0x10>;
-+
-+              mii-bus = <&mdio>;
-+              cpu-port-0 = <5>;
-+              cpu-port-1 = <6>;
-+      };
- };
- &pinctrl {
---- a/arch/arm/boot/dts/armada-385-linksys.dtsi
-+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
-@@ -309,6 +309,18 @@
-                       };
-               };
-       };
-+
-+      mvsw61xx {
-+              #address-cells = <1>;
-+              #size-cells = <0>;
-+              compatible = "marvell,88e6176";
-+              status = "okay";
-+              reg = <0x10>;
-+
-+              mii-bus = <&mdio>;
-+              cpu-port-0 = <5>;
-+              cpu-port-1 = <6>;
-+      };
- };
- &pinctrl {
diff --git a/target/linux/mvebu/patches-4.4/010-build_new_dtbs.patch b/target/linux/mvebu/patches-4.4/010-build_new_dtbs.patch
deleted file mode 100644 (file)
index 6ba9ee6..0000000
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -748,6 +748,8 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
-       armada-385-db-ap.dtb \
-       armada-385-linksys-caiman.dtb \
-       armada-385-linksys-cobra.dtb \
-+      armada-385-linksys-rango.dtb \
-+      armada-385-linksys-shelby.dtb \
-       armada-388-db.dtb \
-       armada-388-gp.dtb \
-       armada-388-rd.dtb
diff --git a/target/linux/mvebu/patches-4.4/020-mtd-nand-pxa3xx_nand-add-support-for-partial-chunks.patch b/target/linux/mvebu/patches-4.4/020-mtd-nand-pxa3xx_nand-add-support-for-partial-chunks.patch
deleted file mode 100644 (file)
index 2e67097..0000000
+++ /dev/null
@@ -1,428 +0,0 @@
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Wed, 10 Feb 2016 14:54:21 +0100
-Subject: [PATCH] mtd: nand: pxa3xx_nand: add support for partial chunks
-
-This commit is needed to properly support the 8-bits ECC configuration
-with 4KB pages.
-
-When pages larger than 2 KB are used on platforms using the PXA3xx
-NAND controller, the reading/programming operations need to be split
-in chunks of 2 KBs or less because the controller FIFO is limited to
-about 2 KB (i.e a bit more than 2 KB to accommodate OOB data). Due to
-this requirement, the data layout on NAND is a bit strange, with ECC
-interleaved with data, at the end of each chunk.
-
-When a 4-bits ECC configuration is used with 4 KB pages, the physical
-data layout on the NAND looks like this:
-
-| 2048 data | 32 spare | 30 ECC | 2048 data | 32 spare | 30 ECC |
-
-So the data chunks have an equal size, 2080 bytes for each chunk,
-which the driver supports properly.
-
-When a 8-bits ECC configuration is used with 4KB pages, the physical
-data layout on the NAND looks like this:
-
-| 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 64 spare | 30 ECC |
-
-So, the spare area is stored in its own chunk, which has a different
-size than the other chunks. Since OOB is not used by UBIFS, the initial
-implementation of the driver has chosen to not support reading this
-additional "spare" chunk of data.
-
-Unfortunately, Marvell has chosen to store the BBT signature in the
-OOB area. Therefore, if the driver doesn't read this spare area, Linux
-has no way of finding the BBT. It thinks there is no BBT, and rewrites
-one, which U-Boot does not recognize, causing compatibility problems
-between the bootloader and the kernel in terms of NAND usage.
-
-To fix this, this commit implements the support for reading a partial
-last chunk. This support is currently only useful for the case of 8
-bits ECC with 4 KB pages, but it will be useful in the future to
-enable other configurations such as 12 bits and 16 bits ECC with 4 KB
-pages, or 8 bits ECC with 8 KB pages, etc. All those configurations
-have a "last" chunk that doesn't have the same size as the other
-chunks.
-
-In order to implement reading of the last chunk, this commit:
-
- - Adds a number of new fields to the pxa3xx_nand_info to describe how
-   many full chunks and how many chunks we have, the size of full
-   chunks and partial chunks, both in terms of data area and spare
-   area.
-
- - Fills in the step_chunk_size and step_spare_size variables to
-   describe how much data and spare should be read/written for the
-   current read/program step.
-
- - Reworks the state machine to accommodate doing the additional read
-   or program step when a last partial chunk is used.
-
-This commit has been tested on a Marvell Armada 398 DB board, with a
-4KB page NAND, tested in both 4 bits ECC and 8 bits ECC
-configurations. Robert Jarzmik has tested on some PXA platforms.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
-Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -228,15 +228,44 @@ struct pxa3xx_nand_info {
-       int                     use_spare;      /* use spare ? */
-       int                     need_wait;
--      unsigned int            data_size;      /* data to be read from FIFO */
--      unsigned int            chunk_size;     /* split commands chunk size */
--      unsigned int            oob_size;
-+      /* Amount of real data per full chunk */
-+      unsigned int            chunk_size;
-+
-+      /* Amount of spare data per full chunk */
-       unsigned int            spare_size;
-+
-+      /* Number of full chunks (i.e chunk_size + spare_size) */
-+      unsigned int            nfullchunks;
-+
-+      /*
-+       * Total number of chunks. If equal to nfullchunks, then there
-+       * are only full chunks. Otherwise, there is one last chunk of
-+       * size (last_chunk_size + last_spare_size)
-+       */
-+      unsigned int            ntotalchunks;
-+
-+      /* Amount of real data in the last chunk */
-+      unsigned int            last_chunk_size;
-+
-+      /* Amount of spare data in the last chunk */
-+      unsigned int            last_spare_size;
-+
-       unsigned int            ecc_size;
-       unsigned int            ecc_err_cnt;
-       unsigned int            max_bitflips;
-       int                     retcode;
-+      /*
-+       * Variables only valid during command
-+       * execution. step_chunk_size and step_spare_size is the
-+       * amount of real data and spare data in the current
-+       * chunk. cur_chunk is the current chunk being
-+       * read/programmed.
-+       */
-+      unsigned int            step_chunk_size;
-+      unsigned int            step_spare_size;
-+      unsigned int            cur_chunk;
-+
-       /* cached register value */
-       uint32_t                reg_ndcr;
-       uint32_t                ndtr0cs0;
-@@ -531,25 +560,6 @@ static int pxa3xx_nand_init(struct pxa3x
-       return 0;
- }
--/*
-- * Set the data and OOB size, depending on the selected
-- * spare and ECC configuration.
-- * Only applicable to READ0, READOOB and PAGEPROG commands.
-- */
--static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info,
--                              struct mtd_info *mtd)
--{
--      int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
--
--      info->data_size = mtd->writesize;
--      if (!oob_enable)
--              return;
--
--      info->oob_size = info->spare_size;
--      if (!info->use_ecc)
--              info->oob_size += info->ecc_size;
--}
--
- /**
-  * NOTE: it is a must to set ND_RUN firstly, then write
-  * command buffer, otherwise, it does not work.
-@@ -665,28 +675,28 @@ static void drain_fifo(struct pxa3xx_nan
- static void handle_data_pio(struct pxa3xx_nand_info *info)
- {
--      unsigned int do_bytes = min(info->data_size, info->chunk_size);
--
-       switch (info->state) {
-       case STATE_PIO_WRITING:
--              writesl(info->mmio_base + NDDB,
--                      info->data_buff + info->data_buff_pos,
--                      DIV_ROUND_UP(do_bytes, 4));
-+              if (info->step_chunk_size)
-+                      writesl(info->mmio_base + NDDB,
-+                              info->data_buff + info->data_buff_pos,
-+                              DIV_ROUND_UP(info->step_chunk_size, 4));
--              if (info->oob_size > 0)
-+              if (info->step_spare_size)
-                       writesl(info->mmio_base + NDDB,
-                               info->oob_buff + info->oob_buff_pos,
--                              DIV_ROUND_UP(info->oob_size, 4));
-+                              DIV_ROUND_UP(info->step_spare_size, 4));
-               break;
-       case STATE_PIO_READING:
--              drain_fifo(info,
--                         info->data_buff + info->data_buff_pos,
--                         DIV_ROUND_UP(do_bytes, 4));
-+              if (info->step_chunk_size)
-+                      drain_fifo(info,
-+                                 info->data_buff + info->data_buff_pos,
-+                                 DIV_ROUND_UP(info->step_chunk_size, 4));
--              if (info->oob_size > 0)
-+              if (info->step_spare_size)
-                       drain_fifo(info,
-                                  info->oob_buff + info->oob_buff_pos,
--                                 DIV_ROUND_UP(info->oob_size, 4));
-+                                 DIV_ROUND_UP(info->step_spare_size, 4));
-               break;
-       default:
-               dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
-@@ -695,9 +705,8 @@ static void handle_data_pio(struct pxa3x
-       }
-       /* Update buffer pointers for multi-page read/write */
--      info->data_buff_pos += do_bytes;
--      info->oob_buff_pos += info->oob_size;
--      info->data_size -= do_bytes;
-+      info->data_buff_pos += info->step_chunk_size;
-+      info->oob_buff_pos += info->step_spare_size;
- }
- static void pxa3xx_nand_data_dma_irq(void *data)
-@@ -738,8 +747,9 @@ static void start_data_dma(struct pxa3xx
-                               info->state);
-               BUG();
-       }
--      info->sg.length = info->data_size +
--              (info->oob_size ? info->spare_size + info->ecc_size : 0);
-+      info->sg.length = info->chunk_size;
-+      if (info->use_spare)
-+              info->sg.length += info->spare_size + info->ecc_size;
-       dma_map_sg(info->dma_chan->device->dev, &info->sg, 1, info->dma_dir);
-       tx = dmaengine_prep_slave_sg(info->dma_chan, &info->sg, 1, direction,
-@@ -900,9 +910,11 @@ static void prepare_start_command(struct
-       /* reset data and oob column point to handle data */
-       info->buf_start         = 0;
-       info->buf_count         = 0;
--      info->oob_size          = 0;
-       info->data_buff_pos     = 0;
-       info->oob_buff_pos      = 0;
-+      info->step_chunk_size   = 0;
-+      info->step_spare_size   = 0;
-+      info->cur_chunk         = 0;
-       info->use_ecc           = 0;
-       info->use_spare         = 1;
-       info->retcode           = ERR_NONE;
-@@ -914,8 +926,6 @@ static void prepare_start_command(struct
-       case NAND_CMD_READ0:
-       case NAND_CMD_PAGEPROG:
-               info->use_ecc = 1;
--      case NAND_CMD_READOOB:
--              pxa3xx_set_datasize(info, mtd);
-               break;
-       case NAND_CMD_PARAM:
-               info->use_spare = 0;
-@@ -974,6 +984,14 @@ static int prepare_set_command(struct px
-               if (command == NAND_CMD_READOOB)
-                       info->buf_start += mtd->writesize;
-+              if (info->cur_chunk < info->nfullchunks) {
-+                      info->step_chunk_size = info->chunk_size;
-+                      info->step_spare_size = info->spare_size;
-+              } else {
-+                      info->step_chunk_size = info->last_chunk_size;
-+                      info->step_spare_size = info->last_spare_size;
-+              }
-+
-               /*
-                * Multiple page read needs an 'extended command type' field,
-                * which is either naked-read or last-read according to the
-@@ -985,8 +1003,8 @@ static int prepare_set_command(struct px
-                       info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8)
-                                       | NDCB0_LEN_OVRD
-                                       | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
--                      info->ndcb3 = info->chunk_size +
--                                    info->oob_size;
-+                      info->ndcb3 = info->step_chunk_size +
-+                              info->step_spare_size;
-               }
-               set_command_address(info, mtd->writesize, column, page_addr);
-@@ -1006,8 +1024,6 @@ static int prepare_set_command(struct px
-                               | NDCB0_EXT_CMD_TYPE(ext_cmd_type)
-                               | addr_cycle
-                               | command;
--                      /* No data transfer in this case */
--                      info->data_size = 0;
-                       exec_cmd = 1;
-               }
-               break;
-@@ -1019,6 +1035,14 @@ static int prepare_set_command(struct px
-                       break;
-               }
-+              if (info->cur_chunk < info->nfullchunks) {
-+                      info->step_chunk_size = info->chunk_size;
-+                      info->step_spare_size = info->spare_size;
-+              } else {
-+                      info->step_chunk_size = info->last_chunk_size;
-+                      info->step_spare_size = info->last_spare_size;
-+              }
-+
-               /* Second command setting for large pages */
-               if (mtd->writesize > PAGE_CHUNK_SIZE) {
-                       /*
-@@ -1029,14 +1053,14 @@ static int prepare_set_command(struct px
-                       info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
-                                       | NDCB0_LEN_OVRD
-                                       | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
--                      info->ndcb3 = info->chunk_size +
--                                    info->oob_size;
-+                      info->ndcb3 = info->step_chunk_size +
-+                                    info->step_spare_size;
-                       /*
-                        * This is the command dispatch that completes a chunked
-                        * page program operation.
-                        */
--                      if (info->data_size == 0) {
-+                      if (info->cur_chunk == info->ntotalchunks) {
-                               info->ndcb0 = NDCB0_CMD_TYPE(0x1)
-                                       | NDCB0_EXT_CMD_TYPE(ext_cmd_type)
-                                       | command;
-@@ -1063,7 +1087,7 @@ static int prepare_set_command(struct px
-                               | command;
-               info->ndcb1 = (column & 0xFF);
-               info->ndcb3 = INIT_BUFFER_SIZE;
--              info->data_size = INIT_BUFFER_SIZE;
-+              info->step_chunk_size = INIT_BUFFER_SIZE;
-               break;
-       case NAND_CMD_READID:
-@@ -1073,7 +1097,7 @@ static int prepare_set_command(struct px
-                               | command;
-               info->ndcb1 = (column & 0xFF);
--              info->data_size = 8;
-+              info->step_chunk_size = 8;
-               break;
-       case NAND_CMD_STATUS:
-               info->buf_count = 1;
-@@ -1081,7 +1105,7 @@ static int prepare_set_command(struct px
-                               | NDCB0_ADDR_CYC(1)
-                               | command;
--              info->data_size = 8;
-+              info->step_chunk_size = 8;
-               break;
-       case NAND_CMD_ERASE1:
-@@ -1220,6 +1244,7 @@ static void nand_cmdfunc_extended(struct
-       init_completion(&info->dev_ready);
-       do {
-               info->state = STATE_PREPARED;
-+
-               exec_cmd = prepare_set_command(info, command, ext_cmd_type,
-                                              column, page_addr);
-               if (!exec_cmd) {
-@@ -1239,22 +1264,30 @@ static void nand_cmdfunc_extended(struct
-                       break;
-               }
-+              /* Only a few commands need several steps */
-+              if (command != NAND_CMD_PAGEPROG &&
-+                  command != NAND_CMD_READ0    &&
-+                  command != NAND_CMD_READOOB)
-+                      break;
-+
-+              info->cur_chunk++;
-+
-               /* Check if the sequence is complete */
--              if (info->data_size == 0 && command != NAND_CMD_PAGEPROG)
-+              if (info->cur_chunk == info->ntotalchunks && command != NAND_CMD_PAGEPROG)
-                       break;
-               /*
-                * After a splitted program command sequence has issued
-                * the command dispatch, the command sequence is complete.
-                */
--              if (info->data_size == 0 &&
-+              if (info->cur_chunk == (info->ntotalchunks + 1) &&
-                   command == NAND_CMD_PAGEPROG &&
-                   ext_cmd_type == EXT_CMD_TYPE_DISPATCH)
-                       break;
-               if (command == NAND_CMD_READ0 || command == NAND_CMD_READOOB) {
-                       /* Last read: issue a 'last naked read' */
--                      if (info->data_size == info->chunk_size)
-+                      if (info->cur_chunk == info->ntotalchunks - 1)
-                               ext_cmd_type = EXT_CMD_TYPE_LAST_RW;
-                       else
-                               ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
-@@ -1264,7 +1297,7 @@ static void nand_cmdfunc_extended(struct
-                * the command dispatch must be issued to complete.
-                */
-               } else if (command == NAND_CMD_PAGEPROG &&
--                         info->data_size == 0) {
-+                         info->cur_chunk == info->ntotalchunks) {
-                               ext_cmd_type = EXT_CMD_TYPE_DISPATCH;
-               }
-       } while (1);
-@@ -1514,6 +1547,8 @@ static int pxa_ecc_init(struct pxa3xx_na
-                       int strength, int ecc_stepsize, int page_size)
- {
-       if (strength == 1 && ecc_stepsize == 512 && page_size == 2048) {
-+              info->nfullchunks = 1;
-+              info->ntotalchunks = 1;
-               info->chunk_size = 2048;
-               info->spare_size = 40;
-               info->ecc_size = 24;
-@@ -1522,6 +1557,8 @@ static int pxa_ecc_init(struct pxa3xx_na
-               ecc->strength = 1;
-       } else if (strength == 1 && ecc_stepsize == 512 && page_size == 512) {
-+              info->nfullchunks = 1;
-+              info->ntotalchunks = 1;
-               info->chunk_size = 512;
-               info->spare_size = 8;
-               info->ecc_size = 8;
-@@ -1535,6 +1572,8 @@ static int pxa_ecc_init(struct pxa3xx_na
-        */
-       } else if (strength == 4 && ecc_stepsize == 512 && page_size == 2048) {
-               info->ecc_bch = 1;
-+              info->nfullchunks = 1;
-+              info->ntotalchunks = 1;
-               info->chunk_size = 2048;
-               info->spare_size = 32;
-               info->ecc_size = 32;
-@@ -1545,6 +1584,8 @@ static int pxa_ecc_init(struct pxa3xx_na
-       } else if (strength == 4 && ecc_stepsize == 512 && page_size == 4096) {
-               info->ecc_bch = 1;
-+              info->nfullchunks = 2;
-+              info->ntotalchunks = 2;
-               info->chunk_size = 2048;
-               info->spare_size = 32;
-               info->ecc_size = 32;
-@@ -1559,8 +1600,12 @@ static int pxa_ecc_init(struct pxa3xx_na
-        */
-       } else if (strength == 8 && ecc_stepsize == 512 && page_size == 4096) {
-               info->ecc_bch = 1;
-+              info->nfullchunks = 4;
-+              info->ntotalchunks = 5;
-               info->chunk_size = 1024;
-               info->spare_size = 0;
-+              info->last_chunk_size = 0;
-+              info->last_spare_size = 64;
-               info->ecc_size = 32;
-               ecc->mode = NAND_ECC_HW;
-               ecc->size = info->chunk_size;
diff --git a/target/linux/mvebu/patches-4.4/021-mtd-pxa3xx_nand-Increase-the-initial-chunk-size.patch b/target/linux/mvebu/patches-4.4/021-mtd-pxa3xx_nand-Increase-the-initial-chunk-size.patch
deleted file mode 100644 (file)
index 0b0e047..0000000
+++ /dev/null
@@ -1,42 +0,0 @@
-From: =?UTF-8?q?Ezequiel=20Garc=C3=ADa?= <ezequiel@vanguardiasur.com.ar>
-Date: Wed, 4 Nov 2015 13:13:41 -0300
-Subject: [PATCH] mtd: pxa3xx_nand: Increase the initial chunk size
-
-The chunk size represents the size of the data chunks, which
-is used by the controllers that allow to split transfered data.
-
-However, the initial chunk size is used in a non-splitted way,
-during device identification. Therefore, it must be large enough
-for all the NAND commands issued during device identification.
-This includes NAND_CMD_PARAM which was recently changed to
-transfer up to 2048 bytes (for the redundant parameter pages).
-
-Thus, the initial chunk size should be 2048 as well.
-
-On Armada 370/XP platforms (NFCv2) booted without the keep-config
-devicetree property, this commit fixes a timeout on the NAND_CMD_PARAM
-command:
-
-  [..]
-  pxa3xx-nand f10d0000.nand: This platform can't do DMA on this device
-  pxa3xx-nand f10d0000.nand: Wait time out!!!
-  nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x38
-  nand: Micron MT29F8G08ABABAWP
-  nand: 1024 MiB, SLC, erase size: 512 KiB, page size: 4096, OOB size: 224
-
-Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
-Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1637,7 +1637,7 @@ static int pxa3xx_nand_scan(struct mtd_i
-               goto KEEP_CONFIG;
-       /* Set a default chunk size */
--      info->chunk_size = 512;
-+      info->chunk_size = PAGE_CHUNK_SIZE;
-       ret = pxa3xx_nand_config_flash(info);
-       if (ret)
diff --git a/target/linux/mvebu/patches-4.4/022-mtd-pxa3xx_nand-Fix-initial-controller-configuration.patch b/target/linux/mvebu/patches-4.4/022-mtd-pxa3xx_nand-Fix-initial-controller-configuration.patch
deleted file mode 100644 (file)
index 7d07fb9..0000000
+++ /dev/null
@@ -1,104 +0,0 @@
-From: =?UTF-8?q?Ezequiel=20Garc=C3=ADa?= <ezequiel@vanguardiasur.com.ar>
-Date: Wed, 4 Nov 2015 13:13:42 -0300
-Subject: [PATCH] mtd: pxa3xx_nand: Fix initial controller configuration
-
-The Data Flash Control Register (NDCR) contains two types
-of parameters: those that are needed for device identification,
-and those that can only be set after device identification.
-
-Therefore, the driver can't set them all at once and instead
-needs to configure the first group before nand_scan_ident()
-and the second group later.
-
-Let's split pxa3xx_nand_config in two halves, and set the
-parameters that depend on the device geometry once this is known.
-
-Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1420,34 +1420,43 @@ static int pxa3xx_nand_waitfunc(struct m
-       return NAND_STATUS_READY;
- }
--static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info)
-+static int pxa3xx_nand_config_ident(struct pxa3xx_nand_info *info)
- {
-       struct platform_device *pdev = info->pdev;
-       struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
--      struct pxa3xx_nand_host *host = info->host[info->cs];
--      struct mtd_info *mtd = host->mtd;
--      struct nand_chip *chip = mtd->priv;
--      /* configure default flash values */
-+      /* Configure default flash values */
-+      info->chunk_size = PAGE_CHUNK_SIZE;
-       info->reg_ndcr = 0x0; /* enable all interrupts */
-       info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
-       info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
--      info->reg_ndcr |= NDCR_SPARE_EN; /* enable spare by default */
-+      info->reg_ndcr |= NDCR_SPARE_EN;
-+
-+      return 0;
-+}
-+
-+static void pxa3xx_nand_config_tail(struct pxa3xx_nand_info *info)
-+{
-+      struct pxa3xx_nand_host *host = info->host[info->cs];
-+      struct mtd_info *mtd = host->mtd;
-+      struct nand_chip *chip = mtd->priv;
-+
-       info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
-       info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0;
-       info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0;
--
--      return 0;
- }
- static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
- {
-+      struct platform_device *pdev = info->pdev;
-+      struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
-       uint32_t ndcr = nand_readl(info, NDCR);
-       /* Set an initial chunk size */
-       info->chunk_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
-       info->reg_ndcr = ndcr &
-               ~(NDCR_INT_MASK | NDCR_ND_ARB_EN | NFCV1_NDCR_ARB_CNTL);
-+      info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
-       info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
-       info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
-       return 0;
-@@ -1636,10 +1645,7 @@ static int pxa3xx_nand_scan(struct mtd_i
-       if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
-               goto KEEP_CONFIG;
--      /* Set a default chunk size */
--      info->chunk_size = PAGE_CHUNK_SIZE;
--
--      ret = pxa3xx_nand_config_flash(info);
-+      ret = pxa3xx_nand_config_ident(info);
-       if (ret)
-               return ret;
-@@ -1652,7 +1658,6 @@ static int pxa3xx_nand_scan(struct mtd_i
-       }
- KEEP_CONFIG:
--      info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
-       if (info->reg_ndcr & NDCR_DWIDTH_M)
-               chip->options |= NAND_BUSWIDTH_16;
-@@ -1737,6 +1742,10 @@ KEEP_CONFIG:
-               host->row_addr_cycles = 3;
-       else
-               host->row_addr_cycles = 2;
-+
-+      if (!pdata->keep_config)
-+              pxa3xx_nand_config_tail(info);
-+
-       return nand_scan_tail(mtd);
- }
diff --git a/target/linux/mvebu/patches-4.4/023-bus-mvebu-mbus-provide-api-for-obtaining-IO-and-DRAM.patch b/target/linux/mvebu/patches-4.4/023-bus-mvebu-mbus-provide-api-for-obtaining-IO-and-DRAM.patch
deleted file mode 100644 (file)
index 58687f3..0000000
+++ /dev/null
@@ -1,94 +0,0 @@
-From: Marcin Wojtas <mw@semihalf.com>
-Date: Mon, 14 Mar 2016 09:39:02 +0100
-Subject: [PATCH] bus: mvebu-mbus: provide api for obtaining IO and DRAM window
- information
-
-This commit enables finding appropriate mbus window and obtaining its
-target id and attribute for given physical address in two separate
-routines, both for IO and DRAM windows. This functionality
-is needed for Armada XP/38x Network Controller's Buffer Manager and
-PnC configuration.
-
-[gregory.clement@free-electrons.com: Fix size test for
-mvebu_mbus_get_dram_win_info]
-
-Signed-off-by: Marcin Wojtas <mw@semihalf.com>
-[DRAM window information reference in LKv3.10]
-Signed-off-by: Evan Wang <xswang@marvell.com>
-Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
-
---- a/drivers/bus/mvebu-mbus.c
-+++ b/drivers/bus/mvebu-mbus.c
-@@ -948,6 +948,58 @@ void mvebu_mbus_get_pcie_io_aperture(str
-       *res = mbus_state.pcie_io_aperture;
- }
-+int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr)
-+{
-+      const struct mbus_dram_target_info *dram;
-+      int i;
-+
-+      /* Get dram info */
-+      dram = mv_mbus_dram_info();
-+      if (!dram) {
-+              pr_err("missing DRAM information\n");
-+              return -ENODEV;
-+      }
-+
-+      /* Try to find matching DRAM window for phyaddr */
-+      for (i = 0; i < dram->num_cs; i++) {
-+              const struct mbus_dram_window *cs = dram->cs + i;
-+
-+              if (cs->base <= phyaddr &&
-+                      phyaddr <= (cs->base + cs->size - 1)) {
-+                      *target = dram->mbus_dram_target_id;
-+                      *attr = cs->mbus_attr;
-+                      return 0;
-+              }
-+      }
-+
-+      pr_err("invalid dram address 0x%x\n", phyaddr);
-+      return -EINVAL;
-+}
-+EXPORT_SYMBOL_GPL(mvebu_mbus_get_dram_win_info);
-+
-+int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target,
-+                             u8 *attr)
-+{
-+      int win;
-+
-+      for (win = 0; win < mbus_state.soc->num_wins; win++) {
-+              u64 wbase;
-+              int enabled;
-+
-+              mvebu_mbus_read_window(&mbus_state, win, &enabled, &wbase,
-+                                     size, target, attr, NULL);
-+
-+              if (!enabled)
-+                      continue;
-+
-+              if (wbase <= phyaddr && phyaddr <= wbase + *size)
-+                      return win;
-+      }
-+
-+      return -EINVAL;
-+}
-+EXPORT_SYMBOL_GPL(mvebu_mbus_get_io_win_info);
-+
- static __init int mvebu_mbus_debugfs_init(void)
- {
-       struct mvebu_mbus_state *s = &mbus_state;
---- a/include/linux/mbus.h
-+++ b/include/linux/mbus.h
-@@ -69,6 +69,9 @@ static inline const struct mbus_dram_tar
- int mvebu_mbus_save_cpu_target(u32 *store_addr);
- void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
- void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
-+int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr);
-+int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target,
-+                             u8 *attr);
- int mvebu_mbus_add_window_remap_by_id(unsigned int target,
-                                     unsigned int attribute,
-                                     phys_addr_t base, size_t size,
diff --git a/target/linux/mvebu/patches-4.4/030-mvneta-consolidate-autoneg-enabling.patch b/target/linux/mvebu/patches-4.4/030-mvneta-consolidate-autoneg-enabling.patch
deleted file mode 100644 (file)
index 1d98c7d..0000000
+++ /dev/null
@@ -1,55 +0,0 @@
-From: Stas Sergeev <stsp@list.ru>
-Date: Wed, 2 Dec 2015 20:33:56 +0300
-Subject: [PATCH] mvneta: consolidate autoneg enabling
-
-This moves autoneg-related bit manipulations to the single place.
-
-CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-CC: netdev@vger.kernel.org
-CC: linux-kernel@vger.kernel.org
-
-Signed-off-by: Stas Sergeev <stsp@users.sourceforge.net>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -1067,15 +1067,28 @@ static void mvneta_defaults_set(struct m
-                      MVNETA_GMAC_AN_SPEED_EN |
-                      MVNETA_GMAC_AN_DUPLEX_EN;
-               mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
-+
-               val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
-               val |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
-               mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
-+
-+              val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
-+              val |= MVNETA_GMAC2_INBAND_AN_ENABLE;
-+              mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
-       } else {
-               val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
-               val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE |
-                      MVNETA_GMAC_AN_SPEED_EN |
-                      MVNETA_GMAC_AN_DUPLEX_EN);
-               mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
-+
-+              val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
-+              val &= ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
-+              mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
-+
-+              val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
-+              val &= ~MVNETA_GMAC2_INBAND_AN_ENABLE;
-+              mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
-       }
-       mvneta_set_ucast_table(pp, -1);
-@@ -3230,9 +3243,6 @@ static int mvneta_port_power_up(struct m
-               return -EINVAL;
-       }
--      if (pp->use_inband_status)
--              ctrl |= MVNETA_GMAC2_INBAND_AN_ENABLE;
--
-       /* Cancel Port Reset */
-       ctrl &= ~MVNETA_GMAC2_PORT_RESET;
-       mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
diff --git a/target/linux/mvebu/patches-4.4/031-mvneta-implement-ethtool-autonegotiation-control.patch b/target/linux/mvebu/patches-4.4/031-mvneta-implement-ethtool-autonegotiation-control.patch
deleted file mode 100644 (file)
index 626b511..0000000
+++ /dev/null
@@ -1,165 +0,0 @@
-From: Stas Sergeev <stsp@list.ru>
-Date: Wed, 2 Dec 2015 20:35:11 +0300
-Subject: [PATCH] mvneta: implement ethtool autonegotiation control
-
-This patch allows to do
-ethtool -s eth0 autoneg off
-ethtool -s eth0 autoneg on
-to disable or enable autonegotiation at run-time.
-Without that functionality, the only way to control the autonegotiation
-is to modify the device tree.
-
-This is needed if you plan to use the same kernel with
-different ethernet switches, the ones that support the in-band
-status and the ones that not.
-
-CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-CC: netdev@vger.kernel.org
-CC: linux-kernel@vger.kernel.org
-
-Signed-off-by: Stas Sergeev <stsp@users.sourceforge.net>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -371,7 +371,7 @@ struct mvneta_port {
-       unsigned int duplex;
-       unsigned int speed;
-       unsigned int tx_csum_limit;
--      int use_inband_status:1;
-+      unsigned int use_inband_status:1;
-       u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
- };
-@@ -973,6 +973,44 @@ static void mvneta_set_other_mcast_table
-               mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
- }
-+static void mvneta_set_autoneg(struct mvneta_port *pp, int enable)
-+{
-+      u32 val;
-+
-+      if (enable) {
-+              val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
-+              val &= ~(MVNETA_GMAC_FORCE_LINK_PASS |
-+                       MVNETA_GMAC_FORCE_LINK_DOWN |
-+                       MVNETA_GMAC_AN_FLOW_CTRL_EN);
-+              val |= MVNETA_GMAC_INBAND_AN_ENABLE |
-+                     MVNETA_GMAC_AN_SPEED_EN |
-+                     MVNETA_GMAC_AN_DUPLEX_EN;
-+              mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
-+
-+              val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
-+              val |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
-+              mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
-+
-+              val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
-+              val |= MVNETA_GMAC2_INBAND_AN_ENABLE;
-+              mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
-+      } else {
-+              val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
-+              val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE |
-+                     MVNETA_GMAC_AN_SPEED_EN |
-+                     MVNETA_GMAC_AN_DUPLEX_EN);
-+              mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
-+
-+              val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
-+              val &= ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
-+              mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
-+
-+              val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
-+              val &= ~MVNETA_GMAC2_INBAND_AN_ENABLE;
-+              mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
-+      }
-+}
-+
- /* This method sets defaults to the NETA port:
-  *    Clears interrupt Cause and Mask registers.
-  *    Clears all MAC tables.
-@@ -1058,39 +1096,7 @@ static void mvneta_defaults_set(struct m
-       val &= ~MVNETA_PHY_POLLING_ENABLE;
-       mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
--      if (pp->use_inband_status) {
--              val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
--              val &= ~(MVNETA_GMAC_FORCE_LINK_PASS |
--                       MVNETA_GMAC_FORCE_LINK_DOWN |
--                       MVNETA_GMAC_AN_FLOW_CTRL_EN);
--              val |= MVNETA_GMAC_INBAND_AN_ENABLE |
--                     MVNETA_GMAC_AN_SPEED_EN |
--                     MVNETA_GMAC_AN_DUPLEX_EN;
--              mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
--
--              val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
--              val |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
--              mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
--
--              val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
--              val |= MVNETA_GMAC2_INBAND_AN_ENABLE;
--              mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
--      } else {
--              val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
--              val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE |
--                     MVNETA_GMAC_AN_SPEED_EN |
--                     MVNETA_GMAC_AN_DUPLEX_EN);
--              mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
--
--              val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
--              val &= ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
--              mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
--
--              val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
--              val &= ~MVNETA_GMAC2_INBAND_AN_ENABLE;
--              mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
--      }
--
-+      mvneta_set_autoneg(pp, pp->use_inband_status);
-       mvneta_set_ucast_table(pp, -1);
-       mvneta_set_special_mcast_table(pp, -1);
-       mvneta_set_other_mcast_table(pp, -1);
-@@ -2956,10 +2962,43 @@ int mvneta_ethtool_get_settings(struct n
- int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
- {
-       struct mvneta_port *pp = netdev_priv(dev);
-+      struct phy_device *phydev = pp->phy_dev;
--      if (!pp->phy_dev)
-+      if (!phydev)
-               return -ENODEV;
-+      if ((cmd->autoneg == AUTONEG_ENABLE) != pp->use_inband_status) {
-+              u32 val;
-+
-+              mvneta_set_autoneg(pp, cmd->autoneg == AUTONEG_ENABLE);
-+
-+              if (cmd->autoneg == AUTONEG_DISABLE) {
-+                      val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
-+                      val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
-+                               MVNETA_GMAC_CONFIG_GMII_SPEED |
-+                               MVNETA_GMAC_CONFIG_FULL_DUPLEX);
-+
-+                      if (phydev->duplex)
-+                              val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
-+
-+                      if (phydev->speed == SPEED_1000)
-+                              val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
-+                      else if (phydev->speed == SPEED_100)
-+                              val |= MVNETA_GMAC_CONFIG_MII_SPEED;
-+
-+                      mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
-+              }
-+
-+              pp->use_inband_status = (cmd->autoneg == AUTONEG_ENABLE);
-+              netdev_info(pp->dev, "autoneg status set to %i\n",
-+                          pp->use_inband_status);
-+
-+              if (netif_running(dev)) {
-+                      mvneta_port_down(pp);
-+                      mvneta_port_up(pp);
-+              }
-+      }
-+
-       return phy_ethtool_sset(pp->phy_dev, cmd);
- }
diff --git a/target/linux/mvebu/patches-4.4/032-net-mvneta-Make-the-default-queue-related-for-each-p.patch b/target/linux/mvebu/patches-4.4/032-net-mvneta-Make-the-default-queue-related-for-each-p.patch
deleted file mode 100644 (file)
index 54c9399..0000000
+++ /dev/null
@@ -1,131 +0,0 @@
-From: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Date: Wed, 9 Dec 2015 18:23:48 +0100
-Subject: [PATCH] net: mvneta: Make the default queue related for each port
-
-Instead of using the same default queue for all the port. Move it in the
-port struct. It will allow have a different default queue for each port.
-
-Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -356,6 +356,7 @@ struct mvneta_port {
-       struct mvneta_tx_queue *txqs;
-       struct net_device *dev;
-       struct notifier_block cpu_notifier;
-+      int rxq_def;
-       /* Core clock */
-       struct clk *clk;
-@@ -819,7 +820,7 @@ static void mvneta_port_up(struct mvneta
-       mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
-       /* Enable all initialized RXQs. */
--      mvreg_write(pp, MVNETA_RXQ_CMD, BIT(rxq_def));
-+      mvreg_write(pp, MVNETA_RXQ_CMD, BIT(pp->rxq_def));
- }
- /* Stop the Ethernet port activity */
-@@ -1067,7 +1068,7 @@ static void mvneta_defaults_set(struct m
-       mvreg_write(pp, MVNETA_ACC_MODE, val);
-       /* Update val of portCfg register accordingly with all RxQueue types */
--      val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
-+      val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
-       mvreg_write(pp, MVNETA_PORT_CONFIG, val);
-       val = 0;
-@@ -2101,19 +2102,19 @@ static void mvneta_set_rx_mode(struct ne
-       if (dev->flags & IFF_PROMISC) {
-               /* Accept all: Multicast + Unicast */
-               mvneta_rx_unicast_promisc_set(pp, 1);
--              mvneta_set_ucast_table(pp, rxq_def);
--              mvneta_set_special_mcast_table(pp, rxq_def);
--              mvneta_set_other_mcast_table(pp, rxq_def);
-+              mvneta_set_ucast_table(pp, pp->rxq_def);
-+              mvneta_set_special_mcast_table(pp, pp->rxq_def);
-+              mvneta_set_other_mcast_table(pp, pp->rxq_def);
-       } else {
-               /* Accept single Unicast */
-               mvneta_rx_unicast_promisc_set(pp, 0);
-               mvneta_set_ucast_table(pp, -1);
--              mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def);
-+              mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def);
-               if (dev->flags & IFF_ALLMULTI) {
-                       /* Accept all multicast */
--                      mvneta_set_special_mcast_table(pp, rxq_def);
--                      mvneta_set_other_mcast_table(pp, rxq_def);
-+                      mvneta_set_special_mcast_table(pp, pp->rxq_def);
-+                      mvneta_set_other_mcast_table(pp, pp->rxq_def);
-               } else {
-                       /* Accept only initialized multicast */
-                       mvneta_set_special_mcast_table(pp, -1);
-@@ -2122,7 +2123,7 @@ static void mvneta_set_rx_mode(struct ne
-                       if (!netdev_mc_empty(dev)) {
-                               netdev_for_each_mc_addr(ha, dev) {
-                                       mvneta_mcast_addr_set(pp, ha->addr,
--                                                            rxq_def);
-+                                                            pp->rxq_def);
-                               }
-                       }
-               }
-@@ -2205,7 +2206,7 @@ static int mvneta_poll(struct napi_struc
-        * RX packets
-        */
-       cause_rx_tx |= port->cause_rx_tx;
--      rx_done = mvneta_rx(pp, budget, &pp->rxqs[rxq_def]);
-+      rx_done = mvneta_rx(pp, budget, &pp->rxqs[pp->rxq_def]);
-       budget -= rx_done;
-       if (budget > 0) {
-@@ -2418,17 +2419,17 @@ static void mvneta_cleanup_txqs(struct m
- /* Cleanup all Rx queues */
- static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
- {
--      mvneta_rxq_deinit(pp, &pp->rxqs[rxq_def]);
-+      mvneta_rxq_deinit(pp, &pp->rxqs[pp->rxq_def]);
- }
- /* Init all Rx queues */
- static int mvneta_setup_rxqs(struct mvneta_port *pp)
- {
--      int err = mvneta_rxq_init(pp, &pp->rxqs[rxq_def]);
-+      int err = mvneta_rxq_init(pp, &pp->rxqs[pp->rxq_def]);
-       if (err) {
-               netdev_err(pp->dev, "%s: can't create rxq=%d\n",
--                         __func__, rxq_def);
-+                         __func__, pp->rxq_def);
-               mvneta_cleanup_rxqs(pp);
-               return err;
-       }
-@@ -2634,7 +2635,7 @@ static int mvneta_set_mac_addr(struct ne
-       mvneta_mac_addr_set(pp, dev->dev_addr, -1);
-       /* Set new addr in hw */
--      mvneta_mac_addr_set(pp, sockaddr->sa_data, rxq_def);
-+      mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def);
-       eth_commit_mac_addr_change(dev, addr);
-       return 0;
-@@ -2753,7 +2754,7 @@ static void mvneta_percpu_elect(struct m
- {
-       int online_cpu_idx, cpu, i = 0;
--      online_cpu_idx = rxq_def % num_online_cpus();
-+      online_cpu_idx = pp->rxq_def % num_online_cpus();
-       for_each_online_cpu(cpu) {
-               if (i == online_cpu_idx)
-@@ -3363,6 +3364,8 @@ static int mvneta_probe(struct platform_
-                                strcmp(managed, "in-band-status") == 0);
-       pp->cpu_notifier.notifier_call = mvneta_percpu_notifier;
-+      pp->rxq_def = rxq_def;
-+
-       pp->clk = devm_clk_get(&pdev->dev, NULL);
-       if (IS_ERR(pp->clk)) {
-               err = PTR_ERR(pp->clk);
diff --git a/target/linux/mvebu/patches-4.4/033-net-mvneta-Associate-RX-queues-with-each-CPU.patch b/target/linux/mvebu/patches-4.4/033-net-mvneta-Associate-RX-queues-with-each-CPU.patch
deleted file mode 100644 (file)
index 636c6cf..0000000
+++ /dev/null
@@ -1,278 +0,0 @@
-From: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Date: Wed, 9 Dec 2015 18:23:49 +0100
-Subject: [PATCH] net: mvneta: Associate RX queues with each CPU
-
-We enable the percpu interrupt for all the CPU and we just associate a
-CPU to a few queue at the neta level. The mapping between the CPUs and
-the queues is static. The queues are associated to the CPU module the
-number of CPUs. However currently we only use on RX queue for a given
-Ethernet port.
-
-Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -110,9 +110,16 @@
- #define MVNETA_CPU_MAP(cpu)                      (0x2540 + ((cpu) << 2))
- #define      MVNETA_CPU_RXQ_ACCESS_ALL_MASK      0x000000ff
- #define      MVNETA_CPU_TXQ_ACCESS_ALL_MASK      0x0000ff00
-+#define      MVNETA_CPU_RXQ_ACCESS(rxq)                BIT(rxq)
- #define MVNETA_RXQ_TIME_COAL_REG(q)              (0x2580 + ((q) << 2))
--/* Exception Interrupt Port/Queue Cause register */
-+/* Exception Interrupt Port/Queue Cause register
-+ *
-+ * Their behavior depend of the mapping done using the PCPX2Q
-+ * registers. For a given CPU if the bit associated to a queue is not
-+ * set, then for the register a read from this CPU will always return
-+ * 0 and a write won't do anything
-+ */
- #define MVNETA_INTR_NEW_CAUSE                    0x25a0
- #define MVNETA_INTR_NEW_MASK                     0x25a4
-@@ -820,7 +827,13 @@ static void mvneta_port_up(struct mvneta
-       mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
-       /* Enable all initialized RXQs. */
--      mvreg_write(pp, MVNETA_RXQ_CMD, BIT(pp->rxq_def));
-+      for (queue = 0; queue < rxq_number; queue++) {
-+              struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
-+
-+              if (rxq->descs != NULL)
-+                      q_map |= (1 << queue);
-+      }
-+      mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
- }
- /* Stop the Ethernet port activity */
-@@ -1026,6 +1039,7 @@ static void mvneta_defaults_set(struct m
-       int cpu;
-       int queue;
-       u32 val;
-+      int max_cpu = num_present_cpus();
-       /* Clear all Cause registers */
-       mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
-@@ -1041,13 +1055,23 @@ static void mvneta_defaults_set(struct m
-       /* Enable MBUS Retry bit16 */
-       mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
--      /* Set CPU queue access map - all CPUs have access to all RX
--       * queues and to all TX queues
-+      /* Set CPU queue access map. CPUs are assigned to the RX
-+       * queues modulo their number and all the TX queues are
-+       * assigned to the CPU associated to the default RX queue.
-        */
--      for_each_present_cpu(cpu)
--              mvreg_write(pp, MVNETA_CPU_MAP(cpu),
--                          (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
--                           MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
-+      for_each_present_cpu(cpu) {
-+              int rxq_map = 0, txq_map = 0;
-+              int rxq;
-+
-+              for (rxq = 0; rxq < rxq_number; rxq++)
-+                      if ((rxq % max_cpu) == cpu)
-+                              rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
-+
-+              if (cpu == rxq_def)
-+                      txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
-+
-+              mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
-+      }
-       /* Reset RX and TX DMAs */
-       mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
-@@ -2174,6 +2198,7 @@ static int mvneta_poll(struct napi_struc
- {
-       int rx_done = 0;
-       u32 cause_rx_tx;
-+      int rx_queue;
-       struct mvneta_port *pp = netdev_priv(napi->dev);
-       struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
-@@ -2205,8 +2230,15 @@ static int mvneta_poll(struct napi_struc
-       /* For the case where the last mvneta_poll did not process all
-        * RX packets
-        */
-+      rx_queue = fls(((cause_rx_tx >> 8) & 0xff));
-+
-       cause_rx_tx |= port->cause_rx_tx;
--      rx_done = mvneta_rx(pp, budget, &pp->rxqs[pp->rxq_def]);
-+
-+      if (rx_queue) {
-+              rx_queue = rx_queue - 1;
-+              rx_done = mvneta_rx(pp, budget, &pp->rxqs[rx_queue]);
-+      }
-+
-       budget -= rx_done;
-       if (budget > 0) {
-@@ -2419,19 +2451,27 @@ static void mvneta_cleanup_txqs(struct m
- /* Cleanup all Rx queues */
- static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
- {
--      mvneta_rxq_deinit(pp, &pp->rxqs[pp->rxq_def]);
-+      int queue;
-+
-+      for (queue = 0; queue < txq_number; queue++)
-+              mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
- }
- /* Init all Rx queues */
- static int mvneta_setup_rxqs(struct mvneta_port *pp)
- {
--      int err = mvneta_rxq_init(pp, &pp->rxqs[pp->rxq_def]);
--      if (err) {
--              netdev_err(pp->dev, "%s: can't create rxq=%d\n",
--                         __func__, pp->rxq_def);
--              mvneta_cleanup_rxqs(pp);
--              return err;
-+      int queue;
-+
-+      for (queue = 0; queue < rxq_number; queue++) {
-+              int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
-+
-+              if (err) {
-+                      netdev_err(pp->dev, "%s: can't create rxq=%d\n",
-+                                 __func__, queue);
-+                      mvneta_cleanup_rxqs(pp);
-+                      return err;
-+              }
-       }
-       return 0;
-@@ -2455,6 +2495,19 @@ static int mvneta_setup_txqs(struct mvne
-       return 0;
- }
-+static void mvneta_percpu_unmask_interrupt(void *arg)
-+{
-+      struct mvneta_port *pp = arg;
-+
-+      /* All the queue are unmasked, but actually only the ones
-+       * maped to this CPU will be unmasked
-+       */
-+      mvreg_write(pp, MVNETA_INTR_NEW_MASK,
-+                  MVNETA_RX_INTR_MASK_ALL |
-+                  MVNETA_TX_INTR_MASK_ALL |
-+                  MVNETA_MISCINTR_INTR_MASK);
-+}
-+
- static void mvneta_start_dev(struct mvneta_port *pp)
- {
-       unsigned int cpu;
-@@ -2472,11 +2525,10 @@ static void mvneta_start_dev(struct mvne
-               napi_enable(&port->napi);
-       }
--      /* Unmask interrupts */
--      mvreg_write(pp, MVNETA_INTR_NEW_MASK,
--                  MVNETA_RX_INTR_MASK(rxq_number) |
--                  MVNETA_TX_INTR_MASK(txq_number) |
--                  MVNETA_MISCINTR_INTR_MASK);
-+      /* Unmask interrupts. It has to be done from each CPU */
-+      for_each_online_cpu(cpu)
-+              smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt,
-+                                       pp, true);
-       mvreg_write(pp, MVNETA_INTR_MISC_MASK,
-                   MVNETA_CAUSE_PHY_STATUS_CHANGE |
-                   MVNETA_CAUSE_LINK_CHANGE |
-@@ -2752,22 +2804,35 @@ static void mvneta_percpu_disable(void *
- static void mvneta_percpu_elect(struct mvneta_port *pp)
- {
--      int online_cpu_idx, cpu, i = 0;
-+      int online_cpu_idx, max_cpu, cpu, i = 0;
-       online_cpu_idx = pp->rxq_def % num_online_cpus();
-+      max_cpu = num_present_cpus();
-       for_each_online_cpu(cpu) {
--              if (i == online_cpu_idx)
--                      /* Enable per-CPU interrupt on the one CPU we
--                       * just elected
-+              int rxq_map = 0, txq_map = 0;
-+              int rxq;
-+
-+              for (rxq = 0; rxq < rxq_number; rxq++)
-+                      if ((rxq % max_cpu) == cpu)
-+                              rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
-+
-+              if (i == online_cpu_idx) {
-+                      /* Map the default receive queue and transmit
-+                       * queue to the elected CPU
-                        */
--                      smp_call_function_single(cpu, mvneta_percpu_enable,
--                                              pp, true);
--              else
--                      /* Disable per-CPU interrupt on all the other CPU */
--                      smp_call_function_single(cpu, mvneta_percpu_disable,
--                                              pp, true);
-+                      rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def);
-+                      txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
-+              }
-+              mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
-+
-+              /* Update the interrupt mask on each CPU according the
-+               * new mapping
-+               */
-+              smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt,
-+                                       pp, true);
-               i++;
-+
-       }
- };
-@@ -2802,12 +2867,22 @@ static int mvneta_percpu_notifier(struct
-               mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
-               napi_enable(&port->napi);
-+
-+              /* Enable per-CPU interrupts on the CPU that is
-+               * brought up.
-+               */
-+              smp_call_function_single(cpu, mvneta_percpu_enable,
-+                                       pp, true);
-+
-               /* Enable per-CPU interrupt on the one CPU we care
-                * about.
-                */
-               mvneta_percpu_elect(pp);
--              /* Unmask all ethernet port interrupts */
-+              /* Unmask all ethernet port interrupts, as this
-+               * notifier is called for each CPU then the CPU to
-+               * Queue mapping is applied
-+               */
-               mvreg_write(pp, MVNETA_INTR_NEW_MASK,
-                       MVNETA_RX_INTR_MASK(rxq_number) |
-                       MVNETA_TX_INTR_MASK(txq_number) |
-@@ -2858,7 +2933,7 @@ static int mvneta_percpu_notifier(struct
- static int mvneta_open(struct net_device *dev)
- {
-       struct mvneta_port *pp = netdev_priv(dev);
--      int ret;
-+      int ret, cpu;
-       pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
-       pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
-@@ -2888,8 +2963,13 @@ static int mvneta_open(struct net_device
-        */
-       mvneta_percpu_disable(pp);
--      /* Elect a CPU to handle our RX queue interrupt */
--      mvneta_percpu_elect(pp);
-+      /* Enable per-CPU interrupt on all the CPU to handle our RX
-+       * queue interrupts
-+       */
-+      for_each_online_cpu(cpu)
-+              smp_call_function_single(cpu, mvneta_percpu_enable,
-+                                       pp, true);
-+
-       /* Register a CPU notifier to handle the case where our CPU
-        * might be taken offline.
diff --git a/target/linux/mvebu/patches-4.4/034-net-mvneta-Add-naive-RSS-support.patch b/target/linux/mvebu/patches-4.4/034-net-mvneta-Add-naive-RSS-support.patch
deleted file mode 100644 (file)
index 629c44c..0000000
+++ /dev/null
@@ -1,191 +0,0 @@
-From: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Date: Wed, 9 Dec 2015 18:23:50 +0100
-Subject: [PATCH] net: mvneta: Add naive RSS support
-
-This patch adds the support for the RSS related ethtool
-function. Currently it only uses one entry in the indirection table which
-allows associating an mvneta interface to a given CPU.
-
-Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Tested-by: Marcin Wojtas <mw@semihalf.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -261,6 +261,11 @@
- #define MVNETA_TX_MTU_MAX             0x3ffff
-+/* The RSS lookup table actually has 256 entries but we do not use
-+ * them yet
-+ */
-+#define MVNETA_RSS_LU_TABLE_SIZE      1
-+
- /* TSO header size */
- #define TSO_HEADER_SIZE 128
-@@ -382,6 +387,8 @@ struct mvneta_port {
-       unsigned int use_inband_status:1;
-       u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
-+
-+      u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
- };
- /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
-@@ -1067,7 +1074,7 @@ static void mvneta_defaults_set(struct m
-                       if ((rxq % max_cpu) == cpu)
-                               rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
--              if (cpu == rxq_def)
-+              if (cpu == pp->rxq_def)
-                       txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
-               mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
-@@ -2508,6 +2515,18 @@ static void mvneta_percpu_unmask_interru
-                   MVNETA_MISCINTR_INTR_MASK);
- }
-+static void mvneta_percpu_mask_interrupt(void *arg)
-+{
-+      struct mvneta_port *pp = arg;
-+
-+      /* All the queue are masked, but actually only the ones
-+       * maped to this CPU will be masked
-+       */
-+      mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
-+      mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
-+      mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
-+}
-+
- static void mvneta_start_dev(struct mvneta_port *pp)
- {
-       unsigned int cpu;
-@@ -3231,6 +3250,106 @@ static int mvneta_ethtool_get_sset_count
-       return -EOPNOTSUPP;
- }
-+static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev)
-+{
-+      return MVNETA_RSS_LU_TABLE_SIZE;
-+}
-+
-+static int mvneta_ethtool_get_rxnfc(struct net_device *dev,
-+                                  struct ethtool_rxnfc *info,
-+                                  u32 *rules __always_unused)
-+{
-+      switch (info->cmd) {
-+      case ETHTOOL_GRXRINGS:
-+              info->data =  rxq_number;
-+              return 0;
-+      case ETHTOOL_GRXFH:
-+              return -EOPNOTSUPP;
-+      default:
-+              return -EOPNOTSUPP;
-+      }
-+}
-+
-+static int  mvneta_config_rss(struct mvneta_port *pp)
-+{
-+      int cpu;
-+      u32 val;
-+
-+      netif_tx_stop_all_queues(pp->dev);
-+
-+      for_each_online_cpu(cpu)
-+              smp_call_function_single(cpu, mvneta_percpu_mask_interrupt,
-+                                       pp, true);
-+
-+      /* We have to synchronise on the napi of each CPU */
-+      for_each_online_cpu(cpu) {
-+              struct mvneta_pcpu_port *pcpu_port =
-+                      per_cpu_ptr(pp->ports, cpu);
-+
-+              napi_synchronize(&pcpu_port->napi);
-+              napi_disable(&pcpu_port->napi);
-+      }
-+
-+      pp->rxq_def = pp->indir[0];
-+
-+      /* Update unicast mapping */
-+      mvneta_set_rx_mode(pp->dev);
-+
-+      /* Update val of portCfg register accordingly with all RxQueue types */
-+      val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
-+      mvreg_write(pp, MVNETA_PORT_CONFIG, val);
-+
-+      /* Update the elected CPU matching the new rxq_def */
-+      mvneta_percpu_elect(pp);
-+
-+      /* We have to synchronise on the napi of each CPU */
-+      for_each_online_cpu(cpu) {
-+              struct mvneta_pcpu_port *pcpu_port =
-+                      per_cpu_ptr(pp->ports, cpu);
-+
-+              napi_enable(&pcpu_port->napi);
-+      }
-+
-+      netif_tx_start_all_queues(pp->dev);
-+
-+      return 0;
-+}
-+
-+static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
-+                                 const u8 *key, const u8 hfunc)
-+{
-+      struct mvneta_port *pp = netdev_priv(dev);
-+      /* We require at least one supported parameter to be changed
-+       * and no change in any of the unsupported parameters
-+       */
-+      if (key ||
-+          (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
-+              return -EOPNOTSUPP;
-+
-+      if (!indir)
-+              return 0;
-+
-+      memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE);
-+
-+      return mvneta_config_rss(pp);
-+}
-+
-+static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
-+                                 u8 *hfunc)
-+{
-+      struct mvneta_port *pp = netdev_priv(dev);
-+
-+      if (hfunc)
-+              *hfunc = ETH_RSS_HASH_TOP;
-+
-+      if (!indir)
-+              return 0;
-+
-+      memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE);
-+
-+      return 0;
-+}
-+
- static const struct net_device_ops mvneta_netdev_ops = {
-       .ndo_open            = mvneta_open,
-       .ndo_stop            = mvneta_stop,
-@@ -3255,6 +3374,10 @@ const struct ethtool_ops mvneta_eth_tool
-       .get_strings    = mvneta_ethtool_get_strings,
-       .get_ethtool_stats = mvneta_ethtool_get_stats,
-       .get_sset_count = mvneta_ethtool_get_sset_count,
-+      .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size,
-+      .get_rxnfc      = mvneta_ethtool_get_rxnfc,
-+      .get_rxfh       = mvneta_ethtool_get_rxfh,
-+      .set_rxfh       = mvneta_ethtool_set_rxfh,
- };
- /* Initialize hw */
-@@ -3446,6 +3569,8 @@ static int mvneta_probe(struct platform_
-       pp->rxq_def = rxq_def;
-+      pp->indir[0] = rxq_def;
-+
-       pp->clk = devm_clk_get(&pdev->dev, NULL);
-       if (IS_ERR(pp->clk)) {
-               err = PTR_ERR(pp->clk);
diff --git a/target/linux/mvebu/patches-4.4/035-net-mvneta-Configure-XPS-support.patch b/target/linux/mvebu/patches-4.4/035-net-mvneta-Configure-XPS-support.patch
deleted file mode 100644 (file)
index 5b35b64..0000000
+++ /dev/null
@@ -1,124 +0,0 @@
-From: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Date: Wed, 9 Dec 2015 18:23:51 +0100
-Subject: [PATCH] net: mvneta: Configure XPS support
-
-With this patch each CPU is associated with its own set of TX queues.
-
-It also setup the XPS with an initial configuration which set the
-affinity matching the hardware configuration.
-
-Suggested-by: Arnd Bergmann <arnd@arndb.de>
-Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -111,6 +111,7 @@
- #define      MVNETA_CPU_RXQ_ACCESS_ALL_MASK      0x000000ff
- #define      MVNETA_CPU_TXQ_ACCESS_ALL_MASK      0x0000ff00
- #define      MVNETA_CPU_RXQ_ACCESS(rxq)                BIT(rxq)
-+#define      MVNETA_CPU_TXQ_ACCESS(txq)                BIT(txq + 8)
- #define MVNETA_RXQ_TIME_COAL_REG(q)              (0x2580 + ((q) << 2))
- /* Exception Interrupt Port/Queue Cause register
-@@ -514,6 +515,9 @@ struct mvneta_tx_queue {
-       /* DMA address of TSO headers */
-       dma_addr_t tso_hdrs_phys;
-+
-+      /* Affinity mask for CPUs*/
-+      cpumask_t affinity_mask;
- };
- struct mvneta_rx_queue {
-@@ -1062,20 +1066,30 @@ static void mvneta_defaults_set(struct m
-       /* Enable MBUS Retry bit16 */
-       mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
--      /* Set CPU queue access map. CPUs are assigned to the RX
--       * queues modulo their number and all the TX queues are
--       * assigned to the CPU associated to the default RX queue.
-+      /* Set CPU queue access map. CPUs are assigned to the RX and
-+       * TX queues modulo their number. If there is only one TX
-+       * queue then it is assigned to the CPU associated to the
-+       * default RX queue.
-        */
-       for_each_present_cpu(cpu) {
-               int rxq_map = 0, txq_map = 0;
--              int rxq;
-+              int rxq, txq;
-               for (rxq = 0; rxq < rxq_number; rxq++)
-                       if ((rxq % max_cpu) == cpu)
-                               rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
--              if (cpu == pp->rxq_def)
--                      txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
-+              for (txq = 0; txq < txq_number; txq++)
-+                      if ((txq % max_cpu) == cpu)
-+                              txq_map |= MVNETA_CPU_TXQ_ACCESS(txq);
-+
-+              /* With only one TX queue we configure a special case
-+               * which will allow to get all the irq on a single
-+               * CPU
-+               */
-+              if (txq_number == 1)
-+                      txq_map = (cpu == pp->rxq_def) ?
-+                              MVNETA_CPU_TXQ_ACCESS(1) : 0;
-               mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
-       }
-@@ -2362,6 +2376,8 @@ static void mvneta_rxq_deinit(struct mvn
- static int mvneta_txq_init(struct mvneta_port *pp,
-                          struct mvneta_tx_queue *txq)
- {
-+      int cpu;
-+
-       txq->size = pp->tx_ring_size;
-       /* A queue must always have room for at least one skb.
-@@ -2414,6 +2430,14 @@ static int mvneta_txq_init(struct mvneta
-       }
-       mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
-+      /* Setup XPS mapping */
-+      if (txq_number > 1)
-+              cpu = txq->id % num_present_cpus();
-+      else
-+              cpu = pp->rxq_def % num_present_cpus();
-+      cpumask_set_cpu(cpu, &txq->affinity_mask);
-+      netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id);
-+
-       return 0;
- }
-@@ -2836,13 +2860,23 @@ static void mvneta_percpu_elect(struct m
-                       if ((rxq % max_cpu) == cpu)
-                               rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
--              if (i == online_cpu_idx) {
--                      /* Map the default receive queue and transmit
--                       * queue to the elected CPU
-+              if (i == online_cpu_idx)
-+                      /* Map the default receive queue queue to the
-+                       * elected CPU
-                        */
-                       rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def);
--                      txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
--              }
-+
-+              /* We update the TX queue map only if we have one
-+               * queue. In this case we associate the TX queue to
-+               * the CPU bound to the default RX queue
-+               */
-+              if (txq_number == 1)
-+                      txq_map = (i == online_cpu_idx) ?
-+                              MVNETA_CPU_TXQ_ACCESS(1) : 0;
-+              else
-+                      txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) &
-+                              MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
-+
-               mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
-               /* Update the interrupt mask on each CPU according the
diff --git a/target/linux/mvebu/patches-4.4/036-net-mvneta-fix-trivial-cut-off-issue-in-mvneta_ethto.patch b/target/linux/mvebu/patches-4.4/036-net-mvneta-fix-trivial-cut-off-issue-in-mvneta_ethto.patch
deleted file mode 100644 (file)
index 2bd7a88..0000000
+++ /dev/null
@@ -1,46 +0,0 @@
-From: Jisheng Zhang <jszhang@marvell.com>
-Date: Wed, 20 Jan 2016 16:36:25 +0800
-Subject: [PATCH] net: mvneta: fix trivial cut-off issue in
- mvneta_ethtool_update_stats
-
-When s->type is T_REG_64, the high 32bits are lost in val. This patch
-fixes this trivial issue.
-
-Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
-Fixes: 9b0cdefa4cd5 ("net: mvneta: add ethtool statistics")
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -3242,26 +3242,25 @@ static void mvneta_ethtool_update_stats(
-       const struct mvneta_statistic *s;
-       void __iomem *base = pp->base;
-       u32 high, low, val;
-+      u64 val64;
-       int i;
-       for (i = 0, s = mvneta_statistics;
-            s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics);
-            s++, i++) {
--              val = 0;
--
-               switch (s->type) {
-               case T_REG_32:
-                       val = readl_relaxed(base + s->offset);
-+                      pp->ethtool_stats[i] += val;
-                       break;
-               case T_REG_64:
-                       /* Docs say to read low 32-bit then high */
-                       low = readl_relaxed(base + s->offset);
-                       high = readl_relaxed(base + s->offset + 4);
--                      val = (u64)high << 32 | low;
-+                      val64 = (u64)high << 32 | low;
-+                      pp->ethtool_stats[i] += val64;
-                       break;
-               }
--
--              pp->ethtool_stats[i] += val;
-       }
- }
diff --git a/target/linux/mvebu/patches-4.4/037-net-mvneta-Fix-for_each_present_cpu-usage.patch b/target/linux/mvebu/patches-4.4/037-net-mvneta-Fix-for_each_present_cpu-usage.patch
deleted file mode 100644 (file)
index 9ded5b7..0000000
+++ /dev/null
@@ -1,55 +0,0 @@
-From: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Date: Thu, 4 Feb 2016 22:09:23 +0100
-Subject: [PATCH] net: mvneta: Fix for_each_present_cpu usage
-
-This patch convert the for_each_present in on_each_cpu, instead of
-applying on the present cpus it will be applied only on the online cpus.
-This fix a bug reported on
-http://thread.gmane.org/gmane.linux.ports.arm.kernel/468173.
-
-Using the macro on_each_cpu (instead of a for_each_* loop) also ensures
-that all the calls will be done all at once.
-
-Fixes: f86428854480 ("net: mvneta: Statically assign queues to CPUs")
-Reported-by: Stefan Roese <stefan.roese@gmail.com>
-Suggested-by: Jisheng Zhang <jszhang@marvell.com>
-Suggested-by: Russell King <rmk+kernel@arm.linux.org.uk>
-Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -2562,7 +2562,7 @@ static void mvneta_start_dev(struct mvne
-       mvneta_port_enable(pp);
-       /* Enable polling on the port */
--      for_each_present_cpu(cpu) {
-+      for_each_online_cpu(cpu) {
-               struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
-               napi_enable(&port->napi);
-@@ -2587,7 +2587,7 @@ static void mvneta_stop_dev(struct mvnet
-       phy_stop(pp->phy_dev);
--      for_each_present_cpu(cpu) {
-+      for_each_online_cpu(cpu) {
-               struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
-               napi_disable(&port->napi);
-@@ -3055,13 +3055,11 @@ err_cleanup_rxqs:
- static int mvneta_stop(struct net_device *dev)
- {
-       struct mvneta_port *pp = netdev_priv(dev);
--      int cpu;
-       mvneta_stop_dev(pp);
-       mvneta_mdio_remove(pp);
-       unregister_cpu_notifier(&pp->cpu_notifier);
--      for_each_present_cpu(cpu)
--              smp_call_function_single(cpu, mvneta_percpu_disable, pp, true);
-+      on_each_cpu(mvneta_percpu_disable, pp, true);
-       free_percpu_irq(dev->irq, pp->ports);
-       mvneta_cleanup_rxqs(pp);
-       mvneta_cleanup_txqs(pp);
diff --git a/target/linux/mvebu/patches-4.4/038-net-mvneta-Fix-the-CPU-choice-in-mvneta_percpu_elect.patch b/target/linux/mvebu/patches-4.4/038-net-mvneta-Fix-the-CPU-choice-in-mvneta_percpu_elect.patch
deleted file mode 100644 (file)
index 4fc9ccc..0000000
+++ /dev/null
@@ -1,57 +0,0 @@
-From: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Date: Thu, 4 Feb 2016 22:09:24 +0100
-Subject: [PATCH] net: mvneta: Fix the CPU choice in mvneta_percpu_elect
-
-When passing to the management of multiple RX queue, the
-mvneta_percpu_elect function was broken. The use of the modulo can lead
-to elect the wrong cpu. For example with rxq_def=2, if the CPU 2 goes
-offline and then online, we ended with the third RX queue activated in
-the same time on CPU 0 and CPU2, which lead to a kernel crash.
-
-With this fix, we don't try to get "the closer" CPU if the default CPU is
-gone, now we just use CPU 0 which always be there. Thanks to this, the
-code becomes more readable, easier to maintain and more predicable.
-
-Cc: stable@vger.kernel.org
-Fixes: 2dcf75e2793c ("net: mvneta: Associate RX queues with each CPU")
-Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -2847,9 +2847,14 @@ static void mvneta_percpu_disable(void *
- static void mvneta_percpu_elect(struct mvneta_port *pp)
- {
--      int online_cpu_idx, max_cpu, cpu, i = 0;
-+      int elected_cpu = 0, max_cpu, cpu, i = 0;
-+
-+      /* Use the cpu associated to the rxq when it is online, in all
-+       * the other cases, use the cpu 0 which can't be offline.
-+       */
-+      if (cpu_online(pp->rxq_def))
-+              elected_cpu = pp->rxq_def;
--      online_cpu_idx = pp->rxq_def % num_online_cpus();
-       max_cpu = num_present_cpus();
-       for_each_online_cpu(cpu) {
-@@ -2860,7 +2865,7 @@ static void mvneta_percpu_elect(struct m
-                       if ((rxq % max_cpu) == cpu)
-                               rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
--              if (i == online_cpu_idx)
-+              if (cpu == elected_cpu)
-                       /* Map the default receive queue queue to the
-                        * elected CPU
-                        */
-@@ -2871,7 +2876,7 @@ static void mvneta_percpu_elect(struct m
-                * the CPU bound to the default RX queue
-                */
-               if (txq_number == 1)
--                      txq_map = (i == online_cpu_idx) ?
-+                      txq_map = (cpu == elected_cpu) ?
-                               MVNETA_CPU_TXQ_ACCESS(1) : 0;
-               else
-                       txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) &
diff --git a/target/linux/mvebu/patches-4.4/039-net-mvneta-Use-on_each_cpu-when-possible.patch b/target/linux/mvebu/patches-4.4/039-net-mvneta-Use-on_each_cpu-when-possible.patch
deleted file mode 100644 (file)
index 76257a2..0000000
+++ /dev/null
@@ -1,68 +0,0 @@
-From: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Date: Thu, 4 Feb 2016 22:09:25 +0100
-Subject: [PATCH] net: mvneta: Use on_each_cpu when possible
-
-Instead of using a for_each_* loop in which we just call the
-smp_call_function_single macro, it is more simple to directly use the
-on_each_cpu macro. Moreover, this macro ensures that the calls will be
-done all at once.
-
-Suggested-by: Russell King <rmk+kernel@arm.linux.org.uk>
-Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -2553,7 +2553,7 @@ static void mvneta_percpu_mask_interrupt
- static void mvneta_start_dev(struct mvneta_port *pp)
- {
--      unsigned int cpu;
-+      int cpu;
-       mvneta_max_rx_size_set(pp, pp->pkt_size);
-       mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
-@@ -2569,9 +2569,8 @@ static void mvneta_start_dev(struct mvne
-       }
-       /* Unmask interrupts. It has to be done from each CPU */
--      for_each_online_cpu(cpu)
--              smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt,
--                                       pp, true);
-+      on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
-+
-       mvreg_write(pp, MVNETA_INTR_MISC_MASK,
-                   MVNETA_CAUSE_PHY_STATUS_CHANGE |
-                   MVNETA_CAUSE_LINK_CHANGE |
-@@ -2991,7 +2990,7 @@ static int mvneta_percpu_notifier(struct
- static int mvneta_open(struct net_device *dev)
- {
-       struct mvneta_port *pp = netdev_priv(dev);
--      int ret, cpu;
-+      int ret;
-       pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
-       pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
-@@ -3024,9 +3023,7 @@ static int mvneta_open(struct net_device
-       /* Enable per-CPU interrupt on all the CPU to handle our RX
-        * queue interrupts
-        */
--      for_each_online_cpu(cpu)
--              smp_call_function_single(cpu, mvneta_percpu_enable,
--                                       pp, true);
-+      on_each_cpu(mvneta_percpu_enable, pp, true);
-       /* Register a CPU notifier to handle the case where our CPU
-@@ -3313,9 +3310,7 @@ static int  mvneta_config_rss(struct mvn
-       netif_tx_stop_all_queues(pp->dev);
--      for_each_online_cpu(cpu)
--              smp_call_function_single(cpu, mvneta_percpu_mask_interrupt,
--                                       pp, true);
-+      on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
-       /* We have to synchronise on the napi of each CPU */
-       for_each_online_cpu(cpu) {
diff --git a/target/linux/mvebu/patches-4.4/040-net-mvneta-Modify-the-queue-related-fields-from-each.patch b/target/linux/mvebu/patches-4.4/040-net-mvneta-Modify-the-queue-related-fields-from-each.patch
deleted file mode 100644 (file)
index b025777..0000000
+++ /dev/null
@@ -1,179 +0,0 @@
-From: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Date: Thu, 4 Feb 2016 22:09:27 +0100
-Subject: [PATCH] net: mvneta: Modify the queue related fields from each cpu
-
-In the MVNETA_INTR_* registers, the queues related fields are per cpu,
-according to the datasheet (comment in [] are added by me):
-"In a multi-CPU system, bits of RX[or TX] queues for which the access by
-the reading[or writing] CPU is disabled are read as 0, and cannot be
-cleared[or written]."
-
-That means that each time we want to manipulate these bits we had to do
-it on each cpu and not only on the current cpu.
-
-Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -1036,6 +1036,43 @@ static void mvneta_set_autoneg(struct mv
-       }
- }
-+static void mvneta_percpu_unmask_interrupt(void *arg)
-+{
-+      struct mvneta_port *pp = arg;
-+
-+      /* All the queue are unmasked, but actually only the ones
-+       * mapped to this CPU will be unmasked
-+       */
-+      mvreg_write(pp, MVNETA_INTR_NEW_MASK,
-+                  MVNETA_RX_INTR_MASK_ALL |
-+                  MVNETA_TX_INTR_MASK_ALL |
-+                  MVNETA_MISCINTR_INTR_MASK);
-+}
-+
-+static void mvneta_percpu_mask_interrupt(void *arg)
-+{
-+      struct mvneta_port *pp = arg;
-+
-+      /* All the queue are masked, but actually only the ones
-+       * mapped to this CPU will be masked
-+       */
-+      mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
-+      mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
-+      mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
-+}
-+
-+static void mvneta_percpu_clear_intr_cause(void *arg)
-+{
-+      struct mvneta_port *pp = arg;
-+
-+      /* All the queue are cleared, but actually only the ones
-+       * mapped to this CPU will be cleared
-+       */
-+      mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
-+      mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
-+      mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
-+}
-+
- /* This method sets defaults to the NETA port:
-  *    Clears interrupt Cause and Mask registers.
-  *    Clears all MAC tables.
-@@ -1053,14 +1090,10 @@ static void mvneta_defaults_set(struct m
-       int max_cpu = num_present_cpus();
-       /* Clear all Cause registers */
--      mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
--      mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
--      mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
-+      on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
-       /* Mask all interrupts */
--      mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
--      mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
--      mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
-+      on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
-       mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
-       /* Enable MBUS Retry bit16 */
-@@ -2526,31 +2559,6 @@ static int mvneta_setup_txqs(struct mvne
-       return 0;
- }
--static void mvneta_percpu_unmask_interrupt(void *arg)
--{
--      struct mvneta_port *pp = arg;
--
--      /* All the queue are unmasked, but actually only the ones
--       * maped to this CPU will be unmasked
--       */
--      mvreg_write(pp, MVNETA_INTR_NEW_MASK,
--                  MVNETA_RX_INTR_MASK_ALL |
--                  MVNETA_TX_INTR_MASK_ALL |
--                  MVNETA_MISCINTR_INTR_MASK);
--}
--
--static void mvneta_percpu_mask_interrupt(void *arg)
--{
--      struct mvneta_port *pp = arg;
--
--      /* All the queue are masked, but actually only the ones
--       * maped to this CPU will be masked
--       */
--      mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
--      mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
--      mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
--}
--
- static void mvneta_start_dev(struct mvneta_port *pp)
- {
-       int cpu;
-@@ -2601,13 +2609,10 @@ static void mvneta_stop_dev(struct mvnet
-       mvneta_port_disable(pp);
-       /* Clear all ethernet port interrupts */
--      mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
--      mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
-+      on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
-       /* Mask all ethernet port interrupts */
--      mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
--      mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
--      mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
-+      on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
-       mvneta_tx_reset(pp);
-       mvneta_rx_reset(pp);
-@@ -2919,9 +2924,7 @@ static int mvneta_percpu_notifier(struct
-               }
-               /* Mask all ethernet port interrupts */
--              mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
--              mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
--              mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
-+              on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
-               napi_enable(&port->napi);
-@@ -2936,14 +2939,8 @@ static int mvneta_percpu_notifier(struct
-                */
-               mvneta_percpu_elect(pp);
--              /* Unmask all ethernet port interrupts, as this
--               * notifier is called for each CPU then the CPU to
--               * Queue mapping is applied
--               */
--              mvreg_write(pp, MVNETA_INTR_NEW_MASK,
--                      MVNETA_RX_INTR_MASK(rxq_number) |
--                      MVNETA_TX_INTR_MASK(txq_number) |
--                      MVNETA_MISCINTR_INTR_MASK);
-+              /* Unmask all ethernet port interrupts */
-+              on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
-               mvreg_write(pp, MVNETA_INTR_MISC_MASK,
-                       MVNETA_CAUSE_PHY_STATUS_CHANGE |
-                       MVNETA_CAUSE_LINK_CHANGE |
-@@ -2954,9 +2951,7 @@ static int mvneta_percpu_notifier(struct
-       case CPU_DOWN_PREPARE_FROZEN:
-               netif_tx_stop_all_queues(pp->dev);
-               /* Mask all ethernet port interrupts */
--              mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
--              mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
--              mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
-+              on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
-               napi_synchronize(&port->napi);
-               napi_disable(&port->napi);
-@@ -2972,10 +2967,7 @@ static int mvneta_percpu_notifier(struct
-               /* Check if a new CPU must be elected now this on is down */
-               mvneta_percpu_elect(pp);
-               /* Unmask all ethernet port interrupts */
--              mvreg_write(pp, MVNETA_INTR_NEW_MASK,
--                      MVNETA_RX_INTR_MASK(rxq_number) |
--                      MVNETA_TX_INTR_MASK(txq_number) |
--                      MVNETA_MISCINTR_INTR_MASK);
-+              on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
-               mvreg_write(pp, MVNETA_INTR_MISC_MASK,
-                       MVNETA_CAUSE_PHY_STATUS_CHANGE |
-                       MVNETA_CAUSE_LINK_CHANGE |
diff --git a/target/linux/mvebu/patches-4.4/041-net-mvneta-The-mvneta_percpu_elect-function-should-b.patch b/target/linux/mvebu/patches-4.4/041-net-mvneta-The-mvneta_percpu_elect-function-should-b.patch
deleted file mode 100644 (file)
index a77bef4..0000000
+++ /dev/null
@@ -1,68 +0,0 @@
-From: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Date: Thu, 4 Feb 2016 22:09:28 +0100
-Subject: [PATCH] net: mvneta: The mvneta_percpu_elect function should be
- atomic
-
-Electing a CPU must be done in an atomic way: it should be done after or
-before the removal/insertion of a CPU and this function is not reentrant.
-
-During the loop of mvneta_percpu_elect we associates the queues to the
-CPUs, if there is a topology change during this loop, then the mapping
-between the CPUs and the queues could be wrong. During this loop the
-interrupt mask is also updating for each CPUs, It should not be changed
-in the same time by other part of the driver.
-
-This patch adds spinlock to create the needed critical sections.
-
-Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -370,6 +370,10 @@ struct mvneta_port {
-       struct net_device *dev;
-       struct notifier_block cpu_notifier;
-       int rxq_def;
-+      /* Protect the access to the percpu interrupt registers,
-+       * ensuring that the configuration remains coherent.
-+       */
-+      spinlock_t lock;
-       /* Core clock */
-       struct clk *clk;
-@@ -2853,6 +2857,12 @@ static void mvneta_percpu_elect(struct m
- {
-       int elected_cpu = 0, max_cpu, cpu, i = 0;
-+      /* Electing a CPU must be done in an atomic way: it should be
-+       * done after or before the removal/insertion of a CPU and
-+       * this function is not reentrant.
-+       */
-+      spin_lock(&pp->lock);
-+
-       /* Use the cpu associated to the rxq when it is online, in all
-        * the other cases, use the cpu 0 which can't be offline.
-        */
-@@ -2896,6 +2906,7 @@ static void mvneta_percpu_elect(struct m
-               i++;
-       }
-+      spin_unlock(&pp->lock);
- };
- static int mvneta_percpu_notifier(struct notifier_block *nfb,
-@@ -2950,8 +2961,13 @@ static int mvneta_percpu_notifier(struct
-       case CPU_DOWN_PREPARE:
-       case CPU_DOWN_PREPARE_FROZEN:
-               netif_tx_stop_all_queues(pp->dev);
-+              /* Thanks to this lock we are sure that any pending
-+               * cpu election is done
-+               */
-+              spin_lock(&pp->lock);
-               /* Mask all ethernet port interrupts */
-               on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
-+              spin_unlock(&pp->lock);
-               napi_synchronize(&port->napi);
-               napi_disable(&port->napi);
diff --git a/target/linux/mvebu/patches-4.4/042-net-mvneta-Fix-race-condition-during-stopping.patch b/target/linux/mvebu/patches-4.4/042-net-mvneta-Fix-race-condition-during-stopping.patch
deleted file mode 100644 (file)
index 9936ebf..0000000
+++ /dev/null
@@ -1,128 +0,0 @@
-From: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Date: Thu, 4 Feb 2016 22:09:29 +0100
-Subject: [PATCH] net: mvneta: Fix race condition during stopping
-
-When stopping the port, the CPU notifier are still there whereas the
-mvneta_stop_dev function calls mvneta_percpu_disable() on each CPUs.
-It was possible to have a new CPU coming at this point which could be
-racy.
-
-This patch adds a flag preventing executing the code notifier for a new
-CPU when the port is stopping. It also uses the spinlock introduces
-previously. To avoid the deadlock, the lock has been moved outside the
-mvneta_percpu_elect function.
-
-Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -374,6 +374,7 @@ struct mvneta_port {
-        * ensuring that the configuration remains coherent.
-        */
-       spinlock_t lock;
-+      bool is_stopped;
-       /* Core clock */
-       struct clk *clk;
-@@ -2853,16 +2854,14 @@ static void mvneta_percpu_disable(void *
-       disable_percpu_irq(pp->dev->irq);
- }
-+/* Electing a CPU must be done in an atomic way: it should be done
-+ * after or before the removal/insertion of a CPU and this function is
-+ * not reentrant.
-+ */
- static void mvneta_percpu_elect(struct mvneta_port *pp)
- {
-       int elected_cpu = 0, max_cpu, cpu, i = 0;
--      /* Electing a CPU must be done in an atomic way: it should be
--       * done after or before the removal/insertion of a CPU and
--       * this function is not reentrant.
--       */
--      spin_lock(&pp->lock);
--
-       /* Use the cpu associated to the rxq when it is online, in all
-        * the other cases, use the cpu 0 which can't be offline.
-        */
-@@ -2906,7 +2905,6 @@ static void mvneta_percpu_elect(struct m
-               i++;
-       }
--      spin_unlock(&pp->lock);
- };
- static int mvneta_percpu_notifier(struct notifier_block *nfb,
-@@ -2920,6 +2918,14 @@ static int mvneta_percpu_notifier(struct
-       switch (action) {
-       case CPU_ONLINE:
-       case CPU_ONLINE_FROZEN:
-+              spin_lock(&pp->lock);
-+              /* Configuring the driver for a new CPU while the
-+               * driver is stopping is racy, so just avoid it.
-+               */
-+              if (pp->is_stopped) {
-+                      spin_unlock(&pp->lock);
-+                      break;
-+              }
-               netif_tx_stop_all_queues(pp->dev);
-               /* We have to synchronise on tha napi of each CPU
-@@ -2957,6 +2963,7 @@ static int mvneta_percpu_notifier(struct
-                       MVNETA_CAUSE_LINK_CHANGE |
-                       MVNETA_CAUSE_PSC_SYNC_CHANGE);
-               netif_tx_start_all_queues(pp->dev);
-+              spin_unlock(&pp->lock);
-               break;
-       case CPU_DOWN_PREPARE:
-       case CPU_DOWN_PREPARE_FROZEN:
-@@ -2981,7 +2988,9 @@ static int mvneta_percpu_notifier(struct
-       case CPU_DEAD:
-       case CPU_DEAD_FROZEN:
-               /* Check if a new CPU must be elected now this on is down */
-+              spin_lock(&pp->lock);
-               mvneta_percpu_elect(pp);
-+              spin_unlock(&pp->lock);
-               /* Unmask all ethernet port interrupts */
-               on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
-               mvreg_write(pp, MVNETA_INTR_MISC_MASK,
-@@ -3033,7 +3042,7 @@ static int mvneta_open(struct net_device
-        */
-       on_each_cpu(mvneta_percpu_enable, pp, true);
--
-+      pp->is_stopped = false;
-       /* Register a CPU notifier to handle the case where our CPU
-        * might be taken offline.
-        */
-@@ -3066,9 +3075,18 @@ static int mvneta_stop(struct net_device
- {
-       struct mvneta_port *pp = netdev_priv(dev);
-+      /* Inform that we are stopping so we don't want to setup the
-+       * driver for new CPUs in the notifiers
-+       */
-+      spin_lock(&pp->lock);
-+      pp->is_stopped = true;
-       mvneta_stop_dev(pp);
-       mvneta_mdio_remove(pp);
-       unregister_cpu_notifier(&pp->cpu_notifier);
-+      /* Now that the notifier are unregistered, we can release le
-+       * lock
-+       */
-+      spin_unlock(&pp->lock);
-       on_each_cpu(mvneta_percpu_disable, pp, true);
-       free_percpu_irq(dev->irq, pp->ports);
-       mvneta_cleanup_rxqs(pp);
-@@ -3339,7 +3357,9 @@ static int  mvneta_config_rss(struct mvn
-       mvreg_write(pp, MVNETA_PORT_CONFIG, val);
-       /* Update the elected CPU matching the new rxq_def */
-+      spin_lock(&pp->lock);
-       mvneta_percpu_elect(pp);
-+      spin_unlock(&pp->lock);
-       /* We have to synchronise on the napi of each CPU */
-       for_each_online_cpu(cpu) {
diff --git a/target/linux/mvebu/patches-4.4/043-net-mvneta-sort-the-headers-in-alphabetic-order.patch b/target/linux/mvebu/patches-4.4/043-net-mvneta-sort-the-headers-in-alphabetic-order.patch
deleted file mode 100644 (file)
index 502c258..0000000
+++ /dev/null
@@ -1,56 +0,0 @@
-From: Jisheng Zhang <jszhang@marvell.com>
-Date: Wed, 20 Jan 2016 19:27:22 +0800
-Subject: [PATCH] net: mvneta: sort the headers in alphabetic order
-
-Sorting the headers in alphabetic order will help to reduce the conflict
-when adding new headers in the future.
-
-Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
-Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -11,28 +11,28 @@
-  * warranty of any kind, whether express or implied.
-  */
--#include <linux/kernel.h>
--#include <linux/netdevice.h>
-+#include <linux/clk.h>
-+#include <linux/cpu.h>
- #include <linux/etherdevice.h>
--#include <linux/platform_device.h>
--#include <linux/skbuff.h>
-+#include <linux/if_vlan.h>
- #include <linux/inetdevice.h>
--#include <linux/mbus.h>
--#include <linux/module.h>
- #include <linux/interrupt.h>
--#include <linux/if_vlan.h>
--#include <net/ip.h>
--#include <net/ipv6.h>
- #include <linux/io.h>
--#include <net/tso.h>
-+#include <linux/kernel.h>
-+#include <linux/mbus.h>
-+#include <linux/module.h>
-+#include <linux/netdevice.h>
- #include <linux/of.h>
-+#include <linux/of_address.h>
- #include <linux/of_irq.h>
- #include <linux/of_mdio.h>
- #include <linux/of_net.h>
--#include <linux/of_address.h>
- #include <linux/phy.h>
--#include <linux/clk.h>
--#include <linux/cpu.h>
-+#include <linux/platform_device.h>
-+#include <linux/skbuff.h>
-+#include <net/ip.h>
-+#include <net/ipv6.h>
-+#include <net/tso.h>
- /* Registers */
- #define MVNETA_RXQ_CONFIG_REG(q)                (0x1400 + ((q) << 2))
diff --git a/target/linux/mvebu/patches-4.4/044-net-add-a-hardware-buffer-management-helper-API.patch b/target/linux/mvebu/patches-4.4/044-net-add-a-hardware-buffer-management-helper-API.patch
deleted file mode 100644 (file)
index d4bc6a0..0000000
+++ /dev/null
@@ -1,159 +0,0 @@
-From: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Date: Mon, 14 Mar 2016 09:39:04 +0100
-Subject: [PATCH] net: add a hardware buffer management helper API
-
-This basic implementation allows to share code between driver using
-hardware buffer management. As the code is hardware agnostic, there is
-few helpers, most of the optimization brought by the an HW BM has to be
-done at driver level.
-
-Tested-by: Sebastian Careba <nitroshift@yahoo.com>
-Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- create mode 100644 include/net/hwbm.h
- create mode 100644 net/core/hwbm.c
-
---- /dev/null
-+++ b/include/net/hwbm.h
-@@ -0,0 +1,28 @@
-+#ifndef _HWBM_H
-+#define _HWBM_H
-+
-+struct hwbm_pool {
-+      /* Capacity of the pool */
-+      int size;
-+      /* Size of the buffers managed */
-+      int frag_size;
-+      /* Number of buffers currently used by this pool */
-+      int buf_num;
-+      /* constructor called during alocation */
-+      int (*construct)(struct hwbm_pool *bm_pool, void *buf);
-+      /* protect acces to the buffer counter*/
-+      spinlock_t lock;
-+      /* private data */
-+      void *priv;
-+};
-+#ifdef CONFIG_HWBM
-+void hwbm_buf_free(struct hwbm_pool *bm_pool, void *buf);
-+int hwbm_pool_refill(struct hwbm_pool *bm_pool, gfp_t gfp);
-+int hwbm_pool_add(struct hwbm_pool *bm_pool, unsigned int buf_num, gfp_t gfp);
-+#else
-+void hwbm_buf_free(struct hwbm_pool *bm_pool, void *buf) {}
-+int hwbm_pool_refill(struct hwbm_pool *bm_pool, gfp_t gfp) { return 0; }
-+int hwbm_pool_add(struct hwbm_pool *bm_pool, unsigned int buf_num, gfp_t gfp)
-+{ return 0; }
-+#endif /* CONFIG_HWBM */
-+#endif /* _HWBM_H */
---- a/net/Kconfig
-+++ b/net/Kconfig
-@@ -259,6 +259,9 @@ config XPS
-       depends on SMP
-       default y
-+config HWBM
-+      bool
-+
- config CGROUP_NET_PRIO
-       bool "Network priority cgroup"
-       depends on CGROUPS
---- a/net/core/Makefile
-+++ b/net/core/Makefile
-@@ -14,6 +14,7 @@ obj-y                     += dev.o ethtool.o dev_addr_
- obj-$(CONFIG_SOCK_DIAG) += sock_diag.o
- obj-$(CONFIG_XFRM) += flow.o
- obj-y += net-sysfs.o
-+obj-$(CONFIG_HWBM) += hwbm.o
- obj-$(CONFIG_PROC_FS) += net-procfs.o
- obj-$(CONFIG_NET_PKTGEN) += pktgen.o
- obj-$(CONFIG_NETPOLL) += netpoll.o
---- /dev/null
-+++ b/net/core/hwbm.c
-@@ -0,0 +1,87 @@
-+/* Support for hardware buffer manager.
-+ *
-+ * Copyright (C) 2016 Marvell
-+ *
-+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ */
-+#include <linux/kernel.h>
-+#include <linux/printk.h>
-+#include <linux/skbuff.h>
-+#include <net/hwbm.h>
-+
-+void hwbm_buf_free(struct hwbm_pool *bm_pool, void *buf)
-+{
-+      if (likely(bm_pool->frag_size <= PAGE_SIZE))
-+              skb_free_frag(buf);
-+      else
-+              kfree(buf);
-+}
-+EXPORT_SYMBOL_GPL(hwbm_buf_free);
-+
-+/* Refill processing for HW buffer management */
-+int hwbm_pool_refill(struct hwbm_pool *bm_pool, gfp_t gfp)
-+{
-+      int frag_size = bm_pool->frag_size;
-+      void *buf;
-+
-+      if (likely(frag_size <= PAGE_SIZE))
-+              buf = netdev_alloc_frag(frag_size);
-+      else
-+              buf = kmalloc(frag_size, gfp);
-+
-+      if (!buf)
-+              return -ENOMEM;
-+
-+      if (bm_pool->construct)
-+              if (bm_pool->construct(bm_pool, buf)) {
-+                      hwbm_buf_free(bm_pool, buf);
-+                      return -ENOMEM;
-+              }
-+
-+      return 0;
-+}
-+EXPORT_SYMBOL_GPL(hwbm_pool_refill);
-+
-+int hwbm_pool_add(struct hwbm_pool *bm_pool, unsigned int buf_num, gfp_t gfp)
-+{
-+      int err, i;
-+      unsigned long flags;
-+
-+      spin_lock_irqsave(&bm_pool->lock, flags);
-+      if (bm_pool->buf_num == bm_pool->size) {
-+              pr_warn("pool already filled\n");
-+              return bm_pool->buf_num;
-+      }
-+
-+      if (buf_num + bm_pool->buf_num > bm_pool->size) {
-+              pr_warn("cannot allocate %d buffers for pool\n",
-+                      buf_num);
-+              return 0;
-+      }
-+
-+      if ((buf_num + bm_pool->buf_num) < bm_pool->buf_num) {
-+              pr_warn("Adding %d buffers to the %d current buffers will overflow\n",
-+                      buf_num,  bm_pool->buf_num);
-+              return 0;
-+      }
-+
-+      for (i = 0; i < buf_num; i++) {
-+              err = hwbm_pool_refill(bm_pool, gfp);
-+              if (err < 0)
-+                      break;
-+      }
-+
-+      /* Update BM driver with number of buffers added to pool */
-+      bm_pool->buf_num += i;
-+
-+      pr_debug("hwpm pool: %d of %d buffers added\n", i, buf_num);
-+      spin_unlock_irqrestore(&bm_pool->lock, flags);
-+
-+      return i;
-+}
-+EXPORT_SYMBOL_GPL(hwbm_pool_add);
diff --git a/target/linux/mvebu/patches-4.4/045-net-mvneta-bm-add-support-for-hardware-buffer-manage.patch b/target/linux/mvebu/patches-4.4/045-net-mvneta-bm-add-support-for-hardware-buffer-manage.patch
deleted file mode 100644 (file)
index d343b39..0000000
+++ /dev/null
@@ -1,1684 +0,0 @@
-From: Marcin Wojtas <mw@semihalf.com>
-Date: Mon, 14 Mar 2016 09:39:03 +0100
-Subject: [PATCH] net: mvneta: bm: add support for hardware buffer management
-
-Buffer manager (BM) is a dedicated hardware unit that can be used by all
-ethernet ports of Armada XP and 38x SoC's. It allows to offload CPU on RX
-path by sparing DRAM access on refilling buffer pool, hardware-based
-filling of descriptor ring data and better memory utilization due to HW
-arbitration for using 'short' pools for small packets.
-
-Tests performed with A388 SoC working as a network bridge between two
-packet generators showed increase of maximum processed 64B packets by
-~20k (~555k packets with BM enabled vs ~535 packets without BM). Also
-when pushing 1500B-packets with a line rate achieved, CPU load decreased
-from around 25% without BM to 20% with BM.
-
-BM comprise up to 4 buffer pointers' (BP) rings kept in DRAM, which
-are called external BP pools - BPPE. Allocating and releasing buffer
-pointers (BP) to/from BPPE is performed indirectly by write/read access
-to a dedicated internal SRAM, where internal BP pools (BPPI) are placed.
-BM hardware controls status of BPPE automatically, as well as assigning
-proper buffers to RX descriptors. For more details please refer to
-Functional Specification of Armada XP or 38x SoC.
-
-In order to enable support for a separate hardware block, common for all
-ports, a new driver has to be implemented ('mvneta_bm'). It provides
-initialization sequence of address space, clocks, registers, SRAM,
-empty pools' structures and also obtaining optional configuration
-from DT (please refer to device tree binding documentation). mvneta_bm
-exposes also a necessary API to mvneta driver, as well as a dedicated
-structure with BM information (bm_priv), whose presence is used as a
-flag notifying of BM usage by port. It has to be ensured that mvneta_bm
-probe is executed prior to the ones in ports' driver. In case BM is not
-used or its probe fails, mvneta falls back to use software buffer
-management.
-
-A sequence executed in mvneta_probe function is modified in order to have
-an access to needed resources before possible port's BM initialization is
-done. According to port-pools mapping provided by DT appropriate registers
-are configured and the buffer pools are filled. RX path is modified
-accordingly. Becaues the hardware allows a wide variety of configuration
-options, following assumptions are made:
-* using BM mechanisms can be selectively disabled/enabled basing
-  on DT configuration among the ports
-* 'long' pool's single buffer size is tied to port's MTU
-* using 'long' pool by port is obligatory and it cannot be shared
-* using 'short' pool for smaller packets is optional
-* one 'short' pool can be shared among all ports
-
-This commit enables hardware buffer management operation cooperating with
-existing mvneta driver. New device tree binding documentation is added and
-the one of mvneta is updated accordingly.
-
-[gregory.clement@free-electrons.com: removed the suspend/resume part]
-
-Signed-off-by: Marcin Wojtas <mw@semihalf.com>
-Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- create mode 100644 Documentation/devicetree/bindings/net/marvell-neta-bm.txt
- create mode 100644 drivers/net/ethernet/marvell/mvneta_bm.c
- create mode 100644 drivers/net/ethernet/marvell/mvneta_bm.h
-
---- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
-+++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
-@@ -13,15 +13,30 @@ Optional properties:
-   Value is presented in bytes. If not used, by default 1600B is set for
-   "marvell,armada-370-neta" and 9800B for others.
-+Optional properties (valid only for Armada XP/38x):
-+
-+- buffer-manager: a phandle to a buffer manager node. Please refer to
-+  Documentation/devicetree/bindings/net/marvell-neta-bm.txt
-+- bm,pool-long: ID of a pool, that will accept all packets of a size
-+  higher than 'short' pool's threshold (if set) and up to MTU value.
-+  Obligatory, when the port is supposed to use hardware
-+  buffer management.
-+- bm,pool-short: ID of a pool, that will be used for accepting
-+  packets of a size lower than given threshold. If not set, the port
-+  will use a single 'long' pool for all packets, as defined above.
-+
- Example:
--ethernet@d0070000 {
-+ethernet@70000 {
-       compatible = "marvell,armada-370-neta";
--      reg = <0xd0070000 0x2500>;
-+      reg = <0x70000 0x2500>;
-       interrupts = <8>;
-       clocks = <&gate_clk 4>;
-       tx-csum-limit = <9800>
-       status = "okay";
-       phy = <&phy0>;
-       phy-mode = "rgmii-id";
-+      buffer-manager = <&bm>;
-+      bm,pool-long = <0>;
-+      bm,pool-short = <1>;
- };
---- /dev/null
-+++ b/Documentation/devicetree/bindings/net/marvell-neta-bm.txt
-@@ -0,0 +1,49 @@
-+* Marvell Armada 380/XP Buffer Manager driver (BM)
-+
-+Required properties:
-+
-+- compatible: should be "marvell,armada-380-neta-bm".
-+- reg: address and length of the register set for the device.
-+- clocks: a pointer to the reference clock for this device.
-+- internal-mem: a phandle to BM internal SRAM definition.
-+
-+Optional properties (port):
-+
-+- pool<0 : 3>,capacity: size of external buffer pointers' ring maintained
-+  in DRAM. Can be set for each pool (id 0 : 3) separately. The value has
-+  to be chosen between 128 and 16352 and it also has to be aligned to 32.
-+  Otherwise the driver would adjust a given number or choose default if
-+  not set.
-+- pool<0 : 3>,pkt-size: maximum size of a packet accepted by a given buffer
-+  pointers' pool (id 0 : 3). It will be taken into consideration only when pool
-+  type is 'short'. For 'long' ones it would be overridden by port's MTU.
-+  If not set a driver will choose a default value.
-+
-+In order to see how to hook the BM to a given ethernet port, please
-+refer to Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt.
-+
-+Example:
-+
-+- main node:
-+
-+bm: bm@c8000 {
-+      compatible = "marvell,armada-380-neta-bm";
-+      reg = <0xc8000 0xac>;
-+      clocks = <&gateclk 13>;
-+      internal-mem = <&bm_bppi>;
-+      status = "okay";
-+      pool2,capacity = <4096>;
-+      pool1,pkt-size = <512>;
-+};
-+
-+- internal SRAM node:
-+
-+bm_bppi: bm-bppi {
-+      compatible = "mmio-sram";
-+      reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
-+      ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
-+      #address-cells = <1>;
-+      #size-cells = <1>;
-+      clocks = <&gateclk 13>;
-+      status = "okay";
-+};
---- a/drivers/net/ethernet/marvell/Kconfig
-+++ b/drivers/net/ethernet/marvell/Kconfig
-@@ -40,6 +40,19 @@ config MVMDIO
-         This driver is used by the MV643XX_ETH and MVNETA drivers.
-+config MVNETA_BM
-+      tristate "Marvell Armada 38x/XP network interface BM support"
-+      depends on MVNETA
-+      ---help---
-+        This driver supports auxiliary block of the network
-+        interface units in the Marvell ARMADA XP and ARMADA 38x SoC
-+        family, which is called buffer manager.
-+
-+        This driver, when enabled, strictly cooperates with mvneta
-+        driver and is common for all network ports of the devices,
-+        even for Armada 370 SoC, which doesn't support hardware
-+        buffer management.
-+
- config MVNETA
-       tristate "Marvell Armada 370/38x/XP network interface support"
-       depends on PLAT_ORION
---- a/drivers/net/ethernet/marvell/Makefile
-+++ b/drivers/net/ethernet/marvell/Makefile
-@@ -4,6 +4,7 @@
- obj-$(CONFIG_MVMDIO) += mvmdio.o
- obj-$(CONFIG_MV643XX_ETH) += mv643xx_eth.o
-+obj-$(CONFIG_MVNETA_BM) += mvneta_bm.o
- obj-$(CONFIG_MVNETA) += mvneta.o
- obj-$(CONFIG_MVPP2) += mvpp2.o
- obj-$(CONFIG_PXA168_ETH) += pxa168_eth.o
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -30,6 +30,7 @@
- #include <linux/phy.h>
- #include <linux/platform_device.h>
- #include <linux/skbuff.h>
-+#include "mvneta_bm.h"
- #include <net/ip.h>
- #include <net/ipv6.h>
- #include <net/tso.h>
-@@ -37,6 +38,10 @@
- /* Registers */
- #define MVNETA_RXQ_CONFIG_REG(q)                (0x1400 + ((q) << 2))
- #define      MVNETA_RXQ_HW_BUF_ALLOC            BIT(0)
-+#define      MVNETA_RXQ_SHORT_POOL_ID_SHIFT   4
-+#define      MVNETA_RXQ_SHORT_POOL_ID_MASK    0x30
-+#define      MVNETA_RXQ_LONG_POOL_ID_SHIFT    6
-+#define      MVNETA_RXQ_LONG_POOL_ID_MASK     0xc0
- #define      MVNETA_RXQ_PKT_OFFSET_ALL_MASK     (0xf    << 8)
- #define      MVNETA_RXQ_PKT_OFFSET_MASK(offs)   ((offs) << 8)
- #define MVNETA_RXQ_THRESHOLD_REG(q)             (0x14c0 + ((q) << 2))
-@@ -50,6 +55,9 @@
- #define MVNETA_RXQ_STATUS_UPDATE_REG(q)         (0x1500 + ((q) << 2))
- #define      MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT  16
- #define      MVNETA_RXQ_ADD_NON_OCCUPIED_MAX    255
-+#define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool)  (0x1700 + ((pool) << 2))
-+#define      MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3
-+#define      MVNETA_PORT_POOL_BUFFER_SZ_MASK  0xfff8
- #define MVNETA_PORT_RX_RESET                    0x1cc0
- #define      MVNETA_PORT_RX_DMA_RESET           BIT(0)
- #define MVNETA_PHY_ADDR                         0x2000
-@@ -107,6 +115,7 @@
- #define MVNETA_GMAC_CLOCK_DIVIDER                0x24f4
- #define      MVNETA_GMAC_1MS_CLOCK_ENABLE        BIT(31)
- #define MVNETA_ACC_MODE                          0x2500
-+#define MVNETA_BM_ADDRESS                        0x2504
- #define MVNETA_CPU_MAP(cpu)                      (0x2540 + ((cpu) << 2))
- #define      MVNETA_CPU_RXQ_ACCESS_ALL_MASK      0x000000ff
- #define      MVNETA_CPU_TXQ_ACCESS_ALL_MASK      0x0000ff00
-@@ -253,7 +262,10 @@
- #define MVNETA_CPU_D_CACHE_LINE_SIZE    32
- #define MVNETA_TX_CSUM_DEF_SIZE               1600
- #define MVNETA_TX_CSUM_MAX_SIZE               9800
--#define MVNETA_ACC_MODE_EXT           1
-+#define MVNETA_ACC_MODE_EXT1          1
-+#define MVNETA_ACC_MODE_EXT2          2
-+
-+#define MVNETA_MAX_DECODE_WIN         6
- /* Timeout constants */
- #define MVNETA_TX_DISABLE_TIMEOUT_MSEC        1000
-@@ -293,7 +305,8 @@
-       ((addr >= txq->tso_hdrs_phys) && \
-        (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
--#define MVNETA_RX_BUF_SIZE(pkt_size)   ((pkt_size) + NET_SKB_PAD)
-+#define MVNETA_RX_GET_BM_POOL_ID(rxd) \
-+      (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
- struct mvneta_statistic {
-       unsigned short offset;
-@@ -359,6 +372,7 @@ struct mvneta_pcpu_port {
- };
- struct mvneta_port {
-+      u8 id;
-       struct mvneta_pcpu_port __percpu        *ports;
-       struct mvneta_pcpu_stats __percpu       *stats;
-@@ -392,6 +406,11 @@ struct mvneta_port {
-       unsigned int tx_csum_limit;
-       unsigned int use_inband_status:1;
-+      struct mvneta_bm *bm_priv;
-+      struct mvneta_bm_pool *pool_long;
-+      struct mvneta_bm_pool *pool_short;
-+      int bm_win_id;
-+
-       u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
-       u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
-@@ -417,6 +436,8 @@ struct mvneta_port {
- #define MVNETA_TX_L4_CSUM_NOT BIT(31)
- #define MVNETA_RXD_ERR_CRC            0x0
-+#define MVNETA_RXD_BM_POOL_SHIFT      13
-+#define MVNETA_RXD_BM_POOL_MASK               (BIT(13) | BIT(14))
- #define MVNETA_RXD_ERR_SUMMARY                BIT(16)
- #define MVNETA_RXD_ERR_OVERRUN                BIT(17)
- #define MVNETA_RXD_ERR_LEN            BIT(18)
-@@ -561,6 +582,9 @@ static int rxq_def;
- static int rx_copybreak __read_mostly = 256;
-+/* HW BM need that each port be identify by a unique ID */
-+static int global_port_id;
-+
- #define MVNETA_DRIVER_NAME "mvneta"
- #define MVNETA_DRIVER_VERSION "1.0"
-@@ -827,6 +851,214 @@ static void mvneta_rxq_bm_disable(struct
-       mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
- }
-+/* Enable buffer management (BM) */
-+static void mvneta_rxq_bm_enable(struct mvneta_port *pp,
-+                               struct mvneta_rx_queue *rxq)
-+{
-+      u32 val;
-+
-+      val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
-+      val |= MVNETA_RXQ_HW_BUF_ALLOC;
-+      mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
-+}
-+
-+/* Notify HW about port's assignment of pool for bigger packets */
-+static void mvneta_rxq_long_pool_set(struct mvneta_port *pp,
-+                                   struct mvneta_rx_queue *rxq)
-+{
-+      u32 val;
-+
-+      val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
-+      val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK;
-+      val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT);
-+
-+      mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
-+}
-+
-+/* Notify HW about port's assignment of pool for smaller packets */
-+static void mvneta_rxq_short_pool_set(struct mvneta_port *pp,
-+                                    struct mvneta_rx_queue *rxq)
-+{
-+      u32 val;
-+
-+      val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
-+      val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK;
-+      val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT);
-+
-+      mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
-+}
-+
-+/* Set port's receive buffer size for assigned BM pool */
-+static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp,
-+                                            int buf_size,
-+                                            u8 pool_id)
-+{
-+      u32 val;
-+
-+      if (!IS_ALIGNED(buf_size, 8)) {
-+              dev_warn(pp->dev->dev.parent,
-+                       "illegal buf_size value %d, round to %d\n",
-+                       buf_size, ALIGN(buf_size, 8));
-+              buf_size = ALIGN(buf_size, 8);
-+      }
-+
-+      val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id));
-+      val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK;
-+      mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val);
-+}
-+
-+/* Configure MBUS window in order to enable access BM internal SRAM */
-+static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize,
-+                                u8 target, u8 attr)
-+{
-+      u32 win_enable, win_protect;
-+      int i;
-+
-+      win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE);
-+
-+      if (pp->bm_win_id < 0) {
-+              /* Find first not occupied window */
-+              for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) {
-+                      if (win_enable & (1 << i)) {
-+                              pp->bm_win_id = i;
-+                              break;
-+                      }
-+              }
-+              if (i == MVNETA_MAX_DECODE_WIN)
-+                      return -ENOMEM;
-+      } else {
-+              i = pp->bm_win_id;
-+      }
-+
-+      mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
-+      mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
-+
-+      if (i < 4)
-+              mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
-+
-+      mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) |
-+                  (attr << 8) | target);
-+
-+      mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000);
-+
-+      win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE);
-+      win_protect |= 3 << (2 * i);
-+      mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
-+
-+      win_enable &= ~(1 << i);
-+      mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
-+
-+      return 0;
-+}
-+
-+/* Assign and initialize pools for port. In case of fail
-+ * buffer manager will remain disabled for current port.
-+ */
-+static int mvneta_bm_port_init(struct platform_device *pdev,
-+                             struct mvneta_port *pp)
-+{
-+      struct device_node *dn = pdev->dev.of_node;
-+      u32 long_pool_id, short_pool_id, wsize;
-+      u8 target, attr;
-+      int err;
-+
-+      /* Get BM window information */
-+      err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize,
-+                                       &target, &attr);
-+      if (err < 0)
-+              return err;
-+
-+      pp->bm_win_id = -1;
-+
-+      /* Open NETA -> BM window */
-+      err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize,
-+                                   target, attr);
-+      if (err < 0) {
-+              netdev_info(pp->dev, "fail to configure mbus window to BM\n");
-+              return err;
-+      }
-+
-+      if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) {
-+              netdev_info(pp->dev, "missing long pool id\n");
-+              return -EINVAL;
-+      }
-+
-+      /* Create port's long pool depending on mtu */
-+      pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id,
-+                                         MVNETA_BM_LONG, pp->id,
-+                                         MVNETA_RX_PKT_SIZE(pp->dev->mtu));
-+      if (!pp->pool_long) {
-+              netdev_info(pp->dev, "fail to obtain long pool for port\n");
-+              return -ENOMEM;
-+      }
-+
-+      pp->pool_long->port_map |= 1 << pp->id;
-+
-+      mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size,
-+                                 pp->pool_long->id);
-+
-+      /* If short pool id is not defined, assume using single pool */
-+      if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id))
-+              short_pool_id = long_pool_id;
-+
-+      /* Create port's short pool */
-+      pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id,
-+                                          MVNETA_BM_SHORT, pp->id,
-+                                          MVNETA_BM_SHORT_PKT_SIZE);
-+      if (!pp->pool_short) {
-+              netdev_info(pp->dev, "fail to obtain short pool for port\n");
-+              mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
-+              return -ENOMEM;
-+      }
-+
-+      if (short_pool_id != long_pool_id) {
-+              pp->pool_short->port_map |= 1 << pp->id;
-+              mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size,
-+                                         pp->pool_short->id);
-+      }
-+
-+      return 0;
-+}
-+
-+/* Update settings of a pool for bigger packets */
-+static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu)
-+{
-+      struct mvneta_bm_pool *bm_pool = pp->pool_long;
-+      int num;
-+
-+      /* Release all buffers from long pool */
-+      mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id);
-+      if (bm_pool->buf_num) {
-+              WARN(1, "cannot free all buffers in pool %d\n",
-+                   bm_pool->id);
-+              goto bm_mtu_err;
-+      }
-+
-+      bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu);
-+      bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size);
-+      bm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
-+                        SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size));
-+
-+      /* Fill entire long pool */
-+      num = mvneta_bm_bufs_add(pp->bm_priv, bm_pool, bm_pool->size);
-+      if (num != bm_pool->size) {
-+              WARN(1, "pool %d: %d of %d allocated\n",
-+                   bm_pool->id, num, bm_pool->size);
-+              goto bm_mtu_err;
-+      }
-+      mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id);
-+
-+      return;
-+
-+bm_mtu_err:
-+      mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
-+      mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id);
-+
-+      pp->bm_priv = NULL;
-+      mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1);
-+      netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n");
-+}
-+
- /* Start the Ethernet port RX and TX activity */
- static void mvneta_port_up(struct mvneta_port *pp)
- {
-@@ -1147,9 +1379,17 @@ static void mvneta_defaults_set(struct m
-       mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
-       /* Set Port Acceleration Mode */
--      val = MVNETA_ACC_MODE_EXT;
-+      if (pp->bm_priv)
-+              /* HW buffer management + legacy parser */
-+              val = MVNETA_ACC_MODE_EXT2;
-+      else
-+              /* SW buffer management + legacy parser */
-+              val = MVNETA_ACC_MODE_EXT1;
-       mvreg_write(pp, MVNETA_ACC_MODE, val);
-+      if (pp->bm_priv)
-+              mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr);
-+
-       /* Update val of portCfg register accordingly with all RxQueue types */
-       val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
-       mvreg_write(pp, MVNETA_PORT_CONFIG, val);
-@@ -1516,23 +1756,25 @@ static void mvneta_txq_done(struct mvnet
-       }
- }
--static void *mvneta_frag_alloc(const struct mvneta_port *pp)
-+void *mvneta_frag_alloc(unsigned int frag_size)
- {
--      if (likely(pp->frag_size <= PAGE_SIZE))
--              return netdev_alloc_frag(pp->frag_size);
-+      if (likely(frag_size <= PAGE_SIZE))
-+              return netdev_alloc_frag(frag_size);
-       else
--              return kmalloc(pp->frag_size, GFP_ATOMIC);
-+              return kmalloc(frag_size, GFP_ATOMIC);
- }
-+EXPORT_SYMBOL_GPL(mvneta_frag_alloc);
--static void mvneta_frag_free(const struct mvneta_port *pp, void *data)
-+void mvneta_frag_free(unsigned int frag_size, void *data)
- {
--      if (likely(pp->frag_size <= PAGE_SIZE))
-+      if (likely(frag_size <= PAGE_SIZE))
-               skb_free_frag(data);
-       else
-               kfree(data);
- }
-+EXPORT_SYMBOL_GPL(mvneta_frag_free);
--/* Refill processing */
-+/* Refill processing for SW buffer management */
- static int mvneta_rx_refill(struct mvneta_port *pp,
-                           struct mvneta_rx_desc *rx_desc)
-@@ -1540,7 +1782,7 @@ static int mvneta_rx_refill(struct mvnet
-       dma_addr_t phys_addr;
-       void *data;
--      data = mvneta_frag_alloc(pp);
-+      data = mvneta_frag_alloc(pp->frag_size);
-       if (!data)
-               return -ENOMEM;
-@@ -1548,7 +1790,7 @@ static int mvneta_rx_refill(struct mvnet
-                                  MVNETA_RX_BUF_SIZE(pp->pkt_size),
-                                  DMA_FROM_DEVICE);
-       if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) {
--              mvneta_frag_free(pp, data);
-+              mvneta_frag_free(pp->frag_size, data);
-               return -ENOMEM;
-       }
-@@ -1594,22 +1836,156 @@ static void mvneta_rxq_drop_pkts(struct
-       int rx_done, i;
-       rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
-+      if (rx_done)
-+              mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
-+
-+      if (pp->bm_priv) {
-+              for (i = 0; i < rx_done; i++) {
-+                      struct mvneta_rx_desc *rx_desc =
-+                                                mvneta_rxq_next_desc_get(rxq);
-+                      u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
-+                      struct mvneta_bm_pool *bm_pool;
-+
-+                      bm_pool = &pp->bm_priv->bm_pools[pool_id];
-+                      /* Return dropped buffer to the pool */
-+                      mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
-+                                            rx_desc->buf_phys_addr);
-+              }
-+              return;
-+      }
-+
-       for (i = 0; i < rxq->size; i++) {
-               struct mvneta_rx_desc *rx_desc = rxq->descs + i;
-               void *data = (void *)rx_desc->buf_cookie;
-               dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
-                                MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
--              mvneta_frag_free(pp, data);
-+              mvneta_frag_free(pp->frag_size, data);
-       }
-+}
--      if (rx_done)
--              mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
-+/* Main rx processing when using software buffer management */
-+static int mvneta_rx_swbm(struct mvneta_port *pp, int rx_todo,
-+                        struct mvneta_rx_queue *rxq)
-+{
-+      struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
-+      struct net_device *dev = pp->dev;
-+      int rx_done;
-+      u32 rcvd_pkts = 0;
-+      u32 rcvd_bytes = 0;
-+
-+      /* Get number of received packets */
-+      rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
-+
-+      if (rx_todo > rx_done)
-+              rx_todo = rx_done;
-+
-+      rx_done = 0;
-+
-+      /* Fairness NAPI loop */
-+      while (rx_done < rx_todo) {
-+              struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
-+              struct sk_buff *skb;
-+              unsigned char *data;
-+              dma_addr_t phys_addr;
-+              u32 rx_status, frag_size;
-+              int rx_bytes, err;
-+
-+              rx_done++;
-+              rx_status = rx_desc->status;
-+              rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
-+              data = (unsigned char *)rx_desc->buf_cookie;
-+              phys_addr = rx_desc->buf_phys_addr;
-+
-+              if (!mvneta_rxq_desc_is_first_last(rx_status) ||
-+                  (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
-+err_drop_frame:
-+                      dev->stats.rx_errors++;
-+                      mvneta_rx_error(pp, rx_desc);
-+                      /* leave the descriptor untouched */
-+                      continue;
-+              }
-+
-+              if (rx_bytes <= rx_copybreak) {
-+              /* better copy a small frame and not unmap the DMA region */
-+                      skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
-+                      if (unlikely(!skb))
-+                              goto err_drop_frame;
-+
-+                      dma_sync_single_range_for_cpu(dev->dev.parent,
-+                                                    rx_desc->buf_phys_addr,
-+                                                    MVNETA_MH_SIZE + NET_SKB_PAD,
-+                                                    rx_bytes,
-+                                                    DMA_FROM_DEVICE);
-+                      memcpy(skb_put(skb, rx_bytes),
-+                             data + MVNETA_MH_SIZE + NET_SKB_PAD,
-+                             rx_bytes);
-+
-+                      skb->protocol = eth_type_trans(skb, dev);
-+                      mvneta_rx_csum(pp, rx_status, skb);
-+                      napi_gro_receive(&port->napi, skb);
-+
-+                      rcvd_pkts++;
-+                      rcvd_bytes += rx_bytes;
-+
-+                      /* leave the descriptor and buffer untouched */
-+                      continue;
-+              }
-+
-+              /* Refill processing */
-+              err = mvneta_rx_refill(pp, rx_desc);
-+              if (err) {
-+                      netdev_err(dev, "Linux processing - Can't refill\n");
-+                      rxq->missed++;
-+                      goto err_drop_frame;
-+              }
-+
-+              frag_size = pp->frag_size;
-+
-+              skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size);
-+
-+              /* After refill old buffer has to be unmapped regardless
-+               * the skb is successfully built or not.
-+               */
-+              dma_unmap_single(dev->dev.parent, phys_addr,
-+                               MVNETA_RX_BUF_SIZE(pp->pkt_size),
-+                               DMA_FROM_DEVICE);
-+
-+              if (!skb)
-+                      goto err_drop_frame;
-+
-+              rcvd_pkts++;
-+              rcvd_bytes += rx_bytes;
-+
-+              /* Linux processing */
-+              skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
-+              skb_put(skb, rx_bytes);
-+
-+              skb->protocol = eth_type_trans(skb, dev);
-+
-+              mvneta_rx_csum(pp, rx_status, skb);
-+
-+              napi_gro_receive(&port->napi, skb);
-+      }
-+
-+      if (rcvd_pkts) {
-+              struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
-+
-+              u64_stats_update_begin(&stats->syncp);
-+              stats->rx_packets += rcvd_pkts;
-+              stats->rx_bytes   += rcvd_bytes;
-+              u64_stats_update_end(&stats->syncp);
-+      }
-+
-+      /* Update rxq management counters */
-+      mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
-+
-+      return rx_done;
- }
--/* Main rx processing */
--static int mvneta_rx(struct mvneta_port *pp, int rx_todo,
--                   struct mvneta_rx_queue *rxq)
-+/* Main rx processing when using hardware buffer management */
-+static int mvneta_rx_hwbm(struct mvneta_port *pp, int rx_todo,
-+                        struct mvneta_rx_queue *rxq)
- {
-       struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
-       struct net_device *dev = pp->dev;
-@@ -1628,21 +2004,29 @@ static int mvneta_rx(struct mvneta_port
-       /* Fairness NAPI loop */
-       while (rx_done < rx_todo) {
-               struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
-+              struct mvneta_bm_pool *bm_pool = NULL;
-               struct sk_buff *skb;
-               unsigned char *data;
-               dma_addr_t phys_addr;
--              u32 rx_status;
-+              u32 rx_status, frag_size;
-               int rx_bytes, err;
-+              u8 pool_id;
-               rx_done++;
-               rx_status = rx_desc->status;
-               rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
-               data = (unsigned char *)rx_desc->buf_cookie;
-               phys_addr = rx_desc->buf_phys_addr;
-+              pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
-+              bm_pool = &pp->bm_priv->bm_pools[pool_id];
-               if (!mvneta_rxq_desc_is_first_last(rx_status) ||
-                   (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
--              err_drop_frame:
-+err_drop_frame_ret_pool:
-+                      /* Return the buffer to the pool */
-+                      mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
-+                                            rx_desc->buf_phys_addr);
-+err_drop_frame:
-                       dev->stats.rx_errors++;
-                       mvneta_rx_error(pp, rx_desc);
-                       /* leave the descriptor untouched */
-@@ -1653,7 +2037,7 @@ static int mvneta_rx(struct mvneta_port
-                       /* better copy a small frame and not unmap the DMA region */
-                       skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
-                       if (unlikely(!skb))
--                              goto err_drop_frame;
-+                              goto err_drop_frame_ret_pool;
-                       dma_sync_single_range_for_cpu(dev->dev.parent,
-                                                     rx_desc->buf_phys_addr,
-@@ -1671,26 +2055,31 @@ static int mvneta_rx(struct mvneta_port
-                       rcvd_pkts++;
-                       rcvd_bytes += rx_bytes;
-+                      /* Return the buffer to the pool */
-+                      mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
-+                                            rx_desc->buf_phys_addr);
-+
-                       /* leave the descriptor and buffer untouched */
-                       continue;
-               }
-               /* Refill processing */
--              err = mvneta_rx_refill(pp, rx_desc);
-+              err = mvneta_bm_pool_refill(pp->bm_priv, bm_pool);
-               if (err) {
-                       netdev_err(dev, "Linux processing - Can't refill\n");
-                       rxq->missed++;
--                      goto err_drop_frame;
-+                      goto err_drop_frame_ret_pool;
-               }
--              skb = build_skb(data, pp->frag_size > PAGE_SIZE ? 0 : pp->frag_size);
-+              frag_size = bm_pool->frag_size;
-+
-+              skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size);
-               /* After refill old buffer has to be unmapped regardless
-                * the skb is successfully built or not.
-                */
--              dma_unmap_single(dev->dev.parent, phys_addr,
--                               MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
--
-+              dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr,
-+                               bm_pool->buf_size, DMA_FROM_DEVICE);
-               if (!skb)
-                       goto err_drop_frame;
-@@ -2295,7 +2684,10 @@ static int mvneta_poll(struct napi_struc
-       if (rx_queue) {
-               rx_queue = rx_queue - 1;
--              rx_done = mvneta_rx(pp, budget, &pp->rxqs[rx_queue]);
-+              if (pp->bm_priv)
-+                      rx_done = mvneta_rx_hwbm(pp, budget, &pp->rxqs[rx_queue]);
-+              else
-+                      rx_done = mvneta_rx_swbm(pp, budget, &pp->rxqs[rx_queue]);
-       }
-       budget -= rx_done;
-@@ -2384,9 +2776,17 @@ static int mvneta_rxq_init(struct mvneta
-       mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
-       mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
--      /* Fill RXQ with buffers from RX pool */
--      mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size));
--      mvneta_rxq_bm_disable(pp, rxq);
-+      if (!pp->bm_priv) {
-+              /* Fill RXQ with buffers from RX pool */
-+              mvneta_rxq_buf_size_set(pp, rxq,
-+                                      MVNETA_RX_BUF_SIZE(pp->pkt_size));
-+              mvneta_rxq_bm_disable(pp, rxq);
-+      } else {
-+              mvneta_rxq_bm_enable(pp, rxq);
-+              mvneta_rxq_long_pool_set(pp, rxq);
-+              mvneta_rxq_short_pool_set(pp, rxq);
-+      }
-+
-       mvneta_rxq_fill(pp, rxq, rxq->size);
-       return 0;
-@@ -2659,6 +3059,9 @@ static int mvneta_change_mtu(struct net_
-       dev->mtu = mtu;
-       if (!netif_running(dev)) {
-+              if (pp->bm_priv)
-+                      mvneta_bm_update_mtu(pp, mtu);
-+
-               netdev_update_features(dev);
-               return 0;
-       }
-@@ -2671,6 +3074,9 @@ static int mvneta_change_mtu(struct net_
-       mvneta_cleanup_txqs(pp);
-       mvneta_cleanup_rxqs(pp);
-+      if (pp->bm_priv)
-+              mvneta_bm_update_mtu(pp, mtu);
-+
-       pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu);
-       pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
-                       SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
-@@ -3563,6 +3969,7 @@ static int mvneta_probe(struct platform_
-       struct resource *res;
-       struct device_node *dn = pdev->dev.of_node;
-       struct device_node *phy_node;
-+      struct device_node *bm_node;
-       struct mvneta_port *pp;
-       struct net_device *dev;
-       const char *dt_mac_addr;
-@@ -3690,26 +4097,39 @@ static int mvneta_probe(struct platform_
-       pp->tx_csum_limit = tx_csum_limit;
-+      dram_target_info = mv_mbus_dram_info();
-+      if (dram_target_info)
-+              mvneta_conf_mbus_windows(pp, dram_target_info);
-+
-       pp->tx_ring_size = MVNETA_MAX_TXD;
-       pp->rx_ring_size = MVNETA_MAX_RXD;
-       pp->dev = dev;
-       SET_NETDEV_DEV(dev, &pdev->dev);
-+      pp->id = global_port_id++;
-+
-+      /* Obtain access to BM resources if enabled and already initialized */
-+      bm_node = of_parse_phandle(dn, "buffer-manager", 0);
-+      if (bm_node && bm_node->data) {
-+              pp->bm_priv = bm_node->data;
-+              err = mvneta_bm_port_init(pdev, pp);
-+              if (err < 0) {
-+                      dev_info(&pdev->dev, "use SW buffer management\n");
-+                      pp->bm_priv = NULL;
-+              }
-+      }
-+
-       err = mvneta_init(&pdev->dev, pp);
-       if (err < 0)
--              goto err_free_stats;
-+              goto err_netdev;
-       err = mvneta_port_power_up(pp, phy_mode);
-       if (err < 0) {
-               dev_err(&pdev->dev, "can't power up port\n");
--              goto err_free_stats;
-+              goto err_netdev;
-       }
--      dram_target_info = mv_mbus_dram_info();
--      if (dram_target_info)
--              mvneta_conf_mbus_windows(pp, dram_target_info);
--
-       for_each_present_cpu(cpu) {
-               struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
-@@ -3744,6 +4164,13 @@ static int mvneta_probe(struct platform_
-       return 0;
-+err_netdev:
-+      unregister_netdev(dev);
-+      if (pp->bm_priv) {
-+              mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
-+              mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
-+                                     1 << pp->id);
-+      }
- err_free_stats:
-       free_percpu(pp->stats);
- err_free_ports:
-@@ -3773,6 +4200,12 @@ static int mvneta_remove(struct platform
-       of_node_put(pp->phy_node);
-       free_netdev(dev);
-+      if (pp->bm_priv) {
-+              mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
-+              mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
-+                                     1 << pp->id);
-+      }
-+
-       return 0;
- }
---- /dev/null
-+++ b/drivers/net/ethernet/marvell/mvneta_bm.c
-@@ -0,0 +1,546 @@
-+/*
-+ * Driver for Marvell NETA network controller Buffer Manager.
-+ *
-+ * Copyright (C) 2015 Marvell
-+ *
-+ * Marcin Wojtas <mw@semihalf.com>
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2. This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/genalloc.h>
-+#include <linux/platform_device.h>
-+#include <linux/netdevice.h>
-+#include <linux/skbuff.h>
-+#include <linux/mbus.h>
-+#include <linux/module.h>
-+#include <linux/io.h>
-+#include <linux/of.h>
-+#include <linux/clk.h>
-+#include "mvneta_bm.h"
-+
-+#define MVNETA_BM_DRIVER_NAME "mvneta_bm"
-+#define MVNETA_BM_DRIVER_VERSION "1.0"
-+
-+static void mvneta_bm_write(struct mvneta_bm *priv, u32 offset, u32 data)
-+{
-+      writel(data, priv->reg_base + offset);
-+}
-+
-+static u32 mvneta_bm_read(struct mvneta_bm *priv, u32 offset)
-+{
-+      return readl(priv->reg_base + offset);
-+}
-+
-+static void mvneta_bm_pool_enable(struct mvneta_bm *priv, int pool_id)
-+{
-+      u32 val;
-+
-+      val = mvneta_bm_read(priv, MVNETA_BM_POOL_BASE_REG(pool_id));
-+      val |= MVNETA_BM_POOL_ENABLE_MASK;
-+      mvneta_bm_write(priv, MVNETA_BM_POOL_BASE_REG(pool_id), val);
-+
-+      /* Clear BM cause register */
-+      mvneta_bm_write(priv, MVNETA_BM_INTR_CAUSE_REG, 0);
-+}
-+
-+static void mvneta_bm_pool_disable(struct mvneta_bm *priv, int pool_id)
-+{
-+      u32 val;
-+
-+      val = mvneta_bm_read(priv, MVNETA_BM_POOL_BASE_REG(pool_id));
-+      val &= ~MVNETA_BM_POOL_ENABLE_MASK;
-+      mvneta_bm_write(priv, MVNETA_BM_POOL_BASE_REG(pool_id), val);
-+}
-+
-+static inline void mvneta_bm_config_set(struct mvneta_bm *priv, u32 mask)
-+{
-+      u32 val;
-+
-+      val = mvneta_bm_read(priv, MVNETA_BM_CONFIG_REG);
-+      val |= mask;
-+      mvneta_bm_write(priv, MVNETA_BM_CONFIG_REG, val);
-+}
-+
-+static inline void mvneta_bm_config_clear(struct mvneta_bm *priv, u32 mask)
-+{
-+      u32 val;
-+
-+      val = mvneta_bm_read(priv, MVNETA_BM_CONFIG_REG);
-+      val &= ~mask;
-+      mvneta_bm_write(priv, MVNETA_BM_CONFIG_REG, val);
-+}
-+
-+static void mvneta_bm_pool_target_set(struct mvneta_bm *priv, int pool_id,
-+                                    u8 target_id, u8 attr)
-+{
-+      u32 val;
-+
-+      val = mvneta_bm_read(priv, MVNETA_BM_XBAR_POOL_REG(pool_id));
-+      val &= ~MVNETA_BM_TARGET_ID_MASK(pool_id);
-+      val &= ~MVNETA_BM_XBAR_ATTR_MASK(pool_id);
-+      val |= MVNETA_BM_TARGET_ID_VAL(pool_id, target_id);
-+      val |= MVNETA_BM_XBAR_ATTR_VAL(pool_id, attr);
-+
-+      mvneta_bm_write(priv, MVNETA_BM_XBAR_POOL_REG(pool_id), val);
-+}
-+
-+/* Allocate skb for BM pool */
-+void *mvneta_buf_alloc(struct mvneta_bm *priv, struct mvneta_bm_pool *bm_pool,
-+                     dma_addr_t *buf_phys_addr)
-+{
-+      void *buf;
-+      dma_addr_t phys_addr;
-+
-+      buf = mvneta_frag_alloc(bm_pool->frag_size);
-+      if (!buf)
-+              return NULL;
-+
-+      /* In order to update buf_cookie field of RX descriptor properly,
-+       * BM hardware expects buf virtual address to be placed in the
-+       * first four bytes of mapped buffer.
-+       */
-+      *(u32 *)buf = (u32)buf;
-+      phys_addr = dma_map_single(&priv->pdev->dev, buf, bm_pool->buf_size,
-+                                 DMA_FROM_DEVICE);
-+      if (unlikely(dma_mapping_error(&priv->pdev->dev, phys_addr))) {
-+              mvneta_frag_free(bm_pool->frag_size, buf);
-+              return NULL;
-+      }
-+      *buf_phys_addr = phys_addr;
-+
-+      return buf;
-+}
-+
-+/* Refill processing for HW buffer management */
-+int mvneta_bm_pool_refill(struct mvneta_bm *priv,
-+                        struct mvneta_bm_pool *bm_pool)
-+{
-+      dma_addr_t buf_phys_addr;
-+      void *buf;
-+
-+      buf = mvneta_buf_alloc(priv, bm_pool, &buf_phys_addr);
-+      if (!buf)
-+              return -ENOMEM;
-+
-+      mvneta_bm_pool_put_bp(priv, bm_pool, buf_phys_addr);
-+
-+      return 0;
-+}
-+EXPORT_SYMBOL_GPL(mvneta_bm_pool_refill);
-+
-+/* Allocate buffers for the pool */
-+int mvneta_bm_bufs_add(struct mvneta_bm *priv, struct mvneta_bm_pool *bm_pool,
-+                     int buf_num)
-+{
-+      int err, i;
-+
-+      if (bm_pool->buf_num == bm_pool->size) {
-+              dev_dbg(&priv->pdev->dev, "pool %d already filled\n",
-+                      bm_pool->id);
-+              return bm_pool->buf_num;
-+      }
-+
-+      if (buf_num < 0 ||
-+          (buf_num + bm_pool->buf_num > bm_pool->size)) {
-+              dev_err(&priv->pdev->dev,
-+                      "cannot allocate %d buffers for pool %d\n",
-+                      buf_num, bm_pool->id);
-+              return 0;
-+      }
-+
-+      for (i = 0; i < buf_num; i++) {
-+              err = mvneta_bm_pool_refill(priv, bm_pool);
-+              if (err < 0)
-+                      break;
-+      }
-+
-+      /* Update BM driver with number of buffers added to pool */
-+      bm_pool->buf_num += i;
-+
-+      dev_dbg(&priv->pdev->dev,
-+              "%s pool %d: pkt_size=%4d, buf_size=%4d, frag_size=%4d\n",
-+              bm_pool->type == MVNETA_BM_SHORT ? "short" : "long",
-+              bm_pool->id, bm_pool->pkt_size, bm_pool->buf_size,
-+              bm_pool->frag_size);
-+
-+      dev_dbg(&priv->pdev->dev,
-+              "%s pool %d: %d of %d buffers added\n",
-+              bm_pool->type == MVNETA_BM_SHORT ? "short" : "long",
-+              bm_pool->id, i, buf_num);
-+
-+      return i;
-+}
-+EXPORT_SYMBOL_GPL(mvneta_bm_bufs_add);
-+
-+/* Create pool */
-+static int mvneta_bm_pool_create(struct mvneta_bm *priv,
-+                               struct mvneta_bm_pool *bm_pool)
-+{
-+      struct platform_device *pdev = priv->pdev;
-+      u8 target_id, attr;
-+      int size_bytes, err;
-+
-+      size_bytes = sizeof(u32) * bm_pool->size;
-+      bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, size_bytes,
-+                                              &bm_pool->phys_addr,
-+                                              GFP_KERNEL);
-+      if (!bm_pool->virt_addr)
-+              return -ENOMEM;
-+
-+      if (!IS_ALIGNED((u32)bm_pool->virt_addr, MVNETA_BM_POOL_PTR_ALIGN)) {
-+              dma_free_coherent(&pdev->dev, size_bytes, bm_pool->virt_addr,
-+                                bm_pool->phys_addr);
-+              dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
-+                      bm_pool->id, MVNETA_BM_POOL_PTR_ALIGN);
-+              return -ENOMEM;
-+      }
-+
-+      err = mvebu_mbus_get_dram_win_info(bm_pool->phys_addr, &target_id,
-+                                         &attr);
-+      if (err < 0) {
-+              dma_free_coherent(&pdev->dev, size_bytes, bm_pool->virt_addr,
-+                                bm_pool->phys_addr);
-+              return err;
-+      }
-+
-+      /* Set pool address */
-+      mvneta_bm_write(priv, MVNETA_BM_POOL_BASE_REG(bm_pool->id),
-+                      bm_pool->phys_addr);
-+
-+      mvneta_bm_pool_target_set(priv, bm_pool->id, target_id,  attr);
-+      mvneta_bm_pool_enable(priv, bm_pool->id);
-+
-+      return 0;
-+}
-+
-+/* Notify the driver that BM pool is being used as specific type and return the
-+ * pool pointer on success
-+ */
-+struct mvneta_bm_pool *mvneta_bm_pool_use(struct mvneta_bm *priv, u8 pool_id,
-+                                        enum mvneta_bm_type type, u8 port_id,
-+                                        int pkt_size)
-+{
-+      struct mvneta_bm_pool *new_pool = &priv->bm_pools[pool_id];
-+      int num, err;
-+
-+      if (new_pool->type == MVNETA_BM_LONG &&
-+          new_pool->port_map != 1 << port_id) {
-+              dev_err(&priv->pdev->dev,
-+                      "long pool cannot be shared by the ports\n");
-+              return NULL;
-+      }
-+
-+      if (new_pool->type == MVNETA_BM_SHORT && new_pool->type != type) {
-+              dev_err(&priv->pdev->dev,
-+                      "mixing pools' types between the ports is forbidden\n");
-+              return NULL;
-+      }
-+
-+      if (new_pool->pkt_size == 0 || type != MVNETA_BM_SHORT)
-+              new_pool->pkt_size = pkt_size;
-+
-+      /* Allocate buffers in case BM pool hasn't been used yet */
-+      if (new_pool->type == MVNETA_BM_FREE) {
-+              new_pool->type = type;
-+              new_pool->buf_size = MVNETA_RX_BUF_SIZE(new_pool->pkt_size);
-+              new_pool->frag_size =
-+                      SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(new_pool->pkt_size)) +
-+                      SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
-+
-+              /* Create new pool */
-+              err = mvneta_bm_pool_create(priv, new_pool);
-+              if (err) {
-+                      dev_err(&priv->pdev->dev, "fail to create pool %d\n",
-+                              new_pool->id);
-+                      return NULL;
-+              }
-+
-+              /* Allocate buffers for this pool */
-+              num = mvneta_bm_bufs_add(priv, new_pool, new_pool->size);
-+              if (num != new_pool->size) {
-+                      WARN(1, "pool %d: %d of %d allocated\n",
-+                           new_pool->id, num, new_pool->size);
-+                      return NULL;
-+              }
-+      }
-+
-+      return new_pool;
-+}
-+EXPORT_SYMBOL_GPL(mvneta_bm_pool_use);
-+
-+/* Free all buffers from the pool */
-+void mvneta_bm_bufs_free(struct mvneta_bm *priv, struct mvneta_bm_pool *bm_pool,
-+                       u8 port_map)
-+{
-+      int i;
-+
-+      bm_pool->port_map &= ~port_map;
-+      if (bm_pool->port_map)
-+              return;
-+
-+      mvneta_bm_config_set(priv, MVNETA_BM_EMPTY_LIMIT_MASK);
-+
-+      for (i = 0; i < bm_pool->buf_num; i++) {
-+              dma_addr_t buf_phys_addr;
-+              u32 *vaddr;
-+
-+              /* Get buffer physical address (indirect access) */
-+              buf_phys_addr = mvneta_bm_pool_get_bp(priv, bm_pool);
-+
-+              /* Work-around to the problems when destroying the pool,
-+               * when it occurs that a read access to BPPI returns 0.
-+               */
-+              if (buf_phys_addr == 0)
-+                      continue;
-+
-+              vaddr = phys_to_virt(buf_phys_addr);
-+              if (!vaddr)
-+                      break;
-+
-+              dma_unmap_single(&priv->pdev->dev, buf_phys_addr,
-+                               bm_pool->buf_size, DMA_FROM_DEVICE);
-+              mvneta_frag_free(bm_pool->frag_size, vaddr);
-+      }
-+
-+      mvneta_bm_config_clear(priv, MVNETA_BM_EMPTY_LIMIT_MASK);
-+
-+      /* Update BM driver with number of buffers removed from pool */
-+      bm_pool->buf_num -= i;
-+}
-+EXPORT_SYMBOL_GPL(mvneta_bm_bufs_free);
-+
-+/* Cleanup pool */
-+void mvneta_bm_pool_destroy(struct mvneta_bm *priv,
-+                          struct mvneta_bm_pool *bm_pool, u8 port_map)
-+{
-+      bm_pool->port_map &= ~port_map;
-+      if (bm_pool->port_map)
-+              return;
-+
-+      bm_pool->type = MVNETA_BM_FREE;
-+
-+      mvneta_bm_bufs_free(priv, bm_pool, port_map);
-+      if (bm_pool->buf_num)
-+              WARN(1, "cannot free all buffers in pool %d\n", bm_pool->id);
-+
-+      if (bm_pool->virt_addr) {
-+              dma_free_coherent(&priv->pdev->dev, sizeof(u32) * bm_pool->size,
-+                                bm_pool->virt_addr, bm_pool->phys_addr);
-+              bm_pool->virt_addr = NULL;
-+      }
-+
-+      mvneta_bm_pool_disable(priv, bm_pool->id);
-+}
-+EXPORT_SYMBOL_GPL(mvneta_bm_pool_destroy);
-+
-+static void mvneta_bm_pools_init(struct mvneta_bm *priv)
-+{
-+      struct device_node *dn = priv->pdev->dev.of_node;
-+      struct mvneta_bm_pool *bm_pool;
-+      char prop[15];
-+      u32 size;
-+      int i;
-+
-+      /* Activate BM unit */
-+      mvneta_bm_write(priv, MVNETA_BM_COMMAND_REG, MVNETA_BM_START_MASK);
-+
-+      /* Create all pools with maximum size */
-+      for (i = 0; i < MVNETA_BM_POOLS_NUM; i++) {
-+              bm_pool = &priv->bm_pools[i];
-+              bm_pool->id = i;
-+              bm_pool->type = MVNETA_BM_FREE;
-+
-+              /* Reset read pointer */
-+              mvneta_bm_write(priv, MVNETA_BM_POOL_READ_PTR_REG(i), 0);
-+
-+              /* Reset write pointer */
-+              mvneta_bm_write(priv, MVNETA_BM_POOL_WRITE_PTR_REG(i), 0);
-+
-+              /* Configure pool size according to DT or use default value */
-+              sprintf(prop, "pool%d,capacity", i);
-+              if (of_property_read_u32(dn, prop, &size)) {
-+                      size = MVNETA_BM_POOL_CAP_DEF;
-+              } else if (size > MVNETA_BM_POOL_CAP_MAX) {
-+                      dev_warn(&priv->pdev->dev,
-+                               "Illegal pool %d capacity %d, set to %d\n",
-+                               i, size, MVNETA_BM_POOL_CAP_MAX);
-+                      size = MVNETA_BM_POOL_CAP_MAX;
-+              } else if (size < MVNETA_BM_POOL_CAP_MIN) {
-+                      dev_warn(&priv->pdev->dev,
-+                               "Illegal pool %d capacity %d, set to %d\n",
-+                               i, size, MVNETA_BM_POOL_CAP_MIN);
-+                      size = MVNETA_BM_POOL_CAP_MIN;
-+              } else if (!IS_ALIGNED(size, MVNETA_BM_POOL_CAP_ALIGN)) {
-+                      dev_warn(&priv->pdev->dev,
-+                               "Illegal pool %d capacity %d, round to %d\n",
-+                               i, size, ALIGN(size,
-+                               MVNETA_BM_POOL_CAP_ALIGN));
-+                      size = ALIGN(size, MVNETA_BM_POOL_CAP_ALIGN);
-+              }
-+              bm_pool->size = size;
-+
-+              mvneta_bm_write(priv, MVNETA_BM_POOL_SIZE_REG(i),
-+                              bm_pool->size);
-+
-+              /* Obtain custom pkt_size from DT */
-+              sprintf(prop, "pool%d,pkt-size", i);
-+              if (of_property_read_u32(dn, prop, &bm_pool->pkt_size))
-+                      bm_pool->pkt_size = 0;
-+      }
-+}
-+
-+static void mvneta_bm_default_set(struct mvneta_bm *priv)
-+{
-+      u32 val;
-+
-+      /* Mask BM all interrupts */
-+      mvneta_bm_write(priv, MVNETA_BM_INTR_MASK_REG, 0);
-+
-+      /* Clear BM cause register */
-+      mvneta_bm_write(priv, MVNETA_BM_INTR_CAUSE_REG, 0);
-+
-+      /* Set BM configuration register */
-+      val = mvneta_bm_read(priv, MVNETA_BM_CONFIG_REG);
-+
-+      /* Reduce MaxInBurstSize from 32 BPs to 16 BPs */
-+      val &= ~MVNETA_BM_MAX_IN_BURST_SIZE_MASK;
-+      val |= MVNETA_BM_MAX_IN_BURST_SIZE_16BP;
-+      mvneta_bm_write(priv, MVNETA_BM_CONFIG_REG, val);
-+}
-+
-+static int mvneta_bm_init(struct mvneta_bm *priv)
-+{
-+      mvneta_bm_default_set(priv);
-+
-+      /* Allocate and initialize BM pools structures */
-+      priv->bm_pools = devm_kcalloc(&priv->pdev->dev, MVNETA_BM_POOLS_NUM,
-+                                    sizeof(struct mvneta_bm_pool),
-+                                    GFP_KERNEL);
-+      if (!priv->bm_pools)
-+              return -ENOMEM;
-+
-+      mvneta_bm_pools_init(priv);
-+
-+      return 0;
-+}
-+
-+static int mvneta_bm_get_sram(struct device_node *dn,
-+                            struct mvneta_bm *priv)
-+{
-+      priv->bppi_pool = of_gen_pool_get(dn, "internal-mem", 0);
-+      if (!priv->bppi_pool)
-+              return -ENOMEM;
-+
-+      priv->bppi_virt_addr = gen_pool_dma_alloc(priv->bppi_pool,
-+                                                MVNETA_BM_BPPI_SIZE,
-+                                                &priv->bppi_phys_addr);
-+      if (!priv->bppi_virt_addr)
-+              return -ENOMEM;
-+
-+      return 0;
-+}
-+
-+static void mvneta_bm_put_sram(struct mvneta_bm *priv)
-+{
-+      gen_pool_free(priv->bppi_pool, priv->bppi_phys_addr,
-+                    MVNETA_BM_BPPI_SIZE);
-+}
-+
-+static int mvneta_bm_probe(struct platform_device *pdev)
-+{
-+      struct device_node *dn = pdev->dev.of_node;
-+      struct mvneta_bm *priv;
-+      struct resource *res;
-+      int err;
-+
-+      priv = devm_kzalloc(&pdev->dev, sizeof(struct mvneta_bm), GFP_KERNEL);
-+      if (!priv)
-+              return -ENOMEM;
-+
-+      res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+      priv->reg_base = devm_ioremap_resource(&pdev->dev, res);
-+      if (IS_ERR(priv->reg_base))
-+              return PTR_ERR(priv->reg_base);
-+
-+      priv->clk = devm_clk_get(&pdev->dev, NULL);
-+      if (IS_ERR(priv->clk))
-+              return PTR_ERR(priv->clk);
-+      err = clk_prepare_enable(priv->clk);
-+      if (err < 0)
-+              return err;
-+
-+      err = mvneta_bm_get_sram(dn, priv);
-+      if (err < 0) {
-+              dev_err(&pdev->dev, "failed to allocate internal memory\n");
-+              goto err_clk;
-+      }
-+
-+      priv->pdev = pdev;
-+
-+      /* Initialize buffer manager internals */
-+      err = mvneta_bm_init(priv);
-+      if (err < 0) {
-+              dev_err(&pdev->dev, "failed to initialize controller\n");
-+              goto err_sram;
-+      }
-+
-+      dn->data = priv;
-+      platform_set_drvdata(pdev, priv);
-+
-+      dev_info(&pdev->dev, "Buffer Manager for network controller enabled\n");
-+
-+      return 0;
-+
-+err_sram:
-+      mvneta_bm_put_sram(priv);
-+err_clk:
-+      clk_disable_unprepare(priv->clk);
-+      return err;
-+}
-+
-+static int mvneta_bm_remove(struct platform_device *pdev)
-+{
-+      struct mvneta_bm *priv = platform_get_drvdata(pdev);
-+      u8 all_ports_map = 0xff;
-+      int i = 0;
-+
-+      for (i = 0; i < MVNETA_BM_POOLS_NUM; i++) {
-+              struct mvneta_bm_pool *bm_pool = &priv->bm_pools[i];
-+
-+              mvneta_bm_pool_destroy(priv, bm_pool, all_ports_map);
-+      }
-+
-+      mvneta_bm_put_sram(priv);
-+
-+      /* Dectivate BM unit */
-+      mvneta_bm_write(priv, MVNETA_BM_COMMAND_REG, MVNETA_BM_STOP_MASK);
-+
-+      clk_disable_unprepare(priv->clk);
-+
-+      return 0;
-+}
-+
-+static const struct of_device_id mvneta_bm_match[] = {
-+      { .compatible = "marvell,armada-380-neta-bm" },
-+      { }
-+};
-+MODULE_DEVICE_TABLE(of, mvneta_bm_match);
-+
-+static struct platform_driver mvneta_bm_driver = {
-+      .probe = mvneta_bm_probe,
-+      .remove = mvneta_bm_remove,
-+      .driver = {
-+              .name = MVNETA_BM_DRIVER_NAME,
-+              .of_match_table = mvneta_bm_match,
-+      },
-+};
-+
-+module_platform_driver(mvneta_bm_driver);
-+
-+MODULE_DESCRIPTION("Marvell NETA Buffer Manager Driver - www.marvell.com");
-+MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>");
-+MODULE_LICENSE("GPL v2");
---- /dev/null
-+++ b/drivers/net/ethernet/marvell/mvneta_bm.h
-@@ -0,0 +1,189 @@
-+/*
-+ * Driver for Marvell NETA network controller Buffer Manager.
-+ *
-+ * Copyright (C) 2015 Marvell
-+ *
-+ * Marcin Wojtas <mw@semihalf.com>
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2. This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+#ifndef _MVNETA_BM_H_
-+#define _MVNETA_BM_H_
-+
-+/* BM Configuration Register */
-+#define MVNETA_BM_CONFIG_REG                  0x0
-+#define    MVNETA_BM_STATUS_MASK              0x30
-+#define    MVNETA_BM_ACTIVE_MASK              BIT(4)
-+#define    MVNETA_BM_MAX_IN_BURST_SIZE_MASK   0x60000
-+#define    MVNETA_BM_MAX_IN_BURST_SIZE_16BP   BIT(18)
-+#define    MVNETA_BM_EMPTY_LIMIT_MASK         BIT(19)
-+
-+/* BM Activation Register */
-+#define MVNETA_BM_COMMAND_REG                 0x4
-+#define    MVNETA_BM_START_MASK                       BIT(0)
-+#define    MVNETA_BM_STOP_MASK                        BIT(1)
-+#define    MVNETA_BM_PAUSE_MASK                       BIT(2)
-+
-+/* BM Xbar interface Register */
-+#define MVNETA_BM_XBAR_01_REG                 0x8
-+#define MVNETA_BM_XBAR_23_REG                 0xc
-+#define MVNETA_BM_XBAR_POOL_REG(pool)         \
-+              (((pool) < 2) ? MVNETA_BM_XBAR_01_REG : MVNETA_BM_XBAR_23_REG)
-+#define     MVNETA_BM_TARGET_ID_OFFS(pool)    (((pool) & 1) ? 16 : 0)
-+#define     MVNETA_BM_TARGET_ID_MASK(pool)    \
-+              (0xf << MVNETA_BM_TARGET_ID_OFFS(pool))
-+#define     MVNETA_BM_TARGET_ID_VAL(pool, id) \
-+              ((id) << MVNETA_BM_TARGET_ID_OFFS(pool))
-+#define     MVNETA_BM_XBAR_ATTR_OFFS(pool)    (((pool) & 1) ? 20 : 4)
-+#define     MVNETA_BM_XBAR_ATTR_MASK(pool)    \
-+              (0xff << MVNETA_BM_XBAR_ATTR_OFFS(pool))
-+#define     MVNETA_BM_XBAR_ATTR_VAL(pool, attr)       \
-+              ((attr) << MVNETA_BM_XBAR_ATTR_OFFS(pool))
-+
-+/* Address of External Buffer Pointers Pool Register */
-+#define MVNETA_BM_POOL_BASE_REG(pool)         (0x10 + ((pool) << 4))
-+#define     MVNETA_BM_POOL_ENABLE_MASK                BIT(0)
-+
-+/* External Buffer Pointers Pool RD pointer Register */
-+#define MVNETA_BM_POOL_READ_PTR_REG(pool)     (0x14 + ((pool) << 4))
-+#define     MVNETA_BM_POOL_SET_READ_PTR_MASK  0xfffc
-+#define     MVNETA_BM_POOL_GET_READ_PTR_OFFS  16
-+#define     MVNETA_BM_POOL_GET_READ_PTR_MASK  0xfffc0000
-+
-+/* External Buffer Pointers Pool WR pointer */
-+#define MVNETA_BM_POOL_WRITE_PTR_REG(pool)    (0x18 + ((pool) << 4))
-+#define     MVNETA_BM_POOL_SET_WRITE_PTR_OFFS 0
-+#define     MVNETA_BM_POOL_SET_WRITE_PTR_MASK 0xfffc
-+#define     MVNETA_BM_POOL_GET_WRITE_PTR_OFFS 16
-+#define     MVNETA_BM_POOL_GET_WRITE_PTR_MASK 0xfffc0000
-+
-+/* External Buffer Pointers Pool Size Register */
-+#define MVNETA_BM_POOL_SIZE_REG(pool)         (0x1c + ((pool) << 4))
-+#define     MVNETA_BM_POOL_SIZE_MASK          0x3fff
-+
-+/* BM Interrupt Cause Register */
-+#define MVNETA_BM_INTR_CAUSE_REG              (0x50)
-+
-+/* BM interrupt Mask Register */
-+#define MVNETA_BM_INTR_MASK_REG                       (0x54)
-+
-+/* Other definitions */
-+#define MVNETA_BM_SHORT_PKT_SIZE              256
-+#define MVNETA_BM_POOLS_NUM                   4
-+#define MVNETA_BM_POOL_CAP_MIN                        128
-+#define MVNETA_BM_POOL_CAP_DEF                        2048
-+#define MVNETA_BM_POOL_CAP_MAX                        \
-+              (16 * 1024 - MVNETA_BM_POOL_CAP_ALIGN)
-+#define MVNETA_BM_POOL_CAP_ALIGN              32
-+#define MVNETA_BM_POOL_PTR_ALIGN              32
-+
-+#define MVNETA_BM_POOL_ACCESS_OFFS            8
-+
-+#define MVNETA_BM_BPPI_SIZE                   0x100000
-+
-+#define MVNETA_RX_BUF_SIZE(pkt_size)   ((pkt_size) + NET_SKB_PAD)
-+
-+enum mvneta_bm_type {
-+      MVNETA_BM_FREE,
-+      MVNETA_BM_LONG,
-+      MVNETA_BM_SHORT
-+};
-+
-+struct mvneta_bm {
-+      void __iomem *reg_base;
-+      struct clk *clk;
-+      struct platform_device *pdev;
-+
-+      struct gen_pool *bppi_pool;
-+      /* BPPI virtual base address */
-+      void __iomem *bppi_virt_addr;
-+      /* BPPI physical base address */
-+      dma_addr_t bppi_phys_addr;
-+
-+      /* BM pools */
-+      struct mvneta_bm_pool *bm_pools;
-+};
-+
-+struct mvneta_bm_pool {
-+      /* Pool number in the range 0-3 */
-+      u8 id;
-+      enum mvneta_bm_type type;
-+
-+      /* Buffer Pointers Pool External (BPPE) size in number of bytes */
-+      int size;
-+      /* Number of buffers used by this pool */
-+      int buf_num;
-+      /* Pool buffer size */
-+      int buf_size;
-+      /* Packet size */
-+      int pkt_size;
-+      /* Single frag size */
-+      u32 frag_size;
-+
-+      /* BPPE virtual base address */
-+      u32 *virt_addr;
-+      /* BPPE physical base address */
-+      dma_addr_t phys_addr;
-+
-+      /* Ports using BM pool */
-+      u8 port_map;
-+
-+      struct mvneta_bm *priv;
-+};
-+
-+/* Declarations and definitions */
-+void *mvneta_frag_alloc(unsigned int frag_size);
-+void mvneta_frag_free(unsigned int frag_size, void *data);
-+
-+#if defined(CONFIG_MVNETA_BM) || defined(CONFIG_MVNETA_BM_MODULE)
-+void mvneta_bm_pool_destroy(struct mvneta_bm *priv,
-+                          struct mvneta_bm_pool *bm_pool, u8 port_map);
-+void mvneta_bm_bufs_free(struct mvneta_bm *priv, struct mvneta_bm_pool *bm_pool,
-+                       u8 port_map);
-+int mvneta_bm_bufs_add(struct mvneta_bm *priv, struct mvneta_bm_pool *bm_pool,
-+                     int buf_num);
-+int mvneta_bm_pool_refill(struct mvneta_bm *priv,
-+                        struct mvneta_bm_pool *bm_pool);
-+struct mvneta_bm_pool *mvneta_bm_pool_use(struct mvneta_bm *priv, u8 pool_id,
-+                                        enum mvneta_bm_type type, u8 port_id,
-+                                        int pkt_size);
-+
-+static inline void mvneta_bm_pool_put_bp(struct mvneta_bm *priv,
-+                                       struct mvneta_bm_pool *bm_pool,
-+                                       dma_addr_t buf_phys_addr)
-+{
-+      writel_relaxed(buf_phys_addr, priv->bppi_virt_addr +
-+                     (bm_pool->id << MVNETA_BM_POOL_ACCESS_OFFS));
-+}
-+
-+static inline u32 mvneta_bm_pool_get_bp(struct mvneta_bm *priv,
-+                                      struct mvneta_bm_pool *bm_pool)
-+{
-+      return readl_relaxed(priv->bppi_virt_addr +
-+                           (bm_pool->id << MVNETA_BM_POOL_ACCESS_OFFS));
-+}
-+#else
-+void mvneta_bm_pool_destroy(struct mvneta_bm *priv,
-+                          struct mvneta_bm_pool *bm_pool, u8 port_map) {}
-+void mvneta_bm_bufs_free(struct mvneta_bm *priv, struct mvneta_bm_pool *bm_pool,
-+                       u8 port_map) {}
-+int mvneta_bm_bufs_add(struct mvneta_bm *priv, struct mvneta_bm_pool *bm_pool,
-+                     int buf_num) { return 0; }
-+int mvneta_bm_pool_refill(struct mvneta_bm *priv,
-+                        struct mvneta_bm_pool *bm_pool) {return 0; }
-+struct mvneta_bm_pool *mvneta_bm_pool_use(struct mvneta_bm *priv, u8 pool_id,
-+                                        enum mvneta_bm_type type, u8 port_id,
-+                                        int pkt_size) { return NULL; }
-+
-+static inline void mvneta_bm_pool_put_bp(struct mvneta_bm *priv,
-+                                       struct mvneta_bm_pool *bm_pool,
-+                                       dma_addr_t buf_phys_addr) {}
-+
-+static inline u32 mvneta_bm_pool_get_bp(struct mvneta_bm *priv,
-+                                      struct mvneta_bm_pool *bm_pool)
-+{ return 0; }
-+#endif /* CONFIG_MVNETA_BM */
-+#endif
diff --git a/target/linux/mvebu/patches-4.4/046-net-mvneta-Use-the-new-hwbm-framework.patch b/target/linux/mvebu/patches-4.4/046-net-mvneta-Use-the-new-hwbm-framework.patch
deleted file mode 100644 (file)
index 210504c..0000000
+++ /dev/null
@@ -1,359 +0,0 @@
-From: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Date: Mon, 14 Mar 2016 09:39:05 +0100
-Subject: [PATCH] net: mvneta: Use the new hwbm framework
-
-Now that the hardware buffer management framework had been introduced,
-let's use it.
-
-Tested-by: Sebastian Careba <nitroshift@yahoo.com>
-Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
-
---- a/drivers/net/ethernet/marvell/Kconfig
-+++ b/drivers/net/ethernet/marvell/Kconfig
-@@ -43,6 +43,7 @@ config MVMDIO
- config MVNETA_BM
-       tristate "Marvell Armada 38x/XP network interface BM support"
-       depends on MVNETA
-+      select HWBM
-       ---help---
-         This driver supports auxiliary block of the network
-         interface units in the Marvell ARMADA XP and ARMADA 38x SoC
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -30,6 +30,7 @@
- #include <linux/phy.h>
- #include <linux/platform_device.h>
- #include <linux/skbuff.h>
-+#include <net/hwbm.h>
- #include "mvneta_bm.h"
- #include <net/ip.h>
- #include <net/ipv6.h>
-@@ -1024,11 +1025,12 @@ static int mvneta_bm_port_init(struct pl
- static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu)
- {
-       struct mvneta_bm_pool *bm_pool = pp->pool_long;
-+      struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool;
-       int num;
-       /* Release all buffers from long pool */
-       mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id);
--      if (bm_pool->buf_num) {
-+      if (hwbm_pool->buf_num) {
-               WARN(1, "cannot free all buffers in pool %d\n",
-                    bm_pool->id);
-               goto bm_mtu_err;
-@@ -1036,14 +1038,14 @@ static void mvneta_bm_update_mtu(struct
-       bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu);
-       bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size);
--      bm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
--                        SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size));
-+      hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
-+                      SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size));
-       /* Fill entire long pool */
--      num = mvneta_bm_bufs_add(pp->bm_priv, bm_pool, bm_pool->size);
--      if (num != bm_pool->size) {
-+      num = hwbm_pool_add(hwbm_pool, hwbm_pool->size, GFP_ATOMIC);
-+      if (num != hwbm_pool->size) {
-               WARN(1, "pool %d: %d of %d allocated\n",
--                   bm_pool->id, num, bm_pool->size);
-+                   bm_pool->id, num, hwbm_pool->size);
-               goto bm_mtu_err;
-       }
-       mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id);
-@@ -2064,14 +2066,14 @@ err_drop_frame:
-               }
-               /* Refill processing */
--              err = mvneta_bm_pool_refill(pp->bm_priv, bm_pool);
-+              err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC);
-               if (err) {
-                       netdev_err(dev, "Linux processing - Can't refill\n");
-                       rxq->missed++;
-                       goto err_drop_frame_ret_pool;
-               }
--              frag_size = bm_pool->frag_size;
-+              frag_size = bm_pool->hwbm_pool.frag_size;
-               skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size);
---- a/drivers/net/ethernet/marvell/mvneta_bm.c
-+++ b/drivers/net/ethernet/marvell/mvneta_bm.c
-@@ -10,16 +10,17 @@
-  * warranty of any kind, whether express or implied.
-  */
--#include <linux/kernel.h>
-+#include <linux/clk.h>
- #include <linux/genalloc.h>
--#include <linux/platform_device.h>
--#include <linux/netdevice.h>
--#include <linux/skbuff.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
- #include <linux/mbus.h>
- #include <linux/module.h>
--#include <linux/io.h>
-+#include <linux/netdevice.h>
- #include <linux/of.h>
--#include <linux/clk.h>
-+#include <linux/platform_device.h>
-+#include <linux/skbuff.h>
-+#include <net/hwbm.h>
- #include "mvneta_bm.h"
- #define MVNETA_BM_DRIVER_NAME "mvneta_bm"
-@@ -88,17 +89,13 @@ static void mvneta_bm_pool_target_set(st
-       mvneta_bm_write(priv, MVNETA_BM_XBAR_POOL_REG(pool_id), val);
- }
--/* Allocate skb for BM pool */
--void *mvneta_buf_alloc(struct mvneta_bm *priv, struct mvneta_bm_pool *bm_pool,
--                     dma_addr_t *buf_phys_addr)
-+int mvneta_bm_construct(struct hwbm_pool *hwbm_pool, void *buf)
- {
--      void *buf;
-+      struct mvneta_bm_pool *bm_pool =
-+              (struct mvneta_bm_pool *)hwbm_pool->priv;
-+      struct mvneta_bm *priv = bm_pool->priv;
-       dma_addr_t phys_addr;
--      buf = mvneta_frag_alloc(bm_pool->frag_size);
--      if (!buf)
--              return NULL;
--
-       /* In order to update buf_cookie field of RX descriptor properly,
-        * BM hardware expects buf virtual address to be placed in the
-        * first four bytes of mapped buffer.
-@@ -106,75 +103,13 @@ void *mvneta_buf_alloc(struct mvneta_bm
-       *(u32 *)buf = (u32)buf;
-       phys_addr = dma_map_single(&priv->pdev->dev, buf, bm_pool->buf_size,
-                                  DMA_FROM_DEVICE);
--      if (unlikely(dma_mapping_error(&priv->pdev->dev, phys_addr))) {
--              mvneta_frag_free(bm_pool->frag_size, buf);
--              return NULL;
--      }
--      *buf_phys_addr = phys_addr;
--
--      return buf;
--}
--
--/* Refill processing for HW buffer management */
--int mvneta_bm_pool_refill(struct mvneta_bm *priv,
--                        struct mvneta_bm_pool *bm_pool)
--{
--      dma_addr_t buf_phys_addr;
--      void *buf;
--
--      buf = mvneta_buf_alloc(priv, bm_pool, &buf_phys_addr);
--      if (!buf)
-+      if (unlikely(dma_mapping_error(&priv->pdev->dev, phys_addr)))
-               return -ENOMEM;
--      mvneta_bm_pool_put_bp(priv, bm_pool, buf_phys_addr);
--
-+      mvneta_bm_pool_put_bp(priv, bm_pool, phys_addr);
-       return 0;
- }
--EXPORT_SYMBOL_GPL(mvneta_bm_pool_refill);
--
--/* Allocate buffers for the pool */
--int mvneta_bm_bufs_add(struct mvneta_bm *priv, struct mvneta_bm_pool *bm_pool,
--                     int buf_num)
--{
--      int err, i;
--
--      if (bm_pool->buf_num == bm_pool->size) {
--              dev_dbg(&priv->pdev->dev, "pool %d already filled\n",
--                      bm_pool->id);
--              return bm_pool->buf_num;
--      }
--
--      if (buf_num < 0 ||
--          (buf_num + bm_pool->buf_num > bm_pool->size)) {
--              dev_err(&priv->pdev->dev,
--                      "cannot allocate %d buffers for pool %d\n",
--                      buf_num, bm_pool->id);
--              return 0;
--      }
--
--      for (i = 0; i < buf_num; i++) {
--              err = mvneta_bm_pool_refill(priv, bm_pool);
--              if (err < 0)
--                      break;
--      }
--
--      /* Update BM driver with number of buffers added to pool */
--      bm_pool->buf_num += i;
--
--      dev_dbg(&priv->pdev->dev,
--              "%s pool %d: pkt_size=%4d, buf_size=%4d, frag_size=%4d\n",
--              bm_pool->type == MVNETA_BM_SHORT ? "short" : "long",
--              bm_pool->id, bm_pool->pkt_size, bm_pool->buf_size,
--              bm_pool->frag_size);
--
--      dev_dbg(&priv->pdev->dev,
--              "%s pool %d: %d of %d buffers added\n",
--              bm_pool->type == MVNETA_BM_SHORT ? "short" : "long",
--              bm_pool->id, i, buf_num);
--
--      return i;
--}
--EXPORT_SYMBOL_GPL(mvneta_bm_bufs_add);
-+EXPORT_SYMBOL_GPL(mvneta_bm_construct);
- /* Create pool */
- static int mvneta_bm_pool_create(struct mvneta_bm *priv,
-@@ -183,8 +118,7 @@ static int mvneta_bm_pool_create(struct
-       struct platform_device *pdev = priv->pdev;
-       u8 target_id, attr;
-       int size_bytes, err;
--
--      size_bytes = sizeof(u32) * bm_pool->size;
-+      size_bytes = sizeof(u32) * bm_pool->hwbm_pool.size;
-       bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, size_bytes,
-                                               &bm_pool->phys_addr,
-                                               GFP_KERNEL);
-@@ -245,11 +179,16 @@ struct mvneta_bm_pool *mvneta_bm_pool_us
-       /* Allocate buffers in case BM pool hasn't been used yet */
-       if (new_pool->type == MVNETA_BM_FREE) {
-+              struct hwbm_pool *hwbm_pool = &new_pool->hwbm_pool;
-+
-+              new_pool->priv = priv;
-               new_pool->type = type;
-               new_pool->buf_size = MVNETA_RX_BUF_SIZE(new_pool->pkt_size);
--              new_pool->frag_size =
-+              hwbm_pool->frag_size =
-                       SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(new_pool->pkt_size)) +
-                       SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
-+              hwbm_pool->construct = mvneta_bm_construct;
-+              hwbm_pool->priv = new_pool;
-               /* Create new pool */
-               err = mvneta_bm_pool_create(priv, new_pool);
-@@ -260,10 +199,10 @@ struct mvneta_bm_pool *mvneta_bm_pool_us
-               }
-               /* Allocate buffers for this pool */
--              num = mvneta_bm_bufs_add(priv, new_pool, new_pool->size);
--              if (num != new_pool->size) {
-+              num = hwbm_pool_add(hwbm_pool, hwbm_pool->size, GFP_ATOMIC);
-+              if (num != hwbm_pool->size) {
-                       WARN(1, "pool %d: %d of %d allocated\n",
--                           new_pool->id, num, new_pool->size);
-+                           new_pool->id, num, hwbm_pool->size);
-                       return NULL;
-               }
-       }
-@@ -284,7 +223,7 @@ void mvneta_bm_bufs_free(struct mvneta_b
-       mvneta_bm_config_set(priv, MVNETA_BM_EMPTY_LIMIT_MASK);
--      for (i = 0; i < bm_pool->buf_num; i++) {
-+      for (i = 0; i < bm_pool->hwbm_pool.buf_num; i++) {
-               dma_addr_t buf_phys_addr;
-               u32 *vaddr;
-@@ -303,13 +242,13 @@ void mvneta_bm_bufs_free(struct mvneta_b
-               dma_unmap_single(&priv->pdev->dev, buf_phys_addr,
-                                bm_pool->buf_size, DMA_FROM_DEVICE);
--              mvneta_frag_free(bm_pool->frag_size, vaddr);
-+              hwbm_buf_free(&bm_pool->hwbm_pool, vaddr);
-       }
-       mvneta_bm_config_clear(priv, MVNETA_BM_EMPTY_LIMIT_MASK);
-       /* Update BM driver with number of buffers removed from pool */
--      bm_pool->buf_num -= i;
-+      bm_pool->hwbm_pool.buf_num -= i;
- }
- EXPORT_SYMBOL_GPL(mvneta_bm_bufs_free);
-@@ -317,6 +256,7 @@ EXPORT_SYMBOL_GPL(mvneta_bm_bufs_free);
- void mvneta_bm_pool_destroy(struct mvneta_bm *priv,
-                           struct mvneta_bm_pool *bm_pool, u8 port_map)
- {
-+      struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool;
-       bm_pool->port_map &= ~port_map;
-       if (bm_pool->port_map)
-               return;
-@@ -324,11 +264,12 @@ void mvneta_bm_pool_destroy(struct mvnet
-       bm_pool->type = MVNETA_BM_FREE;
-       mvneta_bm_bufs_free(priv, bm_pool, port_map);
--      if (bm_pool->buf_num)
-+      if (hwbm_pool->buf_num)
-               WARN(1, "cannot free all buffers in pool %d\n", bm_pool->id);
-       if (bm_pool->virt_addr) {
--              dma_free_coherent(&priv->pdev->dev, sizeof(u32) * bm_pool->size,
-+              dma_free_coherent(&priv->pdev->dev,
-+                                sizeof(u32) * hwbm_pool->size,
-                                 bm_pool->virt_addr, bm_pool->phys_addr);
-               bm_pool->virt_addr = NULL;
-       }
-@@ -381,10 +322,10 @@ static void mvneta_bm_pools_init(struct
-                                MVNETA_BM_POOL_CAP_ALIGN));
-                       size = ALIGN(size, MVNETA_BM_POOL_CAP_ALIGN);
-               }
--              bm_pool->size = size;
-+              bm_pool->hwbm_pool.size = size;
-               mvneta_bm_write(priv, MVNETA_BM_POOL_SIZE_REG(i),
--                              bm_pool->size);
-+                              bm_pool->hwbm_pool.size);
-               /* Obtain custom pkt_size from DT */
-               sprintf(prop, "pool%d,pkt-size", i);
---- a/drivers/net/ethernet/marvell/mvneta_bm.h
-+++ b/drivers/net/ethernet/marvell/mvneta_bm.h
-@@ -108,20 +108,15 @@ struct mvneta_bm {
- };
- struct mvneta_bm_pool {
-+      struct hwbm_pool hwbm_pool;
-       /* Pool number in the range 0-3 */
-       u8 id;
-       enum mvneta_bm_type type;
--      /* Buffer Pointers Pool External (BPPE) size in number of bytes */
--      int size;
--      /* Number of buffers used by this pool */
--      int buf_num;
--      /* Pool buffer size */
--      int buf_size;
-       /* Packet size */
-       int pkt_size;
--      /* Single frag size */
--      u32 frag_size;
-+      /* Size of the buffer acces through DMA*/
-+      u32 buf_size;
-       /* BPPE virtual base address */
-       u32 *virt_addr;
-@@ -143,8 +138,7 @@ void mvneta_bm_pool_destroy(struct mvnet
-                           struct mvneta_bm_pool *bm_pool, u8 port_map);
- void mvneta_bm_bufs_free(struct mvneta_bm *priv, struct mvneta_bm_pool *bm_pool,
-                        u8 port_map);
--int mvneta_bm_bufs_add(struct mvneta_bm *priv, struct mvneta_bm_pool *bm_pool,
--                     int buf_num);
-+int mvneta_bm_construct(struct hwbm_pool *hwbm_pool, void *buf);
- int mvneta_bm_pool_refill(struct mvneta_bm *priv,
-                         struct mvneta_bm_pool *bm_pool);
- struct mvneta_bm_pool *mvneta_bm_pool_use(struct mvneta_bm *priv, u8 pool_id,
-@@ -170,8 +164,7 @@ void mvneta_bm_pool_destroy(struct mvnet
-                           struct mvneta_bm_pool *bm_pool, u8 port_map) {}
- void mvneta_bm_bufs_free(struct mvneta_bm *priv, struct mvneta_bm_pool *bm_pool,
-                        u8 port_map) {}
--int mvneta_bm_bufs_add(struct mvneta_bm *priv, struct mvneta_bm_pool *bm_pool,
--                     int buf_num) { return 0; }
-+int mvneta_bm_construct(struct hwbm_pool *hwbm_pool, void *buf) { return 0; }
- int mvneta_bm_pool_refill(struct mvneta_bm *priv,
-                         struct mvneta_bm_pool *bm_pool) {return 0; }
- struct mvneta_bm_pool *mvneta_bm_pool_use(struct mvneta_bm *priv, u8 pool_id,
diff --git a/target/linux/mvebu/patches-4.4/047-net-mvneta-Fix-spinlock-usage.patch b/target/linux/mvebu/patches-4.4/047-net-mvneta-Fix-spinlock-usage.patch
deleted file mode 100644 (file)
index a8e78df..0000000
+++ /dev/null
@@ -1,52 +0,0 @@
-From: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Date: Sat, 12 Mar 2016 18:44:17 +0100
-Subject: [PATCH] net: mvneta: Fix spinlock usage
-
-In the previous patch, the spinlock was not initialized. While it didn't
-cause any trouble yet it could be a problem to use it uninitialized.
-
-The most annoying part was the critical section protected by the spinlock
-in mvneta_stop(). Some of the functions could sleep as pointed when
-activated CONFIG_DEBUG_ATOMIC_SLEEP. Actually, in mvneta_stop() we only
-need to protect the is_stopped flagged, indeed the code of the notifier
-for CPU online is protected by the same spinlock, so when we get the
-lock, the notifer work is done.
-
-Reported-by: Patrick Uiterwijk <patrick@puiterwijk.org>
-Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -3484,17 +3484,17 @@ static int mvneta_stop(struct net_device
-       struct mvneta_port *pp = netdev_priv(dev);
-       /* Inform that we are stopping so we don't want to setup the
--       * driver for new CPUs in the notifiers
-+       * driver for new CPUs in the notifiers. The code of the
-+       * notifier for CPU online is protected by the same spinlock,
-+       * so when we get the lock, the notifer work is done.
-        */
-       spin_lock(&pp->lock);
-       pp->is_stopped = true;
-+      spin_unlock(&pp->lock);
-+
-       mvneta_stop_dev(pp);
-       mvneta_mdio_remove(pp);
-       unregister_cpu_notifier(&pp->cpu_notifier);
--      /* Now that the notifier are unregistered, we can release le
--       * lock
--       */
--      spin_unlock(&pp->lock);
-       on_each_cpu(mvneta_percpu_disable, pp, true);
-       free_percpu_irq(dev->irq, pp->ports);
-       mvneta_cleanup_rxqs(pp);
-@@ -4027,6 +4027,7 @@ static int mvneta_probe(struct platform_
-       dev->ethtool_ops = &mvneta_eth_tool_ops;
-       pp = netdev_priv(dev);
-+      spin_lock_init(&pp->lock);
-       pp->phy_node = phy_node;
-       pp->phy_interface = phy_mode;
diff --git a/target/linux/mvebu/patches-4.4/048-net-mvneta-fix-error-messages-in-mvneta_port_down-fu.patch b/target/linux/mvebu/patches-4.4/048-net-mvneta-fix-error-messages-in-mvneta_port_down-fu.patch
deleted file mode 100644 (file)
index fd1f1ae..0000000
+++ /dev/null
@@ -1,33 +0,0 @@
-From: Dmitri Epshtein <dima@marvell.com>
-Date: Sat, 12 Mar 2016 18:44:19 +0100
-Subject: [PATCH] net: mvneta: fix error messages in mvneta_port_down function
-
-This commit corrects error printing when shutting down the port.
-
-[gregory.clement@free-electrons.com: split initial commit in two
-individual changes]
-Signed-off-by: Dmitri Epshtein <dima@marvell.com>
-Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -1105,7 +1105,7 @@ static void mvneta_port_down(struct mvne
-       do {
-               if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
-                       netdev_warn(pp->dev,
--                                  "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
-+                                  "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n",
-                                   val);
-                       break;
-               }
-@@ -1144,7 +1144,7 @@ static void mvneta_port_down(struct mvne
-       do {
-               if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
-                       netdev_warn(pp->dev,
--                                  "TX FIFO empty timeout status=0x08%x\n",
-+                                  "TX FIFO empty timeout status=0x%08x\n",
-                                   val);
-                       break;
-               }
diff --git a/target/linux/mvebu/patches-4.4/049-net-mvneta-replace-MVNETA_CPU_D_CACHE_LINE_SIZE-with.patch b/target/linux/mvebu/patches-4.4/049-net-mvneta-replace-MVNETA_CPU_D_CACHE_LINE_SIZE-with.patch
deleted file mode 100644 (file)
index c12d98a..0000000
+++ /dev/null
@@ -1,56 +0,0 @@
-From: Jisheng Zhang <jszhang@marvell.com>
-Date: Wed, 30 Mar 2016 19:55:21 +0800
-Subject: [PATCH] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with
- L1_CACHE_BYTES
-
-The mvneta is also used in some Marvell berlin family SoCs which may
-have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE
-usage with L1_CACHE_BYTES.
-
-And since dma_alloc_coherent() is always cacheline size aligned, so
-remove the align checks.
-
-Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -260,7 +260,6 @@
- #define MVNETA_VLAN_TAG_LEN             4
--#define MVNETA_CPU_D_CACHE_LINE_SIZE    32
- #define MVNETA_TX_CSUM_DEF_SIZE               1600
- #define MVNETA_TX_CSUM_MAX_SIZE               9800
- #define MVNETA_ACC_MODE_EXT1          1
-@@ -300,7 +299,7 @@
- #define MVNETA_RX_PKT_SIZE(mtu) \
-       ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
-             ETH_HLEN + ETH_FCS_LEN,                        \
--            MVNETA_CPU_D_CACHE_LINE_SIZE)
-+            L1_CACHE_BYTES)
- #define IS_TSO_HEADER(txq, addr) \
-       ((addr >= txq->tso_hdrs_phys) && \
-@@ -2762,9 +2761,6 @@ static int mvneta_rxq_init(struct mvneta
-       if (rxq->descs == NULL)
-               return -ENOMEM;
--      BUG_ON(rxq->descs !=
--             PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
--
-       rxq->last_desc = rxq->size - 1;
-       /* Set Rx descriptors queue starting address */
-@@ -2835,10 +2831,6 @@ static int mvneta_txq_init(struct mvneta
-       if (txq->descs == NULL)
-               return -ENOMEM;
--      /* Make sure descriptor address is cache line size aligned  */
--      BUG_ON(txq->descs !=
--             PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
--
-       txq->last_desc = txq->size - 1;
-       /* Set maximum bandwidth for enabled TXQs */
diff --git a/target/linux/mvebu/patches-4.4/050-net-mvneta-fix-changing-MTU-when-using-per-cpu-proce.patch b/target/linux/mvebu/patches-4.4/050-net-mvneta-fix-changing-MTU-when-using-per-cpu-proce.patch
deleted file mode 100644 (file)
index 0786200..0000000
+++ /dev/null
@@ -1,75 +0,0 @@
-From: Marcin Wojtas <