sunxi: delete old kernel versions
authorFelix Fietkau <nbd@nbd.name>
Thu, 12 May 2016 15:52:20 +0000 (17:52 +0200)
committerFelix Fietkau <nbd@nbd.name>
Thu, 12 May 2016 15:52:20 +0000 (17:52 +0200)
Signed-off-by: Felix Fietkau <nbd@nbd.name>
83 files changed:
target/linux/sunxi/config-3.18 [deleted file]
target/linux/sunxi/config-4.1 [deleted file]
target/linux/sunxi/patches-3.18/100-dt-sun7i-add_spi0_pins_a.patch [deleted file]
target/linux/sunxi/patches-3.18/101-dt-sun7i-add-uart3_pins.patch [deleted file]
target/linux/sunxi/patches-3.18/102-dt-sun7i-add_mmc2_pins.patch [deleted file]
target/linux/sunxi/patches-3.18/110-input-add-sun4i-lradc.patch [deleted file]
target/linux/sunxi/patches-3.18/111-dt-sun4i-add-lradc.patch [deleted file]
target/linux/sunxi/patches-3.18/112-dt-sun5i-add-lradc.patch [deleted file]
target/linux/sunxi/patches-3.18/113-dt-sun7i-add-lradc.patch [deleted file]
target/linux/sunxi/patches-3.18/115-input-sun4i-ts-update-temp-curve.patch [deleted file]
target/linux/sunxi/patches-3.18/116-dt-sunxi-update-compats-for-tempcurves.patch [deleted file]
target/linux/sunxi/patches-3.18/130-input-add-axp20x-pek.patch [deleted file]
target/linux/sunxi/patches-3.18/150-pwm-add-sunxi-driver.patch [deleted file]
target/linux/sunxi/patches-3.18/200-mmc-add-sdio-function-subnode.patch [deleted file]
target/linux/sunxi/patches-3.18/201-dt-sun7i-add-oob-irq-to-bcm-sdio-wifi.patch [deleted file]
target/linux/sunxi/patches-3.18/202-dt-sun7i-add-bluetooth-to-cubietruck.patch [deleted file]
target/linux/sunxi/patches-3.18/270-dt-sun7i-add-ss-to-a20.patch [deleted file]
target/linux/sunxi/patches-3.18/271-crypto-add-ss.patch [deleted file]
target/linux/sunxi/patches-3.18/300-dt-sun7i-add-bananapi.patch [deleted file]
target/linux/sunxi/patches-3.18/301-dt-sun7i-add-bananapro.patch [deleted file]
target/linux/sunxi/patches-3.18/302-dt-sun7i-add-lamobo-r1.patch [deleted file]
target/linux/sunxi/patches-4.1/100-mfd-axp20x-add-axp22x-pmic.patch [deleted file]
target/linux/sunxi/patches-4.1/101-regulator-axp20x-prep-support-for-multiple-axp-families.patch [deleted file]
target/linux/sunxi/patches-4.1/102-regulator-axp20x-add-support-for-axp22.patch [deleted file]
target/linux/sunxi/patches-4.1/103-mfd-axp20x-add-missing-registers.patch [deleted file]
target/linux/sunxi/patches-4.1/104-mfd-axp20x-enable-axp22x.patch [deleted file]
target/linux/sunxi/patches-4.1/105-mfd-axp20x-add-axp152-support.patch [deleted file]
target/linux/sunxi/patches-4.1/110-mtd-move-nand_ecc_ctrl-init.patch [deleted file]
target/linux/sunxi/patches-4.1/111-mtd-add-support-for-nand-partitions.patch [deleted file]
target/linux/sunxi/patches-4.1/112-mtd-add-dt-nand-partition-parser.patch [deleted file]
target/linux/sunxi/patches-4.1/113-mtd-nand-add-pst.patch [deleted file]
target/linux/sunxi/patches-4.1/114-mtd-randomizer-into-nand-framework.patch [deleted file]
target/linux/sunxi/patches-4.1/115-mtd-fetch-randomizer-mode.patch [deleted file]
target/linux/sunxi/patches-4.1/116-mtd-add-vendor-specific-initcode-infra.patch [deleted file]
target/linux/sunxi/patches-4.1/117-mtd-nand-add-hynix-init.patch [deleted file]
target/linux/sunxi/patches-4.1/119-mtd-nand-ecc-for-samsung.patch [deleted file]
target/linux/sunxi/patches-4.1/120-mtd-nand-print-ecc-strength.patch [deleted file]
target/linux/sunxi/patches-4.1/121-mtd-print-full-chipid.patch [deleted file]
target/linux/sunxi/patches-4.1/122-mtd-nand-sunxi-add-partition-support.patch [deleted file]
target/linux/sunxi/patches-4.1/123-mtd-nand-sunxi-add-hw-randomizer-support.patch [deleted file]
target/linux/sunxi/patches-4.1/124-mtd-nand-sunxi-fallback-to-chip-config.patch [deleted file]
target/linux/sunxi/patches-4.1/125-mtd-nand-sunxi-extend-bbt_options.patch [deleted file]
target/linux/sunxi/patches-4.1/126-1-dt-sun4i-add-nand-ctrlpin-defs.patch [deleted file]
target/linux/sunxi/patches-4.1/126-2-dt-sun5i-add-nand-ctrlpin-defs.patch [deleted file]
target/linux/sunxi/patches-4.1/126-3-dt-sun7i-add-nand-ctrlpin-defs.patch [deleted file]
target/linux/sunxi/patches-4.1/126-4-dt-sun4i-add-nfc-to-a10.patch [deleted file]
target/linux/sunxi/patches-4.1/126-5-dt-sun4i-add-nfc-to-a10.patch [deleted file]
target/linux/sunxi/patches-4.1/126-6-dt-sun5i-add-nfc-to-a13.patch [deleted file]
target/linux/sunxi/patches-4.1/127-1-dt-sun5i-enable-nand-on-a13-olinuxino.patch [deleted file]
target/linux/sunxi/patches-4.1/127-2-dt-sun7i-enable-nand-on-a20-olinuxino.patch [deleted file]
target/linux/sunxi/patches-4.1/127-3-dt-sun4i-enable-nand-on-cubieboard.patch [deleted file]
target/linux/sunxi/patches-4.1/127-4-dt-sun4i-enable-nand-on-a10-lime.patch [deleted file]
target/linux/sunxi/patches-4.1/127-5-dt-sun4i-enable-nand-on-a10-pcduino.patch [deleted file]
target/linux/sunxi/patches-4.1/127-6-dt-sun7i-enable-nand-on-a20-pcduino3.patch [deleted file]
target/linux/sunxi/patches-4.1/128-1-mtd-nand-store-timing-in-nand_chip.patch [deleted file]
target/linux/sunxi/patches-4.1/128-2-mtd-nand-support-non-ONFI-timings.patch [deleted file]
target/linux/sunxi/patches-4.1/128-3-mtd-nand-add-H27UBG8T2BTR-BC.patch [deleted file]
target/linux/sunxi/patches-4.1/129-nand-sunxi-fix-write-to-USER_DATA-a13.patch [deleted file]
target/linux/sunxi/patches-4.1/140-mmc-sdio-reliability-fix.patch [deleted file]
target/linux/sunxi/patches-4.1/142-arm-add-sunxi-h3.patch [deleted file]
target/linux/sunxi/patches-4.1/143-dmaengine-add-h3.patch [deleted file]
target/linux/sunxi/patches-4.1/160-dmaengine-add-sun4i-driver.patch [deleted file]
target/linux/sunxi/patches-4.1/161-clk-sunxi-add-pll2-for-sun457i.patch [deleted file]
target/linux/sunxi/patches-4.1/162-clk-sunxi-codec-clock.patch [deleted file]
target/linux/sunxi/patches-4.1/163-clk-sunxi-mod1-clock.patch [deleted file]
target/linux/sunxi/patches-4.1/164-1-dt-add-pll2-into-dtsi.patch [deleted file]
target/linux/sunxi/patches-4.1/164-2-dt-add-codec-clock-into-dtsi.patch [deleted file]
target/linux/sunxi/patches-4.1/164-3-dt-sun7i-add-mod1-clocknodes.patch [deleted file]
target/linux/sunxi/patches-4.1/164-4-dt-sun7i-resort-pll-parents-for-audio.patch [deleted file]
target/linux/sunxi/patches-4.1/165-asoc-add-sunxi-codec.patch [deleted file]
target/linux/sunxi/patches-4.1/166-asoc-sunxi-fix-distortion-on-16bit-mono.patch [deleted file]
target/linux/sunxi/patches-4.1/167-1-dt-sun7i-add-codec-node.patch [deleted file]
target/linux/sunxi/patches-4.1/167-2-dt-sun7i-add-codec-to-a20-olinuxino-micro.patch [deleted file]
target/linux/sunxi/patches-4.1/167-3-dt-sun7i-add-codec-to-cubieboard2.patch [deleted file]
target/linux/sunxi/patches-4.1/167-4-dt-sun7i-add-codec-to-cubietruck.patch [deleted file]
target/linux/sunxi/patches-4.1/170-musb-add-driver.patch [deleted file]
target/linux/sunxi/patches-4.1/171-musb-add-support-for-a31.patch [deleted file]
target/linux/sunxi/patches-4.1/190-dt-sun7i-add-ss-to-a20.patch [deleted file]
target/linux/sunxi/patches-4.1/191-dt-sun4i-add-ss-to-a10.patch [deleted file]
target/linux/sunxi/patches-4.1/192-crypto-add-ss.patch [deleted file]
target/linux/sunxi/patches-4.1/201-dt-sun7i-add-oob-irq-to-bcm-sdio-wifi.patch [deleted file]
target/linux/sunxi/patches-4.1/202-dt-sun7i-add-bluetooth-to-cubietruck.patch [deleted file]
target/linux/sunxi/patches-4.1/300-dt-sun7i-add-lamobo-r1.patch [deleted file]

diff --git a/target/linux/sunxi/config-3.18 b/target/linux/sunxi/config-3.18
deleted file mode 100644 (file)
index bdfe88a..0000000
+++ /dev/null
@@ -1,477 +0,0 @@
-CONFIG_ADVISE_SYSCALLS=y
-# CONFIG_AHCI_SUNXI is not set
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_APM_EMULATION is not set
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAS_SG_CHAIN=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-# CONFIG_ARCH_MULTI_CPU_AUTO is not set
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=416
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUNXI=y
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
-# CONFIG_ARM_CPU_SUSPEND is not set
-CONFIG_ARM_ERRATA_430973=y
-CONFIG_ARM_ERRATA_720789=y
-CONFIG_ARM_ERRATA_754322=y
-CONFIG_ARM_ERRATA_775420=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-# CONFIG_ARM_LPAE is not set
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_PSCI=y
-CONFIG_ARM_THUMB=y
-# CONFIG_ARM_THUMBEE is not set
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ATA=y
-CONFIG_ATAGS=y
-# CONFIG_ATA_SFF is not set
-CONFIG_AUDIT=y
-# CONFIG_AUDITSYSCALL is not set
-CONFIG_AUDIT_GENERIC=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_AVERAGE=y
-CONFIG_B53=y
-# CONFIG_B53_MMAP_DRIVER is not set
-CONFIG_B53_PHY_DRIVER=y
-CONFIG_B53_PHY_FIXUP=y
-# CONFIG_B53_SRAB_DRIVER is not set
-CONFIG_BINFMT_MISC=y
-CONFIG_BLK_CGROUP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=y
-CONFIG_BLK_DEV_SR_VENDOR=y
-CONFIG_BOUNCE=y
-# CONFIG_BPF_SYSCALL is not set
-CONFIG_BUILD_BIN2C=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CFQ_GROUP_IOSCHED=y
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_CGROUP_DEVICE=y
-CONFIG_CGROUP_FREEZER=y
-# CONFIG_CGROUP_NET_CLASSID is not set
-# CONFIG_CGROUP_PERF is not set
-# CONFIG_CGROUP_SCHED is not set
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_OF=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk rootwait root=/dev/mmcblk0p2"
-CONFIG_CMDLINE_FORCE=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACTION=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONNECTOR=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_COREDUMP=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_CPUSETS=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRC_T10DIF=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_DEV_SUNXI_SS=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_DCACHE_WORD_ACCESS=y
-# CONFIG_DEBUG_BLK_CGROUP is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_KERNEL is not set
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_MEMORY_INIT=y
-# CONFIG_DEBUG_UART_8250 is not set
-# CONFIG_DEBUG_UART_PL01X is not set
-# CONFIG_DEBUG_USER is not set
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_DIRECT_IO=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_SUN6I=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_DWMAC_SUNXI=y
-# CONFIG_DW_DMAC_CORE is not set
-CONFIG_DYNAMIC_DEBUG=y
-# CONFIG_EEPROM_SUNXI_SID is not set
-CONFIG_ELF_CORE=y
-# CONFIG_EMAC_ROCKCHIP is not set
-# CONFIG_EMBEDDED is not set
-CONFIG_ENABLE_MUST_CHECK=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-CONFIG_EXT4_FS=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FRAME_WARN=2048
-CONFIG_FREEZER=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_AUDITSYSCALL=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_ARM_ARCH_TIMER=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_HW_BREAKPOINT=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZ4=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SMP=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HIGHMEM=y
-# CONFIG_HIGHPTE is not set
-CONFIG_HWMON=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_MUX=y
-# CONFIG_I2C_MUX_GPIO is not set
-# CONFIG_I2C_MUX_PCA9541 is not set
-# CONFIG_I2C_MUX_PCA954x is not set
-CONFIG_I2C_MUX_PINCTRL=y
-CONFIG_I2C_MV64XXX=y
-# CONFIG_I2C_SUN6I_P2WI is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-# CONFIG_INPUT_AXP20X_PEK is not set
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_IOMMU_HELPER=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_IPC_NS=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_KALLSYMS=y
-# CONFIG_KEYBOARD_GPIO is not set
-CONFIG_KEYBOARD_SUN4I_LRADC=y
-CONFIG_KSM=y
-CONFIG_LEDS_GPIO=y
-# CONFIG_LEDS_REGULATOR is not set
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_LIBFDT=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_LZ4_DECOMPRESS=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MACH_SUN4I=y
-CONFIG_MACH_SUN5I=y
-CONFIG_MACH_SUN6I=y
-CONFIG_MACH_SUN7I=y
-# CONFIG_MACH_SUN8I is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MDIO_SUN4I=y
-# CONFIG_MEMCG is not set
-CONFIG_MFD_AXP20X=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_SUN6I_PRCM=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGHT_HAVE_PCI=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-# CONFIG_MMC_BLOCK_BOUNCE is not set
-# CONFIG_MMC_DEBUG is not set
-CONFIG_MMC_SUNXI=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NAMESPACES=y
-CONFIG_NEED_DMA_MAP_STATE=y
-# CONFIG_NEON is not set
-# CONFIG_NET_CLS_CGROUP is not set
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_NS=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_VENDOR_ALLWINNER=y
-CONFIG_NLS=y
-CONFIG_NO_BOOTMEM=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_RESERVED_MEM=y
-CONFIG_OF_TOUCHSCREEN=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PARTITION_ADVANCED is not set
-# CONFIG_PCI is not set
-# CONFIG_PCI_SYSCALL is not set
-CONFIG_PERF_EVENTS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_SUN4I_USB=y
-CONFIG_PID_NS=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PINCTRL_SUN4I_A10=y
-CONFIG_PINCTRL_SUN5I_A10S=y
-CONFIG_PINCTRL_SUN5I_A13=y
-CONFIG_PINCTRL_SUN6I_A31=y
-CONFIG_PINCTRL_SUN6I_A31_R=y
-CONFIG_PINCTRL_SUN7I_A20=y
-# CONFIG_PINCTRL_SUN8I_A23 is not set
-# CONFIG_PINCTRL_SUN8I_A23_R is not set
-CONFIG_PINCTRL_SUNXI_COMMON=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_RUNTIME=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PREEMPT=y
-CONFIG_PREEMPT_COUNT=y
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_RCU=y
-CONFIG_PRINTK_TIME=y
-# CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_PROC_EVENTS=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PROC_PID_CPUSET=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PWM=y
-# CONFIG_PWM_FSL_FTM is not set
-CONFIG_PWM_SUN4I=y
-CONFIG_PWM_SYSFS=y
-# CONFIG_QFMT_V1 is not set
-# CONFIG_QFMT_V2 is not set
-CONFIG_QUOTA=y
-CONFIG_QUOTACTL=y
-CONFIG_QUOTA_NETLINK_INTERFACE=y
-# CONFIG_RCU_BOOST is not set
-CONFIG_RCU_CPU_STALL_VERBOSE=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_IRQ=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_AXP20X=y
-# CONFIG_REGULATOR_DEBUG is not set
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-# CONFIG_REGULATOR_PWM is not set
-# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-CONFIG_RELAY=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESOURCE_COUNTERS=y
-# CONFIG_RFKILL_REGULATOR is not set
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-CONFIG_SATA_AHCI_PLATFORM=y
-CONFIG_SCHED_HRTICK=y
-CONFIG_SCSI=y
-CONFIG_SDIO_UART=y
-# CONFIG_SECCOMP is not set
-CONFIG_SECURITYFS=y
-# CONFIG_SENSORS_PWM_FAN is not set
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SERIAL_8250_NR_UARTS=8
-CONFIG_SERIAL_8250_RUNTIME_UARTS=8
-CONFIG_SERIO=y
-# CONFIG_SERIO_APBPS2 is not set
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-CONFIG_SLUB_CPU_PARTIAL=y
-CONFIG_SLUB_DEBUG=y
-# CONFIG_SLUB_DEBUG_ON is not set
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_SUN4I=y
-CONFIG_SPI_SUN6I=y
-# CONFIG_STAGING is not set
-# CONFIG_STMMAC_DA is not set
-# CONFIG_STMMAC_DEBUG_FS is not set
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_PLATFORM=y
-CONFIG_STOP_MACHINE=y
-CONFIG_STRICT_DEVMEM=y
-# CONFIG_SUN4I_EMAC is not set
-CONFIG_SUN4I_TIMER=y
-CONFIG_SUN5I_HSTIMER=y
-CONFIG_SUNXI_WATCHDOG=y
-CONFIG_SWCONFIG=y
-CONFIG_SWIOTLB=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYSFS_SYSCALL=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TASKSTATS=y
-CONFIG_TASK_DELAY_ACCT=y
-CONFIG_TASK_IO_ACCOUNTING=y
-CONFIG_TASK_XACCT=y
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TOUCHSCREEN_SUN4I=y
-CONFIG_TREE_PREEMPT_RCU=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_UID16=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_NET_DRIVERS=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USELIB=y
-# CONFIG_USER_NS is not set
-CONFIG_USE_OF=y
-CONFIG_UTS_NS=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_XEN is not set
-CONFIG_XFRM_ALGO=y
-CONFIG_XFRM_USER=y
-CONFIG_XPS=y
-CONFIG_XZ_DEC_ARM=y
-# CONFIG_XZ_DEC_ARMTHUMB is not set
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA_FLAG=0
diff --git a/target/linux/sunxi/config-4.1 b/target/linux/sunxi/config-4.1
deleted file mode 100644 (file)
index d083a59..0000000
+++ /dev/null
@@ -1,560 +0,0 @@
-CONFIG_ADVISE_SYSCALLS=y
-# CONFIG_AHCI_SUNXI is not set
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_APM_EMULATION is not set
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAS_SG_CHAIN=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-# CONFIG_ARCH_MULTI_CPU_AUTO is not set
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=416
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUNXI=y
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-# CONFIG_ARM_LPAE is not set
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_PSCI=y
-CONFIG_ARM_THUMB=y
-# CONFIG_ARM_THUMBEE is not set
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ATA=y
-CONFIG_ATAGS=y
-# CONFIG_ATA_SFF is not set
-CONFIG_AUDIT=y
-# CONFIG_AUDITSYSCALL is not set
-CONFIG_AUDIT_GENERIC=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_AVERAGE=y
-CONFIG_B53=y
-# CONFIG_B53_MMAP_DRIVER is not set
-CONFIG_B53_PHY_DRIVER=y
-CONFIG_B53_PHY_FIXUP=y
-# CONFIG_B53_SRAB_DRIVER is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_GENERIC=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_BACKLIGHT_PWM=y
-CONFIG_BINFMT_MISC=y
-CONFIG_BLK_CGROUP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=y
-CONFIG_BLK_DEV_SR_VENDOR=y
-CONFIG_BOUNCE=y
-# CONFIG_BPF_SYSCALL is not set
-CONFIG_BUILD_BIN2C=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CFQ_GROUP_IOSCHED=y
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_CGROUP_DEVICE=y
-CONFIG_CGROUP_FREEZER=y
-# CONFIG_CGROUP_NET_CLASSID is not set
-# CONFIG_CGROUP_PERF is not set
-# CONFIG_CGROUP_SCHED is not set
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_OF=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk rootwait root=/dev/mmcblk0p2"
-CONFIG_CMDLINE_FORCE=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACTION=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONNECTOR=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_COREDUMP=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUSETS=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_STAT_DETAILS is not set
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRC_T10DIF=y
-CONFIG_CRYPTO_ABLK_HELPER=y
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_AES_ARM=y
-CONFIG_CRYPTO_AES_ARM_CE=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_DEV_SUN4I_SS=y
-CONFIG_CRYPTO_GHASH_ARM_CE=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA1_ARM=y
-CONFIG_CRYPTO_SHA1_ARM_CE=y
-CONFIG_CRYPTO_SHA1_ARM_NEON=y
-CONFIG_CRYPTO_SHA256_ARM=y
-CONFIG_CRYPTO_SHA2_ARM_CE=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_SHA512_ARM_NEON=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_DCACHE_WORD_ACCESS=y
-# CONFIG_DEBUG_BLK_CGROUP is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_MEMORY_INIT=y
-# CONFIG_DEBUG_UART_8250 is not set
-# CONFIG_DEBUG_USER is not set
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_DIRECT_IO=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_SUN6I=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_DYNAMIC_DEBUG=y
-# CONFIG_EEPROM_SUNXI_SID is not set
-CONFIG_ELF_CORE=y
-# CONFIG_EMBEDDED is not set
-CONFIG_ENABLE_MUST_CHECK=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-CONFIG_EXT4_FS=y
-CONFIG_FB=y
-# CONFIG_FB_BIG_ENDIAN is not set
-CONFIG_FB_BOTH_ENDIAN=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_FOREIGN_ENDIAN=y
-# CONFIG_FB_LITTLE_ENDIAN is not set
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_SIMPLE=y
-CONFIG_FB_TILEBLITTING=y
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x16=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FRAME_WARN=2048
-CONFIG_FREEZER=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_AUDITSYSCALL=y
-CONFIG_HAVE_ARCH_BITREVERSE=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_ARM_ARCH_TIMER=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_HW_BREAKPOINT=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZ4=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_OPTPROBES=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SMP=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HWMON=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_TIMERIOMEM=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_MV64XXX=y
-# CONFIG_I2C_SUN6I_P2WI is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_AXP20X_PEK=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_IOMMU_HELPER=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_IPC_NS=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_KALLSYMS=y
-CONFIG_KEYBOARD_SUN4I_LRADC=y
-CONFIG_KSM=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_LCD_PLATFORM=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_LIBFDT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_CLUT224=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MACH_SUN4I=y
-CONFIG_MACH_SUN5I=y
-CONFIG_MACH_SUN6I=y
-CONFIG_MACH_SUN7I=y
-CONFIG_MACH_SUN8I=y
-CONFIG_MACH_SUN9I=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MDIO_SUN4I=y
-# CONFIG_MEMCG is not set
-CONFIG_MFD_AXP20X=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_SUN6I_PRCM=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGHT_HAVE_PCI=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-# CONFIG_MMC_BLOCK_BOUNCE is not set
-CONFIG_MMC_SUNXI=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_SUNXI=y
-CONFIG_MTD_OF_NAND_PARTS=y
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NAMESPACES=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-# CONFIG_NET_CLS_CGROUP is not set
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_NS=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_VENDOR_ALLWINNER=y
-CONFIG_NLS=y
-CONFIG_NO_BOOTMEM=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_RESERVED_MEM=y
-CONFIG_OF_TOUCHSCREEN=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PARTITION_ADVANCED is not set
-# CONFIG_PCI is not set
-# CONFIG_PCI_DOMAINS_GENERIC is not set
-# CONFIG_PCI_SYSCALL is not set
-CONFIG_PERF_EVENTS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHY_SUN4I_USB=y
-# CONFIG_PHY_SUN9I_USB is not set
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PINCTRL_SUN4I_A10=y
-CONFIG_PINCTRL_SUN5I_A10S=y
-CONFIG_PINCTRL_SUN5I_A13=y
-CONFIG_PINCTRL_SUN6I_A31=y
-CONFIG_PINCTRL_SUN6I_A31S=y
-CONFIG_PINCTRL_SUN6I_A31_R=y
-CONFIG_PINCTRL_SUN7I_A20=y
-CONFIG_PINCTRL_SUN8I_A23=y
-CONFIG_PINCTRL_SUN8I_A23_R=y
-CONFIG_PINCTRL_SUN9I_A80=y
-CONFIG_PINCTRL_SUNXI_COMMON=y
-# CONFIG_PL310_ERRATA_588369 is not set
-# CONFIG_PL310_ERRATA_727915 is not set
-# CONFIG_PL310_ERRATA_753970 is not set
-# CONFIG_PL310_ERRATA_769419 is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_OPP=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PREEMPT=y
-CONFIG_PREEMPT_COUNT=y
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_RCU=y
-CONFIG_PRINTK_TIME=y
-# CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_PROC_EVENTS=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PROC_PID_CPUSET=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PWM=y
-CONFIG_PWM_SUN4I=y
-CONFIG_PWM_SYSFS=y
-# CONFIG_QFMT_V1 is not set
-# CONFIG_QFMT_V2 is not set
-CONFIG_QUOTA=y
-CONFIG_QUOTACTL=y
-CONFIG_QUOTA_NETLINK_INTERFACE=y
-# CONFIG_RCU_BOOST is not set
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_IRQ=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_SPI=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_AXP20X=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_RELAY=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-CONFIG_SATA_PMP=y
-CONFIG_SCHED_HRTICK=y
-CONFIG_SCSI=y
-CONFIG_SDIO_UART=y
-CONFIG_SECURITYFS=y
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SERIAL_8250_NR_UARTS=8
-CONFIG_SERIAL_8250_RUNTIME_UARTS=8
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-CONFIG_SLUB_CPU_PARTIAL=y
-CONFIG_SLUB_DEBUG=y
-# CONFIG_SLUB_DEBUG_ON is not set
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_SUN4I=y
-CONFIG_SPI_SUN6I=y
-CONFIG_SRCU=y
-# CONFIG_STAGING is not set
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_PLATFORM=y
-CONFIG_STOP_MACHINE=y
-CONFIG_STRICT_DEVMEM=y
-CONFIG_SUN4I_DMA=y
-# CONFIG_SUN4I_EMAC is not set
-CONFIG_SUN4I_TIMER=y
-CONFIG_SUN5I_HSTIMER=y
-CONFIG_SUNXI_WATCHDOG=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWCONFIG=y
-CONFIG_SWIOTLB=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYSFS_SYSCALL=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TASKSTATS=y
-CONFIG_TASK_DELAY_ACCT=y
-CONFIG_TASK_IO_ACCOUNTING=y
-CONFIG_TASK_XACCT=y
-CONFIG_THERMAL=y
-# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
-# CONFIG_THERMAL_EMULATION is not set
-# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
-CONFIG_THERMAL_GOV_STEP_WISE=y
-# CONFIG_THERMAL_GOV_USER_SPACE is not set
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TOUCHSCREEN_SUN4I=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_UID16=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_DWC2=y
-# CONFIG_USB_DWC2_DEBUG is not set
-CONFIG_USB_DWC2_HOST=y
-CONFIG_USB_DWC2_PLATFORM=y
-# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_NET_DRIVERS=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USELIB=y
-# CONFIG_USER_NS is not set
-CONFIG_USE_OF=y
-CONFIG_UTS_NS=y
-CONFIG_VDSO=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_XFRM_ALGO=y
-CONFIG_XFRM_USER=y
-CONFIG_XPS=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA_FLAG=0
diff --git a/target/linux/sunxi/patches-3.18/100-dt-sun7i-add_spi0_pins_a.patch b/target/linux/sunxi/patches-3.18/100-dt-sun7i-add_spi0_pins_a.patch
deleted file mode 100644 (file)
index b81ed44..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-From 0253d14782f80cfd1741d4ddd82b83dd7d44a91e Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 28 Jul 2014 22:44:59 +0200
-Subject: [PATCH] ARM: dts: sun7i: Add spi0_pins_a pinctrl setting
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -784,6 +784,13 @@
-                               allwinner,pull = <0>;
-                       };
-+                      spi0_pins_a: spi0@0 {
-+                              allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14";
-+                              allwinner,function = "spi0";
-+                              allwinner,drive = <0>;
-+                              allwinner,pull = <0>;
-+                      };
-+
-                       spi1_pins_a: spi1@0 {
-                               allwinner,pins = "PI16", "PI17", "PI18", "PI19";
-                               allwinner,function = "spi1";
diff --git a/target/linux/sunxi/patches-3.18/101-dt-sun7i-add-uart3_pins.patch b/target/linux/sunxi/patches-3.18/101-dt-sun7i-add-uart3_pins.patch
deleted file mode 100644 (file)
index 284537a..0000000
+++ /dev/null
@@ -1,29 +0,0 @@
-From e37ccbcd4587b7a2b943e23a9943b8917010b336 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Wed, 1 Oct 2014 08:39:58 +0200
-Subject: [PATCH] ARM: dts: sun7i: Add uart3_pins_b pinctrl setting
-
-The uart3_pins_a multiplexes the uart3 pins to port G, add a pinctrl entry
-for mapping them to port H (as used on the Bananapi).
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -677,6 +677,13 @@
-                               allwinner,pull = <0>;
-                       };
-+                      uart3_pins_b: uart3@1 {
-+                              allwinner,pins = "PH0", "PH1";
-+                              allwinner,function = "uart3";
-+                              allwinner,drive = <0>;
-+                              allwinner,pull = <0>;
-+                      };
-+
-                       uart4_pins_a: uart4@0 {
-                               allwinner,pins = "PG10", "PG11";
-                               allwinner,function = "uart4";
diff --git a/target/linux/sunxi/patches-3.18/102-dt-sun7i-add_mmc2_pins.patch b/target/linux/sunxi/patches-3.18/102-dt-sun7i-add_mmc2_pins.patch
deleted file mode 100644 (file)
index 28128db..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-From f65624ca1b67c5683317b75da2c09ffadc22fa2e Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Wed, 1 Oct 2014 00:40:57 +0200
-Subject: [PATCH] ARM: dts: sun7i: Add mmc2_pins_a pinctrl definition
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -833,6 +833,13 @@
-                               allwinner,pull = <1>;
-                       };
-+                      mmc2_pins_a: mmc2@0 {
-+                              allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11";
-+                              allwinner,function = "mmc2";
-+                              allwinner,drive = <2>;
-+                              allwinner,pull = <1>;
-+                      };
-+
-                       mmc3_pins_a: mmc3@0 {
-                               allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
-                               allwinner,function = "mmc3";
diff --git a/target/linux/sunxi/patches-3.18/110-input-add-sun4i-lradc.patch b/target/linux/sunxi/patches-3.18/110-input-add-sun4i-lradc.patch
deleted file mode 100644 (file)
index 12b4628..0000000
+++ /dev/null
@@ -1,400 +0,0 @@
-From 2c1fab89e83245a520871e807e233e66cbdb7c57 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Wed, 1 Jan 2014 19:44:49 +0100
-Subject: [PATCH] input: Add new sun4i-lradc-keys driver
-
-Allwinnner sunxi SoCs have a low resolution adc (called lradc) which is
-specifically designed to have various (tablet) keys (ie home, back, search,
-etc). attached to it using a resistor network. This adds a driver for this.
-
-There are 2 channels, currently this driver only supports chan0 since there
-are no boards known to use chan1.
-
-This has been tested on an olimex a10s-olinuxino-micro, a13-olinuxino, and
-a20-olinuxino-micro.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
-Changes in v2:
--Change devicetree bindings to use a per key subnode, like gpio-keys does
----
- .../devicetree/bindings/input/sun4i-lradc-keys.txt |  62 +++++
- MAINTAINERS                                        |   7 +
- drivers/input/keyboard/Kconfig                     |  10 +
- drivers/input/keyboard/Makefile                    |   1 +
- drivers/input/keyboard/sun4i-lradc-keys.c          | 258 +++++++++++++++++++++
- 5 files changed, 338 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt
- create mode 100644 drivers/input/keyboard/sun4i-lradc-keys.c
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt
-@@ -0,0 +1,62 @@
-+Allwinner sun4i low res adc attached tablet keys
-+------------------------------------------------
-+
-+Required properties:
-+ - compatible: "allwinner,sun4i-a10-lradc-keys"
-+ - reg: mmio address range of the chip
-+ - interrupts: interrupt to which the chip is connected
-+ - vref-supply: powersupply for the lradc reference voltage
-+
-+Each key is represented as a sub-node of "allwinner,sun4i-a10-lradc-keys":
-+
-+Required subnode-properties:
-+      - label: Descriptive name of the key.
-+      - linux,code: Keycode to emit.
-+      - channel: Channel this key is attached to, mut be 0 or 1.
-+      - voltage: Voltage in µV at lradc input when this key is pressed.
-+
-+Example:
-+
-+#include <dt-bindings/input/input.h>
-+
-+      lradc: lradc@01c22800 {
-+              compatible = "allwinner,sun4i-a10-lradc-keys";
-+              reg = <0x01c22800 0x100>;
-+              interrupts = <31>;
-+              vref-supply = <&reg_vcc3v0>;
-+
-+              button@191 {
-+                      label = "Volume Up";
-+                      linux,code = <KEY_VOLUMEUP>;
-+                      channel = <0>;
-+                      voltage = <191274>;
-+              };
-+
-+              button@392 {
-+                      label = "Volume Down";
-+                      linux,code = <KEY_VOLUMEDOWN>;
-+                      channel = <0>;
-+                      voltage = <392644>;
-+              };
-+
-+              button@601 {
-+                      label = "Menu";
-+                      linux,code = <KEY_MENU>;
-+                      channel = <0>;
-+                      voltage = <601151>;
-+              };
-+
-+              button@795 {
-+                      label = "Enter";
-+                      linux,code = <KEY_ENTER>;
-+                      channel = <0>;
-+                      voltage = <795090>;
-+              };
-+
-+              button@987 {
-+                      label = "Home";
-+                      linux,code = <KEY_HOMEPAGE>;
-+                      channel = <0>;
-+                      voltage = <987387>;
-+              };
-+      };
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -9002,6 +9002,13 @@ F:      arch/m68k/sun3*/
- F:    arch/m68k/include/asm/sun3*
- F:    drivers/net/ethernet/i825xx/sun3*
-+SUN4I LOW RES ADC ATTACHED TABLET KEYS DRIVER
-+M:    Hans de Goede <hdegoede@redhat.com>
-+L:    linux-input@vger.kernel.org
-+S:    Maintained
-+F:    Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt
-+F:    drivers/input/keyboard/sun4i-lradc-keys.c
-+
- SUNDANCE NETWORK DRIVER
- M:    Denis Kirjanov <kda@linux-powerpc.org>
- L:    netdev@vger.kernel.org
---- a/drivers/input/keyboard/Kconfig
-+++ b/drivers/input/keyboard/Kconfig
-@@ -567,6 +567,16 @@ config KEYBOARD_STMPE
-         To compile this driver as a module, choose M here: the module will be
-         called stmpe-keypad.
-+config KEYBOARD_SUN4I_LRADC
-+      tristate "Allwinner sun4i low res adc attached tablet keys support"
-+      depends on ARCH_SUNXI
-+      help
-+        This selects support for the Allwinner low res adc attached tablet
-+        keys found on Allwinner sunxi SoCs.
-+
-+        To compile this driver as a module, choose M here: the
-+        module will be called sun4i-lradc-keys.
-+
- config KEYBOARD_DAVINCI
-       tristate "TI DaVinci Key Scan"
-       depends on ARCH_DAVINCI_DM365
---- a/drivers/input/keyboard/Makefile
-+++ b/drivers/input/keyboard/Makefile
-@@ -53,6 +53,7 @@ obj-$(CONFIG_KEYBOARD_SPEAR)         += spear-k
- obj-$(CONFIG_KEYBOARD_STMPE)          += stmpe-keypad.o
- obj-$(CONFIG_KEYBOARD_STOWAWAY)               += stowaway.o
- obj-$(CONFIG_KEYBOARD_ST_KEYSCAN)     += st-keyscan.o
-+obj-$(CONFIG_KEYBOARD_SUN4I_LRADC)    += sun4i-lradc-keys.o
- obj-$(CONFIG_KEYBOARD_SUNKBD)         += sunkbd.o
- obj-$(CONFIG_KEYBOARD_TC3589X)                += tc3589x-keypad.o
- obj-$(CONFIG_KEYBOARD_TEGRA)          += tegra-kbc.o
---- /dev/null
-+++ b/drivers/input/keyboard/sun4i-lradc-keys.c
-@@ -0,0 +1,258 @@
-+/*
-+ * Allwinner sun4i low res adc attached tablet keys driver
-+ *
-+ * Copyright (C) 2014 Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+/*
-+ * Allwinnner sunxi SoCs have a lradc which is specifically designed to have
-+ * various (tablet) keys (ie home, back, search, etc). attached to it using
-+ * a resistor network. This driver is for the keys on such boards.
-+ *
-+ * There are 2 channels, currently this driver only supports channel 0 since
-+ * there are no boards known to use channel 1.
-+ */
-+
-+#include <linux/err.h>
-+#include <linux/init.h>
-+#include <linux/input.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of_platform.h>
-+#include <linux/platform_device.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/slab.h>
-+
-+#define LRADC_CTRL            0x00
-+#define LRADC_INTC            0x04
-+#define LRADC_INTS            0x08
-+#define LRADC_DATA0           0x0c
-+#define LRADC_DATA1           0x10
-+
-+/* LRADC_CTRL bits */
-+#define FIRST_CONVERT_DLY(x)  ((x) << 24) /* 8 bits */
-+#define CHAN_SELECT(x)                ((x) << 22) /* 2 bits */
-+#define CONTINUE_TIME_SEL(x)  ((x) << 16) /* 4 bits */
-+#define KEY_MODE_SEL(x)               ((x) << 12) /* 2 bits */
-+#define LEVELA_B_CNT(x)               ((x) << 8)  /* 4 bits */
-+#define HOLD_EN(x)            ((x) << 6)
-+#define LEVELB_VOL(x)         ((x) << 4)  /* 2 bits */
-+#define SAMPLE_RATE(x)                ((x) << 2)  /* 2 bits */
-+#define ENABLE(x)             ((x) << 0)
-+
-+/* LRADC_INTC and LRADC_INTS bits */
-+#define CHAN1_KEYUP_IRQ               BIT(12)
-+#define CHAN1_ALRDY_HOLD_IRQ  BIT(11)
-+#define CHAN1_HOLD_IRQ                BIT(10)
-+#define       CHAN1_KEYDOWN_IRQ       BIT(9)
-+#define CHAN1_DATA_IRQ                BIT(8)
-+#define CHAN0_KEYUP_IRQ               BIT(4)
-+#define CHAN0_ALRDY_HOLD_IRQ  BIT(3)
-+#define CHAN0_HOLD_IRQ                BIT(2)
-+#define       CHAN0_KEYDOWN_IRQ       BIT(1)
-+#define CHAN0_DATA_IRQ                BIT(0)
-+
-+struct sun4i_lradc_keymap {
-+      u32 voltage;
-+      u32 keycode;
-+};
-+
-+struct sun4i_lradc_data {
-+      struct device *dev;
-+      struct input_dev *input;
-+      void __iomem *base;
-+      struct regulator *vref_supply;
-+      struct sun4i_lradc_keymap *chan0_map;
-+      u32 chan0_map_count;
-+      u32 chan0_keycode;
-+      u32 vref;
-+};
-+
-+static irqreturn_t sun4i_lradc_irq(int irq, void *dev_id)
-+{
-+      struct sun4i_lradc_data *lradc = dev_id;
-+      u32 i, ints, val, voltage, diff, keycode = 0, closest = 0xffffffff;
-+
-+      ints  = readl(lradc->base + LRADC_INTS);
-+
-+      /*
-+       * lradc supports only one keypress at a time, release does not give
-+       * any info as to which key was released, so we cache the keycode.
-+       */
-+      if ((ints & CHAN0_KEYDOWN_IRQ) && lradc->chan0_keycode == 0) {
-+              val = readl(lradc->base + LRADC_DATA0) & 0x3f;
-+              voltage = val * lradc->vref / 63;
-+
-+              for (i = 0; i < lradc->chan0_map_count; i++) {
-+                      diff = abs(lradc->chan0_map[i].voltage - voltage);
-+                      if (diff < closest) {
-+                              closest = diff;
-+                              keycode = lradc->chan0_map[i].keycode;
-+                      }
-+              }
-+
-+              lradc->chan0_keycode = keycode;
-+              input_report_key(lradc->input, lradc->chan0_keycode, 1);
-+      }
-+
-+      if (ints & CHAN0_KEYUP_IRQ) {
-+              input_report_key(lradc->input, lradc->chan0_keycode, 0);
-+              lradc->chan0_keycode = 0;
-+      }
-+
-+      input_sync(lradc->input);
-+
-+      writel(ints, lradc->base + LRADC_INTS);
-+
-+      return IRQ_HANDLED;
-+}
-+
-+static int sun4i_lradc_open(struct input_dev *dev)
-+{
-+      struct sun4i_lradc_data *lradc = input_get_drvdata(dev);
-+      int ret;
-+
-+      ret = regulator_enable(lradc->vref_supply);
-+      if (ret)
-+              return ret;
-+
-+      /* lradc Vref internally is divided by 2/3 */
-+      lradc->vref = regulator_get_voltage(lradc->vref_supply) * 2 / 3;
-+
-+      /*
-+       * Set sample time to 4 ms / 250 Hz. Wait 2 * 4 ms for key to
-+       * stabilize on press, wait (1 + 1) * 4 ms for key release
-+       */
-+      writel(FIRST_CONVERT_DLY(2) | LEVELA_B_CNT(1) | HOLD_EN(1) |
-+              SAMPLE_RATE(0) | ENABLE(1), lradc->base + LRADC_CTRL);
-+
-+      writel(CHAN0_KEYUP_IRQ | CHAN0_KEYDOWN_IRQ, lradc->base + LRADC_INTC);
-+
-+      return 0;
-+}
-+
-+static void sun4i_lradc_close(struct input_dev *dev)
-+{
-+      struct sun4i_lradc_data *lradc = input_get_drvdata(dev);
-+
-+      /* Disable lradc, leave other settings unchanged */
-+      writel(FIRST_CONVERT_DLY(2) | LEVELA_B_CNT(1) | HOLD_EN(1) |
-+              SAMPLE_RATE(2), lradc->base + LRADC_CTRL);
-+      writel(0, lradc->base + LRADC_INTC);
-+
-+      regulator_disable(lradc->vref_supply);
-+}
-+
-+static int sun4i_lradc_probe(struct platform_device *pdev)
-+{
-+      struct sun4i_lradc_data *lradc;
-+      struct device *dev = &pdev->dev;
-+      struct device_node *pp, *np = dev->of_node;
-+      u32 channel;
-+      int i, ret;
-+
-+      lradc = devm_kzalloc(dev, sizeof(struct sun4i_lradc_data), GFP_KERNEL);
-+      if (!lradc)
-+              return -ENOMEM;
-+
-+      lradc->chan0_map_count = of_get_child_count(np);
-+      lradc->chan0_map = devm_kmalloc(dev, lradc->chan0_map_count *
-+                              sizeof(struct sun4i_lradc_keymap), GFP_KERNEL);
-+      if (!lradc->chan0_map)
-+              return -ENOMEM;
-+
-+      i = 0;
-+      for_each_child_of_node(np, pp) {
-+              struct sun4i_lradc_keymap *map = &lradc->chan0_map[i];
-+
-+              ret = of_property_read_u32(pp, "channel", &channel);
-+              if (ret || channel != 0) {
-+                      dev_err(dev, "%s: Inval channel prop\n", pp->name);
-+                      return -EINVAL;
-+              }
-+
-+              ret = of_property_read_u32(pp, "voltage", &map->voltage);
-+              if (ret) {
-+                      dev_err(dev, "%s: Inval voltage prop\n", pp->name);
-+                      return -EINVAL;
-+              }
-+
-+              ret = of_property_read_u32(pp, "linux,code", &map->keycode);
-+              if (ret) {
-+                      dev_err(dev, "%s: Inval linux,code prop\n", pp->name);
-+                      return -EINVAL;
-+              }
-+
-+              i++;
-+      }
-+
-+      lradc->vref_supply = devm_regulator_get(dev, "vref");
-+      if (IS_ERR(lradc->vref_supply))
-+              return PTR_ERR(lradc->vref_supply);
-+
-+      lradc->dev = dev;
-+      lradc->input = devm_input_allocate_device(dev);
-+      if (!lradc->input)
-+              return -ENOMEM;
-+
-+      lradc->input->name = pdev->name;
-+      lradc->input->phys = "sun4i_lradc/input0";
-+      lradc->input->open = sun4i_lradc_open;
-+      lradc->input->close = sun4i_lradc_close;
-+      lradc->input->id.bustype = BUS_HOST;
-+      lradc->input->id.vendor = 0x0001;
-+      lradc->input->id.product = 0x0001;
-+      lradc->input->id.version = 0x0100;
-+      lradc->input->evbit[0] =  BIT(EV_SYN) | BIT(EV_KEY);
-+      for (i = 0; i < lradc->chan0_map_count; i++)
-+              set_bit(lradc->chan0_map[i].keycode, lradc->input->keybit);
-+      input_set_drvdata(lradc->input, lradc);
-+
-+      lradc->base = devm_ioremap_resource(dev,
-+                            platform_get_resource(pdev, IORESOURCE_MEM, 0));
-+      if (IS_ERR(lradc->base))
-+              return PTR_ERR(lradc->base);
-+
-+      ret = devm_request_irq(dev, platform_get_irq(pdev, 0), sun4i_lradc_irq,
-+                             0, "sun4i-a10-lradc-keys", lradc);
-+      if (ret)
-+              return ret;
-+
-+      ret = input_register_device(lradc->input);
-+      if (ret)
-+              return ret;
-+
-+      platform_set_drvdata(pdev, lradc);
-+      return 0;
-+}
-+
-+static const struct of_device_id sun4i_lradc_of_match[] = {
-+      { .compatible = "allwinner,sun4i-a10-lradc-keys", },
-+      { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, sun4i_lradc_of_match);
-+
-+static struct platform_driver sun4i_lradc_driver = {
-+      .driver = {
-+              .name   = "sun4i-a10-lradc-keys",
-+              .of_match_table = of_match_ptr(sun4i_lradc_of_match),
-+      },
-+      .probe  = sun4i_lradc_probe,
-+};
-+
-+module_platform_driver(sun4i_lradc_driver);
-+
-+MODULE_DESCRIPTION("Allwinner sun4i low res adc attached tablet keys driver");
-+MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
-+MODULE_LICENSE("GPL");
diff --git a/target/linux/sunxi/patches-3.18/111-dt-sun4i-add-lradc.patch b/target/linux/sunxi/patches-3.18/111-dt-sun4i-add-lradc.patch
deleted file mode 100644 (file)
index d2298a4..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-From f39ea4358d2e4b939b8ca55ee344d3c8fdfc0a6a Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Wed, 1 Jan 2014 19:51:36 +0100
-Subject: [PATCH] ARM: dts: sun4i: Add lradc node
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -669,6 +669,13 @@
-                       status = "disabled";
-               };
-+              lradc: lradc@01c22800 {
-+                      compatible = "allwinner,sun4i-a10-lradc-keys";
-+                      reg = <0x01c22800 0x100>;
-+                      interrupts = <31>;
-+                      status = "disabled";
-+              };
-+
-               sid: eeprom@01c23800 {
-                       compatible = "allwinner,sun4i-a10-sid";
-                       reg = <0x01c23800 0x10>;
diff --git a/target/linux/sunxi/patches-3.18/112-dt-sun5i-add-lradc.patch b/target/linux/sunxi/patches-3.18/112-dt-sun5i-add-lradc.patch
deleted file mode 100644 (file)
index edc9016..0000000
+++ /dev/null
@@ -1,167 +0,0 @@
-From 3bf1194692f3a275e0776d3c0b6f17826cc01baa Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Wed, 1 Jan 2014 19:50:33 +0100
-Subject: [PATCH] ARM: dts: sun5i: Add lradc node
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 45 ++++++++++++++++++++++--
- arch/arm/boot/dts/sun5i-a10s.dtsi                |  7 ++++
- arch/arm/boot/dts/sun5i-a13-olinuxino.dts        | 45 ++++++++++++++++++++++--
- arch/arm/boot/dts/sun5i-a13.dtsi                 |  7 ++++
- 4 files changed, 100 insertions(+), 4 deletions(-)
-
---- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
-+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
-@@ -12,8 +12,9 @@
-  */
- /dts-v1/;
--/include/ "sun5i-a10s.dtsi"
--/include/ "sunxi-common-regulators.dtsi"
-+#include "sun5i-a10s.dtsi"
-+#include "sunxi-common-regulators.dtsi"
-+#include <dt-bindings/input/input.h>
- / {
-       model = "Olimex A10s-Olinuxino Micro";
-@@ -98,6 +99,46 @@
-                       };
-               };
-+              lradc: lradc@01c22800 {
-+                      vref-supply = <&reg_vcc3v0>;
-+                      status = "okay";
-+
-+                      button@191 {
-+                              label = "Volume Up";
-+                              linux,code = <KEY_VOLUMEUP>;
-+                              channel = <0>;
-+                              voltage = <191274>;
-+                      };
-+
-+                      button@392 {
-+                              label = "Volume Down";
-+                              linux,code = <KEY_VOLUMEDOWN>;
-+                              channel = <0>;
-+                              voltage = <392644>;
-+                      };
-+
-+                      button@601 {
-+                              label = "Menu";
-+                              linux,code = <KEY_MENU>;
-+                              channel = <0>;
-+                              voltage = <601151>;
-+                      };
-+
-+                      button@795 {
-+                              label = "Enter";
-+                              linux,code = <KEY_ENTER>;
-+                              channel = <0>;
-+                              voltage = <795090>;
-+                      };
-+
-+                      button@987 {
-+                              label = "Home";
-+                              linux,code = <KEY_HOMEPAGE>;
-+                              channel = <0>;
-+                              voltage = <987387>;
-+                      };
-+              };
-+
-               uart0: serial@01c28000 {
-                       pinctrl-names = "default";
-                       pinctrl-0 = <&uart0_pins_a>;
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -520,6 +520,13 @@
-                       reg = <0x01c20c90 0x10>;
-               };
-+              lradc: lradc@01c22800 {
-+                      compatible = "allwinner,sun4i-a10-lradc-keys";
-+                      reg = <0x01c22800 0x100>;
-+                      interrupts = <31>;
-+                      status = "disabled";
-+              };
-+
-               sid: eeprom@01c23800 {
-                       compatible = "allwinner,sun4i-a10-sid";
-                       reg = <0x01c23800 0x10>;
---- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
-+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
-@@ -12,8 +12,9 @@
-  */
- /dts-v1/;
--/include/ "sun5i-a13.dtsi"
--/include/ "sunxi-common-regulators.dtsi"
-+#include "sun5i-a13.dtsi"
-+#include "sunxi-common-regulators.dtsi"
-+#include <dt-bindings/input/input.h>
- / {
-       model = "Olimex A13-Olinuxino";
-@@ -66,6 +67,46 @@
-                       };
-               };
-+              lradc: lradc@01c22800 {
-+                      vref-supply = <&reg_vcc3v0>;
-+                      status = "okay";
-+
-+                      button@191 {
-+                              label = "Volume Up";
-+                              linux,code = <KEY_VOLUMEUP>;
-+                              channel = <0>;
-+                              voltage = <191274>;
-+                      };
-+
-+                      button@392 {
-+                              label = "Volume Down";
-+                              linux,code = <KEY_VOLUMEDOWN>;
-+                              channel = <0>;
-+                              voltage = <392644>;
-+                      };
-+
-+                      button@601 {
-+                              label = "Menu";
-+                              linux,code = <KEY_MENU>;
-+                              channel = <0>;
-+                              voltage = <601151>;
-+                      };
-+
-+                      button@795 {
-+                              label = "Enter";
-+                              linux,code = <KEY_ENTER>;
-+                              channel = <0>;
-+                              voltage = <795090>;
-+                      };
-+
-+                      button@987 {
-+                              label = "Home";
-+                              linux,code = <KEY_HOMEPAGE>;
-+                              channel = <0>;
-+                              voltage = <987387>;
-+                      };
-+              };
-+
-               uart1: serial@01c28400 {
-                       pinctrl-names = "default";
-                       pinctrl-0 = <&uart1_pins_b>;
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -468,6 +468,13 @@
-                       reg = <0x01c20c90 0x10>;
-               };
-+              lradc: lradc@01c22800 {
-+                      compatible = "allwinner,sun4i-a10-lradc-keys";
-+                      reg = <0x01c22800 0x100>;
-+                      interrupts = <31>;
-+                      status = "disabled";
-+              };
-+
-               sid: eeprom@01c23800 {
-                       compatible = "allwinner,sun4i-a10-sid";
-                       reg = <0x01c23800 0x10>;
diff --git a/target/linux/sunxi/patches-3.18/113-dt-sun7i-add-lradc.patch b/target/linux/sunxi/patches-3.18/113-dt-sun7i-add-lradc.patch
deleted file mode 100644 (file)
index ae2c383..0000000
+++ /dev/null
@@ -1,102 +0,0 @@
-From a735a9b354ebc1a17b648ef8c3482c71fdbf40da Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Wed, 1 Jan 2014 20:26:21 +0100
-Subject: [PATCH] ARM: dts: sun7i: Add lradc node
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 59 ++++++++++++++++++++++++-
- arch/arm/boot/dts/sun7i-a20.dtsi                |  7 +++
- 2 files changed, 64 insertions(+), 2 deletions(-)
-
---- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-@@ -12,8 +12,9 @@
-  */
- /dts-v1/;
--/include/ "sun7i-a20.dtsi"
--/include/ "sunxi-common-regulators.dtsi"
-+#include "sun7i-a20.dtsi"
-+#include "sunxi-common-regulators.dtsi"
-+#include <dt-bindings/input/input.h>
- / {
-       model = "Olimex A20-Olinuxino Micro";
-@@ -100,6 +101,60 @@
-                       };
-               };
-+              lradc: lradc@01c22800 {
-+                      vref-supply = <&reg_vcc3v0>;
-+                      status = "okay";
-+
-+                      button@191 {
-+                              label = "Volume Up";
-+                              linux,code = <KEY_VOLUMEUP>;
-+                              channel = <0>;
-+                              voltage = <191274>;
-+                      };
-+
-+                      button@392 {
-+                              label = "Volume Down";
-+                              linux,code = <KEY_VOLUMEDOWN>;
-+                              channel = <0>;
-+                              voltage = <392644>;
-+                      };
-+
-+                      button@601 {
-+                              label = "Menu";
-+                              linux,code = <KEY_MENU>;
-+                              channel = <0>;
-+                              voltage = <601151>;
-+                      };
-+
-+                      button@795 {
-+                              label = "Search";
-+                              linux,code = <KEY_SEARCH>;
-+                              channel = <0>;
-+                              voltage = <795090>;
-+                      };
-+
-+                      button@987 {
-+                              label = "Home";
-+                              linux,code = <KEY_HOMEPAGE>;
-+                              channel = <0>;
-+                              voltage = <987387>;
-+                      };
-+
-+                      button@1184 {
-+                              label = "Esc";
-+                              linux,code = <KEY_ESC>;
-+                              channel = <0>;
-+                              voltage = <1184678>;
-+                      };
-+
-+                      button@1398 {
-+                              label = "Enter";
-+                              linux,code = <KEY_ENTER>;
-+                              channel = <0>;
-+                              voltage = <1398804>;
-+                      };
-+              };
-+
-               uart0: serial@01c28000 {
-                       pinctrl-names = "default";
-                       pinctrl-0 = <&uart0_pins_a>;
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -911,6 +911,13 @@
-                       status = "disabled";
-               };
-+              lradc: lradc@01c22800 {
-+                      compatible = "allwinner,sun4i-a10-lradc-keys";
-+                      reg = <0x01c22800 0x100>;
-+                      interrupts = <0 31 4>;
-+                      status = "disabled";
-+              };
-+
-               sid: eeprom@01c23800 {
-                       compatible = "allwinner,sun7i-a20-sid";
-                       reg = <0x01c23800 0x200>;
diff --git a/target/linux/sunxi/patches-3.18/115-input-sun4i-ts-update-temp-curve.patch b/target/linux/sunxi/patches-3.18/115-input-sun4i-ts-update-temp-curve.patch
deleted file mode 100644 (file)
index 331c93b..0000000
+++ /dev/null
@@ -1,79 +0,0 @@
-From 2e2493cd07405dfa88e53199b47bdbbb5336fdce Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 16 Jun 2014 20:01:12 +0200
-Subject: [PATCH] touchscreen: sun4i-ts: A10 (sun4i) has a different
- temperature curve
-
-Testing has revealed that the temperature in the rtp controller of the A10
-(sun4i) SoC has a different curve then on the A13 (sun5i) and later models.
-
-Add a new sun5i-a13-ts compatible to differentiate the newer models and
-set the curve based on the compatible string.
-
-This fixes the temperature reported on the A10 being much higher then
-expected.
-
-Note the new curve is still not ideal on all A10-s, that seems to have to
-do with there being a large spread between different A10-s out there.
-
-Reported-by: Tong Zhang <lovewilliam@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- .../devicetree/bindings/input/touchscreen/sun4i.txt         |  2 +-
- drivers/input/touchscreen/sun4i-ts.c                        | 13 ++++++++++++-
- 2 files changed, 13 insertions(+), 2 deletions(-)
-
---- a/Documentation/devicetree/bindings/input/touchscreen/sun4i.txt
-+++ b/Documentation/devicetree/bindings/input/touchscreen/sun4i.txt
-@@ -2,7 +2,7 @@ sun4i resistive touchscreen controller
- --------------------------------------
- Required properties:
-- - compatible: "allwinner,sun4i-a10-ts"
-+ - compatible: "allwinner,sun4i-a10-ts" or "allwinner,sun5i-a13-ts"
-  - reg: mmio address range of the chip
-  - interrupts: interrupt to which the chip is connected
---- a/drivers/input/touchscreen/sun4i-ts.c
-+++ b/drivers/input/touchscreen/sun4i-ts.c
-@@ -111,6 +111,8 @@ struct sun4i_ts_data {
-       unsigned int irq;
-       bool ignore_fifo_data;
-       int temp_data;
-+      int temp_offset;
-+      int temp_step;
- };
- static void sun4i_ts_irq_handle_input(struct sun4i_ts_data *ts, u32 reg_val)
-@@ -189,7 +191,8 @@ static ssize_t show_temp(struct device *
-       if (ts->temp_data == -1)
-               return -EAGAIN;
--      return sprintf(buf, "%d\n", (ts->temp_data - 1447) * 100);
-+      return sprintf(buf, "%d\n",
-+                     (ts->temp_data - ts->temp_offset) * ts->temp_step);
- }
- static ssize_t show_temp_label(struct device *dev,
-@@ -224,6 +227,13 @@ static int sun4i_ts_probe(struct platfor
-       ts->dev = dev;
-       ts->ignore_fifo_data = true;
-       ts->temp_data = -1;
-+      if (of_device_is_compatible(np, "allwinner,sun4i-a10-ts")) {
-+              ts->temp_offset = 1900;
-+              ts->temp_step = 100;
-+      } else {
-+              ts->temp_offset = 1447;
-+              ts->temp_step = 100;
-+      }
-       ts_attached = of_property_read_bool(np, "allwinner,ts-attached");
-       if (ts_attached) {
-@@ -318,6 +328,7 @@ static int sun4i_ts_remove(struct platfo
- static const struct of_device_id sun4i_ts_of_match[] = {
-       { .compatible = "allwinner,sun4i-a10-ts", },
-+      { .compatible = "allwinner,sun5i-a13-ts", },
-       { /* sentinel */ }
- };
- MODULE_DEVICE_TABLE(of, sun4i_ts_of_match);
diff --git a/target/linux/sunxi/patches-3.18/116-dt-sunxi-update-compats-for-tempcurves.patch b/target/linux/sunxi/patches-3.18/116-dt-sunxi-update-compats-for-tempcurves.patch
deleted file mode 100644 (file)
index fe8dcdb..0000000
+++ /dev/null
@@ -1,51 +0,0 @@
-From ff774d842a2bf9136b9c7ddd7f5085a9062705ac Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 16 Jun 2014 20:06:43 +0200
-Subject: [PATCH] ARM: dts: sunxi: Adjust touchscreen compatible for sun5i and
- later
-
-The touchscreen controller in the A13 and later has a different temperature
-curve than the one in the original A10, change the compatible for the A13 and
-later so that the kernel will use the correct curve.
-
-Reported-by: Tong Zhang <lovewilliam@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun5i-a10s.dtsi | 2 +-
- arch/arm/boot/dts/sun5i-a13.dtsi  | 2 +-
- arch/arm/boot/dts/sun7i-a20.dtsi  | 2 +-
- 3 files changed, 3 insertions(+), 3 deletions(-)
-
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -533,7 +533,7 @@
-               };
-               rtp: rtp@01c25000 {
--                      compatible = "allwinner,sun4i-a10-ts";
-+                      compatible = "allwinner,sun5i-a13-ts";
-                       reg = <0x01c25000 0x100>;
-                       interrupts = <29>;
-               };
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -481,7 +481,7 @@
-               };
-               rtp: rtp@01c25000 {
--                      compatible = "allwinner,sun4i-a10-ts";
-+                      compatible = "allwinner,sun5i-a13-ts";
-                       reg = <0x01c25000 0x100>;
-                       interrupts = <29>;
-               };
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -924,7 +924,7 @@
-               };
-               rtp: rtp@01c25000 {
--                      compatible = "allwinner,sun4i-a10-ts";
-+                      compatible = "allwinner,sun5i-a13-ts";
-                       reg = <0x01c25000 0x100>;
-                       interrupts = <0 29 4>;
-               };
diff --git a/target/linux/sunxi/patches-3.18/130-input-add-axp20x-pek.patch b/target/linux/sunxi/patches-3.18/130-input-add-axp20x-pek.patch
deleted file mode 100644 (file)
index 28ed6a3..0000000
+++ /dev/null
@@ -1,332 +0,0 @@
-From 63d559304a15ffead2fa1014b93dbcabf516c257 Mon Sep 17 00:00:00 2001
-From: Carlo Caione <carlo@caione.org>
-Date: Mon, 19 May 2014 21:47:45 +0200
-Subject: [PATCH] input: misc: Add driver for AXP20x Power Enable Key
-
-This patch add support for the Power Enable Key found on MFD AXP202 and
-AXP209. Besides the basic support for the button, the driver adds two
-entries in sysfs to configure the time delay for power on/off.
-
-Signed-off-by: Carlo Caione <carlo@caione.org>
-Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
----
- drivers/input/misc/Kconfig      |  11 ++
- drivers/input/misc/Makefile     |   1 +
- drivers/input/misc/axp20x-pek.c | 281 ++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 293 insertions(+)
- create mode 100644 drivers/input/misc/axp20x-pek.c
-
---- a/drivers/input/misc/Kconfig
-+++ b/drivers/input/misc/Kconfig
-@@ -404,6 +404,17 @@ config INPUT_RETU_PWRBUTTON
-         To compile this driver as a module, choose M here. The module will
-         be called retu-pwrbutton.
-+config INPUT_AXP20X_PEK
-+      tristate "X-Powers AXP20X power button driver"
-+      depends on MFD_AXP20X
-+      help
-+        Say Y here if you want to enable power key reporting via the
-+        AXP20X PMIC.
-+
-+        To compile this driver as a module, choose M here. The module will
-+        be called axp20x-pek.
-+
-+
- config INPUT_TWL4030_PWRBUTTON
-       tristate "TWL4030 Power button Driver"
-       depends on TWL4030_CORE
---- a/drivers/input/misc/Makefile
-+++ b/drivers/input/misc/Makefile
-@@ -54,6 +54,7 @@ obj-$(CONFIG_INPUT_POWERMATE)                += powerm
- obj-$(CONFIG_INPUT_PWM_BEEPER)                += pwm-beeper.o
- obj-$(CONFIG_INPUT_RB532_BUTTON)      += rb532_button.o
- obj-$(CONFIG_INPUT_RETU_PWRBUTTON)    += retu-pwrbutton.o
-+obj-$(CONFIG_INPUT_AXP20X_PEK)                += axp20x-pek.o
- obj-$(CONFIG_INPUT_GPIO_ROTARY_ENCODER)       += rotary_encoder.o
- obj-$(CONFIG_INPUT_SGI_BTNS)          += sgi_btns.o
- obj-$(CONFIG_INPUT_SIRFSOC_ONKEY)     += sirfsoc-onkey.o
---- /dev/null
-+++ b/drivers/input/misc/axp20x-pek.c
-@@ -0,0 +1,281 @@
-+/*
-+ * axp20x power button driver.
-+ *
-+ * Copyright (C) 2013 Carlo Caione <carlo@caione.org>
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/errno.h>
-+#include <linux/irq.h>
-+#include <linux/init.h>
-+#include <linux/input.h>
-+#include <linux/interrupt.h>
-+#include <linux/kernel.h>
-+#include <linux/mfd/axp20x.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/regmap.h>
-+#include <linux/slab.h>
-+
-+#define AXP20X_PEK_STARTUP_MASK               (0xc0)
-+#define AXP20X_PEK_SHUTDOWN_MASK      (0x03)
-+
-+struct axp20x_pek {
-+      struct axp20x_dev *axp20x;
-+      struct input_dev *input;
-+      int irq_dbr;
-+      int irq_dbf;
-+};
-+
-+struct axp20x_time {
-+      unsigned int time;
-+      unsigned int idx;
-+};
-+
-+static const struct axp20x_time startup_time[] = {
-+      { .time = 128,  .idx = 0 },
-+      { .time = 1000, .idx = 2 },
-+      { .time = 3000, .idx = 1 },
-+      { .time = 2000, .idx = 3 },
-+};
-+
-+static const struct axp20x_time shutdown_time[] = {
-+      { .time = 4000,  .idx = 0 },
-+      { .time = 6000,  .idx = 1 },
-+      { .time = 8000,  .idx = 2 },
-+      { .time = 10000, .idx = 3 },
-+};
-+
-+struct axp20x_pek_ext_attr {
-+      const struct axp20x_time *p_time;
-+      unsigned int mask;
-+};
-+
-+static struct axp20x_pek_ext_attr axp20x_pek_startup_ext_attr = {
-+      .p_time = startup_time,
-+      .mask   = AXP20X_PEK_STARTUP_MASK,
-+};
-+
-+static struct axp20x_pek_ext_attr axp20x_pek_shutdown_ext_attr = {
-+      .p_time = shutdown_time,
-+      .mask   = AXP20X_PEK_SHUTDOWN_MASK,
-+};
-+
-+static struct axp20x_pek_ext_attr *get_axp_ext_attr(struct device_attribute *attr)
-+{
-+      return container_of(attr, struct dev_ext_attribute, attr)->var;
-+}
-+
-+static ssize_t axp20x_show_ext_attr(struct device *dev, struct device_attribute *attr,
-+                                  char *buf)
-+{
-+      struct axp20x_pek *axp20x_pek = dev_get_drvdata(dev);
-+      struct axp20x_pek_ext_attr *axp20x_ea = get_axp_ext_attr(attr);
-+      unsigned int val;
-+      int ret, i;
-+
-+      ret = regmap_read(axp20x_pek->axp20x->regmap, AXP20X_PEK_KEY, &val);
-+      if (ret != 0)
-+              return ret;
-+
-+      val &= axp20x_ea->mask;
-+      val >>= ffs(axp20x_ea->mask) - 1;
-+
-+      for (i = 0; i < 4; i++)
-+              if (val == axp20x_ea->p_time[i].idx)
-+                      val = axp20x_ea->p_time[i].time;
-+
-+      return sprintf(buf, "%u\n", val);
-+}
-+
-+static ssize_t axp20x_store_ext_attr(struct device *dev, struct device_attribute *attr,
-+                                   const char *buf, size_t count)
-+{
-+      struct axp20x_pek *axp20x_pek = dev_get_drvdata(dev);
-+      struct axp20x_pek_ext_attr *axp20x_ea = get_axp_ext_attr(attr);
-+      char val_str[20];
-+      size_t len;
-+      int ret, i;
-+      unsigned int val, idx = 0;
-+      unsigned int best_err = UINT_MAX;
-+
-+      val_str[sizeof(val_str) - 1] = '\0';
-+      strncpy(val_str, buf, sizeof(val_str) - 1);
-+      len = strlen(val_str);
-+
-+      if (len && val_str[len - 1] == '\n')
-+              val_str[len - 1] = '\0';
-+
-+      ret = kstrtouint(val_str, 10, &val);
-+      if (ret)
-+              return ret;
-+
-+      for (i = 3; i >= 0; i--) {
-+              unsigned int err;
-+
-+              err = abs(axp20x_ea->p_time[i].time - val);
-+              if (err < best_err) {
-+                      best_err = err;
-+                      idx = axp20x_ea->p_time[i].idx;
-+              }
-+
-+              if (!err)
-+                      break;
-+      }
-+
-+      idx <<= ffs(axp20x_ea->mask) - 1;
-+      ret = regmap_update_bits(axp20x_pek->axp20x->regmap,
-+                               AXP20X_PEK_KEY,
-+                               axp20x_ea->mask, idx);
-+      if (ret != 0)
-+              return -EINVAL;
-+      return count;
-+}
-+
-+static struct dev_ext_attribute axp20x_dev_attr_startup = {
-+      .attr   = __ATTR(startup, 0644, axp20x_show_ext_attr, axp20x_store_ext_attr),
-+      .var    = &axp20x_pek_startup_ext_attr
-+};
-+
-+static struct dev_ext_attribute axp20x_dev_attr_shutdown = {
-+      .attr   = __ATTR(shutdown, 0644, axp20x_show_ext_attr, axp20x_store_ext_attr),
-+      .var    = &axp20x_pek_shutdown_ext_attr
-+};
-+
-+static irqreturn_t axp20x_pek_irq(int irq, void *pwr)
-+{
-+      struct input_dev *idev = pwr;
-+      struct axp20x_pek *axp20x_pek = input_get_drvdata(idev);
-+
-+      if (irq == axp20x_pek->irq_dbr)
-+              input_report_key(idev, KEY_POWER, true);
-+      else if (irq == axp20x_pek->irq_dbf)
-+              input_report_key(idev, KEY_POWER, false);
-+
-+      input_sync(idev);
-+
-+      return IRQ_HANDLED;
-+}
-+
-+static int axp20x_pek_probe(struct platform_device *pdev)
-+{
-+      struct axp20x_pek *axp20x_pek;
-+      struct axp20x_dev *axp20x;
-+      struct input_dev *idev;
-+      int error;
-+
-+      axp20x_pek = devm_kzalloc(&pdev->dev, sizeof(struct axp20x_pek),
-+                                GFP_KERNEL);
-+      if (!axp20x_pek)
-+              return -ENOMEM;
-+
-+      axp20x_pek->axp20x = dev_get_drvdata(pdev->dev.parent);
-+      axp20x = axp20x_pek->axp20x;
-+
-+      axp20x_pek->irq_dbr = platform_get_irq_byname(pdev, "PEK_DBR");
-+      if (axp20x_pek->irq_dbr < 0) {
-+              dev_err(&pdev->dev, "No IRQ for PEK_DBR, error=%d\n",
-+                              axp20x_pek->irq_dbr);
-+              return axp20x_pek->irq_dbr;
-+      }
-+      axp20x_pek->irq_dbr = regmap_irq_get_virq(axp20x->regmap_irqc,
-+                                                axp20x_pek->irq_dbr);
-+
-+      axp20x_pek->irq_dbf = platform_get_irq_byname(pdev, "PEK_DBF");
-+      if (axp20x_pek->irq_dbf < 0) {
-+              dev_err(&pdev->dev, "No IRQ for PEK_DBF, error=%d\n",
-+                              axp20x_pek->irq_dbf);
-+              return axp20x_pek->irq_dbf;
-+      }
-+      axp20x_pek->irq_dbf = regmap_irq_get_virq(axp20x->regmap_irqc,
-+                                                axp20x_pek->irq_dbf);
-+
-+      axp20x_pek->input = devm_input_allocate_device(&pdev->dev);
-+      if (!axp20x_pek->input)
-+              return -ENOMEM;
-+
-+      idev = axp20x_pek->input;
-+
-+      idev->name = "axp20x-pek";
-+      idev->phys = "m1kbd/input2";
-+      idev->dev.parent = &pdev->dev;
-+
-+      input_set_capability(idev, EV_KEY, KEY_POWER);
-+
-+      input_set_drvdata(idev, axp20x_pek);
-+
-+      error = devm_request_any_context_irq(&pdev->dev, axp20x_pek->irq_dbr,
-+                                        axp20x_pek_irq, 0,
-+                                        "axp20x-pek-dbr", idev);
-+      if (error < 0) {
-+              dev_err(axp20x->dev, "Failed to request dbr IRQ#%d: %d\n",
-+                      axp20x_pek->irq_dbr, error);
-+
-+              return error;
-+      }
-+
-+      error = devm_request_any_context_irq(&pdev->dev, axp20x_pek->irq_dbf,
-+                                        axp20x_pek_irq, 0,
-+                                        "axp20x-pek-dbf", idev);
-+      if (error < 0) {
-+              dev_err(axp20x->dev, "Failed to request dbf IRQ#%d: %d\n",
-+                      axp20x_pek->irq_dbf, error);
-+              return error;
-+      }
-+
-+      error = device_create_file(&pdev->dev, &axp20x_dev_attr_startup.attr);
-+      if (error)
-+              return error;
-+
-+      error = device_create_file(&pdev->dev, &axp20x_dev_attr_shutdown.attr);
-+      if (error)
-+              goto clear_startup_attr;
-+
-+      error = input_register_device(idev);
-+      if (error) {
-+              dev_err(axp20x->dev, "Can't register input device: %d\n", error);
-+              goto clear_attr;
-+      }
-+
-+      platform_set_drvdata(pdev, axp20x_pek);
-+
-+      return 0;
-+
-+clear_attr:
-+      device_remove_file(&pdev->dev, &axp20x_dev_attr_shutdown.attr);
-+
-+clear_startup_attr:
-+      device_remove_file(&pdev->dev, &axp20x_dev_attr_startup.attr);
-+
-+      return error;
-+}
-+
-+int axp20x_pek_remove(struct platform_device *pdev)
-+{
-+      device_remove_file(&pdev->dev, &axp20x_dev_attr_shutdown.attr);
-+      device_remove_file(&pdev->dev, &axp20x_dev_attr_startup.attr);
-+
-+      return 0;
-+}
-+
-+static struct platform_driver axp20x_pek_driver = {
-+      .probe          = axp20x_pek_probe,
-+      .remove         = axp20x_pek_remove,
-+      .driver         = {
-+              .name           = "axp20x-pek",
-+              .owner          = THIS_MODULE,
-+      },
-+};
-+module_platform_driver(axp20x_pek_driver);
-+
-+MODULE_DESCRIPTION("axp20x Power Button");
-+MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
-+MODULE_LICENSE("GPL");
diff --git a/target/linux/sunxi/patches-3.18/150-pwm-add-sunxi-driver.patch b/target/linux/sunxi/patches-3.18/150-pwm-add-sunxi-driver.patch
deleted file mode 100644 (file)
index 49560c3..0000000
+++ /dev/null
@@ -1,402 +0,0 @@
---- a/drivers/pwm/Kconfig
-+++ b/drivers/pwm/Kconfig
-@@ -263,6 +263,15 @@ config PWM_STI
-         To compile this driver as a module, choose M here: the module
-         will be called pwm-sti.
-+config PWM_SUN4I
-+      tristate "Allwinner sun4i PWM support"
-+      depends on ARCH_SUNXI || COMPILE_TEST
-+      help
-+        Generic PWM framework driver for Allwinner sun4i and sun7i SoCs.
-+
-+        To compile this driver as a module, choose M here: the module
-+        will be called pwm-sun4i.
-+
- config PWM_TEGRA
-       tristate "NVIDIA Tegra PWM support"
-       depends on ARCH_TEGRA
---- a/drivers/pwm/Makefile
-+++ b/drivers/pwm/Makefile
-@@ -24,6 +24,7 @@ obj-$(CONFIG_PWM_ROCKCHIP)   += pwm-rockch
- obj-$(CONFIG_PWM_SAMSUNG)     += pwm-samsung.o
- obj-$(CONFIG_PWM_SPEAR)               += pwm-spear.o
- obj-$(CONFIG_PWM_STI)         += pwm-sti.o
-+obj-$(CONFIG_PWM_SUN4I)               += pwm-sun4i.o
- obj-$(CONFIG_PWM_TEGRA)               += pwm-tegra.o
- obj-$(CONFIG_PWM_TIECAP)      += pwm-tiecap.o
- obj-$(CONFIG_PWM_TIEHRPWM)    += pwm-tiehrpwm.o
---- /dev/null
-+++ b/drivers/pwm/pwm-sun4i.c
-@@ -0,0 +1,371 @@
-+/*
-+ * Driver for Allwinner sun4i Pulse Width Modulation Controller
-+ *
-+ * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
-+ *
-+ * Licensed under GPLv2.
-+ */
-+
-+#include <linux/bitops.h>
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/mutex.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include <linux/pwm.h>
-+#include <linux/slab.h>
-+#include <linux/time.h>
-+
-+#define PWM_CTRL_REG          0x0
-+
-+#define PWM_CH_PRD_BASE               0x4
-+#define PWM_CH_PRD_OFFSET     0x4
-+#define PWM_CH_PRD(ch)                (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
-+
-+#define PWMCH_OFFSET          15
-+#define PWM_PRESCAL_MASK      GENMASK(3, 0)
-+#define PWM_PRESCAL_OFF               0
-+#define PWM_EN                        BIT(4)
-+#define PWM_ACT_STATE         BIT(5)
-+#define PWM_CLK_GATING                BIT(6)
-+#define PWM_MODE              BIT(7)
-+#define PWM_PULSE             BIT(8)
-+#define PWM_BYPASS            BIT(9)
-+
-+#define PWM_RDY_BASE          28
-+#define PWM_RDY_OFFSET                1
-+#define PWM_RDY(ch)           BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
-+
-+#define PWM_PRD(prd)          (((prd) - 1) << 16)
-+#define PWM_PRD_MASK          GENMASK(15, 0)
-+
-+#define PWM_DTY_MASK          GENMASK(15, 0)
-+
-+#define BIT_CH(bit, chan)     ((bit) << ((chan) * PWMCH_OFFSET))
-+
-+static const u32 prescaler_table[] = {
-+      120,
-+      180,
-+      240,
-+      360,
-+      480,
-+      0,
-+      0,
-+      0,
-+      12000,
-+      24000,
-+      36000,
-+      48000,
-+      72000,
-+      0,
-+      0,
-+      0, /* Actually 1 but tested separately */
-+};
-+
-+struct sun4i_pwm_data {
-+      bool has_prescaler_bypass;
-+      bool has_rdy;
-+};
-+
-+struct sun4i_pwm_chip {
-+      struct pwm_chip chip;
-+      struct clk *clk;
-+      void __iomem *base;
-+      struct mutex ctrl_lock;
-+      const struct sun4i_pwm_data *data;
-+};
-+
-+static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
-+{
-+      return container_of(chip, struct sun4i_pwm_chip, chip);
-+}
-+
-+static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
-+                                unsigned long offset)
-+{
-+      return readl(chip->base + offset);
-+}
-+
-+static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
-+                                  u32 val, unsigned long offset)
-+{
-+      writel(val, chip->base + offset);
-+}
-+
-+static int sun4i_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
-+                          int duty_ns, int period_ns)
-+{
-+      struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
-+      u32 clk_rate, prd, dty, val, clk_gate;
-+      u64 div = 0;
-+      unsigned int prescaler = 0;
-+      int err;
-+
-+      clk_rate = clk_get_rate(sun4i_pwm->clk);
-+
-+      if (sun4i_pwm->data->has_prescaler_bypass) {
-+              /* First, test without any prescaler when available */
-+              prescaler = PWM_PRESCAL_MASK;
-+              /*
-+               * When not using any prescaler, the clock period in nanoseconds
-+               * is not an integer so round it half up instead of
-+               * truncating to get less surprising values.
-+               */
-+              div = clk_rate * (u64)period_ns + NSEC_PER_SEC/2;
-+              do_div(div, NSEC_PER_SEC);
-+              if (div - 1 > PWM_PRD_MASK)
-+                      prescaler = 0;
-+      }
-+
-+      if (prescaler == 0) {
-+              /* Go up from the first divider */
-+              for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
-+                      if (!prescaler_table[prescaler])
-+                              continue;
-+                      div = clk_rate / prescaler_table[prescaler];
-+                      div = div * (u64)period_ns;
-+                      do_div(div, NSEC_PER_SEC);
-+                      if (div - 1 <= PWM_PRD_MASK)
-+                              break;
-+              }
-+
-+              if (div - 1 > PWM_PRD_MASK) {
-+                      dev_err(chip->dev, "period exceeds the maximum value\n");
-+                      return -EINVAL;
-+              }
-+      }
-+
-+      prd = div;
-+      div *= duty_ns;
-+      do_div(div, period_ns);
-+      dty = div;
-+
-+      err = clk_prepare_enable(sun4i_pwm->clk);
-+      if (err) {
-+              dev_err(chip->dev, "failed to enable PWM clock\n");
-+              return err;
-+      }
-+
-+      mutex_lock(&sun4i_pwm->ctrl_lock);
-+      val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
-+
-+      if (sun4i_pwm->data->has_rdy && (val & PWM_RDY(pwm->hwpwm))) {
-+              mutex_unlock(&sun4i_pwm->ctrl_lock);
-+              clk_disable_unprepare(sun4i_pwm->clk);
-+              return -EBUSY;
-+      }
-+
-+      clk_gate = val & BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
-+      if (clk_gate) {
-+              val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
-+              sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
-+      }
-+
-+      val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
-+      val &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
-+      val |= BIT_CH(prescaler, pwm->hwpwm);
-+      sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
-+
-+      val = (dty & PWM_DTY_MASK) | PWM_PRD(prd);
-+      sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
-+
-+      if (clk_gate) {
-+              val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
-+              val |= clk_gate;
-+              sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
-+      }
-+
-+      mutex_unlock(&sun4i_pwm->ctrl_lock);
-+      clk_disable_unprepare(sun4i_pwm->clk);
-+
-+      return 0;
-+}
-+
-+static int sun4i_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
-+                                enum pwm_polarity polarity)
-+{
-+      struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
-+      u32 val;
-+      int ret;
-+
-+      ret = clk_prepare_enable(sun4i_pwm->clk);
-+      if (ret) {
-+              dev_err(chip->dev, "failed to enable PWM clock\n");
-+              return ret;
-+      }
-+
-+      mutex_lock(&sun4i_pwm->ctrl_lock);
-+      val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
-+
-+      if (polarity != PWM_POLARITY_NORMAL)
-+              val &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
-+      else
-+              val |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
-+
-+      sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
-+
-+      mutex_unlock(&sun4i_pwm->ctrl_lock);
-+      clk_disable_unprepare(sun4i_pwm->clk);
-+
-+      return 0;
-+}
-+
-+static int sun4i_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
-+{
-+      struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
-+      u32 val;
-+      int ret;
-+
-+      ret = clk_prepare_enable(sun4i_pwm->clk);
-+      if (ret) {
-+              dev_err(chip->dev, "failed to enable PWM clock\n");
-+              return ret;
-+      }
-+
-+      mutex_lock(&sun4i_pwm->ctrl_lock);
-+      val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
-+      val |= BIT_CH(PWM_EN, pwm->hwpwm);
-+      val |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
-+      sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
-+      mutex_unlock(&sun4i_pwm->ctrl_lock);
-+
-+      return 0;
-+}
-+
-+static void sun4i_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
-+{
-+      struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
-+      u32 val;
-+
-+      mutex_lock(&sun4i_pwm->ctrl_lock);
-+      val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
-+      val &= ~BIT_CH(PWM_EN, pwm->hwpwm);
-+      val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
-+      sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
-+      mutex_unlock(&sun4i_pwm->ctrl_lock);
-+
-+      clk_disable_unprepare(sun4i_pwm->clk);
-+}
-+
-+static const struct pwm_ops sun4i_pwm_ops = {
-+      .config = sun4i_pwm_config,
-+      .set_polarity = sun4i_pwm_set_polarity,
-+      .enable = sun4i_pwm_enable,
-+      .disable = sun4i_pwm_disable,
-+      .owner = THIS_MODULE,
-+};
-+
-+static const struct sun4i_pwm_data sun4i_pwm_data_a10 = {
-+      .has_prescaler_bypass = false,
-+      .has_rdy = false,
-+};
-+
-+static const struct sun4i_pwm_data sun4i_pwm_data_a20 = {
-+      .has_prescaler_bypass = true,
-+      .has_rdy = true,
-+};
-+
-+static const struct of_device_id sun4i_pwm_dt_ids[] = {
-+      {
-+              .compatible = "allwinner,sun4i-a10-pwm",
-+              .data = &sun4i_pwm_data_a10,
-+      }, {
-+              .compatible = "allwinner,sun7i-a20-pwm",
-+              .data = &sun4i_pwm_data_a20,
-+      }, {
-+              /* sentinel */
-+      },
-+};
-+MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
-+
-+static int sun4i_pwm_probe(struct platform_device *pdev)
-+{
-+      struct sun4i_pwm_chip *pwm;
-+      struct resource *res;
-+      u32 val;
-+      int i, ret;
-+      const struct of_device_id *match;
-+
-+      match = of_match_device(sun4i_pwm_dt_ids, &pdev->dev);
-+
-+      pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
-+      if (!pwm)
-+              return -ENOMEM;
-+
-+      res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+      pwm->base = devm_ioremap_resource(&pdev->dev, res);
-+      if (IS_ERR(pwm->base))
-+              return PTR_ERR(pwm->base);
-+
-+      pwm->clk = devm_clk_get(&pdev->dev, NULL);
-+      if (IS_ERR(pwm->clk))
-+              return PTR_ERR(pwm->clk);
-+
-+      pwm->chip.dev = &pdev->dev;
-+      pwm->chip.ops = &sun4i_pwm_ops;
-+      pwm->chip.base = -1;
-+      pwm->chip.npwm = 2;
-+      pwm->chip.can_sleep = true;
-+      pwm->chip.of_xlate = of_pwm_xlate_with_flags;
-+      pwm->chip.of_pwm_n_cells = 3;
-+      pwm->data = match->data;
-+
-+      mutex_init(&pwm->ctrl_lock);
-+
-+      ret = pwmchip_add(&pwm->chip);
-+      if (ret < 0) {
-+              dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
-+              goto error;
-+      }
-+
-+      platform_set_drvdata(pdev, pwm);
-+
-+      ret = clk_prepare_enable(pwm->clk);
-+      if (ret) {
-+              dev_err(&pdev->dev, "failed to enable PWM clock\n");
-+              goto clk_error;
-+      }
-+
-+      val = sun4i_pwm_readl(pwm, PWM_CTRL_REG);
-+      for (i = 0; i < pwm->chip.npwm; i++) {
-+              if (!(val & BIT_CH(PWM_ACT_STATE, i)))
-+                      pwm->chip.pwms[i].polarity = PWM_POLARITY_INVERSED;
-+      }
-+      clk_disable_unprepare(pwm->clk);
-+
-+      return 0;
-+
-+clk_error:
-+      pwmchip_remove(&pwm->chip);
-+
-+error:
-+      mutex_destroy(&pwm->ctrl_lock);
-+      return ret;
-+}
-+
-+static int sun4i_pwm_remove(struct platform_device *pdev)
-+{
-+      struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
-+
-+      mutex_destroy(&pwm->ctrl_lock);
-+
-+      return pwmchip_remove(&pwm->chip);
-+}
-+
-+static struct platform_driver sun4i_pwm_driver = {
-+      .driver = {
-+              .name = "sun4i-pwm",
-+              .of_match_table = sun4i_pwm_dt_ids,
-+      },
-+      .probe = sun4i_pwm_probe,
-+      .remove = sun4i_pwm_remove,
-+};
-+module_platform_driver(sun4i_pwm_driver);
-+
-+MODULE_ALIAS("platform:sun4i-pwm");
-+MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
-+MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/sunxi/patches-3.18/200-mmc-add-sdio-function-subnode.patch b/target/linux/sunxi/patches-3.18/200-mmc-add-sdio-function-subnode.patch
deleted file mode 100644 (file)
index dcbb3a4..0000000
+++ /dev/null
@@ -1,140 +0,0 @@
-From 8c2057afe84c074ef7cd3ee2ec8e9bed835b9e93 Mon Sep 17 00:00:00 2001
-From: Sascha Hauer <s.hauer@pengutronix.de>
-Date: Wed, 21 May 2014 19:50:04 +0200
-Subject: [PATCH] mmc: Add SDIO function devicetree subnode parsing
-
-This adds SDIO devicetree subnode parsing to the mmc core. While
-SDIO devices are runtime probable they sometimes need nonprobable
-additional information on embedded systems, like an additional gpio
-interrupt or a clock. This patch makes it possible to supply this
-information from the devicetree. SDIO drivers will find a pointer
-to the devicenode in their devices of_node pointer.
-
-Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-[hdegoede@redhat.com: Misc. cleanups]
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/mmc/core/bus.c      |  4 ++++
- drivers/mmc/core/core.c     | 28 ++++++++++++++++++++++++++++
- drivers/mmc/core/core.h     |  3 +++
- drivers/mmc/core/sdio_bus.c | 11 +++++++++++
- 4 files changed, 46 insertions(+)
-
---- a/drivers/mmc/core/bus.c
-+++ b/drivers/mmc/core/bus.c
-@@ -16,6 +16,7 @@
- #include <linux/err.h>
- #include <linux/slab.h>
- #include <linux/stat.h>
-+#include <linux/of.h>
- #include <linux/pm_runtime.h>
- #include <linux/mmc/card.h>
-@@ -352,6 +353,8 @@ int mmc_add_card(struct mmc_card *card)
- #endif
-       mmc_init_context_info(card->host);
-+      card->dev.of_node = mmc_of_find_child_device(card->host, 0);
-+
-       ret = device_add(&card->dev);
-       if (ret)
-               return ret;
-@@ -380,6 +383,7 @@ void mmc_remove_card(struct mmc_card *ca
-                               mmc_hostname(card->host), card->rca);
-               }
-               device_del(&card->dev);
-+              of_node_put(card->dev.of_node);
-       }
-       put_device(&card->dev);
---- a/drivers/mmc/core/core.c
-+++ b/drivers/mmc/core/core.c
-@@ -1231,6 +1231,34 @@ EXPORT_SYMBOL(mmc_of_parse_voltage);
- #endif /* CONFIG_OF */
-+static int mmc_of_get_func_num(struct device_node *node)
-+{
-+      u32 reg;
-+      int ret;
-+
-+      ret = of_property_read_u32(node, "reg", &reg);
-+      if (ret < 0)
-+              return ret;
-+
-+      return reg;
-+}
-+
-+struct device_node *mmc_of_find_child_device(struct mmc_host *host,
-+              unsigned func_num)
-+{
-+      struct device_node *node;
-+
-+      if (!host->parent || !host->parent->of_node)
-+              return NULL;
-+
-+      for_each_child_of_node(host->parent->of_node, node) {
-+              if (mmc_of_get_func_num(node) == func_num)
-+                      return node;
-+      }
-+
-+      return NULL;
-+}
-+
- #ifdef CONFIG_REGULATOR
- /**
---- a/drivers/mmc/core/core.h
-+++ b/drivers/mmc/core/core.h
-@@ -32,6 +32,9 @@ struct mmc_bus_ops {
- void mmc_attach_bus(struct mmc_host *host, const struct mmc_bus_ops *ops);
- void mmc_detach_bus(struct mmc_host *host);
-+struct device_node *mmc_of_find_child_device(struct mmc_host *host,
-+              unsigned func_num);
-+
- void mmc_init_erase(struct mmc_card *card);
- void mmc_set_chip_select(struct mmc_host *host, int mode);
---- a/drivers/mmc/core/sdio_bus.c
-+++ b/drivers/mmc/core/sdio_bus.c
-@@ -22,7 +22,9 @@
- #include <linux/mmc/card.h>
- #include <linux/mmc/host.h>
- #include <linux/mmc/sdio_func.h>
-+#include <linux/of.h>
-+#include "core.h"
- #include "sdio_cis.h"
- #include "sdio_bus.h"
-@@ -303,6 +305,13 @@ static void sdio_acpi_set_handle(struct
- static inline void sdio_acpi_set_handle(struct sdio_func *func) {}
- #endif
-+static void sdio_set_of_node(struct sdio_func *func)
-+{
-+      struct mmc_host *host = func->card->host;
-+
-+      func->dev.of_node = mmc_of_find_child_device(host, func->num);
-+}
-+
- /*
-  * Register a new SDIO function with the driver model.
-  */
-@@ -312,6 +321,7 @@ int sdio_add_func(struct sdio_func *func
-       dev_set_name(&func->dev, "%s:%d", mmc_card_id(func->card), func->num);
-+      sdio_set_of_node(func);
-       sdio_acpi_set_handle(func);
-       ret = device_add(&func->dev);
-       if (ret == 0) {
-@@ -335,6 +345,7 @@ void sdio_remove_func(struct sdio_func *
-       dev_pm_domain_detach(&func->dev, false);
-       device_del(&func->dev);
-+      of_node_put(func->dev.of_node);
-       put_device(&func->dev);
- }
diff --git a/target/linux/sunxi/patches-3.18/201-dt-sun7i-add-oob-irq-to-bcm-sdio-wifi.patch b/target/linux/sunxi/patches-3.18/201-dt-sun7i-add-oob-irq-to-bcm-sdio-wifi.patch
deleted file mode 100644 (file)
index e2cfeb7..0000000
+++ /dev/null
@@ -1,64 +0,0 @@
-From e4127db9b980a5684c537d9010ed2aaa05a1e79a Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sat, 24 May 2014 20:53:49 +0200
-Subject: [PATCH] ARM: dts: sun7i: Add OOB irq support to boards with broadcom
- sdio wifi
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 11 +++++++++++
- arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts  | 11 +++++++++++
- 2 files changed, 22 insertions(+)
-
---- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
-@@ -31,12 +31,23 @@
-               };
-               mmc3: mmc@01c12000 {
-+                      #address-cells = <1>;
-+                      #size-cells = <0>;
-+
-                       pinctrl-names = "default";
-                       pinctrl-0 = <&mmc3_pins_a>;
-                       vmmc-supply = <&reg_vmmc3>;
-                       bus-width = <4>;
-                       non-removable;
-                       status = "okay";
-+
-+                      brcmf: bcrmf@1 {
-+                              reg = <1>;
-+                              compatible = "brcm,bcm4329-fmac";
-+                              interrupt-parent = <&pio>;
-+                              interrupts = <10 8>; /* PH10 / EINT10 */
-+                              interrupt-names = "host-wake";
-+                      };
-               };
-               usbphy: phy@01c13400 {
---- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
-@@ -29,12 +29,23 @@
-               };
-               mmc3: mmc@01c12000 {
-+                      #address-cells = <1>;
-+                      #size-cells = <0>;
-+
-                       pinctrl-names = "default";
-                       pinctrl-0 = <&mmc3_pins_a>;
-                       vmmc-supply = <&reg_vmmc3>;
-                       bus-width = <4>;
-                       non-removable;
-                       status = "okay";
-+
-+                      brcmf: bcrmf@1 {
-+                              reg = <1>;
-+                              compatible = "brcm,bcm4329-fmac";
-+                              interrupt-parent = <&pio>;
-+                              interrupts = <10 8>; /* PH10 / EINT10 */
-+                              interrupt-names = "host-wake";
-+                      };
-               };
-               usbphy: phy@01c13400 {
diff --git a/target/linux/sunxi/patches-3.18/202-dt-sun7i-add-bluetooth-to-cubietruck.patch b/target/linux/sunxi/patches-3.18/202-dt-sun7i-add-bluetooth-to-cubietruck.patch
deleted file mode 100644 (file)
index 9c0d969..0000000
+++ /dev/null
@@ -1,73 +0,0 @@
-From c6e2b7dad39a7887f935458d1c8de84db06243e1 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Thu, 26 Dec 2013 17:15:47 +0800
-Subject: [PATCH] ARM: dts: sun7i: add bluetooth module to CubieTruck DTS
-
-The CubieTruck has an AMPAK AP6210 WiFi+Bluetooth module. The
-Bluetooth part is a BCM20710 IC connected to UART2 in the A20
-SoC. The IC also takes a 32.768 KHz low power clock input, a power
-enable signal and a wake signal via GPIO.
-
-The Bluetooth module supports out-of-band interrupt signaling via
-GPIO, but this is not supported in this patch.
----
- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 36 ++++++++++++++++++++++++++++++
- 1 file changed, 36 insertions(+)
-
---- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
-@@ -103,6 +103,20 @@
-                               allwinner,drive = <0>;
-                               allwinner,pull = <0>;
-                       };
-+
-+                      bt_pwr_pin: bt_pwr_pin@0 {
-+                              allwinner,pins = "PH18";
-+                              allwinner,function = "gpio_out";
-+                              allwinner,drive = <0>;
-+                              allwinner,pull = <0>;
-+                      };
-+
-+                      bt_wake_pin: bt_wake_pin@0 {
-+                              allwinner,pins = "PH24";
-+                              allwinner,function = "gpio_out";
-+                              allwinner,drive = <0>;
-+                              allwinner,pull = <0>;
-+                      };
-               };
-               pwm: pwm@01c20e00 {
-@@ -123,6 +137,12 @@
-                       status = "okay";
-               };
-+              uart2: serial@01c28800 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&uart2_pins_a>;
-+                      status = "okay";
-+              };
-+
-               i2c0: i2c@01c2ac00 {
-                       pinctrl-names = "default";
-                       pinctrl-0 = <&i2c0_pins_a>;
-@@ -214,4 +234,20 @@
-               enable-active-high;
-               gpio = <&pio 7 9 0>;
-       };
-+
-+      rfkill-switches {
-+              compatible = "simple-bus";
-+              pinctrl-names = "default";
-+
-+              rfkill_bt {
-+                      compatible = "rfkill-gpio";
-+                      pinctrl-0 = <&bt_pwr_pin>, <&clk_out_a_pins_a>;
-+                      rfkill-name = "bt";
-+                      rfkill-type = <2>;
-+                      bt_shutdown-gpios = <0>, <&pio 7 18 0>; /* PH18 */
-+                      bt_reset-gpios = <&pio 7 24 0>; /* PH24 */
-+                      clocks = <&clk_out_a>;
-+                      clock-frequency = <32768>;
-+              };
-+      };
- };
diff --git a/target/linux/sunxi/patches-3.18/270-dt-sun7i-add-ss-to-a20.patch b/target/linux/sunxi/patches-3.18/270-dt-sun7i-add-ss-to-a20.patch
deleted file mode 100644 (file)
index f03e2d9..0000000
+++ /dev/null
@@ -1,17 +0,0 @@
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -577,6 +577,14 @@
-                       status = "disabled";
-               };
-+              crypto: crypto-engine@01c15000 {
-+                      compatible = "allwinner,sun7i-a20-crypto";
-+                      reg = <0x01c15000 0x1000>;
-+                      interrupts = <0 86 4>;
-+                      clocks = <&ahb_gates 5>, <&ss_clk>;
-+                      clock-names = "ahb", "mod";
-+              };
-+
-               spi2: spi@01c17000 {
-                       compatible = "allwinner,sun4i-a10-spi";
-                       reg = <0x01c17000 0x1000>;
diff --git a/target/linux/sunxi/patches-3.18/271-crypto-add-ss.patch b/target/linux/sunxi/patches-3.18/271-crypto-add-ss.patch
deleted file mode 100644 (file)
index 0788c6f..0000000
+++ /dev/null
@@ -1,1493 +0,0 @@
---- a/drivers/crypto/Kconfig
-+++ b/drivers/crypto/Kconfig
-@@ -437,4 +437,21 @@ config CRYPTO_DEV_QCE
-         hardware. To compile this driver as a module, choose M here. The
-         module will be called qcrypto.
-+config CRYPTO_DEV_SUNXI_SS
-+      tristate "Support for Allwinner Security System cryptographic accelerator"
-+      depends on ARCH_SUNXI
-+      select CRYPTO_MD5
-+      select CRYPTO_SHA1
-+      select CRYPTO_AES
-+      select CRYPTO_DES
-+      select CRYPTO_BLKCIPHER
-+      help
-+        Some Allwinner SoC have a crypto accelerator named
-+        Security System. Select this if you want to use it.
-+        The Security System handle AES/DES/3DES ciphers in CBC mode
-+        and SHA1 and MD5 hash algorithms.
-+
-+        To compile this driver as a module, choose M here: the module
-+        will be called sunxi-ss.
-+
- endif # CRYPTO_HW
---- a/drivers/crypto/Makefile
-+++ b/drivers/crypto/Makefile
-@@ -25,3 +25,4 @@ obj-$(CONFIG_CRYPTO_DEV_TALITOS) += tali
- obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
- obj-$(CONFIG_CRYPTO_DEV_QAT) += qat/
- obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/
-+obj-$(CONFIG_CRYPTO_DEV_SUNXI_SS) += sunxi-ss/
---- /dev/null
-+++ b/drivers/crypto/sunxi-ss/Makefile
-@@ -0,0 +1,2 @@
-+obj-$(CONFIG_CRYPTO_DEV_SUNXI_SS) += sunxi-ss.o
-+sunxi-ss-y += sunxi-ss-core.o sunxi-ss-hash.o sunxi-ss-cipher.o
---- /dev/null
-+++ b/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c
-@@ -0,0 +1,489 @@
-+/*
-+ * sunxi-ss-cipher.c - hardware cryptographic accelerator for Allwinner A20 SoC
-+ *
-+ * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie@gmail.com>
-+ *
-+ * This file add support for AES cipher with 128,192,256 bits
-+ * keysize in CBC mode.
-+ * Add support also for DES and 3DES in CBC mode.
-+ *
-+ * You could find the datasheet in Documentation/arm/sunxi/README
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+#include "sunxi-ss.h"
-+
-+extern struct sunxi_ss_ctx *ss;
-+
-+static int sunxi_ss_cipher(struct ablkcipher_request *areq, u32 mode)
-+{
-+      struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
-+      struct sunxi_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
-+      const char *cipher_type;
-+
-+      if (areq->nbytes == 0)
-+              return 0;
-+
-+      if (areq->info == NULL) {
-+              dev_err(ss->dev, "ERROR: Empty IV\n");
-+              return -EINVAL;
-+      }
-+
-+      if (areq->src == NULL || areq->dst == NULL) {
-+              dev_err(ss->dev, "ERROR: Some SGs are NULL\n");
-+              return -EINVAL;
-+      }
-+
-+      cipher_type = crypto_tfm_alg_name(crypto_ablkcipher_tfm(tfm));
-+
-+      if (strcmp("cbc(aes)", cipher_type) == 0) {
-+              mode |= SS_OP_AES | SS_CBC | SS_ENABLED | op->keymode;
-+              return sunxi_ss_aes_poll(areq, mode);
-+      }
-+
-+      if (strcmp("cbc(des)", cipher_type) == 0) {
-+              mode |= SS_OP_DES | SS_CBC | SS_ENABLED | op->keymode;
-+              return sunxi_ss_des_poll(areq, mode);
-+      }
-+
-+      if (strcmp("cbc(des3_ede)", cipher_type) == 0) {
-+              mode |= SS_OP_3DES | SS_CBC | SS_ENABLED | op->keymode;
-+              return sunxi_ss_des_poll(areq, mode);
-+      }
-+
-+      dev_err(ss->dev, "ERROR: Cipher %s not handled\n", cipher_type);
-+      return -EINVAL;
-+}
-+
-+int sunxi_ss_cipher_encrypt(struct ablkcipher_request *areq)
-+{
-+      return sunxi_ss_cipher(areq, SS_ENCRYPTION);
-+}
-+
-+int sunxi_ss_cipher_decrypt(struct ablkcipher_request *areq)
-+{
-+      return sunxi_ss_cipher(areq, SS_DECRYPTION);
-+}
-+
-+int sunxi_ss_cipher_init(struct crypto_tfm *tfm)
-+{
-+      struct sunxi_tfm_ctx *op = crypto_tfm_ctx(tfm);
-+
-+      memset(op, 0, sizeof(struct sunxi_tfm_ctx));
-+      return 0;
-+}
-+
-+/*
-+ * Optimized function for the case where we have only one SG,
-+ * so we can use kmap_atomic
-+ */
-+static int sunxi_ss_aes_poll_atomic(struct ablkcipher_request *areq)
-+{
-+      u32 spaces;
-+      struct scatterlist *in_sg = areq->src;
-+      struct scatterlist *out_sg = areq->dst;
-+      void *src_addr;
-+      void *dst_addr;
-+      unsigned int ileft = areq->nbytes;
-+      unsigned int oleft = areq->nbytes;
-+      unsigned int todo;
-+      u32 *src32;
-+      u32 *dst32;
-+      u32 rx_cnt = 32;
-+      u32 tx_cnt = 0;
-+      int i;
-+
-+      src_addr = kmap_atomic(sg_page(in_sg)) + in_sg->offset;
-+      if (src_addr == NULL) {
-+              dev_err(ss->dev, "kmap_atomic error for src SG\n");
-+              writel(0, ss->base + SS_CTL);
-+              mutex_unlock(&ss->lock);
-+              return -EINVAL;
-+      }
-+
-+      dst_addr = kmap_atomic(sg_page(out_sg)) + out_sg->offset;
-+      if (dst_addr == NULL) {
-+              dev_err(ss->dev, "kmap_atomic error for dst SG\n");
-+              writel(0, ss->base + SS_CTL);
-+              kunmap_atomic(src_addr);
-+              mutex_unlock(&ss->lock);
-+              return -EINVAL;
-+      }
-+
-+      src32 = (u32 *)src_addr;
-+      dst32 = (u32 *)dst_addr;
-+      ileft = areq->nbytes / 4;
-+      oleft = areq->nbytes / 4;
-+      i = 0;
-+      do {
-+              if (ileft > 0 && rx_cnt > 0) {
-+                      todo = min(rx_cnt, ileft);
-+                      ileft -= todo;
-+                      do {
-+                              writel_relaxed(*src32++,
-+                                              ss->base +
-+                                              SS_RXFIFO);
-+                              todo--;
-+                      } while (todo > 0);
-+              }
-+              if (tx_cnt > 0) {
-+                      todo = min(tx_cnt, oleft);
-+                      oleft -= todo;
-+                      do {
-+                              *dst32++ = readl_relaxed(ss->base +
-+                                              SS_TXFIFO);
-+                              todo--;
-+                      } while (todo > 0);
-+              }
-+              spaces = readl_relaxed(ss->base + SS_FCSR);
-+              rx_cnt = SS_RXFIFO_SPACES(spaces);
-+              tx_cnt = SS_TXFIFO_SPACES(spaces);
-+      } while (oleft > 0);
-+      writel(0, ss->base + SS_CTL);
-+      kunmap_atomic(src_addr);
-+      kunmap_atomic(dst_addr);
-+      mutex_unlock(&ss->lock);
-+      return 0;
-+}
-+
-+int sunxi_ss_aes_poll(struct ablkcipher_request *areq, u32 mode)
-+{
-+      u32 spaces;
-+      struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
-+      struct sunxi_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
-+      unsigned int ivsize = crypto_ablkcipher_ivsize(tfm);
-+      /* when activating SS, the default FIFO space is 32 */
-+      u32 rx_cnt = 32;
-+      u32 tx_cnt = 0;
-+      u32 v;
-+      int i;
-+      struct scatterlist *in_sg = areq->src;
-+      struct scatterlist *out_sg = areq->dst;
-+      void *src_addr;
-+      void *dst_addr;
-+      unsigned int ileft = areq->nbytes;
-+      unsigned int oleft = areq->nbytes;
-+      unsigned int sgileft = areq->src->length;
-+      unsigned int sgoleft = areq->dst->length;
-+      unsigned int todo;
-+      u32 *src32;
-+      u32 *dst32;
-+
-+      mutex_lock(&ss->lock);
-+
-+      for (i = 0; i < op->keylen; i += 4)
-+              writel(*(op->key + i/4), ss->base + SS_KEY0 + i);
-+
-+      if (areq->info != NULL) {
-+              for (i = 0; i < 4 && i < ivsize / 4; i++) {
-+                      v = *(u32 *)(areq->info + i * 4);
-+                      writel(v, ss->base + SS_IV0 + i * 4);
-+              }
-+      }
-+      writel(mode, ss->base + SS_CTL);
-+
-+      /* If we have only one SG, we can use kmap_atomic */
-+      if (sg_next(in_sg) == NULL && sg_next(out_sg) == NULL)
-+              return sunxi_ss_aes_poll_atomic(areq);
-+
-+      /*
-+       * If we have more than one SG, we cannot use kmap_atomic since
-+       * we hold the mapping too long
-+       */
-+      src_addr = kmap(sg_page(in_sg)) + in_sg->offset;
-+      if (src_addr == NULL) {
-+              dev_err(ss->dev, "KMAP error for src SG\n");
-+              mutex_unlock(&ss->lock);
-+              return -EINVAL;
-+      }
-+      dst_addr = kmap(sg_page(out_sg)) + out_sg->offset;
-+      if (dst_addr == NULL) {
-+              kunmap(sg_page(in_sg));
-+              dev_err(ss->dev, "KMAP error for dst SG\n");
-+              mutex_unlock(&ss->lock);
-+              return -EINVAL;
-+      }
-+      src32 = (u32 *)src_addr;
-+      dst32 = (u32 *)dst_addr;
-+      ileft = areq->nbytes / 4;
-+      oleft = areq->nbytes / 4;
-+      sgileft = in_sg->length / 4;
-+      sgoleft = out_sg->length / 4;
-+      do {
-+              spaces = readl_relaxed(ss->base + SS_FCSR);
-+              rx_cnt = SS_RXFIFO_SPACES(spaces);
-+              tx_cnt = SS_TXFIFO_SPACES(spaces);
-+              todo = min3(rx_cnt, ileft, sgileft);
-+              if (todo > 0) {
-+                      ileft -= todo;
-+                      sgileft -= todo;
-+              }
-+              while (todo > 0) {
-+                      writel_relaxed(*src32++, ss->base + SS_RXFIFO);
-+                      todo--;
-+              }
-+              if (in_sg != NULL && sgileft == 0 && ileft > 0) {
-+                      kunmap(sg_page(in_sg));
-+                      in_sg = sg_next(in_sg);
-+                      while (in_sg != NULL && in_sg->length == 0)
-+                              in_sg = sg_next(in_sg);
-+                      if (in_sg != NULL && ileft > 0) {
-+                              src_addr = kmap(sg_page(in_sg)) + in_sg->offset;
-+                              if (src_addr == NULL) {
-+                                      dev_err(ss->dev, "ERROR: KMAP for src SG\n");
-+                                      mutex_unlock(&ss->lock);
-+                                      return -EINVAL;
-+                              }
-+                              src32 = src_addr;
-+                              sgileft = in_sg->length / 4;
-+                      }
-+              }
-+              /* do not test oleft since when oleft == 0 we have finished */
-+              todo = min3(tx_cnt, oleft, sgoleft);
-+              if (todo > 0) {
-+                      oleft -= todo;
-+                      sgoleft -= todo;
-+              }
-+              while (todo > 0) {
-+                      *dst32++ = readl_relaxed(ss->base + SS_TXFIFO);
-+                      todo--;
-+              }
-+              if (out_sg != NULL && sgoleft == 0 && oleft >= 0) {
-+                      kunmap(sg_page(out_sg));
-+                      out_sg = sg_next(out_sg);
-+                      while (out_sg != NULL && out_sg->length == 0)
-+                              out_sg = sg_next(out_sg);
-+                      if (out_sg != NULL && oleft > 0) {
-+                              dst_addr = kmap(sg_page(out_sg)) +
-+                                      out_sg->offset;
-+                              if (dst_addr == NULL) {
-+                                      dev_err(ss->dev, "KMAP error\n");
-+                                      mutex_unlock(&ss->lock);
-+                                      return -EINVAL;
-+                              }
-+                              dst32 = dst_addr;
-+                              sgoleft = out_sg->length / 4;
-+                      }
-+              }
-+      } while (oleft > 0);
-+
-+      writel_relaxed(0, ss->base + SS_CTL);
-+      mutex_unlock(&ss->lock);
-+      return 0;
-+}
-+
-+/*
-+ * Pure CPU way of doing DES/3DES with SS
-+ * Since DES and 3DES SGs could be smaller than 4 bytes, I use sg_copy_to_buffer
-+ * for "linearize" them.
-+ * The problem with that is that I alloc (2 x areq->nbytes) for buf_in/buf_out
-+ * TODO: change this system, I need to support other mode than CBC where len
-+ * is not a multiple of 4 and the hack of linearize use too much memory
-+ * SGsrc -> buf_in -> SS -> buf_out -> SGdst
-+ */
-+int sunxi_ss_des_poll(struct ablkcipher_request *areq, u32 mode)
-+{
-+      u32 value, spaces;
-+      size_t nb_in_sg_tx, nb_in_sg_rx;
-+      size_t ir, it;
-+      struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
-+      struct sunxi_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
-+      unsigned int ivsize = crypto_ablkcipher_ivsize(tfm);
-+      u32 tx_cnt = 0;
-+      u32 rx_cnt = 0;
-+      u32 v;
-+      int i;
-+      int no_chunk = 1;
-+      struct scatterlist *in_sg = areq->src;
-+      struct scatterlist *out_sg = areq->dst;
-+
-+      /*
-+       * if we have only SGs with size multiple of 4,
-+       * we can use the SS AES function
-+       */
-+      while (in_sg != NULL && no_chunk == 1) {
-+              if ((in_sg->length % 4) != 0)
-+                      no_chunk = 0;
-+              in_sg = sg_next(in_sg);
-+      }
-+      while (out_sg != NULL && no_chunk == 1) {
-+              if ((out_sg->length % 4) != 0)
-+                      no_chunk = 0;
-+              out_sg = sg_next(out_sg);
-+      }
-+
-+      if (no_chunk == 1)
-+              return sunxi_ss_aes_poll(areq, mode);
-+
-+      in_sg = areq->src;
-+      out_sg = areq->dst;
-+
-+      nb_in_sg_rx = sg_nents(in_sg);
-+      nb_in_sg_tx = sg_nents(out_sg);
-+
-+      /*
-+       * buf_in and buf_out are allocated only one time
-+       * then we keep the buffer until driver end
-+       * the allocation can only grow more
-+       * we do not reduce it for simplification
-+       */
-+      mutex_lock(&ss->bufin_lock);
-+      if (ss->buf_in == NULL) {
-+              ss->buf_in = kmalloc(areq->nbytes, GFP_KERNEL);
-+              ss->buf_in_size = areq->nbytes;
-+      } else {
-+              if (areq->nbytes > ss->buf_in_size) {
-+                      kfree(ss->buf_in);
-+                      ss->buf_in = kmalloc(areq->nbytes, GFP_KERNEL);
-+                      ss->buf_in_size = areq->nbytes;
-+              }
-+      }
-+      if (ss->buf_in == NULL) {
-+              ss->buf_in_size = 0;
-+              mutex_unlock(&ss->bufin_lock);
-+              dev_err(ss->dev, "Unable to allocate pages.\n");
-+              return -ENOMEM;
-+      }
-+      mutex_lock(&ss->bufout_lock);
-+      if (ss->buf_out == NULL) {
-+              ss->buf_out = kmalloc(areq->nbytes, GFP_KERNEL);
-+              if (ss->buf_out == NULL) {
-+                      ss->buf_out_size = 0;
-+                      mutex_unlock(&ss->bufin_lock);
-+                      mutex_unlock(&ss->bufout_lock);
-+                      dev_err(ss->dev, "Unable to allocate pages.\n");
-+                      return -ENOMEM;
-+              }
-+              ss->buf_out_size = areq->nbytes;
-+      } else {
-+              if (areq->nbytes > ss->buf_out_size) {
-+                      kfree(ss->buf_out);
-+                      ss->buf_out = kmalloc(areq->nbytes, GFP_KERNEL);
-+                      if (ss->buf_out == NULL) {
-+                              ss->buf_out_size = 0;
-+                              mutex_unlock(&ss->bufin_lock);
-+                              mutex_unlock(&ss->bufout_lock);
-+                              dev_err(ss->dev, "Unable to allocate pages.\n");
-+                              return -ENOMEM;
-+                      }
-+                      ss->buf_out_size = areq->nbytes;
-+              }
-+      }
-+
-+      sg_copy_to_buffer(areq->src, nb_in_sg_rx, ss->buf_in, areq->nbytes);
-+
-+      ir = 0;
-+      it = 0;
-+      mutex_lock(&ss->lock);
-+
-+      for (i = 0; i < op->keylen; i += 4)
-+              writel(*(op->key + i/4), ss->base + SS_KEY0 + i);
-+      if (areq->info != NULL) {
-+              for (i = 0; i < 4 && i < ivsize / 4; i++) {
-+                      v = *(u32 *)(areq->info + i * 4);
-+                      writel(v, ss->base + SS_IV0 + i * 4);
-+              }
-+      }
-+      writel(mode, ss->base + SS_CTL);
-+
-+      do {
-+              if (rx_cnt == 0 || tx_cnt == 0) {
-+                      spaces = readl(ss->base + SS_FCSR);
-+                      rx_cnt = SS_RXFIFO_SPACES(spaces);
-+                      tx_cnt = SS_TXFIFO_SPACES(spaces);
-+              }
-+              if (rx_cnt > 0 && ir < areq->nbytes) {
-+                      do {
-+                              value = *(u32 *)(ss->buf_in + ir);
-+                              writel(value, ss->base + SS_RXFIFO);
-+                              ir += 4;
-+                              rx_cnt--;
-+                      } while (rx_cnt > 0 && ir < areq->nbytes);
-+              }
-+              if (tx_cnt > 0 && it < areq->nbytes) {
-+                      do {
-+                              value = readl(ss->base + SS_TXFIFO);
-+                              *(u32 *)(ss->buf_out + it) = value;
-+                              it += 4;
-+                              tx_cnt--;
-+                      } while (tx_cnt > 0 && it < areq->nbytes);
-+              }
-+              if (ir == areq->nbytes) {
-+                      mutex_unlock(&ss->bufin_lock);
-+                      ir++;
-+              }
-+      } while (it < areq->nbytes);
-+
-+      writel(0, ss->base + SS_CTL);
-+      mutex_unlock(&ss->lock);
-+
-+      /*
-+       * a simple optimization, since we dont need the hardware for this copy
-+       * we release the lock and do the copy. With that we gain 5/10% perf
-+       */
-+      sg_copy_from_buffer(areq->dst, nb_in_sg_tx, ss->buf_out, areq->nbytes);
-+
-+      mutex_unlock(&ss->bufout_lock);
-+      return 0;
-+}
-+
-+/* check and set the AES key, prepare the mode to be used */
-+int sunxi_ss_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
-+              unsigned int keylen)
-+{
-+      struct sunxi_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
-+
-+      switch (keylen) {
-+      case 128 / 8:
-+              op->keymode = SS_AES_128BITS;
-+              break;
-+      case 192 / 8:
-+              op->keymode = SS_AES_192BITS;
-+              break;
-+      case 256 / 8:
-+              op->keymode = SS_AES_256BITS;
-+              break;
-+      default:
-+              dev_err(ss->dev, "ERROR: Invalid keylen %u\n", keylen);
-+              crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
-+              return -EINVAL;
-+      }
-+      op->keylen = keylen;
-+      memcpy(op->key, key, keylen);
-+      return 0;
-+}
-+
-+/* check and set the DES key, prepare the mode to be used */
-+int sunxi_ss_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
-+              unsigned int keylen)
-+{
-+      struct sunxi_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
-+
-+      if (keylen != DES_KEY_SIZE) {
-+              dev_err(ss->dev, "Invalid keylen %u\n", keylen);
-+              crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
-+              return -EINVAL;
-+      }
-+      op->keylen = keylen;
-+      memcpy(op->key, key, keylen);
-+      return 0;
-+}
-+
-+/* check and set the 3DES key, prepare the mode to be used */
-+int sunxi_ss_des3_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
-+              unsigned int keylen)
-+{
-+      struct sunxi_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
-+
-+      if (keylen != 3 * DES_KEY_SIZE) {
-+              dev_err(ss->dev, "Invalid keylen %u\n", keylen);
-+              crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
-+              return -EINVAL;
-+      }
-+      op->keylen = keylen;
-+      memcpy(op->key, key, keylen);
-+      return 0;
-+}
---- /dev/null
-+++ b/drivers/crypto/sunxi-ss/sunxi-ss-core.c
-@@ -0,0 +1,318 @@
-+/*
-+ * sunxi-ss-core.c - hardware cryptographic accelerator for Allwinner A20 SoC
-+ *
-+ * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie@gmail.com>
-+ *
-+ * Core file which registers crypto algorithms supported by the SS.
-+ *
-+ * You could find a link for the datasheet in Documentation/arm/sunxi/README
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+#include <linux/clk.h>
-+#include <linux/crypto.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <crypto/scatterwalk.h>
-+#include <linux/scatterlist.h>
-+#include <linux/interrupt.h>
-+#include <linux/delay.h>
-+
-+#include "sunxi-ss.h"
-+
-+struct sunxi_ss_ctx *ss;
-+
-+/*
-+ * General notes for whole driver:
-+ *
-+ * After each request the device must be disabled with a write of 0 in SS_CTL
-+ *
-+ * For performance reason, we use writel_relaxed/read_relaxed for all
-+ * operations on RX and TX FIFO and also SS_FCSR.
-+ * Excepts for the last write on TX FIFO.
-+ * For all other registers, we use writel/readl.
-+ * See http://permalink.gmane.org/gmane.linux.ports.arm.kernel/117644
-+ * and http://permalink.gmane.org/gmane.linux.ports.arm.kernel/117640
-+ */
-+
-+static struct ahash_alg sunxi_md5_alg = {
-+      .init = sunxi_hash_init,
-+      .update = sunxi_hash_update,
-+      .final = sunxi_hash_final,
-+      .finup = sunxi_hash_finup,
-+      .digest = sunxi_hash_digest,
-+      .halg = {
-+              .digestsize = MD5_DIGEST_SIZE,
-+              .base = {
-+                      .cra_name = "md5",
-+                      .cra_driver_name = "md5-sunxi-ss",
-+                      .cra_priority = 300,
-+                      .cra_alignmask = 3,
-+                      .cra_flags = CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
-+                      .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
-+                      .cra_ctxsize = sizeof(struct sunxi_req_ctx),
-+                      .cra_module = THIS_MODULE,
-+                      .cra_type = &crypto_ahash_type,
-+                      .cra_init = sunxi_hash_crainit
-+              }
-+      }
-+};
-+
-+static struct ahash_alg sunxi_sha1_alg = {
-+      .init = sunxi_hash_init,
-+      .update = sunxi_hash_update,
-+      .final = sunxi_hash_final,
-+      .finup = sunxi_hash_finup,
-+      .digest = sunxi_hash_digest,
-+      .halg = {
-+              .digestsize = SHA1_DIGEST_SIZE,
-+              .base = {
-+                      .cra_name = "sha1",
-+                      .cra_driver_name = "sha1-sunxi-ss",
-+                      .cra_priority = 300,
-+                      .cra_alignmask = 3,
-+                      .cra_flags = CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
-+                      .cra_blocksize = SHA1_BLOCK_SIZE,
-+                      .cra_ctxsize = sizeof(struct sunxi_req_ctx),
-+                      .cra_module = THIS_MODULE,
-+                      .cra_type = &crypto_ahash_type,
-+                      .cra_init = sunxi_hash_crainit
-+              }
-+      }
-+};
-+
-+static struct crypto_alg sunxi_cipher_algs[] = {
-+{
-+      .cra_name = "cbc(aes)",
-+      .cra_driver_name = "cbc-aes-sunxi-ss",
-+      .cra_priority = 300,
-+      .cra_blocksize = AES_BLOCK_SIZE,
-+      .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
-+      .cra_ctxsize = sizeof(struct sunxi_tfm_ctx),
-+      .cra_module = THIS_MODULE,
-+      .cra_alignmask = 3,
-+      .cra_type = &crypto_ablkcipher_type,
-+      .cra_init = sunxi_ss_cipher_init,
-+      .cra_u = {
-+              .ablkcipher = {
-+                      .min_keysize    = AES_MIN_KEY_SIZE,
-+                      .max_keysize    = AES_MAX_KEY_SIZE,
-+                      .ivsize         = AES_BLOCK_SIZE,
-+                      .setkey         = sunxi_ss_aes_setkey,
-+                      .encrypt        = sunxi_ss_cipher_encrypt,
-+                      .decrypt        = sunxi_ss_cipher_decrypt,
-+              }
-+      }
-+}, {
-+      .cra_name = "cbc(des)",
-+      .cra_driver_name = "cbc-des-sunxi-ss",
-+      .cra_priority = 300,
-+      .cra_blocksize = DES_BLOCK_SIZE,
-+      .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
-+      .cra_ctxsize = sizeof(struct sunxi_req_ctx),
-+      .cra_module = THIS_MODULE,
-+      .cra_alignmask = 3,
-+      .cra_type = &crypto_ablkcipher_type,
-+      .cra_init = sunxi_ss_cipher_init,
-+      .cra_u.ablkcipher = {
-+              .min_keysize    = DES_KEY_SIZE,
-+              .max_keysize    = DES_KEY_SIZE,
-+              .ivsize         = DES_BLOCK_SIZE,
-+              .setkey         = sunxi_ss_des_setkey,
-+              .encrypt        = sunxi_ss_cipher_encrypt,
-+              .decrypt        = sunxi_ss_cipher_decrypt,
-+      }
-+}, {
-+      .cra_name = "cbc(des3_ede)",
-+      .cra_driver_name = "cbc-des3-sunxi-ss",
-+      .cra_priority = 300,
-+      .cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+      .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
-+      .cra_ctxsize = sizeof(struct sunxi_req_ctx),
-+      .cra_module = THIS_MODULE,
-+      .cra_alignmask = 3,
-+      .cra_type = &crypto_ablkcipher_type,
-+      .cra_init = sunxi_ss_cipher_init,
-+      .cra_u.ablkcipher = {
-+              .min_keysize    = DES3_EDE_KEY_SIZE,
-+              .max_keysize    = DES3_EDE_KEY_SIZE,
-+              .ivsize         = DES3_EDE_BLOCK_SIZE,
-+              .setkey         = sunxi_ss_des3_setkey,
-+              .encrypt        = sunxi_ss_cipher_encrypt,
-+              .decrypt        = sunxi_ss_cipher_decrypt,
-+      }
-+}
-+};
-+
-+static int sunxi_ss_probe(struct platform_device *pdev)
-+{
-+      struct resource *res;
-+      u32 v;
-+      int err;
-+      unsigned long cr;
-+      const unsigned long cr_ahb = 24 * 1000 * 1000;
-+      const unsigned long cr_mod = 150 * 1000 * 1000;
-+
-+      if (!pdev->dev.of_node)
-+              return -ENODEV;
-+
-+      ss = devm_kzalloc(&pdev->dev, sizeof(*ss), GFP_KERNEL);
-+      if (ss == NULL)
-+              return -ENOMEM;
-+
-+      res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+      ss->base = devm_ioremap_resource(&pdev->dev, res);
-+      if (IS_ERR(ss->base)) {
-+              dev_err(&pdev->dev, "Cannot request MMIO\n");
-+              return PTR_ERR(ss->base);
-+      }
-+
-+      ss->ssclk = devm_clk_get(&pdev->dev, "mod");
-+      if (IS_ERR(ss->ssclk)) {
-+              err = PTR_ERR(ss->ssclk);
-+              dev_err(&pdev->dev, "Cannot get SS clock err=%d\n", err);
-+              return err;
-+      }
-+      dev_dbg(&pdev->dev, "clock ss acquired\n");
-+
-+      ss->busclk = devm_clk_get(&pdev->dev, "ahb");
-+      if (IS_ERR(ss->busclk)) {
-+              err = PTR_ERR(ss->busclk);
-+              dev_err(&pdev->dev, "Cannot get AHB SS clock err=%d\n", err);
-+              return err;
-+      }
-+      dev_dbg(&pdev->dev, "clock ahb_ss acquired\n");
-+
-+      /* Enable both clocks */
-+      err = clk_prepare_enable(ss->busclk);
-+      if (err != 0) {
-+              dev_err(&pdev->dev, "Cannot prepare_enable busclk\n");
-+              return err;
-+      }
-+      err = clk_prepare_enable(ss->ssclk);
-+      if (err != 0) {
-+              dev_err(&pdev->dev, "Cannot prepare_enable ssclk\n");
-+              clk_disable_unprepare(ss->busclk);
-+              return err;
-+      }
-+
-+      /*
-+       * Check that clock have the correct rates gived in the datasheet
-+       * Try to set the clock to the maximum allowed
-+       */
-+      err = clk_set_rate(ss->ssclk, cr_mod);
-+      if (err != 0) {
-+              dev_err(&pdev->dev, "Cannot set clock rate to ssclk\n");
-+              clk_disable_unprepare(ss->ssclk);
-+              clk_disable_unprepare(ss->busclk);
-+              return err;
-+      }
-+
-+      cr = clk_get_rate(ss->busclk);
-+      if (cr >= cr_ahb)
-+              dev_dbg(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
-+                              cr, cr / 1000000, cr_ahb);
-+      else
-+              dev_warn(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
-+                              cr, cr / 1000000, cr_ahb);
-+
-+      cr = clk_get_rate(ss->ssclk);
-+      if (cr <= cr_mod)
-+              if (cr < cr_mod)
-+                      dev_info(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
-+                                      cr, cr / 1000000, cr_mod);
-+              else
-+                      dev_dbg(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
-+                                      cr, cr / 1000000, cr_mod);
-+      else
-+              dev_warn(&pdev->dev, "Clock ss is at %lu (%lu MHz) (must be <= %lu)\n",
-+                              cr, cr / 1000000, cr_mod);
-+
-+      /*
-+       * Datasheet named it "Die Bonding ID"
-+       * I expect to be a sort of Security System Revision number.
-+       * Since the A80 seems to have an other version of SS
-+       * this info could be useful
-+       */
-+      writel(SS_ENABLED, ss->base + SS_CTL);
-+      v = readl(ss->base + SS_CTL);
-+      v >>= 16;
-+      v &= 0x07;
-+      dev_info(&pdev->dev, "Die ID %d\n", v);
-+      writel(0, ss->base + SS_CTL);
-+
-+      ss->dev = &pdev->dev;
-+
-+      mutex_init(&ss->lock);
-+      mutex_init(&ss->bufin_lock);
-+      mutex_init(&ss->bufout_lock);
-+
-+      err = crypto_register_ahash(&sunxi_md5_alg);
-+      if (err)
-+              goto error_md5;
-+      err = crypto_register_ahash(&sunxi_sha1_alg);
-+      if (err)
-+              goto error_sha1;
-+      err = crypto_register_algs(sunxi_cipher_algs,
-+                      ARRAY_SIZE(sunxi_cipher_algs));
-+      if (err)
-+              goto error_ciphers;
-+
-+      return 0;
-+error_ciphers:
-+      crypto_unregister_ahash(&sunxi_sha1_alg);
-+error_sha1:
-+      crypto_unregister_ahash(&sunxi_md5_alg);
-+error_md5:
-+      clk_disable_unprepare(ss->ssclk);
-+      clk_disable_unprepare(ss->busclk);
-+      return err;
-+}
-+
-+static int __exit sunxi_ss_remove(struct platform_device *pdev)
-+{
-+      if (!pdev->dev.of_node)
-+              return 0;
-+
-+      crypto_unregister_ahash(&sunxi_md5_alg);
-+      crypto_unregister_ahash(&sunxi_sha1_alg);
-+      crypto_unregister_algs(sunxi_cipher_algs,
-+                      ARRAY_SIZE(sunxi_cipher_algs));
-+
-+      if (ss->buf_in != NULL)
-+              kfree(ss->buf_in);
-+      if (ss->buf_out != NULL)
-+              kfree(ss->buf_out);
-+
-+      writel(0, ss->base + SS_CTL);
-+      clk_disable_unprepare(ss->busclk);
-+      clk_disable_unprepare(ss->ssclk);
-+      return 0;
-+}
-+
-+static const struct of_device_id a20ss_crypto_of_match_table[] = {
-+      { .compatible = "allwinner,sun7i-a20-crypto" },
-+      {}
-+};
-+MODULE_DEVICE_TABLE(of, a20ss_crypto_of_match_table);
-+
-+static struct platform_driver sunxi_ss_driver = {
-+      .probe          = sunxi_ss_probe,
-+      .remove         = __exit_p(sunxi_ss_remove),
-+      .driver         = {
-+              .owner          = THIS_MODULE,
-+              .name           = "sunxi-ss",
-+              .of_match_table = a20ss_crypto_of_match_table,
-+      },
-+};
-+
-+module_platform_driver(sunxi_ss_driver);
-+
-+MODULE_DESCRIPTION("Allwinner Security System cryptographic accelerator");
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Corentin LABBE <clabbe.montjoie@gmail.com>");
---- /dev/null
-+++ b/drivers/crypto/sunxi-ss/sunxi-ss-hash.c
-@@ -0,0 +1,445 @@
-+/*
-+ * sunxi-ss-hash.c - hardware cryptographic accelerator for Allwinner A20 SoC
-+ *
-+ * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie@gmail.com>
-+ *
-+ * This file add support for MD5 and SHA1.
-+ *
-+ * You could find the datasheet in Documentation/arm/sunxi/README
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+#include "sunxi-ss.h"
-+
-+/* This is a totaly arbitrary value */
-+#define SS_TIMEOUT 100
-+
-+extern struct sunxi_ss_ctx *ss;
-+
-+int sunxi_hash_crainit(struct crypto_tfm *tfm)
-+{
-+      crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
-+                      sizeof(struct sunxi_req_ctx));
-+      return 0;
-+}
-+
-+/* sunxi_hash_init: initialize request context */
-+int sunxi_hash_init(struct ahash_request *areq)
-+{
-+      const char *hash_type;
-+      struct sunxi_req_ctx *op = ahash_request_ctx(areq);
-+
-+      memset(op, 0, sizeof(struct sunxi_req_ctx));
-+
-+      hash_type = crypto_tfm_alg_name(areq->base.tfm);
-+
-+      if (strcmp(hash_type, "sha1") == 0)
-+              op->mode = SS_OP_SHA1;
-+      if (strcmp(hash_type, "md5") == 0)
-+              op->mode = SS_OP_MD5;
-+      if (op->mode == 0)
-+              return -EINVAL;
-+
-+      return 0;
-+}
-+
-+static u32 rx_cnt;
-+
-+inline void ss_writer(const u32 v)
-+{
-+      u32 spaces;
-+
-+      writel(v, ss->base + SS_RXFIFO);
-+      rx_cnt--;
-+      while (rx_cnt == 0) {
-+              spaces = readl_relaxed(ss->base + SS_FCSR);
-+              rx_cnt = SS_RXFIFO_SPACES(spaces);
-+      }
-+}
-+
-+inline void ss_writer_relaxed(const u32 v)
-+{
-+      u32 spaces;
-+
-+      writel_relaxed(v, ss->base + SS_RXFIFO);
-+      rx_cnt--;
-+      while (rx_cnt == 0) {
-+              spaces = readl_relaxed(ss->base + SS_FCSR);
-+              rx_cnt = SS_RXFIFO_SPACES(spaces);
-+      }
-+}
-+
-+/*
-+ * sunxi_hash_update: update hash engine
-+ *
-+ * Could be used for both SHA1 and MD5
-+ * Write data by step of 32bits and put then in the SS.
-+ *
-+ * Since we cannot leave partial data and hash state in the engine,
-+ * we need to get the hash state at the end of this function.
-+ * After some work, I have found that we can get the hash state every 64o
-+ *
-+ * So the first work is to get the number of bytes to write to SS modulo 64
-+ * The extra bytes will go to two different destination:
-+ * op->wait for full 32bits word
-+ * op->wb (waiting bytes) for partial 32 bits word
-+ * So we can have up to (64/4)-1 op->wait words and 0/1/2/3 bytes in wb
-+ *
-+ * So at the begin of update()
-+ * if op->nwait * 4 + areq->nbytes < 64
-+ * => all data writed to wait buffers and end=0
-+ * if not write all nwait to the device and position end to complete to 64o
-+ *
-+ * example 1:
-+ * update1 60o => nwait=15
-+ * update2 60o => need one more word to have 64o
-+ * end=4
-+ * so write all data in op->wait and one word of SGs
-+ * write remaining data in op->wait
-+ * final state op->nwait=14
-+ */
-+int sunxi_hash_update(struct ahash_request *areq)
-+{
-+      u32 v, ivmode = 0;
-+      unsigned int i = 0;
-+      /*
-+       * i is the total bytes read from SGs, to be compared to areq->nbytes
-+       * i is important because we cannot rely on SG length since the sum of
-+       * SG->length could be greater than areq->nbytes
-+       */
-+
-+      struct sunxi_req_ctx *op = ahash_request_ctx(areq);
-+      struct scatterlist *in_sg;
-+      unsigned int in_i = 0; /* advancement in the current SG */
-+      u64 end;
-+      /*
-+       * end is the position when we need to stop writing to the device,
-+       * to be compared to i
-+       */
-+      int in_r;
-+      void *src_addr;
-+
-+      dev_dbg(ss->dev, "%s %s bc=%llu len=%u mode=%x bw=%u ww=%u",
-+                      __func__, crypto_tfm_alg_name(areq->base.tfm),
-+                      op->byte_count, areq->nbytes, op->mode,
-+                      op->nbw, op->nwait);
-+
-+      if (areq->nbytes == 0)
-+              return 0;
-+
-+      end = ((areq->nbytes + op->nwait * 4 + op->nbw) / 64) * 64
-+              - op->nbw - op->nwait * 4;
-+
-+      if (end > areq->nbytes || areq->nbytes - end > 63) {
-+              dev_err(ss->dev, "ERROR: Bound error %llu %u\n",
-+                              end, areq->nbytes);
-+              return -EINVAL;
-+      }
-+
-+      if (op->nwait > 0 && end > 0) {
-+              /* a precedent update was done */
-+              for (i = 0; i < op->nwait; i++) {
-+                      ss_writer(op->wait[i]);
-+                      op->byte_count += 4;
-+              }
-+              op->nwait = 0;
-+      }
-+
-+      mutex_lock(&ss->lock);
-+      /*
-+       * if some data have been processed before,
-+       * we need to restore the partial hash state
-+       */
-+      if (op->byte_count > 0) {
-+              ivmode = SS_IV_ARBITRARY;
-+              for (i = 0; i < 5; i++)
-+                      writel(op->hash[i], ss->base + SS_IV0 + i * 4);
-+      }
-+      /* Enable the device */
-+      writel(op->mode | SS_ENABLED | ivmode, ss->base + SS_CTL);
-+
-+      rx_cnt = 0;
-+      i = 0;
-+
-+      in_sg = areq->src;
-+      src_addr = kmap(sg_page(in_sg)) + in_sg->offset;
-+      if (src_addr == NULL) {
-+              mutex_unlock(&ss->lock);
-+              dev_err(ss->dev, "ERROR: Cannot kmap source buffer\n");
-+              return -EFAULT;
-+      }
-+      do {
-+              /*
-+               * step 1, if some bytes remains from last SG,
-+               * try to complete them to 4 and send that word
-+               */
-+              if (op->nbw > 0) {
-+                      while (op->nbw < 4 && i < areq->nbytes &&
-+                                      in_i < in_sg->length) {
-+                              op->wb |= (*(u8 *)(src_addr + in_i))
-+                                      << (8 * op->nbw);
-+                              dev_dbg(ss->dev, "%s Complete w=%d wb=%x\n",
-+                                              __func__, op->nbw, op->wb);
-+                              i++;
-+                              in_i++;
-+                              op->nbw++;
-+                      }
-+                      if (op->nbw == 4) {
-+                              if (i <= end) {
-+                                      ss_writer(op->wb);
-+                                      op->byte_count += 4;
-+                              } else {
-+                                      op->wait[op->nwait] = op->wb;
-+                                      op->nwait++;
-+                                      dev_dbg(ss->dev, "%s Keep %u bytes after %llu\n",
-+                                              __func__, op->nwait, end);
-+                              }
-+                              op->nbw = 0;
-+                              op->wb = 0;
-+                      }
-+              }
-+              /* step 2, main loop, read data 4bytes at a time */
-+              while (i < areq->nbytes && in_i < in_sg->length) {
-+                      /* how many bytes we can read, (we need 4) */
-+                      in_r = min(in_sg->length - in_i, areq->nbytes - i);
-+                      if (in_r < 4) {
-+                              /* Not enough data to write to the device */
-+                              op->wb = 0;
-+                              while (in_r > 0) {
-+                                      op->wb |= (*(u8 *)(src_addr + in_i))
-+                                              << (8 * op->nbw);
-+                                      dev_dbg(ss->dev, "%s ending bw=%d wb=%x\n",
-+                                              __func__, op->nbw, op->wb);
-+                                      in_r--;
-+                                      i++;
-+                                      in_i++;
-+                                      op->nbw++;
-+                              }
-+                              goto nextsg;
-+                      }
-+                      v = *(u32 *)(src_addr + in_i);
-+                      if (i < end) {
-+                              /* last write must be done without relaxed */
-+                              if (i + 4 >= end)
-+                                      ss_writer(v);
-+                              else
-+                                      ss_writer_relaxed(v);
-+                              i += 4;
-+                              op->byte_count += 4;
-+                              in_i += 4;
-+                      } else {
-+                              op->wait[op->nwait] = v;
-+                              i += 4;
-+                              in_i += 4;
-+                              op->nwait++;
-+                              dev_dbg(ss->dev, "%s Keep word ww=%u after %llu\n",
-+                                              __func__, op->nwait, end);
-+                              if (op->nwait > 15) {
-+                                      dev_err(ss->dev, "FATAL: Cannot enqueue more, bug?\n");
-+                                      writel(0, ss->base + SS_CTL);
-+                                      mutex_unlock(&ss->lock);
-+                                      return -EIO;
-+                              }
-+                      }
-+              }
-+nextsg:
-+              /* Nothing more to read in this SG */
-+              if (in_i == in_sg->length) {
-+                      kunmap(sg_page(in_sg));
-+                      do {
-+                              in_sg = sg_next(in_sg);
-+                      } while (in_sg != NULL && in_sg->length == 0);
-+                      in_i = 0;
-+                      if (in_sg != NULL) {
-+                              src_addr = kmap(sg_page(in_sg)) + in_sg->offset;
-+                              if (src_addr == NULL) {
-+                                      mutex_unlock(&ss->lock);
-+                                      dev_err(ss->dev, "ERROR: Cannot kmap source buffer\n");
-+                                      return -EFAULT;
-+                              }
-+                      }
-+              }
-+      } while (in_sg != NULL && i < areq->nbytes);
-+
-+      /* ask the device to finish the hashing */
-+      writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL);
-+      i = 0;
-+      do {
-+              v = readl(ss->base + SS_CTL);
-+              i++;
-+      } while (i < SS_TIMEOUT && (v & SS_DATA_END) > 0);
-+      if (i >= SS_TIMEOUT) {
-+              dev_err(ss->dev, "ERROR: %s hash end timeout after %d loop, CTL=%x\n",
-+                              __func__, i, v);
-+              writel(0, ss->base + SS_CTL);
-+              mutex_unlock(&ss->lock);
-+              return -EIO;
-+      }
-+
-+      /* get the partial hash */
-+      if (op->mode == SS_OP_SHA1) {
-+              for (i = 0; i < 5; i++)
-+                      op->hash[i] = readl(ss->base + SS_MD0 + i * 4);
-+      } else {
-+              for (i = 0; i < 4; i++)
-+                      op->hash[i] = readl(ss->base + SS_MD0 + i * 4);
-+      }
-+
-+      writel(0, ss->base + SS_CTL);
-+      mutex_unlock(&ss->lock);
-+      return 0;
-+}
-+
-+/*
-+ * sunxi_hash_final: finalize hashing operation
-+ *
-+ * If we have some remaining bytes, we write them.
-+ * Then ask the SS for finalizing the hashing operation
-+ */
-+int sunxi_hash_final(struct ahash_request *areq)
-+{
-+      u32 v, ivmode = 0;
-+      unsigned int i;
-+      int zeros;
-+      unsigned int index, padlen;
-+      __be64 bits;
-+      struct sunxi_req_ctx *op = ahash_request_ctx(areq);
-+
-+      dev_dbg(ss->dev, "%s byte=%llu len=%u mode=%x bw=%u %x h=%x ww=%u",
-+                      __func__, op->byte_count, areq->nbytes, op->mode,
-+                      op->nbw, op->wb, op->hash[0], op->nwait);
-+
-+      mutex_lock(&ss->lock);
-+      rx_cnt = 0;
-+
-+      /*
-+       * if we have already writed something,
-+       * restore the partial hash state
-+       */
-+      if (op->byte_count > 0) {
-+              ivmode = SS_IV_ARBITRARY;
-+              for (i = 0; i < 5; i++)
-+                      writel(op->hash[i], ss->base + SS_IV0 + i * 4);
-+      }
-+      writel(op->mode | SS_ENABLED | ivmode, ss->base + SS_CTL);
-+
-+      /* write the remaining words of the wait buffer */
-+      if (op->nwait > 0) {
-+              for (i = 0; i < op->nwait; i++) {
-+                      v = op->wait[i];
-+                      ss_writer(v);
-+                      op->byte_count += 4;
-+                      dev_dbg(ss->dev, "%s write %llu i=%u %x\n",
-+                                      __func__, op->byte_count, i, v);
-+              }
-+              op->nwait = 0;
-+      }
-+
-+      /* write the remaining bytes of the nbw buffer */
-+      if (op->nbw > 0) {
-+              op->wb |= ((1 << 7) << (op->nbw * 8));
-+              ss_writer(op->wb);
-+      } else {
-+              ss_writer((1 << 7));
-+      }
-+
-+      /*
-+       * number of space to pad to obtain 64o minus 8(size) minus 4 (final 1)
-+       * I take the operations from other md5/sha1 implementations
-+       */
-+
-+      /* we have already send 4 more byte of which nbw data */
-+      if (op->mode == SS_OP_MD5) {
-+              index = (op->byte_count + 4) & 0x3f;
-+              op->byte_count += op->nbw;
-+              if (index > 56)
-+                      zeros = (120 - index) / 4;
-+              else
-+                      zeros = (56 - index) / 4;
-+      } else {
-+              op->byte_count += op->nbw;
-+              index = op->byte_count & 0x3f;
-+              padlen = (index < 56) ? (56 - index) : ((64+56) - index);
-+              zeros = (padlen - 1) / 4;
-+      }
-+      for (i = 0; i < zeros; i++)
-+              ss_writer(0);
-+
-+      /* write the length of data */
-+      if (op->mode == SS_OP_SHA1) {
-+              bits = cpu_to_be64(op->byte_count << 3);
-+              ss_writer(bits & 0xffffffff);
-+              ss_writer((bits >> 32) & 0xffffffff);
-+      } else {
-+              ss_writer((op->byte_count << 3) & 0xffffffff);
-+              ss_writer((op->byte_count >> 29) & 0xffffffff);
-+      }
-+
-+      /* Tell the SS to stop the hashing */
-+      writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL);
-+
-+      /*
-+       * Wait for SS to finish the hash.
-+       * The timeout could happend only in case of bad overcloking
-+       * or driver bug.
-+       */
-+      i = 0;
-+      do {
-+              v = readl(ss->base + SS_CTL);
-+              i++;
-+      } while (i < SS_TIMEOUT && (v & SS_DATA_END) > 0);
-+      if (i >= SS_TIMEOUT) {
-+              dev_err(ss->dev, "ERROR: hash end timeout %d>%d ctl=%x len=%u\n",
-+                              i, SS_TIMEOUT, v, areq->nbytes);
-+              writel(0, ss->base + SS_CTL);
-+              mutex_unlock(&ss->lock);
-+              return -EIO;
-+      }
-+
-+      /* Get the hash from the device */
-+      if (op->mode == SS_OP_SHA1) {
-+              for (i = 0; i < 5; i++) {
-+                      v = cpu_to_be32(readl(ss->base + SS_MD0 + i * 4));
-+                      memcpy(areq->result + i * 4, &v, 4);
-+              }
-+      } else {
-+              for (i = 0; i < 4; i++) {
-+                      v = readl(ss->base + SS_MD0 + i * 4);
-+                      memcpy(areq->result + i * 4, &v, 4);
-+              }
-+      }
-+      writel(0, ss->base + SS_CTL);
-+      mutex_unlock(&ss->lock);
-+      return 0;
-+}
-+
-+/* sunxi_hash_finup: finalize hashing operation after an update */
-+int sunxi_hash_finup(struct ahash_request *areq)
-+{
-+      int err;
-+
-+      err = sunxi_hash_update(areq);
-+      if (err != 0)
-+              return err;
-+
-+      return sunxi_hash_final(areq);
-+}
-+
-+/* combo of init/update/final functions */
-+int sunxi_hash_digest(struct ahash_request *areq)
-+{
-+      int err;
-+
-+      err = sunxi_hash_init(areq);
-+      if (err != 0)
-+              return err;
-+
-+      err = sunxi_hash_update(areq);
-+      if (err != 0)
-+              return err;
-+
-+      return sunxi_hash_final(areq);
-+}
---- /dev/null
-+++ b/drivers/crypto/sunxi-ss/sunxi-ss.h
-@@ -0,0 +1,193 @@
-+/*
-+ * sunxi-ss.c - hardware cryptographic accelerator for Allwinner A20 SoC
-+ *
-+ * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie@gmail.com>
-+ *
-+ * Support AES cipher with 128,192,256 bits keysize.
-+ * Support MD5 and SHA1 hash algorithms.
-+ * Support DES and 3DES
-+ *
-+ * You could find the datasheet in Documentation/arm/sunxi/README
-+ *
-+ * Licensed under the GPL-2.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/crypto.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <crypto/scatterwalk.h>
-+#include <linux/scatterlist.h>
-+#include <linux/interrupt.h>
-+#include <linux/delay.h>
-+#include <crypto/md5.h>
-+#include <crypto/sha.h>
-+#include <crypto/hash.h>
-+#include <crypto/internal/hash.h>
-+#include <crypto/aes.h>
-+#include <crypto/des.h>
-+#include <crypto/internal/rng.h>
-+
-+#define SS_CTL            0x00
-+#define SS_KEY0           0x04
-+#define SS_KEY1           0x08
-+#define SS_KEY2           0x0C
-+#define SS_KEY3           0x10
-+#define SS_KEY4           0x14
-+#define SS_KEY5           0x18
-+#define SS_KEY6           0x1C
-+#define SS_KEY7           0x20
-+
-+#define SS_IV0            0x24
-+#define SS_IV1            0x28
-+#define SS_IV2            0x2C
-+#define SS_IV3            0x30
-+
-+#define SS_CNT0           0x34
-+#define SS_CNT1           0x38
-+#define SS_CNT2           0x3C
-+#define SS_CNT3           0x40
-+
-+#define SS_FCSR           0x44
-+#define SS_ICSR           0x48
-+
-+#define SS_MD0            0x4C
-+#define SS_MD1            0x50
-+#define SS_MD2            0x54
-+#define SS_MD3            0x58
-+#define SS_MD4            0x5C
-+
-+#define SS_RXFIFO         0x200
-+#define SS_TXFIFO         0x204
-+
-+/* SS_CTL configuration values */
-+
-+/* PRNG generator mode - bit 15 */
-+#define SS_PRNG_ONESHOT               (0 << 15)
-+#define SS_PRNG_CONTINUE      (1 << 15)
-+
-+/* IV mode for hash */
-+#define SS_IV_ARBITRARY               (1 << 14)
-+
-+/* SS operation mode - bits 12-13 */
-+#define SS_ECB                        (0 << 12)
-+#define SS_CBC                        (1 << 12)
-+#define SS_CNT                        (2 << 12)
-+
-+/* Counter width for CNT mode - bits 10-11 */
-+#define SS_CNT_16BITS         (0 << 10)
-+#define SS_CNT_32BITS         (1 << 10)
-+#define SS_CNT_64BITS         (2 << 10)
-+
-+/* Key size for AES - bits 8-9 */
-+#define SS_AES_128BITS                (0 << 8)
-+#define SS_AES_192BITS                (1 << 8)
-+#define SS_AES_256BITS                (2 << 8)
-+
-+/* Operation direction - bit 7 */
-+#define SS_ENCRYPTION         (0 << 7)
-+#define SS_DECRYPTION         (1 << 7)
-+
-+/* SS Method - bits 4-6 */
-+#define SS_OP_AES             (0 << 4)
-+#define SS_OP_DES             (1 << 4)
-+#define SS_OP_3DES            (2 << 4)
-+#define SS_OP_SHA1            (3 << 4)
-+#define SS_OP_MD5             (4 << 4)
-+#define SS_OP_PRNG            (5 << 4)
-+
-+/* Data end bit - bit 2 */
-+#define SS_DATA_END           (1 << 2)
-+
-+/* PRNG start bit - bit 1 */
-+#define SS_PRNG_START         (1 << 1)
-+
-+/* SS Enable bit - bit 0 */
-+#define SS_DISABLED           (0 << 0)
-+#define SS_ENABLED            (1 << 0)
-+
-+/* SS_FCSR configuration values */
-+/* RX FIFO status - bit 30 */
-+#define SS_RXFIFO_FREE                (1 << 30)
-+
-+/* RX FIFO empty spaces - bits 24-29 */
-+#define SS_RXFIFO_SPACES(val) (((val) >> 24) & 0x3f)
-+
-+/* TX FIFO status - bit 22 */
-+#define SS_TXFIFO_AVAILABLE   (1 << 22)
-+
-+/* TX FIFO available spaces - bits 16-21 */
-+#define SS_TXFIFO_SPACES(val) (((val) >> 16) & 0x3f)
-+
-+#define SS_RXFIFO_EMP_INT_PENDING     (1 << 10)
-+#define SS_TXFIFO_AVA_INT_PENDING     (1 << 8)
-+#define SS_RXFIFO_EMP_INT_ENABLE      (1 << 2)
-+#define SS_TXFIFO_AVA_INT_ENABLE      (1 << 0)
-+
-+/* SS_ICSR configuration values */
-+#define SS_ICS_DRQ_ENABLE             (1 << 4)
-+
-+struct sunxi_ss_ctx {
-+      void __iomem *base;
-+      int irq;
-+      struct clk *busclk;
-+      struct clk *ssclk;
-+      struct device *dev;
-+      struct resource *res;
-+      void *buf_in; /* pointer to data to be uploaded to the device */
-+      size_t buf_in_size; /* size of buf_in */
-+      void *buf_out;
-+      size_t buf_out_size;
-+      struct mutex lock; /* control the use of the device */
-+      struct mutex bufout_lock; /* control the use of buf_out*/
-+      struct mutex bufin_lock; /* control the sue of buf_in*/
-+};
-+
-+struct sunxi_tfm_ctx {
-+      u32 key[AES_MAX_KEY_SIZE / 4];/* divided by sizeof(u32) */
-+      u32 keylen;
-+      u32 keymode;
-+};
-+
-+struct sunxi_req_ctx {
-+      u32 mode;
-+      u64 byte_count; /* number of bytes "uploaded" to the device */
-+      u32 wb; /* a partial word waiting to be completed and
-+                      uploaded to the device */
-+      /* number of bytes to be uploaded in the wb word */
-+      unsigned int nbw;
-+      u32 hash[5];
-+      u32 wait[64];
-+      unsigned int nwait;
-+};
-+
-+#define SS_SEED_LEN (192/8)
-+#define SS_DATA_LEN (160/8)
-+
-+struct prng_context {
-+      u32 seed[SS_SEED_LEN/4];
-+      unsigned int slen;
-+};
-+
-+int sunxi_hash_crainit(struct crypto_tfm *tfm);
-+int sunxi_hash_init(struct ahash_request *areq);
-+int sunxi_hash_update(struct ahash_request *areq);
-+int sunxi_hash_final(struct ahash_request *areq);
-+int sunxi_hash_finup(struct ahash_request *areq);
-+int sunxi_hash_digest(struct ahash_request *areq);
-+int sunxi_hash_export(struct ahash_request *areq, void *out);
-+int sunxi_hash_import(struct ahash_request *areq, const void *in);
-+
-+int sunxi_ss_aes_poll(struct ablkcipher_request *areq, u32 mode);
-+int sunxi_ss_des_poll(struct ablkcipher_request *areq, u32 mode);
-+int sunxi_ss_cipher_init(struct crypto_tfm *tfm);
-+int sunxi_ss_cipher_encrypt(struct ablkcipher_request *areq);
-+int sunxi_ss_cipher_decrypt(struct ablkcipher_request *areq);
-+int sunxi_ss_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
-+              unsigned int keylen);
-+int sunxi_ss_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
-+              unsigned int keylen);
-+int sunxi_ss_des3_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
-+              unsigned int keylen);
diff --git a/target/linux/sunxi/patches-3.18/300-dt-sun7i-add-bananapi.patch b/target/linux/sunxi/patches-3.18/300-dt-sun7i-add-bananapi.patch
deleted file mode 100644 (file)
index c60b1fe..0000000
+++ /dev/null
@@ -1,245 +0,0 @@
-From 29b4146ec174f0f598d6b454caa335e8f57e392b Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 28 Jul 2014 23:05:14 +0200
-Subject: [PATCH] ARM: dts: sun7i: Add Banana Pi board
-
-The Banana Pi is an A20 based development board using Raspberry Pi compatible
-IO headers. It comes with 1 GB RAM, 1 Gb ethernet, 2x USB host, sata, hdmi
-and stereo audio out + various expenansion headers:
-
-http://www.lemaker.org/
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/Makefile               |   1 +
- arch/arm/boot/dts/sun7i-a20-bananapi.dts | 214 +++++++++++++++++++++++++++++++
- 2 files changed, 215 insertions(+)
- create mode 100644 arch/arm/boot/dts/sun7i-a20-bananapi.dts
-
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -435,6 +435,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \
-       sun6i-a31-hummingbird.dtb \
-       sun6i-a31-m9.dtb
- dtb-$(CONFIG_MACH_SUN7I) += \
-+      sun7i-a20-bananapi.dtb \
-       sun7i-a20-cubieboard2.dtb \
-       sun7i-a20-cubietruck.dtb \
-       sun7i-a20-hummingbird.dtb \
---- /dev/null
-+++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
-@@ -0,0 +1,214 @@
-+/*
-+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPL or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ *  a) This library is free software; you can redistribute it and/or
-+ *     modify it under the terms of the GNU General Public License as
-+ *     published by the Free Software Foundation; either version 2 of the
-+ *     License, or (at your option) any later version.
-+ *
-+ *     This library is distributed in the hope that it will be useful,
-+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *     GNU General Public License for more details.
-+ *
-+ *     You should have received a copy of the GNU General Public
-+ *     License along with this library; if not, write to the Free
-+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-+ *     MA 02110-1301 USA
-+ *
-+ * Or, alternatively,
-+ *
-+ *  b) Permission is hereby granted, free of charge, to any person
-+ *     obtaining a copy of this software and associated documentation
-+ *     files (the "Software"), to deal in the Software without
-+ *     restriction, including without limitation the rights to use,
-+ *     copy, modify, merge, publish, distribute, sublicense, and/or
-+ *     sell copies of the Software, and to permit persons to whom the
-+ *     Software is furnished to do so, subject to the following
-+ *     conditions:
-+ *
-+ *     The above copyright notice and this permission notice shall be
-+ *     included in all copies or substantial portions of the Software.
-+ *
-+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ *     OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+/dts-v1/;
-+/include/ "sun7i-a20.dtsi"
-+/include/ "sunxi-common-regulators.dtsi"
-+
-+/ {
-+      model = "LeMaker Banana Pi";
-+      compatible = "lemaker,bananapi", "allwinner,sun7i-a20";
-+
-+      soc@01c00000 {
-+              spi0: spi@01c05000 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&spi0_pins_a>;
-+                      status = "okay";
-+              };
-+
-+              mmc0: mmc@01c0f000 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>;
-+                      vmmc-supply = <&reg_vcc3v3>;
-+                      bus-width = <4>;
-+                      cd-gpios = <&pio 7 10 0>; /* PH10 */
-+                      cd-inverted;
-+                      status = "okay";
-+              };
-+
-+              usbphy: phy@01c13400 {
-+                      usb1_vbus-supply = <&reg_usb1_vbus>;
-+                      usb2_vbus-supply = <&reg_usb2_vbus>;
-+                      status = "okay";
-+              };
-+
-+              ehci0: usb@01c14000 {
-+                      status = "okay";
-+              };
-+
-+              ohci0: usb@01c14400 {
-+                      status = "okay";
-+              };
-+
-+              ahci: sata@01c18000 {
-+                      status = "okay";
-+              };
-+
-+              ehci1: usb@01c1c000 {
-+                      status = "okay";
-+              };
-+
-+              ohci1: usb@01c1c400 {
-+                      status = "okay";
-+              };
-+
-+              pinctrl@01c20800 {
-+                      mmc0_cd_pin_bananapi: mmc0_cd_pin@0 {
-+                              allwinner,pins = "PH10";
-+                              allwinner,function = "gpio_in";
-+                              allwinner,drive = <0>;
-+                              allwinner,pull = <1>;
-+                      };
-+
-+                      gmac_power_pin_bananapi: gmac_power_pin@0 {
-+                              allwinner,pins = "PH23";
-+                              allwinner,function = "gpio_out";
-+                              allwinner,drive = <0>;
-+                              allwinner,pull = <0>;
-+                      };
-+
-+                      led_pins_bananapi: led_pins@0 {
-+                              allwinner,pins = "PH24";
-+                              allwinner,function = "gpio_out";
-+                              allwinner,drive = <0>;
-+                              allwinner,pull = <0>;
-+                      };
-+              };
-+
-+              ir0: ir@01c21800 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&ir0_pins_a>;
-+                      status = "okay";
-+              };
-+
-+              uart0: serial@01c28000 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&uart0_pins_a>;
-+                      status = "okay";
-+              };
-+
-+              uart3: serial@01c28c00 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&uart3_pins_b>;
-+                      status = "okay";
-+              };
-+
-+              uart7: serial@01c29c00 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&uart7_pins_a>;
-+                      status = "okay";
-+              };
-+
-+              i2c0: i2c@01c2ac00 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&i2c0_pins_a>;
-+                      status = "okay";
-+
-+                      axp209: pmic@34 {
-+                              compatible = "x-powers,axp209";
-+                              reg = <0x34>;
-+                              interrupt-parent = <&nmi_intc>;
-+                              interrupts = <0 8>;
-+
-+                              interrupt-controller;
-+                              #interrupt-cells = <1>;
-+                      };
-+              };
-+
-+              i2c2: i2c@01c2b400 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&i2c2_pins_a>;
-+                      status = "okay";
-+              };
-+
-+              gmac: ethernet@01c50000 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&gmac_pins_rgmii_a>;
-+                      phy = <&phy1>;
-+                      phy-mode = "rgmii";
-+                      phy-supply = <&reg_gmac_3v3>;
-+                      status = "okay";
-+
-+                      phy1: ethernet-phy@1 {
-+                              reg = <1>;
-+                      };
-+              };
-+      };
-+
-+      leds {
-+              compatible = "gpio-leds";
-+              pinctrl-names = "default";
-+              pinctrl-0 = <&led_pins_bananapi>;
-+
-+              green {
-+                      label = "bananapi:green:usr";
-+                      gpios = <&pio 7 24 0>;
-+              };
-+      };
-+
-+      reg_usb1_vbus: usb1-vbus {
-+              status = "okay";
-+      };
-+
-+      reg_usb2_vbus: usb2-vbus {
-+              status = "okay";
-+      };
-+
-+      reg_gmac_3v3: gmac-3v3 {
-+              compatible = "regulator-fixed";
-+              pinctrl-names = "default";
-+              pinctrl-0 = <&gmac_power_pin_bananapi>;
-+              regulator-name = "gmac-3v3";
-+              regulator-min-microvolt = <3300000>;
-+              regulator-max-microvolt = <3300000>;
-+              startup-delay-us = <50000>;
-+              enable-active-high;
-+              gpio = <&pio 7 23 0>;
-+      };
-+};
diff --git a/target/linux/sunxi/patches-3.18/301-dt-sun7i-add-bananapro.patch b/target/linux/sunxi/patches-3.18/301-dt-sun7i-add-bananapro.patch
deleted file mode 100644 (file)
index c8cdb1d..0000000
+++ /dev/null
@@ -1,291 +0,0 @@
-From 3613d535a77270eaf15a5f988a48434c7d1530f2 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Wed, 7 Jan 2015 20:44:52 +0100
-Subject: [PATCH] ARM: dts: sun7i: Add dts file for Bananapro board
-
-Add support for the new Bananapro A20 development board from lemaker.org.
-This board features 1G RAM, 2 USB A receptacles, 1 micro USB receptacle for
-OTG, 1 micro USB receptacle for power, HDMI, sata, Gbit ethernet, ir receiver,
-3.5 mm jack for a/v out, on board microphone, 40 gpio pins and sdio wifi.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/Makefile                |   1 +
- arch/arm/boot/dts/sun7i-a20-bananapro.dts | 261 ++++++++++++++++++++++++++++++
- 2 files changed, 262 insertions(+)
- create mode 100644 arch/arm/boot/dts/sun7i-a20-bananapro.dts
-
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -436,6 +436,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \
-       sun6i-a31-m9.dtb
- dtb-$(CONFIG_MACH_SUN7I) += \
-       sun7i-a20-bananapi.dtb \
-+      sun7i-a20-bananapro.dtb \
-       sun7i-a20-cubieboard2.dtb \
-       sun7i-a20-cubietruck.dtb \
-       sun7i-a20-hummingbird.dtb \
---- /dev/null
-+++ b/arch/arm/boot/dts/sun7i-a20-bananapro.dts
-@@ -0,0 +1,261 @@
-+/*
-+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPL or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ *  a) This file is free software; you can redistribute it and/or
-+ *     modify it under the terms of the GNU General Public License as
-+ *     published by the Free Software Foundation; either version 2 of the
-+ *     License, or (at your option) any later version.
-+ *
-+ *     This file is distributed in the hope that it will be useful,
-+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *     GNU General Public License for more details.
-+ *
-+ *     You should have received a copy of the GNU General Public
-+ *     License along with this file; if not, write to the Free
-+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-+ *     MA 02110-1301 USA
-+ *
-+ * Or, alternatively,
-+ *
-+ *  b) Permission is hereby granted, free of charge, to any person
-+ *     obtaining a copy of this software and associated documentation
-+ *     files (the "Software"), to deal in the Software without
-+ *     restriction, including without limitation the rights to use,
-+ *     copy, modify, merge, publish, distribute, sublicense, and/or
-+ *     sell copies of the Software, and to permit persons to whom the
-+ *     Software is furnished to do so, subject to the following
-+ *     conditions:
-+ *
-+ *     The above copyright notice and this permission notice shall be
-+ *     included in all copies or substantial portions of the Software.
-+ *
-+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ *     OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+/dts-v1/;
-+/include/ "sun7i-a20.dtsi"
-+/include/ "sunxi-common-regulators.dtsi"
-+
-+/ {
-+      model = "LeMaker Banana Pro";
-+      compatible = "lemaker,bananapro", "allwinner,sun7i-a20";
-+
-+      soc@01c00000 {
-+              spi0: spi@01c05000 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&spi0_pins_a>;
-+                      status = "okay";
-+              };
-+
-+              mmc0: mmc@01c0f000 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>;
-+                      vmmc-supply = <&reg_vcc3v3>;
-+                      bus-width = <4>;
-+                      cd-gpios = <&pio 7 10 0>; /* PH10 */
-+                      cd-inverted;
-+                      status = "okay";
-+              };
-+
-+              mmc3: mmc@01c12000 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&mmc3_pins_a>;
-+                      vmmc-supply = <&reg_vmmc3>;
-+                      bus-width = <4>;
-+                      non-removable;
-+                      status = "okay";
-+              };
-+
-+              usbphy: phy@01c13400 {
-+                      usb1_vbus-supply = <&reg_usb1_vbus>;
-+                      usb2_vbus-supply = <&reg_usb2_vbus>;
-+                      status = "okay";
-+              };
-+
-+              ehci0: usb@01c14000 {
-+                      status = "okay";
-+              };
-+
-+              ohci0: usb@01c14400 {
-+                      status = "okay";
-+              };
-+
-+              ahci: sata@01c18000 {
-+                      status = "okay";
-+              };
-+
-+              ehci1: usb@01c1c000 {
-+                      status = "okay";
-+              };
-+
-+              ohci1: usb@01c1c400 {
-+                      status = "okay";
-+              };
-+
-+              pinctrl@01c20800 {
-+                      usb1_vbus_pin_bananapro: usb1_vbus_pin@0 {
-+                              allwinner,pins = "PH0";
-+                              allwinner,function = "gpio_out";
-+                              allwinner,drive = <0>;
-+                              allwinner,pull = <0>;
-+                      };
-+
-+                      usb2_vbus_pin_bananapro: usb2_vbus_pin@0 {
-+                              allwinner,pins = "PH1";
-+                              allwinner,function = "gpio_out";
-+                              allwinner,drive = <0>;
-+                              allwinner,pull = <0>;
-+                      };
-+
-+                      mmc0_cd_pin_bananapi: mmc0_cd_pin@0 {
-+                              allwinner,pins = "PH10";
-+                              allwinner,function = "gpio_in";
-+                              allwinner,drive = <0>;
-+                              allwinner,pull = <1>;
-+                      };
-+
-+                      vmmc3_pin_bananapro: vmmc3_pin@0 {
-+                              allwinner,pins = "PH22";
-+                              allwinner,function = "gpio_out";
-+                              allwinner,drive = <0>;
-+                              allwinner,pull = <0>;
-+                      };
-+
-+                      gmac_power_pin_bananapi: gmac_power_pin@0 {
-+                              allwinner,pins = "PH23";
-+                              allwinner,function = "gpio_out";
-+                              allwinner,drive = <0>;
-+                              allwinner,pull = <0>;
-+                      };
-+
-+                      led_pins_bananapi: led_pins@0 {
-+                              allwinner,pins = "PH24", "PG2";
-+                              allwinner,function = "gpio_out";
-+                              allwinner,drive = <0>;
-+                              allwinner,pull = <0>;
-+                      };
-+              };
-+
-+              ir0: ir@01c21800 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&ir0_pins_a>;
-+                      status = "okay";
-+              };
-+
-+              uart0: serial@01c28000 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&uart0_pins_a>;
-+                      status = "okay";
-+              };
-+
-+              uart2: serial@01c28800 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&uart2_pins_a>;
-+                      status = "okay";
-+              };
-+
-+              uart7: serial@01c29c00 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&uart7_pins_a>;
-+                      status = "okay";
-+              };
-+
-+              i2c0: i2c@01c2ac00 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&i2c0_pins_a>;
-+                      status = "okay";
-+
-+                      axp209: pmic@34 {
-+                              compatible = "x-powers,axp209";
-+                              reg = <0x34>;
-+                              interrupt-parent = <&nmi_intc>;
-+                              interrupts = <0 8>;
-+
-+                              interrupt-controller;
-+                              #interrupt-cells = <1>;
-+                      };
-+              };
-+
-+              i2c2: i2c@01c2b400 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&i2c2_pins_a>;
-+                      status = "okay";
-+              };
-+
-+              gmac: ethernet@01c50000 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&gmac_pins_rgmii_a>;
-+                      phy = <&phy1>;
-+                      phy-mode = "rgmii";
-+                      phy-supply = <&reg_gmac_3v3>;
-+                      status = "okay";
-+
-+                      phy1: ethernet-phy@1 {
-+                              reg = <1>;
-+                      };
-+              };
-+      };
-+
-+      leds {
-+              compatible = "gpio-leds";
-+              pinctrl-names = "default";
-+              pinctrl-0 = <&led_pins_bananapi>;
-+
-+              green {
-+                      label = "bananapi:green:usr";
-+                      gpios = <&pio 7 24 0>;
-+              };
-+              blue {
-+                      label = "bananapi:blue:usr";
-+                      gpios = <&pio 6 2 0>;
-+              };
-+      };
-+
-+      reg_usb1_vbus: usb1-vbus {
-+              pinctrl-0 = <&usb1_vbus_pin_bananapro>;
-+              gpio = <&pio 7 0 0>; /* PH0 */
-+              status = "okay";
-+      };
-+
-+      reg_usb2_vbus: usb2-vbus {
-+              pinctrl-0 = <&usb2_vbus_pin_bananapro>;
-+              gpio = <&pio 7 1 0>; /* PH1 */
-+              status = "okay";
-+      };
-+
-+      reg_gmac_3v3: gmac-3v3 {
-+              compatible = "regulator-fixed";
-+              pinctrl-names = "default";
-+              pinctrl-0 = <&gmac_power_pin_bananapi>;
-+              regulator-name = "gmac-3v3";
-+              regulator-min-microvolt = <3300000>;
-+              regulator-max-microvolt = <3300000>;
-+              startup-delay-us = <100000>;
-+              enable-active-high;
-+              gpio = <&pio 7 23 0>;
-+      };
-+
-+      reg_vmmc3: vmmc3 {
-+              compatible = "regulator-fixed";
-+              pinctrl-names = "default";
-+              pinctrl-0 = <&vmmc3_pin_bananapro>;
-+              regulator-name = "vmmc3";
-+              regulator-min-microvolt = <3300000>;
-+              regulator-max-microvolt = <3300000>;
-+              enable-active-high;
-+              gpio = <&pio 7 22 0>;
-+      };
-+};
diff --git a/target/linux/sunxi/patches-3.18/302-dt-sun7i-add-lamobo-r1.patch b/target/linux/sunxi/patches-3.18/302-dt-sun7i-add-lamobo-r1.patch
deleted file mode 100644 (file)
index 5d5ba11..0000000
+++ /dev/null
@@ -1,248 +0,0 @@
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -441,6 +441,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
-       sun7i-a20-cubietruck.dtb \
-       sun7i-a20-hummingbird.dtb \
-       sun7i-a20-i12-tvbox.dtb \
-+      sun7i-a20-lamobo-r1.dtb \
-       sun7i-a20-olinuxino-lime.dtb \
-       sun7i-a20-olinuxino-micro.dtb \
-       sun7i-a20-pcduino3.dtb
---- /dev/null
-+++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
-@@ -0,0 +1,235 @@
-+/*
-+ * Copyright 2015 Daniel Golle <daniel@makrotopia.org>
-+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPL or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ *  a) This library is free software; you can redistribute it and/or
-+ *     modify it under the terms of the GNU General Public License as
-+ *     published by the Free Software Foundation; either version 2 of the
-+ *     License, or (at your option) any later version.
-+ *
-+ *     This library is distributed in the hope that it will be useful,
-+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *     GNU General Public License for more details.
-+ *
-+ *     You should have received a copy of the GNU General Public
-+ *     License along with this library; if not, write to the Free
-+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-+ *     MA 02110-1301 USA
-+ *
-+ * Or, alternatively,
-+ *
-+ *  b) Permission is hereby granted, free of charge, to any person
-+ *     obtaining a copy of this software and associated documentation
-+ *     files (the "Software"), to deal in the Software without
-+ *     restriction, including without limitation the rights to use,
-+ *     copy, modify, merge, publish, distribute, sublicense, and/or
-+ *     sell copies of the Software, and to permit persons to whom the
-+ *     Software is furnished to do so, subject to the following
-+ *     conditions:
-+ *
-+ *     The above copyright notice and this permission notice shall be
-+ *     included in all copies or substantial portions of the Software.
-+ *
-+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ *     OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+/dts-v1/;
-+/include/ "sun7i-a20.dtsi"
-+/include/ "sunxi-common-regulators.dtsi"
-+#include <dt-bindings/input/input.h>
-+
-+/ {
-+      model = "Lamobo R1";
-+      compatible = "lamobo,lamobo-r1", "allwinner,sun7i-a20";
-+
-+      soc@01c00000 {
-+              spi0: spi@01c05000 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&spi0_pins_a>;
-+                      status = "okay";
-+              };
-+
-+              mmc0: mmc@01c0f000 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_lamobo>;
-+                      vmmc-supply = <&reg_vcc3v3>;
-+                      bus-width = <4>;
-+                      cd-gpios = <&pio 7 10 0>; /* PH10 */
-+                      cd-inverted;
-+                      status = "okay";
-+              };
-+
-+              usbphy: phy@01c13400 {
-+                      usb1_vbus-supply = <&reg_usb1_vbus>;
-+                      usb2_vbus-supply = <&reg_usb2_vbus>;
-+                      status = "okay";
-+              };
-+
-+              ehci0: usb@01c14000 {
-+                      status = "okay";
-+              };
-+
-+              ohci0: usb@01c14400 {
-+                      status = "okay";
-+              };
-+
-+              ahci: sata@01c18000 {
-+                      target-supply = <&reg_ahci_5v>;
-+                      status = "okay";
-+              };
-+
-+              ehci1: usb@01c1c000 {
-+                      status = "okay";
-+              };
-+
-+              ohci1: usb@01c1c400 {
-+                      status = "okay";
-+              };
-+
-+              pinctrl@01c20800 {
-+                      mmc0_cd_pin_lamobo: mmc0_cd_pin@0 {
-+                              allwinner,pins = "PH10";
-+                              allwinner,function = "gpio_in";
-+                              allwinner,drive = <0>;
-+                              allwinner,pull = <1>;
-+                      };
-+
-+                      gmac_power_pin_lamobo: gmac_power_pin@0 {
-+                              allwinner,pins = "PH23";
-+                              allwinner,function = "gpio_out";
-+                              allwinner,drive = <0>;
-+                              allwinner,pull = <0>;
-+                      };
-+
-+                      led_pins_lamobo: led_pins@0 {
-+                              allwinner,pins = "PH2";
-+                              allwinner,function = "gpio_out";
-+                              allwinner,drive = <1>;
-+                              allwinner,pull = <0>;
-+                      };
-+              };
-+
-+              lradc: lradc@01c22800 {
-+                      allwinner,chan0-step = <200>;
-+                      linux,chan0-keycodes = <KEY_VOLUMEUP KEY_VOLUMEDOWN
-+                                              KEY_MENU KEY_SEARCH KEY_HOME
-+                                              KEY_ESC KEY_ENTER>;
-+                      status = "okay";
-+              };
-+
-+              ir0: ir@01c21800 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&ir0_pins_a>;
-+                      status = "okay";
-+              };
-+
-+              uart0: serial@01c28000 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&uart0_pins_a>;
-+                      status = "okay";
-+              };
-+
-+              uart3: serial@01c28c00 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&uart3_pins_b>;
-+                      status = "okay";
-+              };
-+
-+              uart7: serial@01c29c00 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&uart7_pins_a>;
-+                      status = "okay";
-+              };
-+
-+              i2c0: i2c@01c2ac00 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&i2c0_pins_a>;
-+                      status = "okay";
-+
-+                      axp209: pmic@34 {
-+                              compatible = "x-powers,axp209";
-+                              reg = <0x34>;
-+                              interrupt-parent = <&nmi_intc>;
-+                              interrupts = <0 8>;
-+
-+                              interrupt-controller;
-+                              #interrupt-cells = <1>;
-+                      };
-+              };
-+
-+              i2c1: i2c@01c2b000 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&i2c1_pins_a>;
-+                      status = "okay";
-+              };
-+
-+              i2c2: i2c@01c2b400 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&i2c2_pins_a>;
-+                      status = "okay";
-+              };
-+
-+              gmac: ethernet@01c50000 {
-+                      pinctrl-names = "default";
-+                      pinctrl-0 = <&gmac_pins_rgmii_a>;
-+                      phy = <&phy1>;
-+                      phy-mode = "rgmii";
-+                      phy-supply = <&reg_gmac_3v3>;
-+                      status = "okay";
-+
-+                      phy1: ethernet-phy@1 {
-+                              reg = <1>;
-+                      };
-+              };
-+      };
-+
-+      leds {
-+              compatible = "gpio-leds";
-+              pinctrl-names = "default";
-+              pinctrl-0 = <&led_pins_lamobo>;
-+
-+              green {
-+                      label = "lamobo:green:usr";
-+                      gpios = <&pio 7 24 0>;
-+                      default-state = "on";
-+              };
-+      };
-+
-+      reg_ahci_5v: ahci-5v {
-+              status = "okay";
-+      };
-+
-+      reg_usb1_vbus: usb1-vbus {
-+              status = "okay";
-+      };
-+
-+      reg_usb2_vbus: usb2-vbus {
-+              status = "okay";
-+      };
-+
-+      reg_gmac_3v3: gmac-3v3 {
-+              compatible = "regulator-fixed";
-+              pinctrl-names = "default";
-+              pinctrl-0 = <&gmac_power_pin_lamobo>;
-+              regulator-name = "gmac-3v3";
-+              regulator-min-microvolt = <3300000>;
-+              regulator-max-microvolt = <3300000>;
-+              startup-delay-us = <100000>;
-+              enable-active-high;
-+              gpio = <&pio 7 23 0>;
-+              status = "okay";
-+      };
-+};
diff --git a/target/linux/sunxi/patches-4.1/100-mfd-axp20x-add-axp22x-pmic.patch b/target/linux/sunxi/patches-4.1/100-mfd-axp20x-add-axp22x-pmic.patch
deleted file mode 100644 (file)
index c93adeb..0000000
+++ /dev/null
@@ -1,330 +0,0 @@
-From f05be589ff32e87821b86845625ed3d402d37dc7 Mon Sep 17 00:00:00 2001
-From: Boris BREZILLON <boris.brezillon@free-electrons.com>
-Date: Fri, 10 Apr 2015 12:09:01 +0800
-Subject: [PATCH] mfd: axp20x: Add AXP22x PMIC support
-
-Add support for the AXP22x PMIC devices to the existing AXP20x driver.
-This includes the AXP221 and AXP223, which are identical except for
-the external data bus. Only AXP221 is added for now. AXP223 will be
-added after it's Reduced Serial Bus (RSB) interface is supported.
-
-AXP22x defines a new set of registers, power supplies and regulators,
-but most of the API is similar to the AXP20x ones.
-
-A new irq chip definition is used, even though the available interrupts
-on AXP22x is a subset of those on AXP20x. This is done so the interrupt
-numbers match those on the datasheet.
-
-This patch only enables the interrupts, system power-off function, and PEK
-sub-device. The regulator driver must first support different variants
-before we enable it from the mfd driver.
-
-Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
-[wens@csie.org: fix interrupts and move regulators to separate patch]
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: Lee Jones <lee.jones@linaro.org>
----
- drivers/mfd/axp20x.c       | 98 ++++++++++++++++++++++++++++++++++++++++++++++
- include/linux/mfd/axp20x.h | 86 ++++++++++++++++++++++++++++++++++++++++
- 2 files changed, 184 insertions(+)
-
---- a/drivers/mfd/axp20x.c
-+++ b/drivers/mfd/axp20x.c
-@@ -32,6 +32,7 @@
- static const char * const axp20x_model_names[] = {
-       "AXP202",
-       "AXP209",
-+      "AXP221",
-       "AXP288",
- };
-@@ -54,6 +55,25 @@ static const struct regmap_access_table
-       .n_yes_ranges   = ARRAY_SIZE(axp20x_volatile_ranges),
- };
-+static const struct regmap_range axp22x_writeable_ranges[] = {
-+      regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
-+      regmap_reg_range(AXP20X_DCDC_MODE, AXP22X_BATLOW_THRES1),
-+};
-+
-+static const struct regmap_range axp22x_volatile_ranges[] = {
-+      regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
-+};
-+
-+static const struct regmap_access_table axp22x_writeable_table = {
-+      .yes_ranges     = axp22x_writeable_ranges,
-+      .n_yes_ranges   = ARRAY_SIZE(axp22x_writeable_ranges),
-+};
-+
-+static const struct regmap_access_table axp22x_volatile_table = {
-+      .yes_ranges     = axp22x_volatile_ranges,
-+      .n_yes_ranges   = ARRAY_SIZE(axp22x_volatile_ranges),
-+};
-+
- static const struct regmap_range axp288_writeable_ranges[] = {
-       regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ6_STATE),
-       regmap_reg_range(AXP20X_DCDC_MODE, AXP288_FG_TUNE5),
-@@ -87,6 +107,20 @@ static struct resource axp20x_pek_resour
-       },
- };
-+static struct resource axp22x_pek_resources[] = {
-+      {
-+              .name   = "PEK_DBR",
-+              .start  = AXP22X_IRQ_PEK_RIS_EDGE,
-+              .end    = AXP22X_IRQ_PEK_RIS_EDGE,
-+              .flags  = IORESOURCE_IRQ,
-+      }, {
-+              .name   = "PEK_DBF",
-+              .start  = AXP22X_IRQ_PEK_FAL_EDGE,
-+              .end    = AXP22X_IRQ_PEK_FAL_EDGE,
-+              .flags  = IORESOURCE_IRQ,
-+      },
-+};
-+
- static struct resource axp288_fuel_gauge_resources[] = {
-       {
-               .start = AXP288_IRQ_QWBTU,
-@@ -129,6 +163,15 @@ static const struct regmap_config axp20x
-       .cache_type     = REGCACHE_RBTREE,
- };
-+static const struct regmap_config axp22x_regmap_config = {
-+      .reg_bits       = 8,
-+      .val_bits       = 8,
-+      .wr_table       = &axp22x_writeable_table,
-+      .volatile_table = &axp22x_volatile_table,
-+      .max_register   = AXP22X_BATLOW_THRES1,
-+      .cache_type     = REGCACHE_RBTREE,
-+};
-+
- static const struct regmap_config axp288_regmap_config = {
-       .reg_bits       = 8,
-       .val_bits       = 8,
-@@ -181,6 +224,34 @@ static const struct regmap_irq axp20x_re
-       INIT_REGMAP_IRQ(AXP20X, GPIO0_INPUT,            4, 0),
- };
-+static const struct regmap_irq axp22x_regmap_irqs[] = {
-+      INIT_REGMAP_IRQ(AXP22X, ACIN_OVER_V,            0, 7),
-+      INIT_REGMAP_IRQ(AXP22X, ACIN_PLUGIN,            0, 6),
-+      INIT_REGMAP_IRQ(AXP22X, ACIN_REMOVAL,           0, 5),
-+      INIT_REGMAP_IRQ(AXP22X, VBUS_OVER_V,            0, 4),
-+      INIT_REGMAP_IRQ(AXP22X, VBUS_PLUGIN,            0, 3),
-+      INIT_REGMAP_IRQ(AXP22X, VBUS_REMOVAL,           0, 2),
-+      INIT_REGMAP_IRQ(AXP22X, VBUS_V_LOW,             0, 1),
-+      INIT_REGMAP_IRQ(AXP22X, BATT_PLUGIN,            1, 7),
-+      INIT_REGMAP_IRQ(AXP22X, BATT_REMOVAL,           1, 6),
-+      INIT_REGMAP_IRQ(AXP22X, BATT_ENT_ACT_MODE,      1, 5),
-+      INIT_REGMAP_IRQ(AXP22X, BATT_EXIT_ACT_MODE,     1, 4),
-+      INIT_REGMAP_IRQ(AXP22X, CHARG,                  1, 3),
-+      INIT_REGMAP_IRQ(AXP22X, CHARG_DONE,             1, 2),
-+      INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_HIGH,         1, 1),
-+      INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_LOW,          1, 0),
-+      INIT_REGMAP_IRQ(AXP22X, DIE_TEMP_HIGH,          2, 7),
-+      INIT_REGMAP_IRQ(AXP22X, PEK_SHORT,              2, 1),
-+      INIT_REGMAP_IRQ(AXP22X, PEK_LONG,               2, 0),
-+      INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL1,           3, 1),
-+      INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL2,           3, 0),
-+      INIT_REGMAP_IRQ(AXP22X, TIMER,                  4, 7),
-+      INIT_REGMAP_IRQ(AXP22X, PEK_RIS_EDGE,           4, 6),
-+      INIT_REGMAP_IRQ(AXP22X, PEK_FAL_EDGE,           4, 5),
-+      INIT_REGMAP_IRQ(AXP22X, GPIO1_INPUT,            4, 1),
-+      INIT_REGMAP_IRQ(AXP22X, GPIO0_INPUT,            4, 0),
-+};
-+
- /* some IRQs are compatible with axp20x models */
- static const struct regmap_irq axp288_regmap_irqs[] = {
-       INIT_REGMAP_IRQ(AXP288, VBUS_FALL,              0, 2),
-@@ -224,6 +295,7 @@ static const struct regmap_irq axp288_re
- static const struct of_device_id axp20x_of_match[] = {
-       { .compatible = "x-powers,axp202", .data = (void *) AXP202_ID },
-       { .compatible = "x-powers,axp209", .data = (void *) AXP209_ID },
-+      { .compatible = "x-powers,axp221", .data = (void *) AXP221_ID },
-       { },
- };
- MODULE_DEVICE_TABLE(of, axp20x_of_match);
-@@ -258,6 +330,18 @@ static const struct regmap_irq_chip axp2
- };
-+static const struct regmap_irq_chip axp22x_regmap_irq_chip = {
-+      .name                   = "axp22x_irq_chip",
-+      .status_base            = AXP20X_IRQ1_STATE,
-+      .ack_base               = AXP20X_IRQ1_STATE,
-+      .mask_base              = AXP20X_IRQ1_EN,
-+      .mask_invert            = true,
-+      .init_ack_masked        = true,
-+      .irqs                   = axp22x_regmap_irqs,
-+      .num_irqs               = ARRAY_SIZE(axp22x_regmap_irqs),
-+      .num_regs               = 5,
-+};
-+
- static const struct regmap_irq_chip axp288_regmap_irq_chip = {
-       .name                   = "axp288_irq_chip",
-       .status_base            = AXP20X_IRQ1_STATE,
-@@ -281,6 +365,14 @@ static struct mfd_cell axp20x_cells[] =
-       },
- };
-+static struct mfd_cell axp22x_cells[] = {
-+      {
-+              .name                   = "axp20x-pek",
-+              .num_resources          = ARRAY_SIZE(axp22x_pek_resources),
-+              .resources              = axp22x_pek_resources,
-+      },
-+};
-+
- static struct resource axp288_adc_resources[] = {
-       {
-               .name  = "GPADC",
-@@ -426,6 +518,12 @@ static int axp20x_match_device(struct ax
-               axp20x->regmap_cfg = &axp20x_regmap_config;
-               axp20x->regmap_irq_chip = &axp20x_regmap_irq_chip;
-               break;
-+      case AXP221_ID:
-+              axp20x->nr_cells = ARRAY_SIZE(axp22x_cells);
-+              axp20x->cells = axp22x_cells;
-+              axp20x->regmap_cfg = &axp22x_regmap_config;
-+              axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip;
-+              break;
-       case AXP288_ID:
-               axp20x->cells = axp288_cells;
-               axp20x->nr_cells = ARRAY_SIZE(axp288_cells);
---- a/include/linux/mfd/axp20x.h
-+++ b/include/linux/mfd/axp20x.h
-@@ -14,6 +14,7 @@
- enum {
-       AXP202_ID = 0,
-       AXP209_ID,
-+      AXP221_ID,
-       AXP288_ID,
-       NR_AXP20X_VARIANTS,
- };
-@@ -45,6 +46,28 @@ enum {
- #define AXP20X_V_LTF_DISCHRG          0x3c
- #define AXP20X_V_HTF_DISCHRG          0x3d
-+#define AXP22X_PWR_OUT_CTRL1          0x10
-+#define AXP22X_PWR_OUT_CTRL2          0x12
-+#define AXP22X_PWR_OUT_CTRL3          0x13
-+#define AXP22X_DLDO1_V_OUT            0x15
-+#define AXP22X_DLDO2_V_OUT            0x16
-+#define AXP22X_DLDO3_V_OUT            0x17
-+#define AXP22X_DLDO4_V_OUT            0x18
-+#define AXP22X_ELDO1_V_OUT            0x19
-+#define AXP22X_ELDO2_V_OUT            0x1a
-+#define AXP22X_ELDO3_V_OUT            0x1b
-+#define AXP22X_DC5LDO_V_OUT           0x1c
-+#define AXP22X_DCDC1_V_OUT            0x21
-+#define AXP22X_DCDC2_V_OUT            0x22
-+#define AXP22X_DCDC3_V_OUT            0x23
-+#define AXP22X_DCDC4_V_OUT            0x24
-+#define AXP22X_DCDC5_V_OUT            0x25
-+#define AXP22X_DCDC23_V_RAMP_CTRL     0x27
-+#define AXP22X_ALDO1_V_OUT            0x28
-+#define AXP22X_ALDO2_V_OUT            0x29
-+#define AXP22X_ALDO3_V_OUT            0x2a
-+#define AXP22X_CHRG_CTRL3             0x35
-+
- /* Interrupt */
- #define AXP20X_IRQ1_EN                        0x40
- #define AXP20X_IRQ2_EN                        0x41
-@@ -100,6 +123,9 @@ enum {
- #define AXP20X_VBUS_MON                       0x8b
- #define AXP20X_OVER_TMP                       0x8f
-+#define AXP22X_PWREN_CTRL1            0x8c
-+#define AXP22X_PWREN_CTRL2            0x8d
-+
- /* GPIO */
- #define AXP20X_GPIO0_CTRL             0x90
- #define AXP20X_LDO5_V_OUT             0x91
-@@ -108,6 +134,11 @@ enum {
- #define AXP20X_GPIO20_SS              0x94
- #define AXP20X_GPIO3_CTRL             0x95
-+#define AXP22X_LDO_IO0_V_OUT          0x91
-+#define AXP22X_LDO_IO1_V_OUT          0x93
-+#define AXP22X_GPIO_STATE             0x94
-+#define AXP22X_GPIO_PULL_DOWN         0x95
-+
- /* Battery */
- #define AXP20X_CHRG_CC_31_24          0xb0
- #define AXP20X_CHRG_CC_23_16          0xb1
-@@ -120,6 +151,9 @@ enum {
- #define AXP20X_CC_CTRL                        0xb8
- #define AXP20X_FG_RES                 0xb9
-+/* AXP22X specific registers */
-+#define AXP22X_BATLOW_THRES1          0xe6
-+
- /* AXP288 specific registers */
- #define AXP288_PMIC_ADC_H               0x56
- #define AXP288_PMIC_ADC_L               0x57
-@@ -158,6 +192,30 @@ enum {
-       AXP20X_REG_ID_MAX,
- };
-+enum {
-+      AXP22X_DCDC1 = 0,
-+      AXP22X_DCDC2,
-+      AXP22X_DCDC3,
-+      AXP22X_DCDC4,
-+      AXP22X_DCDC5,
-+      AXP22X_DC1SW,
-+      AXP22X_DC5LDO,
-+      AXP22X_ALDO1,
-+      AXP22X_ALDO2,
-+      AXP22X_ALDO3,
-+      AXP22X_ELDO1,
-+      AXP22X_ELDO2,
-+      AXP22X_ELDO3,
-+      AXP22X_DLDO1,
-+      AXP22X_DLDO2,
-+      AXP22X_DLDO3,
-+      AXP22X_DLDO4,
-+      AXP22X_RTC_LDO,
-+      AXP22X_LDO_IO0,
-+      AXP22X_LDO_IO1,
-+      AXP22X_REG_ID_MAX,
-+};
-+
- /* IRQs */
- enum {
-       AXP20X_IRQ_ACIN_OVER_V = 1,
-@@ -199,6 +257,34 @@ enum {
-       AXP20X_IRQ_GPIO0_INPUT,
- };
-+enum axp22x_irqs {
-+      AXP22X_IRQ_ACIN_OVER_V = 1,
-+      AXP22X_IRQ_ACIN_PLUGIN,
-+      AXP22X_IRQ_ACIN_REMOVAL,
-+      AXP22X_IRQ_VBUS_OVER_V,
-+      AXP22X_IRQ_VBUS_PLUGIN,
-+      AXP22X_IRQ_VBUS_REMOVAL,
-+      AXP22X_IRQ_VBUS_V_LOW,
-+      AXP22X_IRQ_BATT_PLUGIN,
-+      AXP22X_IRQ_BATT_REMOVAL,
-+      AXP22X_IRQ_BATT_ENT_ACT_MODE,
-+      AXP22X_IRQ_BATT_EXIT_ACT_MODE,
-+      AXP22X_IRQ_CHARG,
-+      AXP22X_IRQ_CHARG_DONE,
-+      AXP22X_IRQ_BATT_TEMP_HIGH,
-+      AXP22X_IRQ_BATT_TEMP_LOW,
-+      AXP22X_IRQ_DIE_TEMP_HIGH,
-+      AXP22X_IRQ_PEK_SHORT,
-+      AXP22X_IRQ_PEK_LONG,
-+      AXP22X_IRQ_LOW_PWR_LVL1,
-+      AXP22X_IRQ_LOW_PWR_LVL2,
-+      AXP22X_IRQ_TIMER,
-+      AXP22X_IRQ_PEK_RIS_EDGE,
-+      AXP22X_IRQ_PEK_FAL_EDGE,
-+      AXP22X_IRQ_GPIO1_INPUT,
-+      AXP22X_IRQ_GPIO0_INPUT,
-+};
-+
- enum axp288_irqs {
-       AXP288_IRQ_VBUS_FALL     = 2,
-       AXP288_IRQ_VBUS_RISE,
diff --git a/target/linux/sunxi/patches-4.1/101-regulator-axp20x-prep-support-for-multiple-axp-families.patch b/target/linux/sunxi/patches-4.1/101-regulator-axp20x-prep-support-for-multiple-axp-families.patch
deleted file mode 100644 (file)
index 21fe2ec..0000000
+++ /dev/null
@@ -1,278 +0,0 @@
-From f95b73ba272eac5495e69e12795d5ea8bc81d2cd Mon Sep 17 00:00:00 2001
-From: Boris BREZILLON <boris.brezillon@free-electrons.com>
-Date: Fri, 10 Apr 2015 12:09:03 +0800
-Subject: [PATCH] regulator: axp20x: Prepare support for multiple AXP chip
- families
-
-Rework the AXP20X_ macros and probe function to support the several chip
-families, so that each family can define it's own set of regulators.
-
-Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
-[wens@csie.org: Support different DC-DC work frequency ranges]
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Reviewed-by: Mark Brown <broonie@kernel.org>
-Signed-off-by: Lee Jones <lee.jones@linaro.org>
----
- drivers/regulator/axp20x-regulator.c | 143 +++++++++++++++++++++++------------
- 1 file changed, 94 insertions(+), 49 deletions(-)
-
---- a/drivers/regulator/axp20x-regulator.c
-+++ b/drivers/regulator/axp20x-regulator.c
-@@ -32,15 +32,15 @@
- #define AXP20X_FREQ_DCDC_MASK         0x0f
--#define AXP20X_DESC_IO(_id, _match, _supply, _min, _max, _step, _vreg, _vmask,        \
--                     _ereg, _emask, _enable_val, _disable_val)                \
--      [AXP20X_##_id] = {                                                      \
-+#define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg,  \
-+                  _vmask, _ereg, _emask, _enable_val, _disable_val)           \
-+      [_family##_##_id] = {                                                   \
-               .name           = #_id,                                         \
-               .supply_name    = (_supply),                                    \
-               .of_match       = of_match_ptr(_match),                         \
-               .regulators_node = of_match_ptr("regulators"),                  \
-               .type           = REGULATOR_VOLTAGE,                            \
--              .id             = AXP20X_##_id,                                 \
-+              .id             = _family##_##_id,                              \
-               .n_voltages     = (((_max) - (_min)) / (_step) + 1),            \
-               .owner          = THIS_MODULE,                                  \
-               .min_uV         = (_min) * 1000,                                \
-@@ -54,15 +54,15 @@
-               .ops            = &axp20x_ops,                                  \
-       }
--#define AXP20X_DESC(_id, _match, _supply, _min, _max, _step, _vreg, _vmask,   \
--                  _ereg, _emask)                                              \
--      [AXP20X_##_id] = {                                                      \
-+#define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg,     \
-+               _vmask, _ereg, _emask)                                         \
-+      [_family##_##_id] = {                                                   \
-               .name           = #_id,                                         \
-               .supply_name    = (_supply),                                    \
-               .of_match       = of_match_ptr(_match),                         \
-               .regulators_node = of_match_ptr("regulators"),                  \
-               .type           = REGULATOR_VOLTAGE,                            \
--              .id             = AXP20X_##_id,                                 \
-+              .id             = _family##_##_id,                              \
-               .n_voltages     = (((_max) - (_min)) / (_step) + 1),            \
-               .owner          = THIS_MODULE,                                  \
-               .min_uV         = (_min) * 1000,                                \
-@@ -74,29 +74,29 @@
-               .ops            = &axp20x_ops,                                  \
-       }
--#define AXP20X_DESC_FIXED(_id, _match, _supply, _volt)                                \
--      [AXP20X_##_id] = {                                                      \
-+#define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt)                  \
-+      [_family##_##_id] = {                                                   \
-               .name           = #_id,                                         \
-               .supply_name    = (_supply),                                    \
-               .of_match       = of_match_ptr(_match),                         \
-               .regulators_node = of_match_ptr("regulators"),                  \
-               .type           = REGULATOR_VOLTAGE,                            \
--              .id             = AXP20X_##_id,                                 \
-+              .id             = _family##_##_id,                              \
-               .n_voltages     = 1,                                            \
-               .owner          = THIS_MODULE,                                  \
-               .min_uV         = (_volt) * 1000,                               \
-               .ops            = &axp20x_ops_fixed                             \
-       }
--#define AXP20X_DESC_TABLE(_id, _match, _supply, _table, _vreg, _vmask, _ereg, \
--                        _emask)                                               \
--      [AXP20X_##_id] = {                                                      \
-+#define AXP_DESC_TABLE(_family, _id, _match, _supply, _table, _vreg, _vmask,  \
-+                     _ereg, _emask)                                           \
-+      [_family##_##_id] = {                                                   \
-               .name           = #_id,                                         \
-               .supply_name    = (_supply),                                    \
-               .of_match       = of_match_ptr(_match),                         \
-               .regulators_node = of_match_ptr("regulators"),                  \
-               .type           = REGULATOR_VOLTAGE,                            \
--              .id             = AXP20X_##_id,                                 \
-+              .id             = _family##_##_id,                              \
-               .n_voltages     = ARRAY_SIZE(_table),                           \
-               .owner          = THIS_MODULE,                                  \
-               .vsel_reg       = (_vreg),                                      \
-@@ -136,37 +136,57 @@ static struct regulator_ops axp20x_ops =
- };
- static const struct regulator_desc axp20x_regulators[] = {
--      AXP20X_DESC(DCDC2, "dcdc2", "vin2", 700, 2275, 25, AXP20X_DCDC2_V_OUT,
--                  0x3f, AXP20X_PWR_OUT_CTRL, 0x10),
--      AXP20X_DESC(DCDC3, "dcdc3", "vin3", 700, 3500, 25, AXP20X_DCDC3_V_OUT,
--                  0x7f, AXP20X_PWR_OUT_CTRL, 0x02),
--      AXP20X_DESC_FIXED(LDO1, "ldo1", "acin", 1300),
--      AXP20X_DESC(LDO2, "ldo2", "ldo24in", 1800, 3300, 100,
--                  AXP20X_LDO24_V_OUT, 0xf0, AXP20X_PWR_OUT_CTRL, 0x04),
--      AXP20X_DESC(LDO3, "ldo3", "ldo3in", 700, 3500, 25, AXP20X_LDO3_V_OUT,
--                  0x7f, AXP20X_PWR_OUT_CTRL, 0x40),
--      AXP20X_DESC_TABLE(LDO4, "ldo4", "ldo24in", axp20x_ldo4_data,
--                        AXP20X_LDO24_V_OUT, 0x0f, AXP20X_PWR_OUT_CTRL, 0x08),
--      AXP20X_DESC_IO(LDO5, "ldo5", "ldo5in", 1800, 3300, 100,
--                     AXP20X_LDO5_V_OUT, 0xf0, AXP20X_GPIO0_CTRL, 0x07,
--                     AXP20X_IO_ENABLED, AXP20X_IO_DISABLED),
-+      AXP_DESC(AXP20X, DCDC2, "dcdc2", "vin2", 700, 2275, 25,
-+               AXP20X_DCDC2_V_OUT, 0x3f, AXP20X_PWR_OUT_CTRL, 0x10),
-+      AXP_DESC(AXP20X, DCDC3, "dcdc3", "vin3", 700, 3500, 25,
-+               AXP20X_DCDC3_V_OUT, 0x7f, AXP20X_PWR_OUT_CTRL, 0x02),
-+      AXP_DESC_FIXED(AXP20X, LDO1, "ldo1", "acin", 1300),
-+      AXP_DESC(AXP20X, LDO2, "ldo2", "ldo24in", 1800, 3300, 100,
-+               AXP20X_LDO24_V_OUT, 0xf0, AXP20X_PWR_OUT_CTRL, 0x04),
-+      AXP_DESC(AXP20X, LDO3, "ldo3", "ldo3in", 700, 3500, 25,
-+               AXP20X_LDO3_V_OUT, 0x7f, AXP20X_PWR_OUT_CTRL, 0x40),
-+      AXP_DESC_TABLE(AXP20X, LDO4, "ldo4", "ldo24in", axp20x_ldo4_data,
-+                     AXP20X_LDO24_V_OUT, 0x0f, AXP20X_PWR_OUT_CTRL, 0x08),
-+      AXP_DESC_IO(AXP20X, LDO5, "ldo5", "ldo5in", 1800, 3300, 100,
-+                  AXP20X_LDO5_V_OUT, 0xf0, AXP20X_GPIO0_CTRL, 0x07,
-+                  AXP20X_IO_ENABLED, AXP20X_IO_DISABLED),
- };
- static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)
- {
-       struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
-+      u32 min, max, def, step;
--      if (dcdcfreq < 750) {
--              dcdcfreq = 750;
--              dev_warn(&pdev->dev, "DCDC frequency too low. Set to 750kHz\n");
-+      switch (axp20x->variant) {
-+      case AXP202_ID:
-+      case AXP209_ID:
-+              min = 750;
-+              max = 1875;
-+              def = 1500;
-+              step = 75;
-+              break;
-+      default:
-+              dev_err(&pdev->dev,
-+                      "Setting DCDC frequency for unsupported AXP variant\n");
-+              return -EINVAL;
-       }
--      if (dcdcfreq > 1875) {
--              dcdcfreq = 1875;
--              dev_warn(&pdev->dev, "DCDC frequency too high. Set to 1875kHz\n");
-+      if (dcdcfreq == 0)
-+              dcdcfreq = def;
-+
-+      if (dcdcfreq < min) {
-+              dcdcfreq = min;
-+              dev_warn(&pdev->dev, "DCDC frequency too low. Set to %ukHz\n",
-+                       min);
-       }
--      dcdcfreq = (dcdcfreq - 750) / 75;
-+      if (dcdcfreq > max) {
-+              dcdcfreq = max;
-+              dev_warn(&pdev->dev, "DCDC frequency too high. Set to %ukHz\n",
-+                       max);
-+      }
-+
-+      dcdcfreq = (dcdcfreq - min) / step;
-       return regmap_update_bits(axp20x->regmap, AXP20X_DCDC_FREQ,
-                                 AXP20X_FREQ_DCDC_MASK, dcdcfreq);
-@@ -176,7 +196,7 @@ static int axp20x_regulator_parse_dt(str
- {
-       struct device_node *np, *regulators;
-       int ret;
--      u32 dcdcfreq;
-+      u32 dcdcfreq = 0;
-       np = of_node_get(pdev->dev.parent->of_node);
-       if (!np)
-@@ -186,7 +206,6 @@ static int axp20x_regulator_parse_dt(str
-       if (!regulators) {
-               dev_warn(&pdev->dev, "regulators node not found\n");
-       } else {
--              dcdcfreq = 1500;
-               of_property_read_u32(regulators, "x-powers,dcdc-freq", &dcdcfreq);
-               ret = axp20x_set_dcdc_freq(pdev, dcdcfreq);
-               if (ret < 0) {
-@@ -202,15 +221,27 @@ static int axp20x_regulator_parse_dt(str
- static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 workmode)
- {
--      unsigned int mask = AXP20X_WORKMODE_DCDC2_MASK;
-+      struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
-+      unsigned int mask;
--      if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3))
-+      switch (axp20x->variant) {
-+      case AXP202_ID:
-+      case AXP209_ID:
-+              if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3))
-+                      return -EINVAL;
-+
-+              mask = AXP20X_WORKMODE_DCDC2_MASK;
-+              if (id == AXP20X_DCDC3)
-+                      mask = AXP20X_WORKMODE_DCDC3_MASK;
-+
-+              workmode <<= ffs(mask) - 1;
-+              break;
-+
-+      default:
-+              /* should not happen */
-+              WARN_ON(1);
-               return -EINVAL;
--
--      if (id == AXP20X_DCDC3)
--              mask = AXP20X_WORKMODE_DCDC3_MASK;
--
--      workmode <<= ffs(mask) - 1;
-+      }
-       return regmap_update_bits(rdev->regmap, AXP20X_DCDC_MODE, mask, workmode);
- }
-@@ -219,22 +250,36 @@ static int axp20x_regulator_probe(struct
- {
-       struct regulator_dev *rdev;
-       struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
-+      const struct regulator_desc *regulators;
-       struct regulator_config config = {
-               .dev = pdev->dev.parent,
-               .regmap = axp20x->regmap,
-+              .driver_data = axp20x,
-       };
--      int ret, i;
-+      int ret, i, nregulators;
-       u32 workmode;
-+      switch (axp20x->variant) {
-+      case AXP202_ID:
-+      case AXP209_ID:
-+              regulators = axp20x_regulators;
-+              nregulators = AXP20X_REG_ID_MAX;
-+              break;
-+      default:
-+              dev_err(&pdev->dev, "Unsupported AXP variant: %ld\n",
-+                      axp20x->variant);
-+              return -EINVAL;
-+      }
-+
-       /* This only sets the dcdc freq. Ignore any errors */
-       axp20x_regulator_parse_dt(pdev);
--      for (i = 0; i < AXP20X_REG_ID_MAX; i++) {
--              rdev = devm_regulator_register(&pdev->dev, &axp20x_regulators[i],
-+      for (i = 0; i < nregulators; i++) {
-+              rdev = devm_regulator_register(&pdev->dev, &regulators[i],
-                                              &config);
-               if (IS_ERR(rdev)) {
-                       dev_err(&pdev->dev, "Failed to register %s\n",
--                              axp20x_regulators[i].name);
-+                              regulators[i].name);
-                       return PTR_ERR(rdev);
-               }
-@@ -245,7 +290,7 @@ static int axp20x_regulator_probe(struct
-               if (!ret) {
-                       if (axp20x_set_dcdc_workmode(rdev, i, workmode))
-                               dev_err(&pdev->dev, "Failed to set workmode on %s\n",
--                                      axp20x_regulators[i].name);
-+                                      rdev->desc->name);
-               }
-       }
diff --git a/target/linux/sunxi/patches-4.1/102-regulator-axp20x-add-support-for-axp22.patch b/target/linux/sunxi/patches-4.1/102-regulator-axp20x-add-support-for-axp22.patch
deleted file mode 100644 (file)
index cc5bc4f..0000000
+++ /dev/null
@@ -1,170 +0,0 @@
-From c3f89434c9d778572cf09e8327bd047b11d48b90 Mon Sep 17 00:00:00 2001
-From: Boris BREZILLON <boris.brezillon@free-electrons.com>
-Date: Fri, 10 Apr 2015 12:09:04 +0800
-Subject: [PATCH] regulator: axp20x: Add support for AXP22X regulators
-
-Add AXP22X regulator definitions and variant id associations.
-This introduces a new "switch" type output for one of the regulators.
-It is a switchable secondary output of one regulator, with the same
-voltage level as the primary output.
-
-Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
-[wens@csie.org: Moved variant choosing to multi family support patch]
-[wens@csie.org: Add dc-dc work frequency range]
-[wens@csie.org: Add "switch" type output regulator DC1SW]
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Reviewed-by: Mark Brown <broonie@kernel.org>
-Signed-off-by: Lee Jones <lee.jones@linaro.org>
----
- drivers/regulator/axp20x-regulator.c | 96 ++++++++++++++++++++++++++++++++++++
- 1 file changed, 96 insertions(+)
-
---- a/drivers/regulator/axp20x-regulator.c
-+++ b/drivers/regulator/axp20x-regulator.c
-@@ -27,8 +27,12 @@
- #define AXP20X_IO_ENABLED             0x03
- #define AXP20X_IO_DISABLED            0x07
-+#define AXP22X_IO_ENABLED             0x04
-+#define AXP22X_IO_DISABLED            0x03
-+
- #define AXP20X_WORKMODE_DCDC2_MASK    BIT(2)
- #define AXP20X_WORKMODE_DCDC3_MASK    BIT(1)
-+#define AXP22X_WORKMODE_DCDCX_MASK(x) BIT(x)
- #define AXP20X_FREQ_DCDC_MASK         0x0f
-@@ -74,6 +78,26 @@
-               .ops            = &axp20x_ops,                                  \
-       }
-+#define AXP_DESC_SW(_family, _id, _match, _supply, _min, _max, _step, _vreg,  \
-+                  _vmask, _ereg, _emask)                                      \
-+      [_family##_##_id] = {                                                   \
-+              .name           = #_id,                                         \
-+              .supply_name    = (_supply),                                    \
-+              .of_match       = of_match_ptr(_match),                         \
-+              .regulators_node = of_match_ptr("regulators"),                  \
-+              .type           = REGULATOR_VOLTAGE,                            \
-+              .id             = _family##_##_id,                              \
-+              .n_voltages     = (((_max) - (_min)) / (_step) + 1),            \
-+              .owner          = THIS_MODULE,                                  \
-+              .min_uV         = (_min) * 1000,                                \
-+              .uV_step        = (_step) * 1000,                               \
-+              .vsel_reg       = (_vreg),                                      \
-+              .vsel_mask      = (_vmask),                                     \
-+              .enable_reg     = (_ereg),                                      \
-+              .enable_mask    = (_emask),                                     \
-+              .ops            = &axp20x_ops_sw,                               \
-+      }
-+
- #define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt)                  \
-       [_family##_##_id] = {                                                   \
-               .name           = #_id,                                         \
-@@ -135,6 +159,14 @@ static struct regulator_ops axp20x_ops =
-       .is_enabled             = regulator_is_enabled_regmap,
- };
-+static struct regulator_ops axp20x_ops_sw = {
-+      .get_voltage_sel        = regulator_get_voltage_sel_regmap,
-+      .list_voltage           = regulator_list_voltage_linear,
-+      .enable                 = regulator_enable_regmap,
-+      .disable                = regulator_disable_regmap,
-+      .is_enabled             = regulator_is_enabled_regmap,
-+};
-+
- static const struct regulator_desc axp20x_regulators[] = {
-       AXP_DESC(AXP20X, DCDC2, "dcdc2", "vin2", 700, 2275, 25,
-                AXP20X_DCDC2_V_OUT, 0x3f, AXP20X_PWR_OUT_CTRL, 0x10),
-@@ -152,6 +184,52 @@ static const struct regulator_desc axp20
-                   AXP20X_IO_ENABLED, AXP20X_IO_DISABLED),
- };
-+static const struct regulator_desc axp22x_regulators[] = {
-+      AXP_DESC(AXP22X, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
-+               AXP22X_DCDC1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(1)),
-+      AXP_DESC(AXP22X, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
-+               AXP22X_DCDC2_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, BIT(2)),
-+      AXP_DESC(AXP22X, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
-+               AXP22X_DCDC3_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, BIT(3)),
-+      AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20,
-+               AXP22X_DCDC4_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, BIT(3)),
-+      AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
-+               AXP22X_DCDC5_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(4)),
-+      /* secondary switchable output of DCDC1 */
-+      AXP_DESC_SW(AXP22X, DC1SW, "dc1sw", "dcdc1", 1600, 3400, 100,
-+                  AXP22X_DCDC1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(7)),
-+      /* LDO regulator internally chained to DCDC5 */
-+      AXP_DESC(AXP22X, DC5LDO, "dc5ldo", "dcdc5", 700, 1400, 100,
-+               AXP22X_DC5LDO_V_OUT, 0x7, AXP22X_PWR_OUT_CTRL1, BIT(0)),
-+      AXP_DESC(AXP22X, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
-+               AXP22X_ALDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(6)),
-+      AXP_DESC(AXP22X, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
-+               AXP22X_ALDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(7)),
-+      AXP_DESC(AXP22X, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
-+               AXP22X_ALDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(7)),
-+      AXP_DESC(AXP22X, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
-+               AXP22X_DLDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(3)),
-+      AXP_DESC(AXP22X, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
-+               AXP22X_DLDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(4)),
-+      AXP_DESC(AXP22X, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
-+               AXP22X_DLDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(5)),
-+      AXP_DESC(AXP22X, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
-+               AXP22X_DLDO4_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(6)),
-+      AXP_DESC(AXP22X, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
-+               AXP22X_ELDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(0)),
-+      AXP_DESC(AXP22X, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
-+               AXP22X_ELDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(1)),
-+      AXP_DESC(AXP22X, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
-+               AXP22X_ELDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(2)),
-+      AXP_DESC_IO(AXP22X, LDO_IO0, "ldo_io0", "ips", 1800, 3300, 100,
-+                  AXP22X_LDO_IO0_V_OUT, 0x1f, AXP20X_GPIO0_CTRL, 0x07,
-+                  AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
-+      AXP_DESC_IO(AXP22X, LDO_IO1, "ldo_io1", "ips", 1800, 3300, 100,
-+                  AXP22X_LDO_IO1_V_OUT, 0x1f, AXP20X_GPIO1_CTRL, 0x07,
-+                  AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
-+      AXP_DESC_FIXED(AXP22X, RTC_LDO, "rtc_ldo", "ips", 3000),
-+};
-+
- static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)
- {
-       struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
-@@ -165,6 +243,12 @@ static int axp20x_set_dcdc_freq(struct p
-               def = 1500;
-               step = 75;
-               break;
-+      case AXP221_ID:
-+              min = 1800;
-+              max = 4050;
-+              def = 3000;
-+              step = 150;
-+              break;
-       default:
-               dev_err(&pdev->dev,
-                       "Setting DCDC frequency for unsupported AXP variant\n");
-@@ -237,6 +321,14 @@ static int axp20x_set_dcdc_workmode(stru
-               workmode <<= ffs(mask) - 1;
-               break;
-+      case AXP221_ID:
-+              if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5)
-+                      return -EINVAL;
-+
-+              mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP22X_DCDC1);
-+              workmode <<= id - AXP22X_DCDC1;
-+              break;
-+
-       default:
-               /* should not happen */
-               WARN_ON(1);
-@@ -265,6 +357,10 @@ static int axp20x_regulator_probe(struct
-               regulators = axp20x_regulators;
-               nregulators = AXP20X_REG_ID_MAX;
-               break;
-+      case AXP221_ID:
-+              regulators = axp22x_regulators;
-+              nregulators = AXP22X_REG_ID_MAX;
-+              break;
-       default:
-               dev_err(&pdev->dev, "Unsupported AXP variant: %ld\n",
-                       axp20x->variant);
diff --git a/target/linux/sunxi/patches-4.1/103-mfd-axp20x-add-missing-registers.patch b/target/linux/sunxi/patches-4.1/103-mfd-axp20x-add-missing-registers.patch
deleted file mode 100644 (file)
index a458579..0000000
+++ /dev/null
@@ -1,71 +0,0 @@
-From 5469e15c9a0025e8822762ab9acfc3ee50e55c2c Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Bruno=20Pr=C3=A9mont?= <bonbons@linux-vserver.org>
-Date: Tue, 9 Jun 2015 08:30:48 +0200
-Subject: [PATCH] mfd: axp20x: Add missing registers, and mark more registers
- volatile
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Add an extra set of registers which is necessary tu support the PMICs
-battery charger function, and mark registers which contain status bits,
-gpio status, and adc readings as volatile.
-
-Cc: Bruno Prémont <bonbons@linux-vserver.org>
-Signed-off-by: Bruno Prémont <bonbons@linux-vserver.org>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
-Acked-by: Lee Jones <lee.jones@linaro.org>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
-Changes in v2:
--Add a AXP20X_OCV_MAX define
-Changes in v3:
--Add Bruno's S-o-b
----
- drivers/mfd/axp20x.c       | 8 +++++++-
- include/linux/mfd/axp20x.h | 6 ++++++
- 2 files changed, 13 insertions(+), 1 deletion(-)
-
---- a/drivers/mfd/axp20x.c
-+++ b/drivers/mfd/axp20x.c
-@@ -39,10 +39,16 @@ static const char * const axp20x_model_n
- static const struct regmap_range axp20x_writeable_ranges[] = {
-       regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
-       regmap_reg_range(AXP20X_DCDC_MODE, AXP20X_FG_RES),
-+      regmap_reg_range(AXP20X_RDC_H, AXP20X_OCV(15)),
- };
- static const struct regmap_range axp20x_volatile_ranges[] = {
-+      regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_USB_OTG_STATUS),
-+      regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2),
-       regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
-+      regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L),
-+      regmap_reg_range(AXP20X_GPIO20_SS, AXP20X_GPIO3_CTRL),
-+      regmap_reg_range(AXP20X_FG_RES, AXP20X_RDC_L),
- };
- static const struct regmap_access_table axp20x_writeable_table = {
-@@ -159,7 +165,7 @@ static const struct regmap_config axp20x
-       .val_bits       = 8,
-       .wr_table       = &axp20x_writeable_table,
-       .volatile_table = &axp20x_volatile_table,
--      .max_register   = AXP20X_FG_RES,
-+      .max_register   = AXP20X_OCV(AXP20X_OCV_MAX),
-       .cache_type     = REGCACHE_RBTREE,
- };
---- a/include/linux/mfd/axp20x.h
-+++ b/include/linux/mfd/axp20x.h
-@@ -151,6 +151,12 @@ enum {
- #define AXP20X_CC_CTRL                        0xb8
- #define AXP20X_FG_RES                 0xb9
-+/* OCV */
-+#define AXP20X_RDC_H                  0xba
-+#define AXP20X_RDC_L                  0xbb
-+#define AXP20X_OCV(m)                 (0xc0 + (m))
-+#define AXP20X_OCV_MAX                        0xf
-+
- /* AXP22X specific registers */
- #define AXP22X_BATLOW_THRES1          0xe6
diff --git a/target/linux/sunxi/patches-4.1/104-mfd-axp20x-enable-axp22x.patch b/target/linux/sunxi/patches-4.1/104-mfd-axp20x-enable-axp22x.patch
deleted file mode 100644 (file)
index f0c9055..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-From 6d4fa89dcd85e2427da83319ce75e5df5febcc96 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Fri, 10 Apr 2015 12:09:06 +0800
-Subject: [PATCH] mfd: axp20x: Enable AXP22X regulators
-
-Now that the axp20x-regulators driver supports different variants of the
-AXP family, we can enable regulator support for AXP22X without the risk
-of incorrectly configuring regulators.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: Lee Jones <lee.jones@linaro.org>
----
- drivers/mfd/axp20x.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/mfd/axp20x.c
-+++ b/drivers/mfd/axp20x.c
-@@ -376,6 +376,8 @@ static struct mfd_cell axp22x_cells[] =
-               .name                   = "axp20x-pek",
-               .num_resources          = ARRAY_SIZE(axp22x_pek_resources),
-               .resources              = axp22x_pek_resources,
-+      }, {
-+              .name                   = "axp20x-regulator",
-       },
- };
diff --git a/target/linux/sunxi/patches-4.1/105-mfd-axp20x-add-axp152-support.patch b/target/linux/sunxi/patches-4.1/105-mfd-axp20x-add-axp152-support.patch
deleted file mode 100644 (file)
index a653f94..0000000
+++ /dev/null
@@ -1,261 +0,0 @@
-From a50e5abe10c95108ece5d3a91027570e66b5f238 Mon Sep 17 00:00:00 2001
-From: Michal Suchanek <hramrach@gmail.com>
-Date: Sat, 11 Jul 2015 14:59:56 +0200
-Subject: [PATCH] mfd: axp20x: Add axp152 support
-
-The axp152 is a stripped down version of the axp202 pmic with the battery
-charging function removed as it is intended for top-set boxes.
-
-Signed-off-by: Michal Suchanek <hramrach@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
-Signed-off-by: Lee Jones <lee.jones@linaro.org>
----
- drivers/mfd/axp20x.c       | 83 ++++++++++++++++++++++++++++++++++++++++++++++
- include/linux/mfd/axp20x.h | 61 +++++++++++++++++++++++++++++++++-
- 2 files changed, 143 insertions(+), 1 deletion(-)
-
---- a/drivers/mfd/axp20x.c
-+++ b/drivers/mfd/axp20x.c
-@@ -30,12 +30,34 @@
- #define AXP20X_OFF    0x80
- static const char * const axp20x_model_names[] = {
-+      "AXP152",
-       "AXP202",
-       "AXP209",
-       "AXP221",
-       "AXP288",
- };
-+static const struct regmap_range axp152_writeable_ranges[] = {
-+      regmap_reg_range(AXP152_LDO3456_DC1234_CTRL, AXP152_IRQ3_STATE),
-+      regmap_reg_range(AXP152_DCDC_MODE, AXP152_PWM1_DUTY_CYCLE),
-+};
-+
-+static const struct regmap_range axp152_volatile_ranges[] = {
-+      regmap_reg_range(AXP152_PWR_OP_MODE, AXP152_PWR_OP_MODE),
-+      regmap_reg_range(AXP152_IRQ1_EN, AXP152_IRQ3_STATE),
-+      regmap_reg_range(AXP152_GPIO_INPUT, AXP152_GPIO_INPUT),
-+};
-+
-+static const struct regmap_access_table axp152_writeable_table = {
-+      .yes_ranges     = axp152_writeable_ranges,
-+      .n_yes_ranges   = ARRAY_SIZE(axp152_writeable_ranges),
-+};
-+
-+static const struct regmap_access_table axp152_volatile_table = {
-+      .yes_ranges     = axp152_volatile_ranges,
-+      .n_yes_ranges   = ARRAY_SIZE(axp152_volatile_ranges),
-+};
-+
- static const struct regmap_range axp20x_writeable_ranges[] = {
-       regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
-       regmap_reg_range(AXP20X_DCDC_MODE, AXP20X_FG_RES),
-@@ -99,6 +121,11 @@ static const struct regmap_access_table
-       .n_yes_ranges   = ARRAY_SIZE(axp288_volatile_ranges),
- };
-+static struct resource axp152_pek_resources[] = {
-+      DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
-+      DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
-+};
-+
- static struct resource axp20x_pek_resources[] = {
-       {
-               .name   = "PEK_DBR",
-@@ -160,6 +187,15 @@ static struct resource axp288_fuel_gauge
-       },
- };
-+static const struct regmap_config axp152_regmap_config = {
-+      .reg_bits       = 8,
-+      .val_bits       = 8,
-+      .wr_table       = &axp152_writeable_table,
-+      .volatile_table = &axp152_volatile_table,
-+      .max_register   = AXP152_PWM1_DUTY_CYCLE,
-+      .cache_type     = REGCACHE_RBTREE,
-+};
-+
- static const struct regmap_config axp20x_regmap_config = {
-       .reg_bits       = 8,
-       .val_bits       = 8,
-@@ -190,6 +226,26 @@ static const struct regmap_config axp288
- #define INIT_REGMAP_IRQ(_variant, _irq, _off, _mask)                  \
-       [_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) }
-+static const struct regmap_irq axp152_regmap_irqs[] = {
-+      INIT_REGMAP_IRQ(AXP152, LDO0IN_CONNECT,         0, 6),
-+      INIT_REGMAP_IRQ(AXP152, LDO0IN_REMOVAL,         0, 5),
-+      INIT_REGMAP_IRQ(AXP152, ALDO0IN_CONNECT,        0, 3),
-+      INIT_REGMAP_IRQ(AXP152, ALDO0IN_REMOVAL,        0, 2),
-+      INIT_REGMAP_IRQ(AXP152, DCDC1_V_LOW,            1, 5),
-+      INIT_REGMAP_IRQ(AXP152, DCDC2_V_LOW,            1, 4),
-+      INIT_REGMAP_IRQ(AXP152, DCDC3_V_LOW,            1, 3),
-+      INIT_REGMAP_IRQ(AXP152, DCDC4_V_LOW,            1, 2),
-+      INIT_REGMAP_IRQ(AXP152, PEK_SHORT,              1, 1),
-+      INIT_REGMAP_IRQ(AXP152, PEK_LONG,               1, 0),
-+      INIT_REGMAP_IRQ(AXP152, TIMER,                  2, 7),
-+      INIT_REGMAP_IRQ(AXP152, PEK_RIS_EDGE,           2, 6),
-+      INIT_REGMAP_IRQ(AXP152, PEK_FAL_EDGE,           2, 5),
-+      INIT_REGMAP_IRQ(AXP152, GPIO3_INPUT,            2, 3),
-+      INIT_REGMAP_IRQ(AXP152, GPIO2_INPUT,            2, 2),
-+      INIT_REGMAP_IRQ(AXP152, GPIO1_INPUT,            2, 1),
-+      INIT_REGMAP_IRQ(AXP152, GPIO0_INPUT,            2, 0),
-+};
-+
- static const struct regmap_irq axp20x_regmap_irqs[] = {
-       INIT_REGMAP_IRQ(AXP20X, ACIN_OVER_V,            0, 7),
-       INIT_REGMAP_IRQ(AXP20X, ACIN_PLUGIN,            0, 6),
-@@ -299,6 +355,7 @@ static const struct regmap_irq axp288_re
- };
- static const struct of_device_id axp20x_of_match[] = {
-+      { .compatible = "x-powers,axp152", .data = (void *) AXP152_ID },
-       { .compatible = "x-powers,axp202", .data = (void *) AXP202_ID },
-       { .compatible = "x-powers,axp209", .data = (void *) AXP209_ID },
-       { .compatible = "x-powers,axp221", .data = (void *) AXP221_ID },
-@@ -323,6 +380,18 @@ static const struct acpi_device_id axp20
- };
- MODULE_DEVICE_TABLE(acpi, axp20x_acpi_match);
-+static const struct regmap_irq_chip axp152_regmap_irq_chip = {
-+      .name                   = "axp152_irq_chip",
-+      .status_base            = AXP152_IRQ1_STATE,
-+      .ack_base               = AXP152_IRQ1_STATE,
-+      .mask_base              = AXP152_IRQ1_EN,
-+      .mask_invert            = true,
-+      .init_ack_masked        = true,
-+      .irqs                   = axp152_regmap_irqs,
-+      .num_irqs               = ARRAY_SIZE(axp152_regmap_irqs),
-+      .num_regs               = 3,
-+};
-+
- static const struct regmap_irq_chip axp20x_regmap_irq_chip = {
-       .name                   = "axp20x_irq_chip",
-       .status_base            = AXP20X_IRQ1_STATE,
-@@ -381,6 +450,14 @@ static struct mfd_cell axp22x_cells[] =
-       },
- };
-+static struct mfd_cell axp152_cells[] = {
-+      {
-+              .name                   = "axp20x-pek",
-+              .num_resources          = ARRAY_SIZE(axp152_pek_resources),
-+              .resources              = axp152_pek_resources,
-+      },
-+};
-+
- static struct resource axp288_adc_resources[] = {
-       {
-               .name  = "GPADC",
-@@ -519,6 +596,12 @@ static int axp20x_match_device(struct ax
-       }
-       switch (axp20x->variant) {
-+      case AXP152_ID:
-+              axp20x->nr_cells = ARRAY_SIZE(axp152_cells);
-+              axp20x->cells = axp152_cells;
-+              axp20x->regmap_cfg = &axp152_regmap_config;
-+              axp20x->regmap_irq_chip = &axp152_regmap_irq_chip;
-+              break;
-       case AXP202_ID:
-       case AXP209_ID:
-               axp20x->nr_cells = ARRAY_SIZE(axp20x_cells);
---- a/include/linux/mfd/axp20x.h
-+++ b/include/linux/mfd/axp20x.h
-@@ -12,7 +12,8 @@
- #define __LINUX_MFD_AXP20X_H
- enum {
--      AXP202_ID = 0,
-+      AXP152_ID = 0,
-+      AXP202_ID,
-       AXP209_ID,
-       AXP221_ID,
-       AXP288_ID,
-@@ -22,6 +23,24 @@ enum {
- #define AXP20X_DATACACHE(m)           (0x04 + (m))
- /* Power supply */
-+#define AXP152_PWR_OP_MODE            0x01
-+#define AXP152_LDO3456_DC1234_CTRL    0x12
-+#define AXP152_ALDO_OP_MODE           0x13
-+#define AXP152_LDO0_CTRL              0x15
-+#define AXP152_DCDC2_V_OUT            0x23
-+#define AXP152_DCDC2_V_SCAL           0x25
-+#define AXP152_DCDC1_V_OUT            0x26
-+#define AXP152_DCDC3_V_OUT            0x27
-+#define AXP152_ALDO12_V_OUT           0x28
-+#define AXP152_DLDO1_V_OUT            0x29
-+#define AXP152_DLDO2_V_OUT            0x2a
-+#define AXP152_DCDC4_V_OUT            0x2b
-+#define AXP152_V_OFF                  0x31
-+#define AXP152_OFF_CTRL                       0x32
-+#define AXP152_PEK_KEY                        0x36
-+#define AXP152_DCDC_FREQ              0x37
-+#define AXP152_DCDC_MODE              0x80
-+
- #define AXP20X_PWR_INPUT_STATUS               0x00
- #define AXP20X_PWR_OP_MODE            0x01
- #define AXP20X_USB_OTG_STATUS         0x02
-@@ -69,6 +88,13 @@ enum {
- #define AXP22X_CHRG_CTRL3             0x35
- /* Interrupt */
-+#define AXP152_IRQ1_EN                        0x40
-+#define AXP152_IRQ2_EN                        0x41
-+#define AXP152_IRQ3_EN                        0x42
-+#define AXP152_IRQ1_STATE             0x48
-+#define AXP152_IRQ2_STATE             0x49
-+#define AXP152_IRQ3_STATE             0x4a
-+
- #define AXP20X_IRQ1_EN                        0x40
- #define AXP20X_IRQ2_EN                        0x41
- #define AXP20X_IRQ3_EN                        0x42
-@@ -127,6 +153,19 @@ enum {
- #define AXP22X_PWREN_CTRL2            0x8d
- /* GPIO */
-+#define AXP152_GPIO0_CTRL             0x90
-+#define AXP152_GPIO1_CTRL             0x91
-+#define AXP152_GPIO2_CTRL             0x92
-+#define AXP152_GPIO3_CTRL             0x93
-+#define AXP152_LDOGPIO2_V_OUT         0x96
-+#define AXP152_GPIO_INPUT             0x97
-+#define AXP152_PWM0_FREQ_X            0x98
-+#define AXP152_PWM0_FREQ_Y            0x99
-+#define AXP152_PWM0_DUTY_CYCLE                0x9a
-+#define AXP152_PWM1_FREQ_X            0x9b
-+#define AXP152_PWM1_FREQ_Y            0x9c
-+#define AXP152_PWM1_DUTY_CYCLE                0x9d
-+
- #define AXP20X_GPIO0_CTRL             0x90
- #define AXP20X_LDO5_V_OUT             0x91
- #define AXP20X_GPIO1_CTRL             0x92
-@@ -224,6 +263,26 @@ enum {
- /* IRQs */
- enum {
-+      AXP152_IRQ_LDO0IN_CONNECT = 1,
-+      AXP152_IRQ_LDO0IN_REMOVAL,
-+      AXP152_IRQ_ALDO0IN_CONNECT,
-+      AXP152_IRQ_ALDO0IN_REMOVAL,
-+      AXP152_IRQ_DCDC1_V_LOW,
-+      AXP152_IRQ_DCDC2_V_LOW,
-+      AXP152_IRQ_DCDC3_V_LOW,
-+      AXP152_IRQ_DCDC4_V_LOW,
-+      AXP152_IRQ_PEK_SHORT,
-+      AXP152_IRQ_PEK_LONG,
-+      AXP152_IRQ_TIMER,
-+      AXP152_IRQ_PEK_RIS_EDGE,
-+      AXP152_IRQ_PEK_FAL_EDGE,
-+      AXP152_IRQ_GPIO3_INPUT,
-+      AXP152_IRQ_GPIO2_INPUT,
-+      AXP152_IRQ_GPIO1_INPUT,
-+      AXP152_IRQ_GPIO0_INPUT,
-+};
-+
-+enum {
-       AXP20X_IRQ_ACIN_OVER_V = 1,
-       AXP20X_IRQ_ACIN_PLUGIN,
-       AXP20X_IRQ_ACIN_REMOVAL,
diff --git a/target/linux/sunxi/patches-4.1/110-mtd-move-nand_ecc_ctrl-init.patch b/target/linux/sunxi/patches-4.1/110-mtd-move-nand_ecc_ctrl-init.patch
deleted file mode 100644 (file)
index f1af823..0000000
+++ /dev/null
@@ -1,135 +0,0 @@
-From 3282055a7d0a304d541dbdbe2e32167e1a2f117c Mon Sep 17 00:00:00 2001
-From: Boris BREZILLON <boris.brezillon@free-electrons.com>
-Date: Mon, 28 Jul 2014 14:20:54 +0200
-Subject: [PATCH] mtd: nand: Take nand_ecc_ctrl initialization out of
- nand_scan_tail
-
-Take ECC initialization code portion out of nand_scan_tail so that we can
-re-use this implementation.
-
-This commit only moves some code around and makes no functional changes.
-
-Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/mtd/nand/nand_base.c | 91 +++++++++++++++++++++++++++-----------------
- 1 file changed, 56 insertions(+), 35 deletions(-)
-
---- a/drivers/mtd/nand/nand_base.c
-+++ b/drivers/mtd/nand/nand_base.c
-@@ -3892,42 +3892,15 @@ static bool nand_ecc_strength_good(struc
-       return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
- }
--/**
-- * nand_scan_tail - [NAND Interface] Scan for the NAND device
-- * @mtd: MTD device structure
-- *
-- * This is the second phase of the normal nand_scan() function. It fills out
-- * all the uninitialized function pointers with the defaults and scans for a
-- * bad block table if appropriate.
-+/*
-+ * Initialize ECC struct:
-+ *  - fill ECC struct with default function/values when these ones are undefined
-+ *  - fill ECC infos based on MTD device
-  */
--int nand_scan_tail(struct mtd_info *mtd)
-+static int nand_ecc_ctrl_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc)
- {
-       int i;
--      struct nand_chip *chip = mtd->priv;
--      struct nand_ecc_ctrl *ecc = &chip->ecc;
--      struct nand_buffers *nbuf;
--      /* New bad blocks should be marked in OOB, flash-based BBT, or both */
--      BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
--                      !(chip->bbt_options & NAND_BBT_USE_FLASH));
--
--      if (!(chip->options & NAND_OWN_BUFFERS)) {
--              nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize
--                              + mtd->oobsize * 3, GFP_KERNEL);
--              if (!nbuf)
--                      return -ENOMEM;
--              nbuf->ecccalc = (uint8_t *)(nbuf + 1);
--              nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
--              nbuf->databuf = nbuf->ecccode + mtd->oobsize;
--
--              chip->buffers = nbuf;
--      } else {
--              if (!chip->buffers)
--                      return -ENOMEM;
--      }
--
--      /* Set the internal oob buffer location, just after the page data */
--      chip->oob_poi = chip->buffers->databuf + mtd->writesize;
-       /*
-        * If no default placement scheme is given, select an appropriate one.
-@@ -3953,9 +3926,6 @@ int nand_scan_tail(struct mtd_info *mtd)
-               }
-       }
--      if (!chip->write_page)
--              chip->write_page = nand_write_page;
--
-       /*
-        * Check ECC mode, default to software if 3byte/512byte hardware ECC is
-        * selected and we have 256 byte pagesize fallback to software ECC
-@@ -4125,6 +4095,57 @@ int nand_scan_tail(struct mtd_info *mtd)
-       }
-       ecc->total = ecc->steps * ecc->bytes;
-+      return 0;
-+}
-+
-+/**
-+ * nand_scan_tail - [NAND Interface] Scan for the NAND device
-+ * @mtd: MTD device structure
-+ *
-+ * This is the second phase of the normal nand_scan() function. It fills out
-+ * all the uninitialized function pointers with the defaults and scans for a
-+ * bad block table if appropriate.
-+ */
-+int nand_scan_tail(struct mtd_info *mtd)
-+{
-+      int ret;
-+      struct nand_chip *chip = mtd->priv;
-+      struct nand_ecc_ctrl *ecc = &chip->ecc;
-+      struct nand_buffers *nbuf;
-+
-+      /* New bad blocks should be marked in OOB, flash-based BBT, or both */
-+      BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
-+                      !(chip->bbt_options & NAND_BBT_USE_FLASH));
-+
-+      if (!(chip->options & NAND_OWN_BUFFERS)) {
-+              nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize
-+                              + mtd->oobsize * 3, GFP_KERNEL);
-+              if (!nbuf)
-+                      return -ENOMEM;
-+              nbuf->ecccalc = (uint8_t *)(nbuf + 1);
-+              nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
-+              nbuf->databuf = nbuf->ecccode + mtd->oobsize;
-+              chip->buffers = nbuf;
-+      } else {
-+              if (!chip->buffers)
-+                      return -ENOMEM;
-+      }
-+
-+      /* Set the internal oob buffer location, just after the page data */
-+      chip->oob_poi = chip->buffers->databuf + mtd->writesize;
-+
-+      if (!chip->write_page)
-+              chip->write_page = nand_write_page;
-+
-+      /* Initialize ECC struct */
-+      ret = nand_ecc_ctrl_init(mtd, ecc);
-+      if (ret) {
-+              if (!(chip->options & NAND_OWN_BUFFERS))
-+                      kfree(chip->buffers);
-+
-+              return ret;
-+      }
-+
-       /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
-       if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
-               switch (ecc->steps) {
diff --git a/target/linux/sunxi/patches-4.1/111-mtd-add-support-for-nand-partitions.patch b/target/linux/sunxi/patches-4.1/111-mtd-add-support-for-nand-partitions.patch
deleted file mode 100644 (file)
index d4eaeec..0000000
+++ /dev/null
@@ -1,1295 +0,0 @@
-From a95cc309cf74eed3fc457dec3dcc44d9bf79e0e6 Mon Sep 17 00:00:00 2001
-From: Boris BREZILLON <boris.brezillon@free-electrons.com>
-Date: Mon, 28 Jul 2014 15:01:15 +0200
-Subject: [PATCH] mtd: nand: Add support for NAND partitions
-
-Add support for NAND partitions, and indirectly for per partition ECC
-config, and also per partiton random seed support for the upcoming
-randomizer support.
-
-This is necessary to be able to use different ECC / randomizer settings for
-the parts of the NAND which are read directly by a bootrom (which has a
-fixed ECC / random seed setting) and the generic data part of the NAND for
-which we often want a stronger ECC and / or random seed.
-
-Provide helper functions to add/delete/allocate nand partitions.
-NAND core code now make use of the partition specific nand_ecc_ctrl struct
-(if available) when doing read/write operations.
-
-Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/mtd/nand/Kconfig     |   4 +
- drivers/mtd/nand/Makefile    |   2 +
- drivers/mtd/nand/nand_base.c | 712 +++++++++++++++++++++++++++++++++++--------
- drivers/mtd/nand/nand_bch.c  |  16 +-
- drivers/mtd/nand/nand_ecc.c  |   4 +-
- include/linux/mtd/nand.h     |  38 +++
- 6 files changed, 635 insertions(+), 141 deletions(-)
-
---- a/drivers/mtd/nand/Kconfig
-+++ b/drivers/mtd/nand/Kconfig
-@@ -22,6 +22,10 @@ menuconfig MTD_NAND
- if MTD_NAND
-+config MTD_OF_NAND_PARTS
-+      tristate
-+      default n
-+
- config MTD_NAND_BCH
-       tristate
-       select BCH
---- a/drivers/mtd/nand/Makefile
-+++ b/drivers/mtd/nand/Makefile
-@@ -53,4 +53,6 @@ obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) +=
- obj-$(CONFIG_MTD_NAND_SUNXI)          += sunxi_nand.o
- obj-$(CONFIG_MTD_NAND_HISI504)                += hisi504_nand.o
-+obj-$(CONFIG_MTD_OF_NAND_PARTS)               += ofnandpart.o
-+
- nand-objs := nand_base.o nand_bbt.o nand_timings.o
---- a/drivers/mtd/nand/nand_base.c
-+++ b/drivers/mtd/nand/nand_base.c
-@@ -1134,26 +1134,26 @@ static int nand_read_page_raw_syndrome(s
-                                      struct nand_chip *chip, uint8_t *buf,
-                                      int oob_required, int page)
- {
--      int eccsize = chip->ecc.size;
--      int eccbytes = chip->ecc.bytes;
-+      int eccsize = chip->cur_ecc->size;
-+      int eccbytes = chip->cur_ecc->bytes;
-       uint8_t *oob = chip->oob_poi;
-       int steps, size;
--      for (steps = chip->ecc.steps; steps > 0; steps--) {
-+      for (steps = chip->cur_ecc->steps; steps > 0; steps--) {
-               chip->read_buf(mtd, buf, eccsize);
-               buf += eccsize;
--              if (chip->ecc.prepad) {
--                      chip->read_buf(mtd, oob, chip->ecc.prepad);
--                      oob += chip->ecc.prepad;
-+              if (chip->cur_ecc->prepad) {
-+                      chip->read_buf(mtd, oob, chip->cur_ecc->prepad);
-+                      oob += chip->cur_ecc->prepad;
-               }
-               chip->read_buf(mtd, oob, eccbytes);
-               oob += eccbytes;
--              if (chip->ecc.postpad) {
--                      chip->read_buf(mtd, oob, chip->ecc.postpad);
--                      oob += chip->ecc.postpad;
-+              if (chip->cur_ecc->postpad) {
-+                      chip->read_buf(mtd, oob, chip->cur_ecc->postpad);
-+                      oob += chip->cur_ecc->postpad;
-               }
-       }
-@@ -1175,30 +1175,31 @@ static int nand_read_page_raw_syndrome(s
- static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
-                               uint8_t *buf, int oob_required, int page)
- {
--      int i, eccsize = chip->ecc.size;
--      int eccbytes = chip->ecc.bytes;
--      int eccsteps = chip->ecc.steps;
-+      int i, eccsize = chip->cur_ecc->size;
-+      int eccbytes = chip->cur_ecc->bytes;
-+      int eccsteps = chip->cur_ecc->steps;
-       uint8_t *p = buf;
-       uint8_t *ecc_calc = chip->buffers->ecccalc;
-       uint8_t *ecc_code = chip->buffers->ecccode;
--      uint32_t *eccpos = chip->ecc.layout->eccpos;
-+      uint32_t *eccpos = chip->cur_ecc->layout->eccpos;
-       unsigned int max_bitflips = 0;
--      chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
-+      chip->cur_ecc->read_page_raw(mtd, chip, buf, 1, page);
-       for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
--              chip->ecc.calculate(mtd, p, &ecc_calc[i]);
-+              chip->cur_ecc->calculate(mtd, p, &ecc_calc[i]);
--      for (i = 0; i < chip->ecc.total; i++)
-+      for (i = 0; i < chip->cur_ecc->total; i++)
-               ecc_code[i] = chip->oob_poi[eccpos[i]];
--      eccsteps = chip->ecc.steps;
-+      eccsteps = chip->cur_ecc->steps;
-       p = buf;
-       for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
-               int stat;
--              stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
-+              stat = chip->cur_ecc->correct(mtd, p, &ecc_code[i],
-+                                            &ecc_calc[i]);
-               if (stat < 0) {
-                       mtd->ecc_stats.failed++;
-               } else {
-@@ -1223,7 +1224,7 @@ static int nand_read_subpage(struct mtd_
-                       int page)
- {
-       int start_step, end_step, num_steps;
--      uint32_t *eccpos = chip->ecc.layout->eccpos;
-+      uint32_t *eccpos = chip->cur_ecc->layout->eccpos;
-       uint8_t *p;
-       int data_col_addr, i, gaps = 0;
-       int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
-@@ -1232,16 +1233,16 @@ static int nand_read_subpage(struct mtd_
-       unsigned int max_bitflips = 0;
-       /* Column address within the page aligned to ECC size (256bytes) */
--      start_step = data_offs / chip->ecc.size;
--      end_step = (data_offs + readlen - 1) / chip->ecc.size;
-+      start_step = data_offs / chip->cur_ecc->size;
-+      end_step = (data_offs + readlen - 1) / chip->cur_ecc->size;
-       num_steps = end_step - start_step + 1;
--      index = start_step * chip->ecc.bytes;
-+      index = start_step * chip->cur_ecc->bytes;
-       /* Data size aligned to ECC ecc.size */
--      datafrag_len = num_steps * chip->ecc.size;
--      eccfrag_len = num_steps * chip->ecc.bytes;
-+      datafrag_len = num_steps * chip->cur_ecc->size;
-+      eccfrag_len = num_steps * chip->cur_ecc->bytes;
--      data_col_addr = start_step * chip->ecc.size;
-+      data_col_addr = start_step * chip->cur_ecc->size;
-       /* If we read not a page aligned data */
-       if (data_col_addr != 0)
-               chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
-@@ -1250,8 +1251,9 @@ static int nand_read_subpage(struct mtd_
-       chip->read_buf(mtd, p, datafrag_len);
-       /* Calculate ECC */
--      for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
--              chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
-+      for (i = 0; i < eccfrag_len;
-+           i += chip->cur_ecc->bytes, p += chip->cur_ecc->size)
-+              chip->cur_ecc->calculate(mtd, p, &chip->buffers->ecccalc[i]);
-       /*
-        * The performance is faster if we position offsets according to
-@@ -1275,7 +1277,8 @@ static int nand_read_subpage(struct mtd_
-               aligned_len = eccfrag_len;
-               if (eccpos[index] & (busw - 1))
-                       aligned_len++;
--              if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
-+              if (eccpos[index + (num_steps * chip->cur_ecc->bytes)] &
-+                  (busw - 1))
-                       aligned_len++;
-               chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
-@@ -1287,11 +1290,13 @@ static int nand_read_subpage(struct mtd_
-               chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
-       p = bufpoi + data_col_addr;
--      for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
-+      for (i = 0; i < eccfrag_len;
-+           i += chip->cur_ecc->bytes, p += chip->cur_ecc->size) {
-               int stat;
--              stat = chip->ecc.correct(mtd, p,
--                      &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
-+              stat = chip->cur_ecc->correct(mtd, p,
-+                                            &chip->buffers->ecccode[i],
-+                                            &chip->buffers->ecccalc[i]);
-               if (stat < 0) {
-                       mtd->ecc_stats.failed++;
-               } else {
-@@ -1315,32 +1320,33 @@ static int nand_read_subpage(struct mtd_
- static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
-                               uint8_t *buf, int oob_required, int page)
- {
--      int i, eccsize = chip->ecc.size;
--      int eccbytes = chip->ecc.bytes;
--      int eccsteps = chip->ecc.steps;
-+      int i, eccsize = chip->cur_ecc->size;
-+      int eccbytes = chip->cur_ecc->bytes;
-+      int eccsteps = chip->cur_ecc->steps;
-       uint8_t *p = buf;
-       uint8_t *ecc_calc = chip->buffers->ecccalc;
-       uint8_t *ecc_code = chip->buffers->ecccode;
--      uint32_t *eccpos = chip->ecc.layout->eccpos;
-+      uint32_t *eccpos = chip->cur_ecc->layout->eccpos;
-       unsigned int max_bitflips = 0;
-       for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
--              chip->ecc.hwctl(mtd, NAND_ECC_READ);
-+              chip->cur_ecc->hwctl(mtd, NAND_ECC_READ);
-               chip->read_buf(mtd, p, eccsize);
--              chip->ecc.calculate(mtd, p, &ecc_calc[i]);
-+              chip->cur_ecc->calculate(mtd, p, &ecc_calc[i]);
-       }
-       chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
--      for (i = 0; i < chip->ecc.total; i++)
-+      for (i = 0; i < chip->cur_ecc->total; i++)
-               ecc_code[i] = chip->oob_poi[eccpos[i]];
--      eccsteps = chip->ecc.steps;
-+      eccsteps = chip->cur_ecc->steps;
-       p = buf;
-       for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
-               int stat;
--              stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
-+              stat = chip->cur_ecc->correct(mtd, p, &ecc_code[i],
-+                                            &ecc_calc[i]);
-               if (stat < 0) {
-                       mtd->ecc_stats.failed++;
-               } else {
-@@ -1368,12 +1374,12 @@ static int nand_read_page_hwecc(struct m
- static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
-       struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
- {
--      int i, eccsize = chip->ecc.size;
--      int eccbytes = chip->ecc.bytes;
--      int eccsteps = chip->ecc.steps;
-+      int i, eccsize = chip->cur_ecc->size;
-+      int eccbytes = chip->cur_ecc->bytes;
-+      int eccsteps = chip->cur_ecc->steps;
-       uint8_t *p = buf;
-       uint8_t *ecc_code = chip->buffers->ecccode;
--      uint32_t *eccpos = chip->ecc.layout->eccpos;
-+      uint32_t *eccpos = chip->cur_ecc->layout->eccpos;
-       uint8_t *ecc_calc = chip->buffers->ecccalc;
-       unsigned int max_bitflips = 0;
-@@ -1382,17 +1388,17 @@ static int nand_read_page_hwecc_oob_firs
-       chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
-       chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
--      for (i = 0; i < chip->ecc.total; i++)
-+      for (i = 0; i < chip->cur_ecc->total; i++)
-               ecc_code[i] = chip->oob_poi[eccpos[i]];
-       for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
-               int stat;
--              chip->ecc.hwctl(mtd, NAND_ECC_READ);
-+              chip->cur_ecc->hwctl(mtd, NAND_ECC_READ);
-               chip->read_buf(mtd, p, eccsize);
--              chip->ecc.calculate(mtd, p, &ecc_calc[i]);
-+              chip->cur_ecc->calculate(mtd, p, &ecc_calc[i]);
--              stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
-+              stat = chip->cur_ecc->correct(mtd, p, &ecc_code[i], NULL);
-               if (stat < 0) {
-                       mtd->ecc_stats.failed++;
-               } else {
-@@ -1417,9 +1423,9 @@ static int nand_read_page_hwecc_oob_firs
- static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
-                                  uint8_t *buf, int oob_required, int page)
- {
--      int i, eccsize = chip->ecc.size;
--      int eccbytes = chip->ecc.bytes;
--      int eccsteps = chip->ecc.steps;
-+      int i, eccsize = chip->cur_ecc->size;
-+      int eccbytes = chip->cur_ecc->bytes;
-+      int eccsteps = chip->cur_ecc->steps;
-       uint8_t *p = buf;
-       uint8_t *oob = chip->oob_poi;
-       unsigned int max_bitflips = 0;
-@@ -1427,17 +1433,17 @@ static int nand_read_page_syndrome(struc
-       for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
-               int stat;
--              chip->ecc.hwctl(mtd, NAND_ECC_READ);
-+              chip->cur_ecc->hwctl(mtd, NAND_ECC_READ);
-               chip->read_buf(mtd, p, eccsize);
--              if (chip->ecc.prepad) {
--                      chip->read_buf(mtd, oob, chip->ecc.prepad);
--                      oob += chip->ecc.prepad;
-+              if (chip->cur_ecc->prepad) {
-+                      chip->read_buf(mtd, oob, chip->cur_ecc->prepad);
-+                      oob += chip->cur_ecc->prepad;
-               }
--              chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
-+              chip->cur_ecc->hwctl(mtd, NAND_ECC_READSYN);
-               chip->read_buf(mtd, oob, eccbytes);
--              stat = chip->ecc.correct(mtd, p, oob, NULL);
-+              stat = chip->cur_ecc->correct(mtd, p, oob, NULL);
-               if (stat < 0) {
-                       mtd->ecc_stats.failed++;
-@@ -1448,9 +1454,9 @@ static int nand_read_page_syndrome(struc
-               oob += eccbytes;
--              if (chip->ecc.postpad) {
--                      chip->read_buf(mtd, oob, chip->ecc.postpad);
--                      oob += chip->ecc.postpad;
-+              if (chip->cur_ecc->postpad) {
-+                      chip->read_buf(mtd, oob, chip->cur_ecc->postpad);
-+                      oob += chip->cur_ecc->postpad;
-               }
-       }
-@@ -1480,7 +1486,7 @@ static uint8_t *nand_transfer_oob(struct
-               return oob + len;
-       case MTD_OPS_AUTO_OOB: {
--              struct nand_oobfree *free = chip->ecc.layout->oobfree;
-+              struct nand_oobfree *free = chip->cur_ecc->layout->oobfree;
-               uint32_t boffs = 0, roffs = ops->ooboffs;
-               size_t bytes = 0;
-@@ -1600,17 +1606,21 @@ read_retry:
-                        * the read methods return max bitflips per ecc step.
-                        */
-                       if (unlikely(ops->mode == MTD_OPS_RAW))
--                              ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
--                                                            oob_required,
--                                                            page);
-+                              ret = chip->cur_ecc->read_page_raw(mtd, chip,
-+                                                              bufpoi,
-+                                                              oob_required,
-+                                                              page);
-                       else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
-                                !oob)
--                              ret = chip->ecc.read_subpage(mtd, chip,
--                                                      col, bytes, bufpoi,
--                                                      page);
-+                              ret = chip->cur_ecc->read_subpage(mtd, chip,
-+                                                                col, bytes,
-+                                                                bufpoi,
-+                                                                page);
-                       else
--                              ret = chip->ecc.read_page(mtd, chip, bufpoi,
--                                                        oob_required, page);
-+                              ret = chip->cur_ecc->read_page(mtd, chip,
-+                                                             bufpoi,
-+                                                             oob_required,
-+                                                             page);
-                       if (ret < 0) {
-                               if (use_bufpoi)
-                                       /* Invalidate page cache */
-@@ -1746,6 +1756,39 @@ static int nand_read(struct mtd_info *mt
- }
- /**
-+ * nand_part_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
-+ * @mtd: MTD device structure
-+ * @from: offset to read from
-+ * @len: number of bytes to read
-+ * @retlen: pointer to variable to store the number of read bytes
-+ * @buf: the databuffer to put data
-+ *
-+ * Get hold of the chip and call nand_do_read.
-+ */
-+static int nand_part_read(struct mtd_info *mtd, loff_t from, size_t len,
-+                        size_t *retlen, uint8_t *buf)
-+{
-+      struct nand_chip *chip = mtd->priv;
-+      struct nand_part *part = to_nand_part(mtd);
-+      struct mtd_oob_ops ops;
-+      int ret;
-+
-+      from += part->offset;
-+      nand_get_device(part->master, FL_READING);
-+      if (part->ecc)
-+              chip->cur_ecc = part->ecc;
-+      ops.len = len;
-+      ops.datbuf = buf;
-+      ops.oobbuf = NULL;
-+      ops.mode = MTD_OPS_PLACE_OOB;
-+      ret = nand_do_read_ops(part->master, from, &ops);
-+      *retlen = ops.retlen;
-+      chip->cur_ecc = &chip->ecc;
-+      nand_release_device(part->master);
-+      return ret;
-+}
-+
-+/**
-  * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
-  * @mtd: mtd info structure
-  * @chip: nand chip info structure
-@@ -1770,13 +1813,14 @@ static int nand_read_oob_syndrome(struct
-                                 int page)
- {
-       int length = mtd->oobsize;
--      int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
--      int eccsize = chip->ecc.size;
-+      int chunk = chip->cur_ecc->bytes + chip->cur_ecc->prepad +
-+                  chip->cur_ecc->postpad;
-+      int eccsize = chip->cur_ecc->size;
-       uint8_t *bufpoi = chip->oob_poi;
-       int i, toread, sndrnd = 0, pos;
--      chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
--      for (i = 0; i < chip->ecc.steps; i++) {
-+      chip->cmdfunc(mtd, NAND_CMD_READ0, chip->cur_ecc->size, page);
-+      for (i = 0; i < chip->cur_ecc->steps; i++) {
-               if (sndrnd) {
-                       pos = eccsize + i * (eccsize + chunk);
-                       if (mtd->writesize > 512)
-@@ -1829,9 +1873,10 @@ static int nand_write_oob_std(struct mtd
- static int nand_write_oob_syndrome(struct mtd_info *mtd,
-                                  struct nand_chip *chip, int page)
- {
--      int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
--      int eccsize = chip->ecc.size, length = mtd->oobsize;
--      int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
-+      int chunk = chip->cur_ecc->bytes + chip->cur_ecc->prepad +
-+                  chip->cur_ecc->postpad;
-+      int eccsize = chip->cur_ecc->size, length = mtd->oobsize;
-+      int i, len, pos, status = 0, sndcmd = 0, steps = chip->cur_ecc->steps;
-       const uint8_t *bufpoi = chip->oob_poi;
-       /*
-@@ -1839,7 +1884,7 @@ static int nand_write_oob_syndrome(struc
-        * or
-        * data-pad-ecc-pad-data-pad .... ecc-pad-oob
-        */
--      if (!chip->ecc.prepad && !chip->ecc.postpad) {
-+      if (!chip->cur_ecc->prepad && !chip->cur_ecc->postpad) {
-               pos = steps * (eccsize + chunk);
-               steps = 0;
-       } else
-@@ -1903,7 +1948,7 @@ static int nand_do_read_oob(struct mtd_i
-       stats = mtd->ecc_stats;
-       if (ops->mode == MTD_OPS_AUTO_OOB)
--              len = chip->ecc.layout->oobavail;
-+              len = chip->cur_ecc->layout->oobavail;
-       else
-               len = mtd->oobsize;
-@@ -1931,9 +1976,9 @@ static int nand_do_read_oob(struct mtd_i
-       while (1) {
-               if (ops->mode == MTD_OPS_RAW)
--                      ret = chip->ecc.read_oob_raw(mtd, chip, page);
-+                      ret = chip->cur_ecc->read_oob_raw(mtd, chip, page);
-               else
--                      ret = chip->ecc.read_oob(mtd, chip, page);
-+                      ret = chip->cur_ecc->read_oob(mtd, chip, page);
-               if (ret < 0)
-                       break;
-@@ -2021,6 +2066,56 @@ out:
-       return ret;
- }
-+/**
-+ * nand_part_read_oob - [MTD Interface] NAND read data and/or out-of-band
-+ * @mtd: MTD device structure
-+ * @from: offset to read from
-+ * @ops: oob operation description structure
-+ *
-+ * NAND read data and/or out-of-band data.
-+ */
-+static int nand_part_read_oob(struct mtd_info *mtd, loff_t from,
-+                       struct mtd_oob_ops *ops)
-+{
-+      struct nand_chip *chip = mtd->priv;
-+      struct nand_part *part = to_nand_part(mtd);
-+      int ret = -ENOTSUPP;
-+
-+      ops->retlen = 0;
-+
-+      /* Do not allow reads past end of device */
-+      if (ops->datbuf && (from + ops->len) > mtd->size) {
-+              pr_debug("%s: attempt to read beyond end of device\n",
-+                              __func__);
-+              return -EINVAL;
-+      }
-+
-+      from += part->offset;
-+      nand_get_device(part->master, FL_READING);
-+      if (part->ecc)
-+              chip->cur_ecc = part->ecc;
-+
-+      switch (ops->mode) {
-+      case MTD_OPS_PLACE_OOB:
-+      case MTD_OPS_AUTO_OOB:
-+      case MTD_OPS_RAW:
-+              break;
-+
-+      default:
-+              goto out;
-+      }
-+
-+      if (!ops->datbuf)
-+              ret = nand_do_read_oob(part->master, from, ops);
-+      else
-+              ret = nand_do_read_ops(part->master, from, ops);
-+
-+out:
-+      chip->cur_ecc = &chip->ecc;
-+      nand_release_device(part->master);
-+      return ret;
-+}
-+
- /**
-  * nand_write_page_raw - [INTERN] raw page write function
-@@ -2054,26 +2149,26 @@ static int nand_write_page_raw_syndrome(
-                                       struct nand_chip *chip,
-                                       const uint8_t *buf, int oob_required)
- {
--      int eccsize = chip->ecc.size;
--      int eccbytes = chip->ecc.bytes;
-+      int eccsize = chip->cur_ecc->size;
-+      int eccbytes = chip->cur_ecc->bytes;
-       uint8_t *oob = chip->oob_poi;
-       int steps, size;
--      for (steps = chip->ecc.steps; steps > 0; steps--) {
-+      for (steps = chip->cur_ecc->steps; steps > 0; steps--) {
-               chip->write_buf(mtd, buf, eccsize);
-               buf += eccsize;
--              if (chip->ecc.prepad) {
--                      chip->write_buf(mtd, oob, chip->ecc.prepad);
--                      oob += chip->ecc.prepad;
-+              if (chip->cur_ecc->prepad) {
-+                      chip->write_buf(mtd, oob, chip->cur_ecc->prepad);
-+                      oob += chip->cur_ecc->prepad;
-               }
-               chip->write_buf(mtd, oob, eccbytes);
-               oob += eccbytes;
--              if (chip->ecc.postpad) {
--                      chip->write_buf(mtd, oob, chip->ecc.postpad);
--                      oob += chip->ecc.postpad;
-+              if (chip->cur_ecc->postpad) {
-+                      chip->write_buf(mtd, oob, chip->cur_ecc->postpad);
-+                      oob += chip->cur_ecc->postpad;
-               }
-       }
-@@ -2093,21 +2188,21 @@ static int nand_write_page_raw_syndrome(
- static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
-                                 const uint8_t *buf, int oob_required)
- {
--      int i, eccsize = chip->ecc.size;
--      int eccbytes = chip->ecc.bytes;
--      int eccsteps = chip->ecc.steps;
-+      int i, eccsize = chip->cur_ecc->size;
-+      int eccbytes = chip->cur_ecc->bytes;
-+      int eccsteps = chip->cur_ecc->steps;
-       uint8_t *ecc_calc = chip->buffers->ecccalc;
-       const uint8_t *p = buf;
--      uint32_t *eccpos = chip->ecc.layout->eccpos;
-+      uint32_t *eccpos = chip->cur_ecc->layout->eccpos;
-       /* Software ECC calculation */
-       for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
--              chip->ecc.calculate(mtd, p, &ecc_calc[i]);
-+              chip->cur_ecc->calculate(mtd, p, &ecc_calc[i]);
--      for (i = 0; i < chip->ecc.total; i++)
-+      for (i = 0; i < chip->cur_ecc->total; i++)
-               chip->oob_poi[eccpos[i]] = ecc_calc[i];
--      return chip->ecc.write_page_raw(mtd, chip, buf, 1);
-+      return chip->cur_ecc->write_page_raw(mtd, chip, buf, 1);
- }
- /**
-@@ -2120,20 +2215,20 @@ static int nand_write_page_swecc(struct
- static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
-                                 const uint8_t *buf, int oob_required)
- {
--      int i, eccsize = chip->ecc.size;
--      int eccbytes = chip->ecc.bytes;
--      int eccsteps = chip->ecc.steps;
-+      int i, eccsize = chip->cur_ecc->size;
-+      int eccbytes = chip->cur_ecc->bytes;
-+      int eccsteps = chip->cur_ecc->steps;
-       uint8_t *ecc_calc = chip->buffers->ecccalc;
-       const uint8_t *p = buf;
--      uint32_t *eccpos = chip->ecc.layout->eccpos;
-+      uint32_t *eccpos = chip->cur_ecc->layout->eccpos;
-       for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
--              chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
-+              chip->cur_ecc->hwctl(mtd, NAND_ECC_WRITE);
-               chip->write_buf(mtd, p, eccsize);
--              chip->ecc.calculate(mtd, p, &ecc_calc[i]);
-+              chip->cur_ecc->calculate(mtd, p, &ecc_calc[i]);
-       }
--      for (i = 0; i < chip->ecc.total; i++)
-+      for (i = 0; i < chip->cur_ecc->total; i++)
-               chip->oob_poi[eccpos[i]] = ecc_calc[i];
-       chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
-@@ -2158,10 +2253,10 @@ static int nand_write_subpage_hwecc(stru
- {
-       uint8_t *oob_buf  = chip->oob_poi;
-       uint8_t *ecc_calc = chip->buffers->ecccalc;
--      int ecc_size      = chip->ecc.size;
--      int ecc_bytes     = chip->ecc.bytes;
--      int ecc_steps     = chip->ecc.steps;
--      uint32_t *eccpos  = chip->ecc.layout->eccpos;
-+      int ecc_size      = chip->cur_ecc->size;
-+      int ecc_bytes     = chip->cur_ecc->bytes;
-+      int ecc_steps     = chip->cur_ecc->steps;
-+      uint32_t *eccpos  = chip->cur_ecc->layout->eccpos;
-       uint32_t start_step = offset / ecc_size;
-       uint32_t end_step   = (offset + data_len - 1) / ecc_size;
-       int oob_bytes       = mtd->oobsize / ecc_steps;
-@@ -2169,7 +2264,7 @@ static int nand_write_subpage_hwecc(stru
-       for (step = 0; step < ecc_steps; step++) {
-               /* configure controller for WRITE access */
--              chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
-+              chip->cur_ecc->hwctl(mtd, NAND_ECC_WRITE);
-               /* write data (untouched subpages already masked by 0xFF) */
-               chip->write_buf(mtd, buf, ecc_size);
-@@ -2178,7 +2273,7 @@ static int nand_write_subpage_hwecc(stru
-               if ((step < start_step) || (step > end_step))
-                       memset(ecc_calc, 0xff, ecc_bytes);
-               else
--                      chip->ecc.calculate(mtd, buf, ecc_calc);
-+                      chip->cur_ecc->calculate(mtd, buf, ecc_calc);
-               /* mask OOB of un-touched subpages by padding 0xFF */
-               /* if oob_required, preserve OOB metadata of written subpage */
-@@ -2193,7 +2288,7 @@ static int nand_write_subpage_hwecc(stru
-       /* copy calculated ECC for whole page to chip->buffer->oob */
-       /* this include masked-value(0xFF) for unwritten subpages */
-       ecc_calc = chip->buffers->ecccalc;
--      for (i = 0; i < chip->ecc.total; i++)
-+      for (i = 0; i < chip->cur_ecc->total; i++)
-               chip->oob_poi[eccpos[i]] = ecc_calc[i];
-       /* write OOB buffer to NAND device */
-@@ -2217,29 +2312,29 @@ static int nand_write_page_syndrome(stru
-                                   struct nand_chip *chip,
-                                   const uint8_t *buf, int oob_required)
- {
--      int i, eccsize = chip->ecc.size;
--      int eccbytes = chip->ecc.bytes;
--      int eccsteps = chip->ecc.steps;
-+      int i, eccsize = chip->cur_ecc->size;
-+      int eccbytes = chip->cur_ecc->bytes;
-+      int eccsteps = chip->cur_ecc->steps;
-       const uint8_t *p = buf;
-       uint8_t *oob = chip->oob_poi;
-       for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
--              chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
-+              chip->cur_ecc->hwctl(mtd, NAND_ECC_WRITE);
-               chip->write_buf(mtd, p, eccsize);
--              if (chip->ecc.prepad) {
--                      chip->write_buf(mtd, oob, chip->ecc.prepad);
--                      oob += chip->ecc.prepad;
-+              if (chip->cur_ecc->prepad) {
-+                      chip->write_buf(mtd, oob, chip->cur_ecc->prepad);
-+                      oob += chip->cur_ecc->prepad;
-               }
--              chip->ecc.calculate(mtd, p, oob);
-+              chip->cur_ecc->calculate(mtd, p, oob);
-               chip->write_buf(mtd, oob, eccbytes);
-               oob += eccbytes;
--              if (chip->ecc.postpad) {
--                      chip->write_buf(mtd, oob, chip->ecc.postpad);
--                      oob += chip->ecc.postpad;
-+              if (chip->cur_ecc->postpad) {
-+                      chip->write_buf(mtd, oob, chip->cur_ecc->postpad);
-+                      oob += chip->cur_ecc->postpad;
-               }
-       }
-@@ -2270,7 +2365,7 @@ static int nand_write_page(struct mtd_in
-       int status, subpage;
-       if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
--              chip->ecc.write_subpage)
-+              chip->cur_ecc->write_subpage)
-               subpage = offset || (data_len < mtd->writesize);
-       else
-               subpage = 0;
-@@ -2278,13 +2373,15 @@ static int nand_write_page(struct mtd_in
-       chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
-       if (unlikely(raw))
--              status = chip->ecc.write_page_raw(mtd, chip, buf,
--                                                      oob_required);
-+              status = chip->cur_ecc->write_page_raw(mtd, chip, buf,
-+                                                     oob_required);
-       else if (subpage)
--              status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
--                                                       buf, oob_required);
-+              status = chip->cur_ecc->write_subpage(mtd, chip, offset,
-+                                                    data_len, buf,
-+                                                    oob_required);
-       else
--              status = chip->ecc.write_page(mtd, chip, buf, oob_required);
-+              status = chip->cur_ecc->write_page(mtd, chip, buf,
-+                                                 oob_required);
-       if (status < 0)
-               return status;
-@@ -2343,7 +2440,7 @@ static uint8_t *nand_fill_oob(struct mtd
-               return oob + len;
-       case MTD_OPS_AUTO_OOB: {
--              struct nand_oobfree *free = chip->ecc.layout->oobfree;
-+              struct nand_oobfree *free = chip->cur_ecc->layout->oobfree;
-               uint32_t boffs = 0, woffs = ops->ooboffs;
-               size_t bytes = 0;
-@@ -2539,6 +2636,46 @@ static int panic_nand_write(struct mtd_i
- }
- /**
-+ * panic_nand_part_write - [MTD Interface] NAND write with ECC
-+ * @mtd: MTD device structure
-+ * @to: offset to write to
-+ * @len: number of bytes to write
-+ * @retlen: pointer to variable to store the number of written bytes
-+ * @buf: the data to write
-+ *
-+ * NAND write with ECC. Used when performing writes in interrupt context, this
-+ * may for example be called by mtdoops when writing an oops while in panic.
-+ */
-+static int panic_nand_part_write(struct mtd_info *mtd, loff_t to, size_t len,
-+                          size_t *retlen, const uint8_t *buf)
-+{
-+      struct nand_chip *chip = mtd->priv;
-+      struct nand_part *part = to_nand_part(mtd);
-+      struct mtd_oob_ops ops;
-+      int ret;
-+
-+      to += part->offset;
-+      /* Wait for the device to get ready */
-+      panic_nand_wait(part->master, chip, 400);
-+
-+      /* Grab the device */
-+      panic_nand_get_device(chip, part->master, FL_WRITING);
-+      if (part->ecc)
-+              chip->cur_ecc = part->ecc;
-+
-+      ops.len = len;
-+      ops.datbuf = (uint8_t *)buf;
-+      ops.oobbuf = NULL;
-+      ops.mode = MTD_OPS_PLACE_OOB;
-+
-+      ret = nand_do_write_ops(part->master, to, &ops);
-+
-+      chip->cur_ecc = &chip->ecc;
-+      *retlen = ops.retlen;
-+      return ret;
-+}
-+
-+/**
-  * nand_write - [MTD Interface] NAND write with ECC
-  * @mtd: MTD device structure
-  * @to: offset to write to
-@@ -2566,6 +2703,39 @@ static int nand_write(struct mtd_info *m
- }
- /**
-+ * nand_part_write - [MTD Interface] NAND write with ECC
-+ * @mtd: MTD device structure
-+ * @to: offset to write to
-+ * @len: number of bytes to write
-+ * @retlen: pointer to variable to store the number of written bytes
-+ * @buf: the data to write
-+ *
-+ * NAND write with ECC.
-+ */
-+static int nand_part_write(struct mtd_info *mtd, loff_t to, size_t len,
-+                        size_t *retlen, const uint8_t *buf)
-+{
-+      struct nand_chip *chip = mtd->priv;
-+      struct nand_part *part = to_nand_part(mtd);
-+      struct mtd_oob_ops ops;
-+      int ret;
-+
-+      to += part->offset;
-+      nand_get_device(part->master, FL_WRITING);
-+      if (part->ecc)
-+              chip->cur_ecc = part->ecc;
-+      ops.len = len;
-+      ops.datbuf = (uint8_t *)buf;
-+      ops.oobbuf = NULL;
-+      ops.mode = MTD_OPS_PLACE_OOB;
-+      ret = nand_do_write_ops(part->master, to, &ops);
-+      *retlen = ops.retlen;
-+      chip->cur_ecc = &chip->ecc;
-+      nand_release_device(part->master);
-+      return ret;
-+}
-+
-+/**
-  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
-  * @mtd: MTD device structure
-  * @to: offset to write to
-@@ -2583,7 +2753,7 @@ static int nand_do_write_oob(struct mtd_
-                        __func__, (unsigned int)to, (int)ops->ooblen);
-       if (ops->mode == MTD_OPS_AUTO_OOB)
--              len = chip->ecc.layout->oobavail;
-+              len = chip->cur_ecc->layout->oobavail;
-       else
-               len = mtd->oobsize;
-@@ -2637,9 +2807,11 @@ static int nand_do_write_oob(struct mtd_
-       nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
-       if (ops->mode == MTD_OPS_RAW)
--              status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
-+              status = chip->cur_ecc->write_oob_raw(mtd, chip,
-+                                                    page & chip->pagemask);
-       else
--              status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
-+              status = chip->cur_ecc->write_oob(mtd, chip,
-+                                                page & chip->pagemask);
-       chip->select_chip(mtd, -1);
-@@ -2694,6 +2866,54 @@ out:
- }
- /**
-+ * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
-+ * @mtd: MTD device structure
-+ * @to: offset to write to
-+ * @ops: oob operation description structure
-+ */
-+static int nand_part_write_oob(struct mtd_info *mtd, loff_t to,
-+                        struct mtd_oob_ops *ops)
-+{
-+      struct nand_chip *chip = mtd->priv;
-+      struct nand_part *part = to_nand_part(mtd);
-+      int ret = -ENOTSUPP;
-+
-+      ops->retlen = 0;
-+
-+      /* Do not allow writes past end of device */
-+      if (ops->datbuf && (to + ops->len) > mtd->size) {
-+              pr_debug("%s: attempt to write beyond end of device\n",
-+                              __func__);
-+              return -EINVAL;
-+      }
-+
-+      to += part->offset;
-+      nand_get_device(part->master, FL_WRITING);
-+      if (part->ecc)
-+              chip->cur_ecc = part->ecc;
-+
-+      switch (ops->mode) {
-+      case MTD_OPS_PLACE_OOB:
-+      case MTD_OPS_AUTO_OOB:
-+      case MTD_OPS_RAW:
-+              break;
-+
-+      default:
-+              goto out;
-+      }
-+
-+      if (!ops->datbuf)
-+              ret = nand_do_write_oob(part->master, to, ops);
-+      else
-+              ret = nand_do_write_ops(part->master, to, ops);
-+
-+out:
-+      chip->cur_ecc = &chip->ecc;
-+      nand_release_device(part->master);
-+      return ret;
-+}
-+
-+/**
-  * single_erase - [GENERIC] NAND standard block erase command function
-  * @mtd: MTD device structure
-  * @page: the page address of the block which will be erased
-@@ -2723,6 +2943,29 @@ static int nand_erase(struct mtd_info *m
- }
- /**
-+ * nand_part_erase - [MTD Interface] erase partition block(s)
-+ * @mtd: MTD device structure
-+ * @instr: erase instruction
-+ *
-+ * Erase one ore more blocks.
-+ */
-+static int nand_part_erase(struct mtd_info *mtd, struct erase_info *instr)
-+{
-+      struct nand_part *part = to_nand_part(mtd);
-+      int ret;
-+
-+      instr->addr += part->offset;
-+      ret = nand_erase_nand(part->master, instr, 0);
-+      if (ret) {
-+              if (instr->fail_addr != MTD_FAIL_ADDR_UNKNOWN)
-+                      instr->fail_addr -= part->offset;
-+              instr->addr -= part->offset;
-+      }
-+
-+      return ret;
-+}
-+
-+/**
-  * nand_erase_nand - [INTERN] erase block(s)
-  * @mtd: MTD device structure
-  * @instr: erase instruction
-@@ -2864,6 +3107,18 @@ static int nand_block_isbad(struct mtd_i
- }
- /**
-+ * nand_part_block_isbad - [MTD Interface] Check if block at offset is bad
-+ * @mtd: MTD device structure
-+ * @offs: offset relative to mtd start
-+ */
-+static int nand_part_block_isbad(struct mtd_info *mtd, loff_t offs)
-+{
-+      struct nand_part *part = to_nand_part(mtd);
-+
-+      return nand_block_checkbad(part->master, part->offset + offs, 1, 0);
-+}
-+
-+/**
-  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
-  * @mtd: MTD device structure
-  * @ofs: offset relative to mtd start
-@@ -2884,6 +3139,33 @@ static int nand_block_markbad(struct mtd
- }
- /**
-+ * nand_part_block_markbad - [MTD Interface] Mark block at the given offset as
-+ *                         bad
-+ * @mtd: MTD device structure
-+ * @ofs: offset relative to mtd start
-+ */
-+static int nand_part_block_markbad(struct mtd_info *mtd, loff_t ofs)
-+{
-+      struct nand_part *part = to_nand_part(mtd);
-+      int ret;
-+
-+      ofs += part->offset;
-+      ret = nand_block_isbad(part->master, ofs);
-+      if (ret) {
-+              /* If it was bad already, return success and do nothing */
-+              if (ret > 0)
-+                      return 0;
-+              return ret;
-+      }
-+
-+      ret = nand_block_markbad_lowlevel(part->master, ofs);
-+      if (!ret)
-+              mtd->ecc_stats.badblocks++;
-+
-+      return ret;
-+}
-+
-+/**
-  * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
-  * @mtd: MTD device structure
-  * @chip: nand chip info structure
-@@ -4099,6 +4381,169 @@ static int nand_ecc_ctrl_init(struct mtd
- }
- /**
-+ * nand_add_partition - [NAND Interface] Add a NAND partition to a NAND device
-+ * @master: MTD device structure representing the NAND device
-+ * @part: NAND partition to add to the NAND device
-+ *
-+ * Adds a NAND partition to a NAND device.
-+ * The NAND partition cannot overlap with another existing partition.
-+ *
-+ * Returns zero in case of success and a negative error code in case of failure.
-+ */
-+int nand_add_partition(struct mtd_info *master, struct nand_part *part)
-+{
-+      struct nand_chip *chip = master->priv;
-+      struct mtd_info *mtd = &part->mtd;
-+      struct nand_ecc_ctrl *ecc = part->ecc;
-+      struct nand_part *pos;
-+      bool inserted = false;
-+      int ret;
-+
-+      /* set up the MTD object for this partition */
-+      mtd->type = master->type;
-+      mtd->flags = master->flags & ~mtd->flags;
-+      mtd->writesize = master->writesize;
-+      mtd->writebufsize = master->writebufsize;
-+      mtd->oobsize = master->oobsize;
-+      mtd->oobavail = master->oobavail;
-+      mtd->subpage_sft = master->subpage_sft;
-+      mtd->erasesize = master->erasesize;
-+
-+      mtd->priv = chip;
-+      mtd->owner = master->owner;
-+      mtd->backing_dev_info = master->backing_dev_info;
-+
-+      mtd->dev.parent = master->dev.parent;
-+
-+      if (ecc) {
-+              ret = nand_ecc_ctrl_init(mtd, ecc);
-+              if (ret)
-+                      return ret;
-+      } else {
-+              ecc = &chip->ecc;
-+      }
-+
-+      mtd->_erase = nand_part_erase;
-+      mtd->_point = NULL;
-+      mtd->_unpoint = NULL;
-+      mtd->_read = nand_part_read;
-+      mtd->_write = nand_part_write;
-+      mtd->_panic_write = panic_nand_part_write;
-+      mtd->_read_oob = nand_part_read_oob;
-+      mtd->_write_oob = nand_part_write_oob;
-+      mtd->_sync = nand_sync;
-+      mtd->_lock = NULL;
-+      mtd->_unlock = NULL;
-+      mtd->_suspend = nand_suspend;
-+      mtd->_resume = nand_resume;
-+      mtd->_block_isbad = nand_part_block_isbad;
-+      mtd->_block_markbad = nand_part_block_markbad;
-+
-+      /* propagate ecc info to mtd_info */
-+      mtd->ecclayout = ecc->layout;
-+      mtd->ecc_strength = ecc->strength;
-+      mtd->ecc_step_size = ecc->size;
-+      /*
-+       * Initialize bitflip_threshold to its default prior scan_bbt() call.
-+       * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
-+       * properly set.
-+       */
-+      if (!mtd->bitflip_threshold)
-+              mtd->bitflip_threshold = mtd->ecc_strength;
-+
-+      part->master = master;
-+
-+      mutex_lock(&chip->part_lock);
-+      list_for_each_entry(pos, &chip->partitions, node) {
-+              if (part->offset >= pos->offset + pos->mtd.size) {
-+                      continue;
-+              } else if (part->offset + mtd->size > pos->offset) {
-+                      ret = -EINVAL;
-+                      goto out;
-+              }
-+
-+              list_add(&part->node, pos->node.prev);
-+              inserted = true;
-+              break;
-+      }
-+
-+      if (!inserted)
-+              list_add_tail(&part->node, &chip->partitions);
-+
-+      ret = mtd_device_register(mtd, NULL, 0);
-+      if (ret) {
-+              list_del(&part->node);
-+              goto out;
-+      }
-+
-+      if (master->_block_isbad) {
-+              uint64_t offs = 0;
-+
-+              while (offs < mtd->size) {
-+                      if (mtd_block_isreserved(master, offs + part->offset))
-+                              mtd->ecc_stats.bbtblocks++;
-+                      else if (mtd_block_isbad(master, offs + part->offset))
-+                              mtd->ecc_stats.badblocks++;
-+                      offs += mtd->erasesize;
-+              }
-+      }
-+
-+out:
-+      mutex_unlock(&chip->part_lock);
-+      return ret;
-+}
-+EXPORT_SYMBOL(nand_add_partition);
-+
-+/**
-+ * nand_del_partition - [NAND Interface] Delete a NAND part from a NAND dev
-+ * @part: NAND partition to delete
-+ *
-+ * Deletes a NAND partition from a NAND device.
-+ */
-+void nand_del_partition(struct nand_part *part)
-+{
-+      struct nand_chip *chip = part->mtd.priv;
-+
-+      mutex_lock(&chip->part_lock);
-+      mtd_device_unregister(&part->mtd);
-+      list_del(&part->node);
-+      mutex_unlock(&chip->part_lock);
-+
-+      if (part->ecc && part->ecc->mode == NAND_ECC_SOFT_BCH)
-+              nand_bch_free((struct nand_bch_control *)part->ecc->priv);
-+
-+      if (part->release)
-+              part->release(part);
-+}
-+EXPORT_SYMBOL(nand_del_partition);
-+
-+/*
-+ * NAND part release function. Used by nandpart_alloc as its release function.
-+ */
-+static void nandpart_release(struct nand_part *part)
-+{
-+      kfree(part);
-+}
-+
-+/**
-+ * nandpart_alloc - [NAND Interface] Allocate a NAND part struct
-+ *
-+ * Allocate a NAND partition and assign the nandpart release function.
-+ * This nand_part struct must be filled before passing it to the
-+ * nand_add_partition function.
-+ */
-+struct nand_part *nandpart_alloc(void)
-+{
-+      struct nand_part *part = kzalloc(sizeof(*part), GFP_KERNEL);
-+      if (!part)
-+              return ERR_PTR(-ENOMEM);
-+      part->release = nandpart_release;
-+
-+      return part;
-+}
-+EXPORT_SYMBOL(nandpart_alloc);
-+
-+/**
-  * nand_scan_tail - [NAND Interface] Scan for the NAND device
-  * @mtd: MTD device structure
-  *
-@@ -4146,6 +4591,11 @@ int nand_scan_tail(struct mtd_info *mtd)
-               return ret;
-       }
-+      INIT_LIST_HEAD(&chip->partitions);
-+      mutex_init(&chip->part_lock);
-+
-+      chip->cur_ecc = &chip->ecc;
-+
-       /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
-       if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
-               switch (ecc->steps) {
---- a/drivers/mtd/nand/nand_bch.c
-+++ b/drivers/mtd/nand/nand_bch.c
-@@ -53,14 +53,14 @@ int nand_bch_calculate_ecc(struct mtd_in
-                          unsigned char *code)
- {
-       const struct nand_chip *chip = mtd->priv;
--      struct nand_bch_control *nbc = chip->ecc.priv;
-+      struct nand_bch_control *nbc = chip->cur_ecc->priv;
-       unsigned int i;
--      memset(code, 0, chip->ecc.bytes);
--      encode_bch(nbc->bch, buf, chip->ecc.size, code);
-+      memset(code, 0, chip->cur_ecc->bytes);
-+      encode_bch(nbc->bch, buf, chip->cur_ecc->size, code);
-       /* apply mask so that an erased page is a valid codeword */
--      for (i = 0; i < chip->ecc.bytes; i++)
-+      for (i = 0; i < chip->cur_ecc->bytes; i++)
-               code[i] ^= nbc->eccmask[i];
-       return 0;
-@@ -80,15 +80,15 @@ int nand_bch_correct_data(struct mtd_inf
-                         unsigned char *read_ecc, unsigned char *calc_ecc)
- {
-       const struct nand_chip *chip = mtd->priv;
--      struct nand_bch_control *nbc = chip->ecc.priv;
-+      struct nand_bch_control *nbc = chip->cur_ecc->priv;
-       unsigned int *errloc = nbc->errloc;
-       int i, count;
--      count = decode_bch(nbc->bch, NULL, chip->ecc.size, read_ecc, calc_ecc,
--                         NULL, errloc);
-+      count = decode_bch(nbc->bch, NULL, chip->cur_ecc->size, read_ecc,
-+                         calc_ecc, NULL, errloc);
-       if (count > 0) {
-               for (i = 0; i < count; i++) {
--                      if (errloc[i] < (chip->ecc.size*8))
-+                      if (errloc[i] < (chip->cur_ecc->size*8))
-                               /* error is located in data, correct it */
-                               buf[errloc[i] >> 3] ^= (1 << (errloc[i] & 7));
-                       /* else error in ecc, no action needed */
---- a/drivers/mtd/nand/nand_ecc.c
-+++ b/drivers/mtd/nand/nand_ecc.c
-@@ -424,7 +424,7 @@ int nand_calculate_ecc(struct mtd_info *
-                      unsigned char *code)
- {
-       __nand_calculate_ecc(buf,
--                      ((struct nand_chip *)mtd->priv)->ecc.size, code);
-+                      ((struct nand_chip *)mtd->priv)->cur_ecc->size, code);
-       return 0;
- }
-@@ -524,7 +524,7 @@ int nand_correct_data(struct mtd_info *m
-                     unsigned char *read_ecc, unsigned char *calc_ecc)
- {
-       return __nand_correct_data(buf, read_ecc, calc_ecc,
--                                 ((struct nand_chip *)mtd->priv)->ecc.size);
-+                      ((struct nand_chip *)mtd->priv)->cur_ecc->size);
- }
- EXPORT_SYMBOL(nand_correct_data);
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -708,6 +708,7 @@ struct nand_chip {
-       struct nand_hw_control *controller;
-       struct nand_ecc_ctrl ecc;
-+      struct nand_ecc_ctrl *cur_ecc;
-       struct nand_buffers *buffers;
-       struct nand_hw_control hwcontrol;
-@@ -717,9 +718,46 @@ struct nand_chip {
-       struct nand_bbt_descr *badblock_pattern;
-+      struct list_head partitions;
-+      struct mutex part_lock;
-+
-       void *priv;
- };
-+/**
-+ * struct nand_part - NAND partition structure
-+ * @node:     list node used to attach the partition to its NAND dev
-+ * @mtd:      MTD partiton info
-+ * @master:   MTD device representing the NAND chip
-+ * @offset:   partition offset
-+ * @ecc:      partition specific ECC struct
-+ * @release:  function used to release this nand_part struct
-+ *
-+ * NAND partitions work as standard MTD partitions except it can override
-+ * NAND chip ECC handling.
-+ * This is particularly useful for SoCs that need specific ECC configs to boot
-+ * from NAND while these ECC configs do not fit the NAND chip ECC requirements.
-+ */
-+struct nand_part {
-+      struct list_head node;
-+      struct mtd_info mtd;
-+      struct mtd_info *master;
-+      uint64_t offset;
-+      struct nand_ecc_ctrl *ecc;
-+      void (*release)(struct nand_part *part);
-+};
-+
-+static inline struct nand_part *to_nand_part(struct mtd_info *mtd)
-+{
-+      return container_of(mtd, struct nand_part, mtd);
-+}
-+
-+int nand_add_partition(struct mtd_info *master, struct nand_part *part);
-+
-+void nand_del_partition(struct nand_part *part);
-+
-+struct nand_part *nandpart_alloc(void);
-+
- /*
-  * NAND Flash Manufacturer ID Codes
-  */
diff --git a/target/linux/sunxi/patches-4.1/112-mtd-add-dt-nand-partition-parser.patch b/target/linux/sunxi/patches-4.1/112-mtd-add-dt-nand-partition-parser.patch
deleted file mode 100644 (file)
index 76f0051..0000000
+++ /dev/null
@@ -1,152 +0,0 @@
-From 0460e9868fd82a3675db02f6ceb6edfd8501c194 Mon Sep 17 00:00:00 2001
-From: Boris BREZILLON <boris.brezillon@free-electrons.com>
-Date: Mon, 28 Jul 2014 14:31:42 +0200
-Subject: [PATCH] mtd: nand: Add DT NAND partition parser
-
-Add a of_nandpart_parse function to help parsing NAND partitions from DT.
-This function should be called from NAND controller drivers just after the
-nand_scan_tail in place of mtd_device_parse_register.
-The caller can specify a parser function to retrieve HW specific
-informations from the DT.
-
-Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/mtd/nand/ofnandpart.c | 104 ++++++++++++++++++++++++++++++++++++++++++
- include/linux/mtd/nand.h      |  17 +++++++
- 2 files changed, 121 insertions(+)
- create mode 100644 drivers/mtd/nand/ofnandpart.c
-
---- /dev/null
-+++ b/drivers/mtd/nand/ofnandpart.c
-@@ -0,0 +1,104 @@
-+/*
-+ * NAND Flash partitions described by the OF (or flattened) device tree
-+ *
-+ * Copyright © 2014 Boris BREZILLON <b.brezillon.dev@gmail.com>
-+ *
-+ * This program is free software; you can redistribute  it and/or modify it
-+ * under  the terms of  the GNU General  Public License as published by the
-+ * Free Software Foundation;  either version 2 of the  License, or (at your
-+ * option) any later version.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/of.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/slab.h>
-+#include <linux/mtd/nand.h>
-+
-+static inline bool node_has_compatible(struct device_node *pp)
-+{
-+      return of_get_property(pp, "compatible", NULL);
-+}
-+
-+int ofnandpart_parse(struct mtd_info *master,
-+                   const struct ofnandpart_data *data)
-+{
-+      struct device_node *node;
-+      const char *partname;
-+      struct device_node *pp;
-+      int i;
-+
-+      if (!data)
-+              return 0;
-+
-+      node = data->node;
-+      if (!node)
-+              return 0;
-+
-+      i = 0;
-+      for_each_child_of_node(node,  pp) {
-+              const __be32 *reg;
-+              int len;
-+              int a_cells, s_cells;
-+              uint64_t offset, size;
-+              uint32_t mask_flags = 0;
-+              struct nand_part *part;
-+
-+              if (node_has_compatible(pp))
-+                      continue;
-+
-+              reg = of_get_property(pp, "reg", &len);
-+              if (!reg)
-+                      continue;
-+
-+              a_cells = of_n_addr_cells(pp);
-+              s_cells = of_n_size_cells(pp);
-+              offset = of_read_number(reg, a_cells);
-+              size = of_read_number(reg + a_cells, s_cells);
-+
-+              partname = of_get_property(pp, "label", &len);
-+              if (!partname)
-+                      partname = of_get_property(pp, "name", &len);
-+
-+              if (of_get_property(pp, "read-only", &len))
-+                      mask_flags |= MTD_WRITEABLE;
-+
-+              if (of_get_property(pp, "lock", &len))
-+                      mask_flags |= MTD_POWERUP_LOCK;
-+
-+              if (data->parse)
-+                      part = data->parse(data->priv, master, pp);
-+              else
-+                      part = nandpart_alloc();
-+
-+              if (IS_ERR(part))
-+                      continue;
-+
-+              part->offset = offset;
-+              part->master = master;
-+              part->mtd.name = partname;
-+              part->mtd.size = size;
-+              part->mtd.flags = mask_flags;
-+
-+              if (nand_add_partition(master, part)) {
-+                      if (part->release)
-+                              part->release(part);
-+                      continue;
-+              }
-+
-+              i++;
-+      }
-+
-+      if (!i) {
-+              of_node_put(pp);
-+              pr_err("No valid partition found on %s\n", node->full_name);
-+      }
-+
-+      return i;
-+}
-+EXPORT_SYMBOL(ofnandpart_parse);
-+
-+MODULE_LICENSE("GPL");
-+MODULE_DESCRIPTION("Parser for NAND flash partitioning information in device tree");
-+MODULE_AUTHOR("Boris BREZILLON");
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -1014,6 +1014,23 @@ static inline int jedec_feature(struct n
-               : 0;
- }
-+/**
-+ * struct ofnandpart_data - struct used to retrieve NAND partitions from a DT
-+ *                        node
-+ * @parse:            driver specific parser function
-+ * @priv:             driver private data
-+ * @node:             OF node containing NAND partitions
-+ */
-+struct ofnandpart_data {
-+      struct nand_part *(*parse)(void *priv, struct mtd_info *master,
-+                                 struct device_node *pp);
-+      void *priv;
-+      struct device_node *node;
-+};
-+
-+int ofnandpart_parse(struct mtd_info *master,
-+                   const struct ofnandpart_data *data);
-+
- /*
-  * struct nand_sdr_timings - SDR NAND chip timings
-  *
diff --git a/target/linux/sunxi/patches-4.1/113-mtd-nand-add-pst.patch b/target/linux/sunxi/patches-4.1/113-mtd-nand-add-pst.patch
deleted file mode 100644 (file)
index 45b9679..0000000
+++ /dev/null
@@ -1,261 +0,0 @@
-From bec69bb8e85151729014d859106dcc3fe652b1d4 Mon Sep 17 00:00:00 2001
-From: Boris BREZILLON <boris.brezillon@free-electrons.com>
-Date: Mon, 28 Jul 2014 14:45:40 +0200
-Subject: [PATCH] mtd: nand: Add page status table (pst)
-
-Page status table is an byte array storing pages status.
-It defines 3 status:
- - unknown: the page has not been read yet and we do not know its current
-   state
- - empty: the page contains only FFs
- - filled: the page has been filled with data
-
-Care must be taken: an empty page does not mean it can be written, because
-it might have already been written with only FFs.
-
-These page status are useful to check wether the controller should try to
-correct errors (using ECC) or a derandomize data (using a randomizer
-block).
-
-Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/mtd/nand/nand_base.c | 154 +++++++++++++++++++++++++++++++++++++++++++