ath79: update WA/XC devices UBNT_VERSION to 8.7.4
[openwrt/staging/wigyori.git] / target / linux / ath79 / dts / ar7100.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "ath79.dtsi"
4
5 / {
6 compatible = "qca,ar7100";
7
8 chosen {
9 bootargs = "console=ttyS0,115200";
10 };
11
12 cpus {
13 #address-cells = <1>;
14 #size-cells = <0>;
15
16 cpu@0 {
17 device_type = "cpu";
18 compatible = "mips,mips24Kc";
19 clocks = <&pll ATH79_CLK_CPU>;
20 reg = <0>;
21 };
22 };
23
24 extosc: ref {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-output-names = "ref";
28 clock-frequency = <40000000>;
29 };
30
31 ahb {
32 apb {
33 ddr_ctrl: memory-controller@18000000 {
34 compatible = "qca,ar7100-ddr-controller";
35 reg = <0x18000000 0x100>;
36
37 #qca,ddr-wb-channel-cells = <1>;
38 };
39
40 uart: uart@18020000 {
41 compatible = "ns16550a";
42 reg = <0x18020000 0x20>;
43 interrupts = <3>;
44
45 clocks = <&pll ATH79_CLK_AHB>;
46 clock-names = "uart";
47
48 reg-io-width = <4>;
49 reg-shift = <2>;
50 no-loopback-test;
51 };
52
53 usb_phy: usb-phy@18030000 {
54 compatible = "qca,ar7100-usb-phy";
55 reg = <0x18030000 0x10>;
56
57 reset-names = "usb-phy", "usb-host", "usb-ohci-dll";
58 resets = <&rst 4>, <&rst 5>, <&rst 6>;
59
60 #phy-cells = <0>;
61
62 status = "disabled";
63 };
64
65 gpio: gpio@18040000 {
66 compatible = "qca,ar7100-gpio";
67 reg = <0x18040000 0x28>;
68 interrupts = <2>;
69
70 ngpios = <16>;
71
72 gpio-controller;
73 #gpio-cells = <2>;
74
75 interrupt-controller;
76 #interrupt-cells = <2>;
77 };
78
79 pll: pll-controller@18050000 {
80 compatible = "qca,ar7100-pll", "syscon";
81 reg = <0x18050000 0x20>;
82
83 clocks = <&extosc>;
84 clock-names = "ref";
85
86 #clock-cells = <1>;
87 clock-output-names = "cpu", "ddr", "ahb";
88 };
89
90 wdt: wdt@18060008 {
91 compatible = "qca,ar7130-wdt";
92 reg = <0x18060008 0x8>;
93
94 interrupts = <4>;
95
96 clocks = <&pll ATH79_CLK_AHB>;
97 clock-names = "wdt";
98 };
99
100 pci_intc: interrupt-controller@18060018 {
101 compatible = "qca,ar7100-misc-intc";
102 reg = <0x18060018 0x4>;
103 interrupt-parent = <&cpuintc>;
104 interrupts = <2>;
105 interrupt-controller;
106 #interrupt-cells = <1>;
107 };
108
109 rst: reset-controller@18060024 {
110 compatible = "qca,ar7100-reset";
111 reg = <0x18060024 0x4>;
112
113 #reset-cells = <1>;
114 };
115
116 pcie0: pcie@17010000 {
117 compatible = "qca,ar7100-pci";
118 #address-cells = <3>;
119 #size-cells = <2>;
120 bus-range = <0x0 0x0>;
121 reg = <0x17010000 0x100>;
122 reg-names = "cfg_base";
123 ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000 /* pci memory */
124 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
125
126 device_type = "pci";
127
128 interrupt-parent = <&pci_intc>;
129 interrupts = <4>;
130
131 #interrupt-cells = <1>;
132
133 interrupt-map-mask = <0xf800 0 0 0>;
134 interrupt-map = <0x8800 0 0 0 &pci_intc 0
135 0x9000 0 0 0 &pci_intc 1
136 0x9800 0 0 0 &pci_intc 2>;
137
138 status = "disabled";
139 };
140 };
141 };
142
143 usb2: usb@1b000000 {
144 compatible = "generic-ehci";
145 reg = <0x1b000000 0x1000>;
146
147 interrupt-parent = <&cpuintc>;
148 interrupts = <3>;
149
150 phy-names = "usb-phy";
151 phys = <&usb_phy>;
152
153 has-synopsys-hc-bug;
154
155 status = "disabled";
156
157 #address-cells = <1>;
158 #size-cells = <0>;
159
160 usb_ehci_port: port@1 {
161 reg = <1>;
162 #trigger-source-cells = <0>;
163 };
164 };
165
166 usb1: usb@1c000000 {
167 compatible = "generic-ohci";
168 reg = <0x1c000000 0x1000>;
169
170 interrupt-parent = <&miscintc>;
171 interrupts = <6>;
172
173 phy-names = "usb-phy";
174 phys = <&usb_phy>;
175
176 status = "disabled";
177
178 #address-cells = <1>;
179 #size-cells = <0>;
180
181 usb_ohci_port: port@1 {
182 reg = <1>;
183 #trigger-source-cells = <0>;
184 };
185 };
186
187 spi: spi@1f000000 {
188 compatible = "qca,ar7100-spi";
189 reg = <0x1f000000 0x10>;
190
191 clocks = <&pll ATH79_CLK_AHB>;
192 clock-names = "ahb";
193
194 #address-cells = <1>;
195 #size-cells = <0>;
196
197 status = "disabled";
198 };
199 };
200
201 &cpuintc {
202 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
203 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
204 <&ddr_ctrl 0>, <&ddr_ctrl 1>;
205 };
206
207 &miscintc {
208 compatible = "qca,ar7100-misc-intc";
209 };
210
211 &eth0 {
212 compatible = "qca,ar7100-eth", "syscon";
213 reg = <0x19000000 0x200
214 0x18070000 0x4>;
215
216 pll-data = <0x00110000 0x00001099 0x00991099>;
217 pll-reg = <0x4 0x10 17>;
218 pll-handle = <&pll>;
219 phy-mode = "rgmii";
220
221 resets = <&rst 9>;
222 reset-names = "mac";
223 qca,mac-idx = <0>;
224 };
225
226 &mdio1 {
227 builtin-switch;
228 };
229
230 &eth1 {
231 compatible = "qca,ar7100-eth", "syscon";
232 reg = <0x1a000000 0x200
233 0x18070004 0x4>;
234
235 pll-data = <0x00110000 0x00001099 0x00991099>;
236 pll-reg = <0x4 0x14 19>;
237 pll-handle = <&pll>;
238
239 phy-mode = "rgmii";
240
241 resets = <&rst 13>;
242 reset-names = "mac";
243 qca,mac-idx = <1>;
244 };