oxnas: reboot target
authorDaniel Golle <daniel@makrotopia.org>
Thu, 31 May 2018 15:28:38 +0000 (17:28 +0200)
committerDaniel Golle <daniel@makrotopia.org>
Mon, 18 Jun 2018 16:44:14 +0000 (18:44 +0200)
Reboot the oxnas target based on Linux 4.14 by rebasing our support on
top of the now-existing upstream kernel support.
This commit brings oxnas support to the level of v4.17 having upstream
drivers for Ethernet, Serial and NAND flash.
Botch up OpenWrt's local drivers for EHCI, SATA and PCIe based on the
new platform code and device-tree.
Re-introduce base-files from old oxnas target which works for now but
needs further clean-up towards generic board support.

Functional issues:
 * PCIe won't come up (hence no USB3 on Shuttle KD20)
 * I2C bus of Akitio myCloud device is likely not to work (missing
   debounce support in new pinctrl driver)

Code-style issues:
 * plla/pllb needs further cleanup -- currently their users are writing
   into the syscon regmap after acquireling the clk instead of using
   defined clk_*_*() functions to setup multipliers and dividors.
 * PCIe phy needs its own little driver.
 * SATA driver is a monster and should be split into an mfd having
   a raidctrl regmap, sata controller, sata ports and sata phy.

Tested on MitraStar STG-212 aka. Medion Akoya MD86xxx and Shuttle KD20.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(squash-picked commit 17511a7ea8 and commit dcc34574ef from master)

81 files changed:
package/boot/uboot-oxnas/src/include/configs/ox820.h
target/linux/oxnas/Makefile
target/linux/oxnas/config-4.14 [new file with mode: 0644]
target/linux/oxnas/config-4.4 [deleted file]
target/linux/oxnas/files/arch/arm/boot/dts/ox820-akitio-mycloud.dts [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/boot/dts/ox820-akitio.dts [deleted file]
target/linux/oxnas/files/arch/arm/boot/dts/ox820-cloudengines-pogoplug-pro.dts [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/boot/dts/ox820-kd20.dts [deleted file]
target/linux/oxnas/files/arch/arm/boot/dts/ox820-mitrastar-stg212.dts [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-pro.dts [deleted file]
target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-v3.dts [deleted file]
target/linux/oxnas/files/arch/arm/boot/dts/ox820-shuttle-kd20.dts [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/boot/dts/ox820-stg212.dts [deleted file]
target/linux/oxnas/files/arch/arm/boot/dts/ox820.dtsi [deleted file]
target/linux/oxnas/files/arch/arm/configs/ox820_defconfig [deleted file]
target/linux/oxnas/files/arch/arm/include/debug/uncompress-ox820.h [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/mach-oxnas/Kconfig [deleted file]
target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile [deleted file]
target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile.boot [deleted file]
target/linux/oxnas/files/arch/arm/mach-oxnas/fiq.S [deleted file]
target/linux/oxnas/files/arch/arm/mach-oxnas/headsmp.S [deleted file]
target/linux/oxnas/files/arch/arm/mach-oxnas/hotplug.c [deleted file]
target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/hardware.h [deleted file]
target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/iomap.h [deleted file]
target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/irqs.h [deleted file]
target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/smp.h [deleted file]
target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/timex.h [deleted file]
target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/uncompress.h [deleted file]
target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/utils.h [deleted file]
target/linux/oxnas/files/arch/arm/mach-oxnas/mach-ox820.c [deleted file]
target/linux/oxnas/files/arch/arm/mach-oxnas/platsmp.c [deleted file]
target/linux/oxnas/files/drivers/ata/sata_oxnas.c
target/linux/oxnas/files/drivers/clk/clk-oxnas.c [deleted file]
target/linux/oxnas/files/drivers/clocksource/oxnas_rps_timer.c [deleted file]
target/linux/oxnas/files/drivers/irqchip/irq-rps.c [deleted file]
target/linux/oxnas/files/drivers/mtd/nand/oxnas_nand.c [deleted file]
target/linux/oxnas/files/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c [deleted file]
target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c
target/linux/oxnas/files/drivers/pinctrl/pinctrl-oxnas.c [deleted file]
target/linux/oxnas/files/drivers/reset/reset-ox820.c [deleted file]
target/linux/oxnas/files/drivers/usb/host/ehci-oxnas.c
target/linux/oxnas/image/Makefile
target/linux/oxnas/image/ox810se.mk [new file with mode: 0644]
target/linux/oxnas/image/ox820.mk [new file with mode: 0644]
target/linux/oxnas/modules.mk
target/linux/oxnas/ox810se/config-default [new file with mode: 0644]
target/linux/oxnas/ox810se/profiles/00-default.mk [new file with mode: 0644]
target/linux/oxnas/ox810se/target.mk [new file with mode: 0644]
target/linux/oxnas/ox820/config-default [new file with mode: 0644]
target/linux/oxnas/ox820/profiles/00-default.mk [new file with mode: 0644]
target/linux/oxnas/ox820/target.mk [new file with mode: 0644]
target/linux/oxnas/patches-4.14/0001-ARM-dts-rename-oxnas-dts-files.patch [new file with mode: 0644]
target/linux/oxnas/patches-4.14/0002-MAINTAINERS-update-ARM-OXNAS-platform-support-patter.patch [new file with mode: 0644]
target/linux/oxnas/patches-4.14/0003-ARM-configs-add-OXNAS-v6-defconfig.patch [new file with mode: 0644]
target/linux/oxnas/patches-4.14/050-ox820-remove-left-overs.patch [new file with mode: 0644]
target/linux/oxnas/patches-4.14/100-oxnas-clk-plla-pllb.patch [new file with mode: 0644]
target/linux/oxnas/patches-4.14/340-oxnas-pcie.patch [new file with mode: 0644]
target/linux/oxnas/patches-4.14/500-oxnas-sata.patch [new file with mode: 0644]
target/linux/oxnas/patches-4.14/510-ox820-libata-leds.patch [new file with mode: 0644]
target/linux/oxnas/patches-4.14/800-oxnas-ehci.patch [new file with mode: 0644]
target/linux/oxnas/patches-4.14/996-generic-Mangle-bootloader-s-kernel-arguments.patch [new file with mode: 0644]
target/linux/oxnas/patches-4.14/999-libata-hacks.patch [new file with mode: 0644]
target/linux/oxnas/patches-4.4/0072-mtd-backport-v4.7-0day-patches-from-Boris.patch [deleted file]
target/linux/oxnas/patches-4.4/0073-of-mtd-prepare-helper-reading-NAND-ECC-algo-from-DT.patch [deleted file]
target/linux/oxnas/patches-4.4/0074-mtd-nand-import-nand_hw_control_init.patch [deleted file]
target/linux/oxnas/patches-4.4/010-arm_introduce-dma-fiq-irq-broadcast.patch [deleted file]
target/linux/oxnas/patches-4.4/250-add-plxtech-vendor-prefix.patch [deleted file]
target/linux/oxnas/patches-4.4/300-introduce-oxnas-platform.patch [deleted file]
target/linux/oxnas/patches-4.4/310-oxnas-clocksource.patch [deleted file]
target/linux/oxnas/patches-4.4/320-oxnas-irqchip.patch [deleted file]
target/linux/oxnas/patches-4.4/330-oxnas-pinctrl.patch [deleted file]
target/linux/oxnas/patches-4.4/340-oxnas-pcie.patch [deleted file]
target/linux/oxnas/patches-4.4/350-oxnas-reset.patch [deleted file]
target/linux/oxnas/patches-4.4/400-oxnas-nand.patch [deleted file]
target/linux/oxnas/patches-4.4/500-oxnas-sata.patch [deleted file]
target/linux/oxnas/patches-4.4/700-oxnas-dwmac.patch [deleted file]
target/linux/oxnas/patches-4.4/800-oxnas-ehci.patch [deleted file]
target/linux/oxnas/patches-4.4/900-more-boards.patch [deleted file]
target/linux/oxnas/patches-4.4/996-ATAG_DTB_COMPAT_CMDLINE_MANGLE.patch [deleted file]
target/linux/oxnas/patches-4.4/999-libata-hacks.patch [deleted file]
target/linux/oxnas/profiles/00-default.mk [deleted file]

index 85ee3b4..65618ae 100644 (file)
 #define CONFIG_CMD_GETTIME
 #define CONFIG_CMD_BOOTMENU
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_BOOZ
 
 #define CONFIG_DOS_PARTITION
 #define CONFIG_EFI_PARTITION
index 0d9d356..52d57f3 100644 (file)
@@ -1,29 +1,21 @@
-#
-# Copyright (C) 2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
 include $(TOPDIR)/rules.mk
 
 ARCH:=arm
 BOARD:=oxnas
-BOARDNAME:=PLXTECH/Oxford NAS782x/OX82x
+BOARDNAME:=PLXTECH/Oxford NAS782x/OX8xx
+SUBTARGETS:=ox810se ox820
+FEATURES:=gpio ramdisk rtc squashfs
 DEVICE_TYPE:=nas
-FEATURES:=gpio nand pcie usb ramdisk rtc squashfs ubifs
-CPU_TYPE:=mpcore
 
 MAINTAINER:=Daniel Golle <daniel@makrotopia.org>
 
-KERNEL_PATCHVER:=4.4
+KERNEL_PATCHVER:=4.14
 
 include $(INCLUDE_DIR)/target.mk
 
 DEFAULT_PACKAGES += \
-       kmod-ata-core kmod-ata-oxnas-sata kmod-button-hotplug \
-       kmod-input-gpio-keys-polled kmod-usb-ledtrig-usbport \
-       kmod-ledtrig-timer kmod-leds-gpio kmod-usb2-oxnas \
-       kmod-usb-storage uboot-envtools uboot-oxnas-ox820
+       kmod-button-hotplug kmod-input-gpio-keys-polled \
+       kmod-ledtrig-timer kmod-leds-gpio uboot-envtools
 
 KERNELNAME:=zImage dtbs
 
diff --git a/target/linux/oxnas/config-4.14 b/target/linux/oxnas/config-4.14
new file mode 100644 (file)
index 0000000..4d6943a
--- /dev/null
@@ -0,0 +1,359 @@
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_ARCH_HAS_SET_MEMORY=y
+CONFIG_ARCH_HAS_SG_CHAIN=y
+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
+CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set
+CONFIG_ARCH_OXNAS=y
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ARM=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
+# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_PMU=y
+# CONFIG_ARM_SMMU is not set
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_TIMER_SP804=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ATAGS=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINARY_PRINTF=y
+CONFIG_BLK_CMDLINE_PARSER=y
+CONFIG_BLK_DEBUG_FS=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=65536
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_SCSI_REQUEST=y
+# CONFIG_BPF_SYSCALL is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=64
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+CONFIG_CMDLINE_PARTITION=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_OXNAS=y
+CONFIG_COMPACTION=y
+CONFIG_COMPAT_BRK=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_COREDUMP=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_ACOMP2=y
+# CONFIG_CRYPTO_ARC4 is not set
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_DEBUG_ALIGN_RODATA=y
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_USER is not set
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_LZ4=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_DEVMEM=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DMA_CMA=y
+CONFIG_DNOTIFY=y
+CONFIG_DTC=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_DWMAC_DWC_QOS_ETH is not set
+CONFIG_DWMAC_GENERIC=y
+CONFIG_DWMAC_OXNAS=y
+CONFIG_EARLY_PRINTK=y
+# CONFIG_EDAC_SUPPORT is not set
+CONFIG_ELF_CORE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GRO_CELLS=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+# CONFIG_HAVE_ARCH_BITREVERSE is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_HAVE_EBPF_JIT=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_OPTPROBES=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_UID16=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HID=y
+CONFIG_HID_GENERIC=y
+CONFIG_HWMON=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HZ_FIXED=0
+CONFIG_ICPLUS_PHY=y
+CONFIG_INET_DIAG=y
+# CONFIG_INET_DIAG_DESTROY is not set
+# CONFIG_INET_RAW_DIAG is not set
+CONFIG_INET_TCP_DIAG=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_IOMMU_HELPER=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISDN is not set
+CONFIG_JBD2=y
+# CONFIG_JFFS2_FS is not set
+CONFIG_KALLSYMS=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_XZ is not set
+CONFIG_KEXEC=y
+CONFIG_KEXEC_CORE=y
+# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_NETDEV is not set
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_LIBFDT=y
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MULTI_IRQ_HANDLER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NLS=y
+CONFIG_NOP_TRACER=y
+CONFIG_NO_BOOTMEM=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OXNAS_RPS_TIMER=y
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_OXNAS=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_PPS=y
+CONFIG_PROBE_EVENTS=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RCU_TRACE=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_GZIP=y
+CONFIG_RD_LZ4=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_LZO=y
+CONFIG_RD_XZ=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_OXNAS=y
+CONFIG_RING_BUFFER=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHED_INFO is not set
+# CONFIG_SCSI_DMA is not set
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIO=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SIMPLE_PM_BUS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_SOCK_DIAG=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SRCU=y
+CONFIG_STACKTRACE=y
+# CONFIG_STAGING is not set
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UPROBES=y
+CONFIG_UPROBE_EVENTS=y
+CONFIG_USB_SUPPORT=y
+# CONFIG_USERIO is not set
+CONFIG_USE_OF=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_VERSATILE_FPGA_IRQ=y
+CONFIG_VERSATILE_FPGA_IRQ_NR=4
+CONFIG_VFAT_FS=y
+# CONFIG_VFP is not set
+# CONFIG_VLAN_8021Q is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_WATCHDOG is not set
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
diff --git a/target/linux/oxnas/config-4.4 b/target/linux/oxnas/config-4.4
deleted file mode 100644 (file)
index 0c6e992..0000000
+++ /dev/null
@@ -1,366 +0,0 @@
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_APM_EMULATION is not set
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAS_SG_CHAIN=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OXNAS=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARCH_WANT_LIBATA_LEDS=y
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
-# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
-CONFIG_ARM_CPUIDLE=y
-# CONFIG_ARM_CPU_SUSPEND is not set
-CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8
-CONFIG_ARM_DMA_USE_IOMMU=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_SMMU=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ATAGS=y
-CONFIG_ATA_LEDS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BLK_DEV_BSG=y
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
-CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=1
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_OF=y
-CONFIG_CLKSRC_PROBE=y
-CONFIG_CLKSRC_RPS_TIMER=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="console=ttyS0,115200n8 earlyprintk=serial"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACTION=y
-CONFIG_CONSOLE_POLL=y
-CONFIG_COREDUMP=y
-CONFIG_CPU_32v6=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_ABRT_EV6=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V6=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_PABRT_V6=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-# CONFIG_CPU_SW_DOMAIN_PAN is not set
-CONFIG_CPU_TLB_V6=y
-CONFIG_CPU_V6K=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_ICEDCC=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/icedcc.S"
-# CONFIG_DEBUG_UART_8250 is not set
-# CONFIG_DEBUG_USER is not set
-CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=16
-CONFIG_DEPRECATED_PARAM_STRUCT=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_CACHE_FIQ_BROADCAST=y
-# CONFIG_DMA_CACHE_RWFO is not set
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-CONFIG_DT_IDLE_STATES=y
-CONFIG_DWMAC_GENERIC=y
-CONFIG_DWMAC_OXNAS=y
-# CONFIG_DWMAC_SUNXI is not set
-# CONFIG_DW_DMAC_PCI is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_FIQ=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_AUDITSYSCALL=y
-# CONFIG_HAVE_ARCH_BITREVERSE is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_ARM_SCU=y
-CONFIG_HAVE_ARM_TWD=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_OPTPROBES=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SMP=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_INPUT=y
-# CONFIG_INPUT_MISC is not set
-CONFIG_IOMMU_API=y
-CONFIG_IOMMU_HELPER=y
-CONFIG_IOMMU_IO_PGTABLE=y
-CONFIG_IOMMU_IO_PGTABLE_LPAE=y
-# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
-CONFIG_IOMMU_SUPPORT=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-# CONFIG_IP_MULTICAST is not set
-CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_BOOTP is not set
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IP_PNP_RARP is not set
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_ISDN is not set
-# CONFIG_JFFS2_FS is not set
-CONFIG_JUMP_LABEL=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_KGDB=y
-# CONFIG_KGDB_KDB is not set
-CONFIG_KGDB_SERIAL_CONSOLE=y
-# CONFIG_KGDB_TESTS is not set
-# CONFIG_LDM_DEBUG is not set
-CONFIG_LDM_PARTITION=y
-# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
-# CONFIG_LEDS_TRIGGER_NETDEV is not set
-# CONFIG_LEDS_TRIGGER_TIMER is not set
-CONFIG_LIBFDT=y
-CONFIG_LOCKUP_DETECTOR=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MACH_OX820=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAILBOX=y
-# CONFIG_MAILBOX_TEST is not set
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_PCI=y
-CONFIG_MIGRATION=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MODULE_STRIPPED is not set
-# CONFIG_MTD_CFI is not set
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_OXNAS=y
-# CONFIG_MTD_SPLIT_FIRMWARE is not set
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-# CONFIG_MTD_UBI_FASTMAP is not set
-# CONFIG_MTD_UBI_GLUEBI is not set
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NLS=y
-CONFIG_NO_BOOTMEM=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=2
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_ADDRESS_PCI=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IOMMU=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_OF_RESERVED_MEM=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-# CONFIG_PCIEASPM_DEBUG is not set
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-# CONFIG_PCIEASPM_POWERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_PME=y
-# CONFIG_PCI_DOMAINS_GENERIC is not set
-CONFIG_PCI_OXNAS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_OXNAS=y
-CONFIG_PLXTECH_RPS=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_GPIO=y
-CONFIG_POWER_RESET_SYSCON_POWEROFF=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PWM=y
-CONFIG_PWM_SYSFS=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_RCU_CPU_STALL_TIMEOUT=21
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RELAY=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_CONTROLLER_OXNAS=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_CMOS is not set
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-# CONFIG_SCHED_INFO is not set
-CONFIG_SCSI=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_NR_UARTS=1
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_RUNTIME_UARTS=1
-# CONFIG_SERIAL_KGDB_NMI is not set
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SRCU=y
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_PLATFORM=y
-# CONFIG_STRIP_ASM_SYMS is not set
-CONFIG_SWIOTLB=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TREE_RCU=y
-CONFIG_UBIFS_FS=y
-# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-CONFIG_UBIFS_FS_LZO=y
-CONFIG_UBIFS_FS_ZLIB=y
-CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h"
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-# CONFIG_USB_EHCI_HCD is not set
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_USE_OF=y
-CONFIG_VECTORS_BASE=0xffff0000
-# CONFIG_VFIO is not set
-# CONFIG_VFP is not set
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_XPS=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA_FLAG=0
diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-akitio-mycloud.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-akitio-mycloud.dts
new file mode 100644 (file)
index 0000000..c0bf34c
--- /dev/null
@@ -0,0 +1,157 @@
+/dts-v1/;
+
+#include "ox820.dtsi"
+
+#include <dt-bindings/input/input.h>
+
+/ {
+       model = "Akitio MyCloud";
+
+       compatible = "akitio,mycloud", "oxsemi,ox820";
+
+       chosen {
+               bootargs = "earlyprintk";
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory {
+               /* 128Mbytes DDR */
+               reg = <0x60000000 0x8000000>;
+       };
+
+       aliases {
+               serial0 = &uart0;
+               gpio0 = &gpio0;
+               gpio1 = &gpio1;
+       };
+
+       i2c-gpio {
+               compatible = "i2c-gpio";
+               gpios = <&gpio1 9 0 &gpio1 10 0>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_i2c>;
+               i2c-gpio,delay-us = <10>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               ds1307: rtc@68 {
+                       compatible = "dallas,ds1307";
+                       reg = <0x68>;
+               };
+       };
+
+       gpio-keys-polled {
+               compatible = "gpio-keys-polled";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_buttons>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               poll-interval = <100>;
+               power {
+                       label = "power";
+                       gpios = <&gpio0 11 1>;
+                       linux,code = <KEY_POWER>;
+               };
+               reset {
+                       label = "reset";
+                       gpios = <&gpio1 6 1>;
+                       linux,code = <KEY_RESTART>;
+               };
+       };
+
+       gpio-leds {
+               compatible = "gpio-leds";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_leds>;
+               status {
+                       label = "akitio:red:status";
+                       gpios = <&gpio0 29 0>;
+               };
+       };
+
+       gpio-poweroff {
+               compatible = "gpio-poweroff";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_poweroff>;
+               gpios = <&gpio1 13 2>;
+       };
+};
+
+&pinctrl {
+       pinctrl_i2c: i2c-0 {
+               i2c {
+                       pins = "gpio41", "gpio42"; /* MF_B9, MF_B10 */
+                       function = "gpio";
+                       /* ToDo: find a way to set debounce for those pins */
+               };
+       };
+       pinctrl_buttons: buttons-0 {
+               buttons {
+                       pins = "gpio11", "gpio38"; /* MF_A11, MF_B6 GPIO */
+                       function = "gpio";
+               };
+       };
+       pinctrl_leds: leds-0 {
+               leds {
+                       pins = "gpio29"; /* MF_A29 GPIO */
+                       function = "gpio";
+               };
+       };
+       pinctrl_poweroff: poweroff-0 {
+               poweroff {
+                       pins = "gpio45"; /* MF_B13 GPIO */
+                       function = "gpio";
+               };
+       };
+};
+
+&uart0 {
+       status = "okay";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart0>;
+};
+
+&nandc {
+       status = "okay";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_nand>;
+
+       nand@0 {
+               reg = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               nand-ecc-mode = "soft";
+               nand-ecc-algo = "hamming";
+
+               partition@0 {
+                       label = "boot";
+                       reg = <0x0 0x26c0000>;
+               };
+
+               partition@26c0000 {
+                       label = "ubi";
+                       reg = <0x26c0000 0xd940000>;
+               };
+       };
+};
+
+&etha {
+       status = "okay";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_etha_mdio>;
+};
+
+&ehci {
+       status = "okay";
+};
+
+&sata {
+       status = "okay";
+       nr-ports = <2>;
+};
+
+&pcie0 {
+       status = "okay";
+};
diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-akitio.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-akitio.dts
deleted file mode 100644 (file)
index 54aad1d..0000000
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * Copyright (C) 2016 Daniel Golle <daniel@makrotopia.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/dts-v1/;
-#include "ox820.dtsi"
-
-#include <dt-bindings/input/input.h>
-
-/ {
-       model = "Akitio MyCloud mini";
-
-       chosen {
-               bootargs = "console=ttyS0,115200n8 earlyprintk=serial";
-       };
-
-       pcie-controller@47C00000 {
-               status = "disabled";
-       };
-
-       uart@44200000 {
-               status = "okay";
-       };
-
-       sata@45900000 {
-               status = "okay";
-               nr-ports = <2>;
-       };
-
-       nand@41000000 {
-               status = "okay";
-
-       };
-
-       ethernet@40400000 {
-               status = "okay";
-       };
-
-       ehci@40200100 {
-               status = "okay";
-       };
-
-       i2c-gpio {
-               compatible = "i2c-gpio";
-               gpios = <&GPIOB 9 0 &GPIOB 10 0>;
-               pinctrl-names = "default";
-               pinctrl-0 = <&pinctrl_i2c>;
-               i2c-gpio,delay-us = <10>;
-               #address-cells = <1>;
-               #size-cells = <0>;
-               ds1307: rtc@68 {
-                       compatible = "dallas,ds1307";
-                       reg = <0x68>;
-               };
-       };
-
-       gpio-keys-polled {
-               compatible = "gpio-keys-polled";
-               pinctrl-names = "default";
-               pinctrl-0 = <&pinctrl_buttons>;
-               #address-cells = <1>;
-               #size-cells = <0>;
-               poll-interval = <100>;
-               power {
-                       label = "power";
-                       gpios = <&GPIOA 11 1>;
-                       linux,code = <KEY_POWER>;
-               };
-               reset {
-                       label = "reset";
-                       gpios = <&GPIOB 6 1>;
-                       linux,code = <KEY_RESTART>;
-               };
-       };
-
-       gpio-leds {
-               compatible = "gpio-leds";
-               pinctrl-names = "default";
-               pinctrl-0 = <&pinctrl_leds>;
-               status {
-                       label = "akitio:red:status";
-                       gpios = <&GPIOA 29 0>;
-               };
-       };
-
-       gpio-poweroff {
-               compatible = "gpio-poweroff";
-               pinctrl-names = "default";
-               pinctrl-0 = <&pinctrl_poweroff>;
-               gpios = <&GPIOB 13 2>;
-       };
-
-       pinctrl {
-               i2c {
-                       pinctrl_i2c: i2c-0 {
-                               plxtech,pins =
-                                       <1  9 0 4       /* MF_B9 GPIO debounce */
-                                        1 10 0 4>;     /* MF_B10 GPIO debounce */
-                       };
-               };
-               buttons {
-                       pinctrl_buttons: buttons-0 {
-                               plxtech,pins =
-                                       <0 11 0 0       /* MF_A11 GPIO */
-                                        1  6 0 0>;     /* MF_B6 GPIO */
-                       };
-               };
-               leds {
-                       pinctrl_leds: leds-0 {
-                               plxtech,pins =
-                                       <0 29 0 0>;     /* MF_A29 GPIO */
-                       };
-               };
-               poweroff {
-                       pinctrl_poweroff: poweroff-0 {
-                               plxtech,pins =
-                                       <1 13 0 0>;     /* MF_B13 GPIO */
-                       };
-               };
-       };
-};
-
-&nandc {
-       status = "okay";
-
-       nand@0 {
-               reg = <0>;
-               #address-cells = <1>;
-               #size-cells = <1>;
-               nand-ecc-mode = "soft";
-               nand-ecc-algo = "hamming";
-
-               partition@0 {
-                       label = "boot";
-                       reg = <0x00000000 0x026c0000>;
-               };
-
-               partition@26c0000 {
-                       label = "ubi";
-                       reg = <0x026c0000 0x0d940000>;
-               };
-       };
-};
diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-cloudengines-pogoplug-pro.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-cloudengines-pogoplug-pro.dts
new file mode 100644 (file)
index 0000000..363fd30
--- /dev/null
@@ -0,0 +1,98 @@
+/*
+ * cloudengines-pogoplug-series-3.dtsi - Device tree file for Cloud Engines PogoPlug Series 3
+ *
+ * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+#include "ox820.dtsi"
+
+/ {
+       model = "Cloud Engines PogoPlug Pro";
+
+       compatible = "cloudengines,pogoplugpro", "oxsemi,ox820";
+
+       chosen {
+               bootargs = "earlyprintk";
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory {
+               /* 128Mbytes DDR */
+               reg = <0x60000000 0x8000000>;
+       };
+
+       aliases {
+               serial0 = &uart0;
+               gpio0 = &gpio0;
+               gpio1 = &gpio1;
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               blue {
+                       label = "pogoplug:blue";
+                       gpios = <&gpio0 2 0>;
+                       default-state = "keep";
+               };
+
+               orange {
+                       label = "pogoplug:orange";
+                       gpios = <&gpio1 16 1>;
+                       default-state = "keep";
+               };
+
+               green {
+                       label = "pogoplug:green";
+                       gpios = <&gpio1 17 1>;
+                       default-state = "keep";
+               };
+       };
+};
+
+&uart0 {
+       status = "okay";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart0>;
+};
+
+&nandc {
+       status = "okay";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_nand>;
+
+       nand@0 {
+               reg = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               nand-ecc-mode = "soft";
+               nand-ecc-algo = "hamming";
+
+               partition@0 {
+                       label = "boot";
+                       reg = <0x00000000 0x00e00000>;
+                       read-only;
+               };
+
+               partition@e00000 {
+                       label = "ubi";
+                       reg = <0x00e00000 0x07200000>;
+               };
+       };
+};
+
+&etha {
+       status = "okay";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_etha_mdio>;
+};
+
+&pcie0 {
+       status = "okay";
+};
diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-kd20.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-kd20.dts
deleted file mode 100644 (file)
index a59addc..0000000
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * Copyright (C) 2014 Daniel Golle <daniel@makrotopia.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/dts-v1/;
-#include "ox820.dtsi"
-
-#include <dt-bindings/input/input.h>
-
-/ {
-       model = "Shuttle KD20";
-
-       chosen {
-               bootargs = "console=ttyS0,115200n8 earlyprintk=serial mem=256M";
-       };
-
-       pcie-controller@47C00000 {
-               status = "okay";
-       };
-
-       uart@44200000 {
-               status = "okay";
-       };
-
-       sata@45900000 {
-               status = "okay";
-               nr-ports = <2>;
-       };
-
-       ethernet@40400000 {
-               status = "okay";
-               snps,phy-addr = <1>;
-               phy-mode = "rgmii-id";
-       };
-
-       ehci@40200100 {
-               status = "okay";
-       };
-
-       i2c-gpio {
-               compatible = "i2c-gpio";
-               gpios = <&GPIOB 9 0 &GPIOB 10 0>;
-               i2c-gpio,delay-us = <10>;
-               #address-cells = <1>;
-               #size-cells = <0>;
-               pcf8563: rtc@51 {
-                       compatible = "nxp,pcf8563";
-                       reg = <0x51>;
-               };
-       };
-
-       gpio-keys-polled {
-               compatible = "gpio-keys-polled";
-               #address-cells = <1>;
-               #size-cells = <0>;
-               poll-interval = <100>;
-
-               power {
-                       label = "power";
-                       gpios = <&GPIOA 10 1>;
-                       linux,code = <KEY_POWER>;
-               };
-               reset {
-                       label = "reset";
-                       gpios = <&GPIOA 11 1>;
-                       linux,code = <KEY_RESTART>;
-               };
-               eject1 {
-                       label = "eject1";
-                       gpios = <&GPIOA 5 1>;
-                       linux,code = <KEY_EJECTCD>;
-               };
-               eject2 {
-                       label = "eject2";
-                       gpios = <&GPIOA 6 1>;
-                       linux,code = <162>;
-               };
-       };
-
-       gpio-leds {
-               compatible = "gpio-leds";
-               status {
-                       label = "kd20:blue:status";
-                       gpios = <&GPIOB 16 0>;
-               };
-               status2 {
-                       label = "kd20:red:status";
-                       gpios = <&GPIOB 17 0>;
-               };
-               hdd1blue {
-                       label = "kd20:blue:hdd1";
-                       gpios = <&GPIOA 27 0>;
-                       linux,default-trigger = "ata1";
-               };
-               hdd1red {
-                       label = "kd20:red:hdd1";
-                       gpios = <&GPIOB 4 0>;
-               };
-               hdd2blue {
-                       label = "kd20:blue:hdd2";
-                       gpios = <&GPIOB 6 0>;
-                       linux,default-trigger = "ata2";
-               };
-               hdd2red {
-                       label = "kd20:red:hdd2";
-                       gpios = <&GPIOB 7 0>;
-               };
-               usb {
-                       label = "kd20:blue:usb";
-                       gpios = <&GPIOB 8 0>;
-               };
-       };
-
-       beeper: beeper {
-               compatible = "gpio-beeper";
-               gpios = <&GPIOB 11 0>;
-       };
-
-       gpio-fan {
-               compatible = "gpio-fan";
-               gpios = <&GPIOA 2 1>;
-               gpio-fan,speed-map = <0    0
-                                     3000 1>;
-       };
-
-       gpio-poweroff {
-               compatible = "gpio-poweroff";
-               gpios = <&GPIOA 9 0>;
-       };
-};
-
-&nandc {
-       status = "okay";
-
-       nand@0 {
-               reg = <0>;
-               #address-cells = <1>;
-               #size-cells = <1>;
-               nand-ecc-mode = "soft";
-               nand-ecc-algo = "hamming";
-
-               partition@0 {
-                       label = "stage1";
-                       reg = <0x00000000 0x00040000>;
-                       read-only;
-               };
-
-               partition@40000 {
-                       label = "u-boot";
-                       reg = <0x00040000 0x00200000>;
-                       read-only;
-               };
-
-               partition@240000 {
-                       label = "initrd";
-                       reg = <0x00240000 0x00600000>;
-               };
-
-               partition@840000 {
-                       label = "kernel";
-                       reg = <0x00840000 0x007C0000>;
-               };
-
-               partition@e00000 {
-                       label = "ubi";
-                       reg = <0x01000000 0x07000000>;
-               };
-       };
-};
diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-mitrastar-stg212.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-mitrastar-stg212.dts
new file mode 100644 (file)
index 0000000..834ea77
--- /dev/null
@@ -0,0 +1,116 @@
+/dts-v1/;
+
+#include "ox820.dtsi"
+
+#include <dt-bindings/input/input.h>
+
+/ {
+       model = "MitraStar Technology Corp. STG-212";
+
+       compatible = "mitrastar,stg-212", "oxsemi,ox820";
+
+       chosen {
+               bootargs = "earlyprintk";
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory {
+               /* 128Mbytes DDR */
+               reg = <0x60000000 0x8000000>;
+       };
+
+       aliases {
+               serial0 = &uart0;
+               gpio0 = &gpio0;
+               gpio1 = &gpio1;
+       };
+
+       gpio-keys-polled {
+               compatible = "gpio-keys-polled";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               poll-interval = <100>;
+
+               reset {
+                       label = "reset";
+                       gpios = <&gpio1 11 1>;
+                       linux,code = <KEY_RESTART>;
+               };
+               copy {
+                       label = "copy";
+                       gpios = <&gpio1 13 1>;
+                       linux,code = <KEY_COPY>;
+               };
+       };
+
+       gpio-leds {
+               compatible = "gpio-leds";
+               status {
+                       label = "zyxel:blue:status";
+                       gpios = <&gpio1 5 0>;
+               };
+               status2 {
+                       label = "zyxel:red:status";
+                       gpios = <&gpio1 6 1>;
+               };
+               copy {
+                       label = "zyxel:orange:copy";
+                       gpios = <&gpio1 8 1>;
+               };
+       };
+
+       i2c-gpio {
+               compatible = "i2c-gpio";
+               gpios = <&gpio1 9 0 &gpio1 10 0>;
+               i2c-gpio,delay-us = <10>;
+       };
+
+};
+
+&uart0 {
+       status = "okay";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart0>;
+};
+
+&nandc {
+       status = "okay";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_nand>;
+
+       nand@0 {
+               reg = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               nand-ecc-mode = "soft";
+               nand-ecc-algo = "hamming";
+
+               partition@0 {
+                       label = "boot";
+                       reg = <0x00000000 0x00e00000>;
+                       read-only;
+               };
+
+               partition@e00000 {
+                       label = "ubi";
+                       reg = <0x00e00000 0x07200000>;
+               };
+       };
+};
+
+&etha {
+       status = "okay";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_etha_mdio>;
+};
+
+&ehci {
+       status = "okay";
+};
+
+&sata {
+       status = "okay";
+};
diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-pro.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-pro.dts
deleted file mode 100644 (file)
index 5b087e9..0000000
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/dts-v1/;
-#include "ox820.dtsi"
-
-/ {
-       model = "Pogoplug Pro";
-
-       chosen {
-               bootargs = "console=ttyS0,115200n8 earlyprintk=serial";
-       };
-
-       pcie-controller@47C00000 {
-               status = "okay";
-       };
-
-       uart@44200000 {
-               status = "okay";
-       };
-
-       sata@45900000 {
-               status = "okay";
-       };
-
-       ethernet@40400000 {
-               status = "okay";
-       };
-
-       ehci@40200100 {
-               status = "okay";
-       };
-
-       pinctrl {
-               leds {
-                       pinctrl_leds: leds-0 {
-                               plxtech,pins =
-                                       <0 2 0 0        /* MF_A2 */
-                                        1 16 0 0       /* MF_B16 */
-                                        1 17 0 0>;     /* MF_B17 */
-                       };
-               };
-       };
-
-       leds {
-               compatible = "gpio-leds";
-               pinctrl-names = "default";
-               pinctrl-0 = <&pinctrl_leds>;
-
-               blue {
-                       label = "pogoplug:blue:internal";
-                       gpios = <&GPIOA 2 0>;
-
-               };
-
-               orange {
-                       label = "pogoplug:orange:usr";
-                       gpios = <&GPIOB 16 1>;
-               };
-
-               green {
-                       label = "pogoplug:green:usr";
-                       gpios = <&GPIOB 17 1>;
-               };
-       };
-};
-
-&nandc {
-       status = "okay";
-
-       nand@0 {
-               reg = <0>;
-               #address-cells = <1>;
-               #size-cells = <1>;
-               nand-ecc-mode = "soft";
-               nand-ecc-algo = "hamming";
-
-               partition@0 {
-                       label = "boot";
-                       reg = <0x00000000 0x00e00000>;
-                       /*read-only;*/
-               };
-
-               partition@e00000 {
-                       label = "ubi";
-                       reg = <0x00e00000 0x07200000>;
-               };
-       };
-};
diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-v3.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-v3.dts
deleted file mode 100644 (file)
index be0f6c9..0000000
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright (C) 2014 Daniel Golle <daniel@makrotopia.org>
- * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/dts-v1/;
-#include "ox820.dtsi"
-
-/ {
-       model = "Pogoplug V3";
-
-       chosen {
-               bootargs = "console=ttyS0,115200n8 earlyprintk=serial";
-       };
-
-       uart@44200000 {
-               status = "okay";
-       };
-
-       sata@45900000 {
-               status = "okay";
-       };
-
-       ethernet@40400000 {
-               status = "okay";
-       };
-
-       ehci@40200100 {
-               status = "okay";
-       };
-
-       pinctrl {
-               leds {
-                       pinctrl_leds: leds-0 {
-                               plxtech,pins =
-                                       <0 2 0 0        /* MF_A2 */
-                                        1 16 0 0       /* MF_B16 */
-                                        1 17 0 0>;     /* MF_B17 */
-                       };
-               };
-       };
-
-       leds {
-               compatible = "gpio-leds";
-               pinctrl-names = "default";
-               pinctrl-0 = <&pinctrl_leds>;
-
-               blue {
-                       label = "pogoplug:blue:internal";
-                       gpios = <&GPIOA 2 0>;
-               };
-
-               orange {
-                       label = "pogoplug:orange:usr";
-                       gpios = <&GPIOB 16 1>;
-               };
-
-               green {
-                       label = "pogoplug:green:usr";
-                       gpios = <&GPIOB 17 1>;
-               };
-       };
-
-};
-
-&nandc {
-       status = "okay";
-
-       nand@0 {
-               reg = <0>;
-               #address-cells = <1>;
-               #size-cells = <1>;
-               nand-ecc-mode = "soft";
-               nand-ecc-algo = "hamming";
-
-               partition@0 {
-                       label = "boot";
-                       reg = <0x00000000 0x00e00000>;
-                       /*read-only;*/
-               };
-
-               partition@e00000 {
-                       label = "ubi";
-                       reg = <0x00e00000 0x07200000>;
-               };
-       };
-};
diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-shuttle-kd20.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-shuttle-kd20.dts
new file mode 100644 (file)
index 0000000..badfa25
--- /dev/null
@@ -0,0 +1,187 @@
+/dts-v1/;
+
+#include "ox820.dtsi"
+
+#include <dt-bindings/input/input.h>
+
+/ {
+       model = "Shuttle KD20";
+
+       compatible = "shuttle,kd20", "oxsemi,ox820";
+
+       chosen {
+               bootargs = "earlyprintk";
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory {
+               /* 128Mbytes DDR */
+               reg = <0x60000000 0x8000000>;
+       };
+
+       aliases {
+               serial0 = &uart0;
+               gpio0 = &gpio0;
+               gpio1 = &gpio1;
+       };
+
+       i2c-gpio {
+               compatible = "i2c-gpio";
+               gpios = <&gpio1 9 0 &gpio1 10 0>;
+               i2c-gpio,delay-us = <10>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               rtc0: rtc@51 {
+                       compatible = "nxp,pcf8563";
+                       reg = <0x51>;
+               };
+       };
+
+       gpio-keys-polled {
+               compatible = "gpio-keys-polled";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               poll-interval = <100>;
+
+               power {
+                       label = "power";
+                       gpios = <&gpio0 10 1>;
+                       linux,code = <KEY_POWER>;
+               };
+               reset {
+                       label = "reset";
+                       gpios = <&gpio0 11 1>;
+                       linux,code = <KEY_RESTART>;
+               };
+               eject1 {
+                       label = "eject1";
+                       gpios = <&gpio0 5 1>;
+                       linux,code = <KEY_EJECTCD>;
+               };
+               eject2 {
+                       label = "eject2";
+                       gpios = <&gpio0 6 1>;
+                       linux,code = <162>;
+               };
+       };
+
+       gpio-leds {
+               compatible = "gpio-leds";
+               status {
+                       label = "kd20:blue:status";
+                       gpios = <&gpio1 16 0>;
+               };
+               status2 {
+                       label = "kd20:red:status";
+                       gpios = <&gpio1 17 0>;
+               };
+               hdd1blue {
+                       label = "kd20:blue:hdd1";
+                       gpios = <&gpio0 27 0>;
+                       linux,default-trigger = "ata1";
+               };
+               hdd1red {
+                       label = "kd20:red:hdd1";
+                       gpios = <&gpio1 4 0>;
+               };
+               hdd2blue {
+                       label = "kd20:blue:hdd2";
+                       gpios = <&gpio1 6 0>;
+                       linux,default-trigger = "ata2";
+               };
+               hdd2red {
+                       label = "kd20:red:hdd2";
+                       gpios = <&gpio1 7 0>;
+               };
+               usb {
+                       label = "kd20:blue:usb";
+                       gpios = <&gpio1 8 0>;
+               };
+       };
+
+       beeper: beeper {
+               compatible = "gpio-beeper";
+               gpios = <&gpio1 11 0>;
+       };
+
+       gpio-fan {
+               compatible = "gpio-fan";
+               gpios = <&gpio0 2 1>;
+               gpio-fan,speed-map = <0    0
+                                     3000 1>;
+       };
+
+       gpio-poweroff {
+               compatible = "gpio-poweroff";
+               gpios = <&gpio0 9 0>;
+       };
+};
+
+&uart0 {
+       status = "okay";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart0>;
+};
+
+&nandc {
+       status = "okay";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_nand>;
+
+       nand@0 {
+               reg = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               nand-ecc-mode = "soft";
+               nand-ecc-algo = "hamming";
+
+               partition@0 {
+                       label = "stage1";
+                       reg = <0x00000000 0x00040000>;
+                       read-only;
+               };
+
+               partition@40000 {
+                       label = "u-boot";
+                       reg = <0x00040000 0x00200000>;
+                       read-only;
+               };
+
+               partition@240000 {
+                       label = "initrd";
+                       reg = <0x00240000 0x00600000>;
+               };
+
+               partition@840000 {
+                       label = "kernel";
+                       reg = <0x00840000 0x007C0000>;
+               };
+
+               partition@e00000 {
+                       label = "ubi";
+                       reg = <0x01000000 0x07000000>;
+               };
+       };
+};
+
+&etha {
+       status = "okay";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_etha_mdio>;
+};
+
+&ehci {
+       status = "okay";
+};
+
+&sata {
+       status = "okay";
+       nr-ports = <2>;
+};
+
+&pcie0 {
+       status = "okay";
+};
diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-stg212.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-stg212.dts
deleted file mode 100644 (file)
index ad93d4e..0000000
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Copyright (C) 2013 OpenWrt.org
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/dts-v1/;
-
-#include "ox820.dtsi"
-
-#include <dt-bindings/input/input.h>
-
-/ {
-       model = "MitraStar Technology Corp. STG-212";
-
-       chosen {
-               bootargs = "console=ttyS0,115200n8 earlyprintk=serial mem=128M";
-       };
-
-       uart@44200000 {
-               status = "okay";
-       };
-
-       sata@45900000 {
-               status = "okay";
-       };
-
-
-       ethernet@40400000 {
-               status = "okay";
-       };
-
-       ehci@40200100 {
-               status = "okay";
-       };
-
-       gpio-keys-polled {
-               compatible = "gpio-keys-polled";
-               #address-cells = <1>;
-               #size-cells = <0>;
-               poll-interval = <100>;
-
-               reset {
-                       label = "reset";
-                       gpios = <&GPIOB 11 1>;
-                       linux,code = <KEY_RESTART>;
-               };
-               copy {
-                       label = "copy";
-                       gpios = <&GPIOB 13 1>;
-                       linux,code = <KEY_COPY>;
-               };
-       };
-
-       gpio-leds {
-               compatible = "gpio-leds";
-               status {
-                       label = "zyxel:blue:status";
-                       gpios = <&GPIOB 5 0>;
-               };
-               status2 {
-                       label = "zyxel:red:status";
-                       gpios = <&GPIOB 6 1>;
-               };
-               copy {
-                       label = "zyxel:orange:copy";
-                       gpios = <&GPIOB 8 1>;
-               };
-       };
-
-       i2c-gpio {
-               compatible = "i2c-gpio";
-               gpios = <&GPIOB 9 0 &GPIOB 10 0>;
-               i2c-gpio,delay-us = <10>;
-       };
-
-};
-
-&nandc {
-       status = "okay";
-
-       nand@0 {
-               reg = <0>;
-               #address-cells = <1>;
-               #size-cells = <1>;
-               nand-ecc-mode = "soft";
-               nand-ecc-algo = "hamming";
-
-               partition@0 {
-                       label = "boot";
-                       reg = <0x00000000 0x00e00000>;
-                       read-only;
-               };
-
-               partition@e00000 {
-                       label = "ubi";
-                       reg = <0x00e00000 0x07200000>;
-               };
-       };
-};
diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820.dtsi b/target/linux/oxnas/files/arch/arm/boot/dts/ox820.dtsi
deleted file mode 100644 (file)
index c096a7d..0000000
+++ /dev/null
@@ -1,342 +0,0 @@
-/*
- * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include "skeleton.dtsi"
-
-/ {
-       compatible = "plxtech,nas7820", "plxtech,nas782x";
-       interrupt-parent = <&gic>;
-
-       aliases {
-               serial0 = &uart0;
-               /* alias to determine bank index */
-               gpio0 = &GPIOA;
-               gpio1 = &GPIOB;
-
-               ethernet0 = &gmac;
-       };
-
-       cpus {
-               cpu@0 {
-                       compatible = "arm,arm11mpcore";
-               };
-               cpu@1 {
-                       compatible = "arm,arm11mpcore";
-               };
-       };
-
-       gic: gic@47001000 {
-               compatible = "arm,arm11mp-gic";
-               interrupt-controller;
-               #interrupt-cells = <3>;
-               reg = <0x47001000 0x1000>,
-                     <0x47000100 0x0100>;
-       };
-
-       rst: reset-controller@44E00034 {
-               compatible = "plxtech,nas782x-reset";
-               #reset-cells = <1>;
-               reg = <0x44E00034 0x8>; /* currently not used */
-       };
-
-       rps: rps@44400000 {
-               compatible = "plxtech,nas782x-rps";
-               interrupt-controller;
-               #interrupt-cells = <1>;
-               reg = <0x44400000 0x14>;
-               interrupts = <0 5 0x304>;
-       };
-
-       /* external oscillator */
-       osc: oscillator {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency  = <25000000>;
-       };
-
-       sysclk: sysclk {
-               compatible = "fixed-factor-clock";
-               #clock-cells = <0>;
-               clock-div = <4>;
-               clock-mult = <1>;
-               clocks = <&osc>;
-       };
-
-       plla: plla@44e001f0 {
-               compatible = "plxtech,nas782x-plla";
-               #clock-cells = <0>;
-               clocks = <&osc>;
-               reg = <0x44e001f0 0x10>;
-       };
-
-       pllb: pllb@44f001f0 {
-               compatible = "plxtech,nas782x-pllb";
-               #clock-cells = <0>;
-               clocks = <&osc>;
-               reg = <0x44f001f0 0x10>;
-               resets = <&rst 31>;
-       };
-
-       stdclk: stdclk {
-               compatible = "plxtech,nas782x-stdclk";
-               #clock-cells = <1>;
-               clocks = <&osc>;
-       };
-
-       twdclk: twdclk {
-               compatible = "fixed-factor-clock";
-               #clock-cells = <0>;
-               clock-div = <2>;
-               clock-mult = <1>;
-               clocks = <&plla>;
-       };
-
-       gmacclk: gmacclk {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency  = <125000000>;
-       };
-
-       pinctrl {
-               /* act as a simple bus, so children will be probed automatically */
-               #address-cells = <1>;
-               #size-cells = <1>;
-               compatible = "plxtech,nas782x-pinctrl", "simple-bus";
-               ranges;
-
-               plxtech,mux-mask = <
-                        0xFFFFFFFF 0xCC0FFDF9 0xFC000E60 0x0F03F7E0 0xF00C0FE0
-                        0x0003FFFF 0x00037FFF 0x0003FFF8 0x00000F00 0x0003F7F3
-                       >;
-
-               GPIOA: gpio@44000000 {
-                       compatible = "plxtech,nas782x-gpio";
-                       reg = <0x44000000 0x100>, <0x44E00000 0x200>;
-                       interrupts = <0 21 0x304>;
-                       #gpio-cells = <2>;
-                       gpio-controller;
-                       interrupt-controller;
-                       #interrupt-cells = <2>;
-                       #gpio-lines = <32>; /* real gpio pin count */
-               };
-
-               GPIOB: gpio@44100000 {
-                       compatible = "plxtech,nas782x-gpio";
-                       reg = <0x44100000 0x100>, <0x44F00000 0x200>;
-                       interrupts = <0 22 0x304>;
-                       #gpio-cells = <2>;
-                       gpio-controller;
-                       interrupt-controller;
-                       #interrupt-cells = <2>;
-                       #gpio-lines = <18>; /* real gpio pin count */
-               };
-
-               uart0 {
-                       pinctrl_uart0: uart0-0 {
-                               plxtech,pins =
-                                       <0 30 5 0       /* MF_A30 PINMUX_ALT PINMUX_UARTA_SIN */
-                                        0 31 5 0>;     /* MF_A31 PINMUX_ALT PINMUX_UARTA_SOUT */
-                       };
-               };
-
-               gmac0 {
-                       pinctrl_gmac0: gmac0-0 {
-                               plxtech,pins =
-                                       <0 3 1 0        /* MF_A3 PINMUX_2 PINMUX_MACA_MDC */
-                                        0 4 1 0>;      /* MF_A4 PINMUX_2 PINMUX_MACA_MDIO */
-                       };
-               };
-
-               nand0 {
-                       pinctrl_nand0: nand0-0 {
-                               plxtech,pins =
-                                       <0 12 1 0       /* MF_A12 PINMUX_2 PINMUX_STATIC_DATA0 */
-                                        0 13 1 0       /* MF_A13 PINMUX_2 PINMUX_STATIC_DATA1 */
-                                        0 14 1 0       /* MF_A14 PINMUX_2 PINMUX_STATIC_DATA2 */
-                                        0 15 1 0       /* MF_A15 PINMUX_2 PINMUX_STATIC_DATA3 */
-                                        0 16 1 0       /* MF_A16 PINMUX_2 PINMUX_STATIC_DATA4 */
-                                        0 17 1 0       /* MF_A17 PINMUX_2 PINMUX_STATIC_DATA5 */
-                                        0 18 1 0       /* MF_A18 PINMUX_2 PINMUX_STATIC_DATA6 */
-                                        0 19 1 0       /* MF_A19 PINMUX_2 PINMUX_STATIC_DATA7 */
-
-                                        0 20 1 0       /* MF_A20 PINMUX_2 PINMUX_STATIC_NWE */
-                                        0 21 1 0       /* MF_A21 PINMUX_2 PINMUX_STATIC_NOE */
-                                        0 22 1 0       /* MF_A22 PINMUX_2 PINMUX_STATIC_NCS */
-                                        0 23 1 0       /* MF_A23 PINMUX_2 PINMUX_STATIC_ADDR18 */
-                                        0 24 1 0>;     /* MF_A24 PINMUX_2 PINMUX_STATIC_ADDR19 */
-                       };
-               };
-       };
-
-       pcie-controller@47C00000 {
-               compatible = "plxtech,nas782x-pcie";
-               device_type = "pci";
-               #address-cells = <3>;
-               #size-cells = <2>;
-
-               /*              flag & space    bus address     host address    size */
-               ranges = <      0x82000000      0 0x48000000    0x48000000      0 0x2000000
-                               0xC2000000      0 0x4A000000    0x4A000000      0 0x1E00000
-                               0x81000000      0 0x4BE00000    0x4BE00000      0 0x0100000
-                               0x80000000      0 0x4BF00000    0x4BF00000      0 0x0100000>;
-
-               bus-range = <0x00 0x7f>;
-
-               /*      cfg                     inbound translator      phy*/
-               reg =   <0x47C00000 0x1000>,    <0x47D00000 0x100>,      <0x44A00000 0x10>;
-
-               #interrupt-cells = <1>;
-               /* wild card mask, match all bus address & interrupt specifier */
-               /* format: bus address mask, interrupt specifier mask */
-               /* each bit 1 means need match, 0 means ignored when match */
-               interrupt-map-mask = <0 0 0 0>;
-               /* format: a list of: bus address, interrupt specifier,
-                * parent interrupt controller & specifier */
-               interrupt-map = <0 0 0 0 &gic 0 19 0x304>;
-
-               gpios = <&GPIOB 12 0>;
-               clocks = <&stdclk 8>, <&pllb>;
-               clock-names = "pcie", "busclk";
-               resets = <&rst 7>, <&rst 14>;
-               reset-names = "pcie", "phy";
-
-               plxtech,pcie-hcsl-bit = <2>;
-               plxtech,pcie-ctrl-offset = <0x120>;
-               plxtech,pcie-outbound-offset = <0x138>;
-               status = "disabled";
-       };
-
-       pcie-controller@47E00000 {
-               compatible = "plxtech,nas782x-pcie";
-               device_type = "pci";
-               #address-cells = <3>;
-               #size-cells = <2>;
-
-               /*              flag & space    bus address     host address    size */
-               ranges = <      0x82000000      0 0x4C000000    0x4C000000      0 0x2000000
-                               0xC2000000      0 0x4E000000    0x4E000000      0 0x1E00000
-                               0x81000000      0 0x4FE00000    0x4FE00000      0 0x0100000
-                               0x80000000      0 0x4FF00000    0x4FF00000      0 0x0100000>;
-
-               bus-range = <0x80 0xff>;
-
-               /*      cfg                     inbound translator      phy*/
-               reg =   <0x47E00000 0x1000>,    <0x47F00000 0x100>,     <0x44A00000 0x10>;
-
-               #interrupt-cells = <1>;
-               /* wild card mask, match all bus address & interrupt specifier */
-               /* format: bus address mask, interrupt specifier mask */
-               /* each bit 1 means need match, 0 means ignored when match */
-               interrupt-map-mask = <0 0 0 0>;
-               /* format: a list of: bus address, interrupt specifier,
-                * parent interrupt controller & specifier */
-               interrupt-map = <0 0 0 0 &gic 0 20 0x304>;
-
-               /* gpios = <&GPIOB 12 0>; */
-               clocks = <&stdclk 11>, <&pllb>;
-               clock-names = "pcie", "busclk";
-               resets = <&rst 23>, <&rst 14>;
-               reset-names = "pcie", "phy";
-
-               plxtech,pcie-hcsl-bit = <3>;
-               plxtech,pcie-ctrl-offset = <0x124>;
-               plxtech,pcie-outbound-offset = <0x174>;
-               status = "disabled";
-       };
-
-       local-timer@47000600 {
-               compatible = "arm,arm11mp-twd-timer";
-               reg = <0x47000600 0x20>;
-               interrupts = <1 13 0x304>;      /* percpu, irq 29, cpu mask 3, level high */
-               clocks = <&twdclk>;
-       };
-
-       watchdog@47000620 {
-               compatible = "mpcore_wdt";
-               reg = <0x47000620 0x20>;
-               interrupts = <1 14 0x304>;      /* percpu, irq 30, cpu mask 3, level high */
-               clocks = <&twdclk>;
-       };
-
-       timer@44400200 {
-               compatible = "plxtech,nas782x-rps-timer";
-               reg = <0x44400200 0x40>;
-               clocks = <&sysclk>;
-       };
-
-       uart0: uart@44200000 {
-               compatible = "ns16550a";
-               reg = <0x44200000 0x100>;
-               clock-frequency = <6250000>;
-               interrupts = <0 23 0x304>;
-               reg-shift = <0>;
-               fifo-size = <16>;
-               reg-io-width = <1>;
-               current-speed = <115200>;
-               no-loopback-test;
-               pinctrl-names = "default";
-               pinctrl-0 = <&pinctrl_uart0>;
-               status = "disabled";
-       };
-
-       sata@45900000 {
-               compatible = "plxtech,nas782x-sata";
-                       /*      ports           dmactl          sgdma   */
-               reg = <0x45900000 0x20000>, <0x459A0000 0x40>, <0x459B0000 0x20>,
-                       /*      core            phy             descriptors (optional)  */
-                       <0x459E0000 0x2000>, <0x44900000 0x0C>, <0x50000000 0x1000>;
-               interrupts = <0 18 0x304>;
-               clocks = <&stdclk 4>;
-               resets = <&rst 11>, <&rst 12>, <&rst 13>;
-               reset-names = "sata", "link", "phy";
-               nr-ports = <1>;
-               status = "disabled";
-       };
-
-       nandc: nand-controller@41000000 {
-               compatible = "oxsemi,ox820-nand";
-               reg = <0x41000000 0x100000>;
-               clocks = <&stdclk 9>;
-               pinctrl-names = "default";
-               pinctrl-0 = <&pinctrl_nand0>;
-               resets = <&rst 15>;
-               #address-cells = <1>;
-               #size-cells = <0>;
-               status = "disabled";
-       };
-
-       gmac: ethernet@40400000 {
-               compatible = "plxtech,nas782x-gmac", "snps,dwmac";
-               reg = <0x40400000 0x2000>;
-               interrupts = <0 8 0x304>, <0 17 0x304>;
-               interrupt-names = "macirq", "eth_wake_irq";
-               mac-address = [000000000000]; /* Filled in by U-Boot */
-               phy-mode = "rgmii";
-               clocks = <&stdclk 7>, <&gmacclk>;
-               clock-names = "gmac", "stmmaceth";
-               pinctrl-names = "default";
-               pinctrl-0 = <&pinctrl_gmac0>;
-               resets = <&rst 6>;
-               status = "disabled";
-       };
-
-       ehci@40200100 {
-               compatible = "plxtech,nas782x-ehci";
-               reg = <0x40200100 0xf00>;
-               interrupts = <0 7 0x304>;
-               clocks = <&stdclk 6>, <&pllb>, <&stdclk 12>;
-               clock-names = "usb", "refsrc", "phyref";
-               resets = <&rst 4>, <&rst 5>, <&rst 26>;
-               reset-names = "host", "phya", "phyb";
-               /* Otherwise ref300 is used, which is derived from sata phy
-                * in that case, usb depends on sata initialization */
-               /* FIXME: how to make this dependency explicit ? */
-               plxtech,ehci_use_pllb;
-               status = "disabled";
-       };
-};
diff --git a/target/linux/oxnas/files/arch/arm/configs/ox820_defconfig b/target/linux/oxnas/files/arch/arm/configs/ox820_defconfig
deleted file mode 100644 (file)
index bb0a9d6..0000000
+++ /dev/null
@@ -1,104 +0,0 @@
-CONFIG_CROSS_COMPILE="arm-linux-gnueabi-"
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_CGROUPS=y
-CONFIG_NAMESPACES=y
-CONFIG_EMBEDDED=y
-# CONFIG_COMPAT_BRK is not set
-CONFIG_JUMP_LABEL=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_ARCH_OXNAS=y
-# CONFIG_DMA_CACHE_RWFO is not set
-CONFIG_DMA_CACHE_FIQ_BROADCAST=y
-CONFIG_PCI=y
-CONFIG_PCI_OXNAS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_HOTPLUG_CPU=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_UACCESS_WITH_MEMCPY=y
-CONFIG_USE_OF=y
-CONFIG_BINFMT_MISC=y
-# CONFIG_SUSPEND is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IPV6=y
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-CONFIG_MAC80211_RC_PID=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_OXNAS=y
-CONFIG_MTD_UBI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_ATA=y
-CONFIG_SATA_OXNAS=y
-CONFIG_NETDEVICES=y
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_DEBUG_FS=y
-CONFIG_STMMAC_DA=y
-CONFIG_ATH_CARDS=y
-CONFIG_ATH9K=y
-CONFIG_ATH9K_LEGACY_RATE_CONTROL=y
-# CONFIG_RTL_CARDS is not set
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_8250=y
-# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=1
-CONFIG_SERIAL_8250_RUNTIME_UARTS=1
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_OXNAS=y
-CONFIG_USB_STORAGE=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_ONESHOT=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-CONFIG_COMMON_CLK_DEBUG=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT4_FS=y
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_NTFS_FS=m
-CONFIG_NTFS_RW=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_UBIFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_PRINTK_TIME=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_UART_8250=y
-CONFIG_DEBUG_UART_PHYS=0x44200000
-CONFIG_DEBUG_UART_VIRT=0xF0000000
-CONFIG_DEBUG_UART_8250_SHIFT=0
-CONFIG_EARLY_PRINTK=y
-CONFIG_CRYPTO_ANSI_CPRNG=y
diff --git a/target/linux/oxnas/files/arch/arm/include/debug/uncompress-ox820.h b/target/linux/oxnas/files/arch/arm/include/debug/uncompress-ox820.h
new file mode 100644 (file)
index 0000000..fbc3727
--- /dev/null
@@ -0,0 +1,32 @@
+/* linux/include/asm-arm/arch-oxnas/uncompress.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#define OXNAS_UART1_BASE 0x44200000
+
+static inline void putc(int c)
+{
+       static volatile unsigned char *uart =
+               (volatile unsigned char *)OXNAS_UART1_BASE;
+
+       while (!(uart[5] & 0x20)) {     /* LSR reg THR empty bit */
+               barrier();
+       }
+       uart[0] = c;                    /* THR register */
+}
+
+static inline void flush(void)
+{
+}
+
+#define arch_decomp_setup()
+
+#define arch_decomp_wdog()
+
+#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/Kconfig b/target/linux/oxnas/files/arch/arm/mach-oxnas/Kconfig
deleted file mode 100644 (file)
index 6bdf3f6..0000000
+++ /dev/null
@@ -1,25 +0,0 @@
-choice
-       prompt "Oxnas platform type"
-       default MACH_OXNAS
-       depends on ARCH_OXNAS
-
-config MACH_OX820
-       bool "Generic NAS7820 Support"
-       select ARM_GIC
-       select GENERIC_CLOCKEVENTS
-       select CPU_V6K
-       select HAVE_ARM_SCU if SMP
-       select HAVE_ARM_TWD if SMP
-       select HAVE_SMP
-       select PLXTECH_RPS
-       select CLKSRC_OF
-       select CLKSRC_RPS_TIMER
-       select USB_ARCH_HAS_EHCI
-       select PINCTRL_OXNAS
-       select PINCTRL
-       select RESET_CONTROLLER_OXNAS
-       select ARCH_WANT_LIBATA_LEDS
-       help
-         Include support for the ox820 platform.
-
-endchoice
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile b/target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile
deleted file mode 100644 (file)
index 6862c34..0000000
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-obj-$(CONFIG_MACH_OX820)               += mach-ox820.o
-obj-$(CONFIG_SMP)                      += platsmp.o headsmp.o
-obj-$(CONFIG_DMA_CACHE_FIQ_BROADCAST)  += fiq.o
-obj-$(CONFIG_HOTPLUG_CPU)              += hotplug.o
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile.boot b/target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile.boot
deleted file mode 100644 (file)
index b52e473..0000000
+++ /dev/null
@@ -1,2 +0,0 @@
-   zreladdr-y  += 0x60008000
-params_phys-y  := 0x60000100
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/fiq.S b/target/linux/oxnas/files/arch/arm/mach-oxnas/fiq.S
deleted file mode 100644 (file)
index 6acd5a7..0000000
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- *  Copyright (C) 2012 Gateworks Corporation
- *      Chris Lang <clang@gateworks.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <asm/asm-offsets.h>
-
-#define D_CACHE_LINE_SIZE 32
-
-       .text
-
-/*
- * R8  - DMA Start Address
- * R9  - DMA Length
- * R10 - DMA Direction
- * R11 - DMA type
- * R12 - fiq_buffer Address
-*/
-
-       .global ox820_fiq_end
-ENTRY(ox820_fiq_start)
-       str     r8, [r13]
-
-       ldmia   r12, {r8, r9, r10}
-       and     r11, r10, #0x3000000
-       and     r10, r10, #0xff
-
-       teq     r11, #0x1000000
-       beq     ox820_dma_map_area
-       teq     r11, #0x2000000
-       beq     ox820_dma_unmap_area
-       /* fall through */
-ox820_dma_flush_range:
-       bic     r8, r8, #D_CACHE_LINE_SIZE - 1
-1:
-       mcr     p15, 0, r8, c7, c14, 1          @ clean & invalidate D line
-       add     r8, r8, #D_CACHE_LINE_SIZE
-       cmp     r8, r9
-       blo     1b
-       /* fall through */
-ox820_fiq_exit:
-       mov     r8, #0
-       str     r8, [r12, #8]
-       mcr     p15, 0, r8, c7, c10, 4          @ drain write buffer
-       subs    pc, lr, #4
-
-ox820_dma_map_area:
-       add     r9, r9, r8
-       teq     r10, #DMA_FROM_DEVICE
-       beq     ox820_dma_inv_range
-       teq     r10, #DMA_TO_DEVICE
-       bne     ox820_dma_flush_range
-       /* fall through */
-ox820_dma_clean_range:
-       bic     r8, r8, #D_CACHE_LINE_SIZE - 1
-1:
-       mcr     p15, 0, r8, c7, c10, 1          @ clean D line
-       add     r8, r8, #D_CACHE_LINE_SIZE
-       cmp     r8, r9
-       blo     1b
-       b       ox820_fiq_exit
-
-ox820_dma_unmap_area:
-       add     r9, r9, r8
-       teq     r10, #DMA_TO_DEVICE
-       beq     ox820_fiq_exit
-       /* fall through */
-ox820_dma_inv_range:
-       tst     r8, #D_CACHE_LINE_SIZE - 1
-       bic     r8, r8, #D_CACHE_LINE_SIZE - 1
-       mcrne   p15, 0, r8, c7, c10, 1          @ clean D line
-       tst     r9, #D_CACHE_LINE_SIZE - 1
-       bic     r9, r9, #D_CACHE_LINE_SIZE - 1
-       mcrne   p15, 0, r9, c7, c14, 1          @ clean & invalidate D line
-1:
-       mcr     p15, 0, r8, c7, c6, 1           @ invalidate D line
-       add     r8, r8, #D_CACHE_LINE_SIZE
-       cmp     r8, r9
-       blo     1b
-       b       ox820_fiq_exit
-
-ox820_fiq_end:
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/headsmp.S b/target/linux/oxnas/files/arch/arm/mach-oxnas/headsmp.S
deleted file mode 100644 (file)
index a63edae..0000000
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- *  linux/arch/arm/mach-ox820/headsmp.S
- *
- *  Copyright (c) 2003 ARM Limited
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-
-       __INIT
-
-/*
- * OX820 specific entry point for secondary CPUs.
- */
-ENTRY(ox820_secondary_startup)
-       mov r4, #0
-       /* invalidate both caches and branch target cache */
-       mcr p15, 0, r4, c7, c7, 0
-       /*
-        * we've been released from the holding pen: secondary_stack
-        * should now contain the SVC stack for this core
-        */
-       b       secondary_startup
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/hotplug.c b/target/linux/oxnas/files/arch/arm/mach-oxnas/hotplug.c
deleted file mode 100644 (file)
index e3c9cb5..0000000
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- *  linux/arch/arm/mach-realview/hotplug.c
- *
- *  Copyright (C) 2002 ARM Ltd.
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
-
-#include <asm/cp15.h>
-#include <asm/smp_plat.h>
-
-static inline void cpu_enter_lowpower(void)
-{
-       unsigned int v;
-
-       asm volatile(
-       "       mcr     p15, 0, %1, c7, c5, 0\n"
-       "       mcr     p15, 0, %1, c7, c10, 4\n"
-       /*
-        * Turn off coherency
-        */
-       "       mrc     p15, 0, %0, c1, c0, 1\n"
-       "       bic     %0, %0, #0x20\n"
-       "       mcr     p15, 0, %0, c1, c0, 1\n"
-       "       mrc     p15, 0, %0, c1, c0, 0\n"
-       "       bic     %0, %0, %2\n"
-       "       mcr     p15, 0, %0, c1, c0, 0\n"
-         : "=&r" (v)
-         : "r" (0), "Ir" (CR_C)
-         : "cc");
-}
-
-static inline void cpu_leave_lowpower(void)
-{
-       unsigned int v;
-
-       asm volatile(   "mrc    p15, 0, %0, c1, c0, 0\n"
-       "       orr     %0, %0, %1\n"
-       "       mcr     p15, 0, %0, c1, c0, 0\n"
-       "       mrc     p15, 0, %0, c1, c0, 1\n"
-       "       orr     %0, %0, #0x20\n"
-       "       mcr     p15, 0, %0, c1, c0, 1\n"
-         : "=&r" (v)
-         : "Ir" (CR_C)
-         : "cc");
-}
-
-static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
-{
-       /*
-        * there is no power-control hardware on this platform, so all
-        * we can do is put the core into WFI; this is safe as the calling
-        * code will have already disabled interrupts
-        */
-       for (;;) {
-               /*
-                * here's the WFI
-                */
-               asm(".word      0xe320f003\n"
-                   :
-                   :
-                   : "memory", "cc");
-
-               if (pen_release == cpu_logical_map(cpu)) {
-                       /*
-                        * OK, proper wakeup, we're done
-                        */
-                       break;
-               }
-
-               /*
-                * Getting here, means that we have come out of WFI without
-                * having been woken up - this shouldn't happen
-                *
-                * Just note it happening - when we're woken, we can report
-                * its occurrence.
-                */
-               (*spurious)++;
-       }
-}
-
-/*
- * platform-specific code to shutdown a CPU
- *
- * Called with IRQs disabled
- */
-void ox820_cpu_die(unsigned int cpu)
-{
-       int spurious = 0;
-
-       /*
-        * we're ready for shutdown now, so do it
-        */
-       cpu_enter_lowpower();
-       platform_do_lowpower(cpu, &spurious);
-
-       /*
-        * bring this CPU back into the world of cache
-        * coherency, and then restore interrupts
-        */
-       cpu_leave_lowpower();
-
-       if (spurious)
-               pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
-}
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/hardware.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/hardware.h
deleted file mode 100644 (file)
index caae772..0000000
+++ /dev/null
@@ -1,233 +0,0 @@
-/*
- * arch/arm/mach-0x820/include/mach/hardware.h
- *
- * Copyright (C) 2009 Oxford Semiconductor Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <linux/io.h>
-#include <mach/iomap.h>
-
-/*
- * Location of flags and vectors in SRAM for controlling the booting of the
- * secondary ARM11 processors.
- */
-
-#define OXNAS_SCU_BASE_VA              OXNAS_PERCPU_BASE_VA
-#define OXNAS_GICN_BASE_VA(n)          (OXNAS_PERCPU_BASE_VA + 0x200 + n*0x100)
-
-#define HOLDINGPEN_CPU                 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc8)
-#define HOLDINGPEN_LOCATION            IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc4)
-
-/**
- * System block reset and clock control
- */
-#define SYS_CTRL_PCI_STAT              IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x20)
-#define SYSCTRL_CLK_STAT               IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x24)
-#define SYS_CTRL_CLK_SET_CTRL          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x2C)
-#define SYS_CTRL_CLK_CLR_CTRL          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x30)
-#define SYS_CTRL_RST_SET_CTRL          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x34)
-#define SYS_CTRL_RST_CLR_CTRL          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x38)
-
-#define SYS_CTRL_PLLSYS_CTRL           IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x48)
-#define SYS_CTRL_CLK_CTRL              IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x64)
-#define SYS_CTRL_PLLSYS_KEY_CTRL       IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x6C)
-#define SYS_CTRL_GMAC_CTRL             IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x78)
-#define SYS_CTRL_GMAC_DELAY_CTRL       IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x100)
-
-/* Scratch registers */
-#define SYS_CTRL_SCRATCHWORD0          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc4)
-#define SYS_CTRL_SCRATCHWORD1          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc8)
-#define SYS_CTRL_SCRATCHWORD2          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xcc)
-#define SYS_CTRL_SCRATCHWORD3          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xd0)
-
-#define SYS_CTRL_PLLA_CTRL0            IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F0)
-#define SYS_CTRL_PLLA_CTRL1            IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F4)
-#define SYS_CTRL_PLLA_CTRL2            IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F8)
-#define SYS_CTRL_PLLA_CTRL3            IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1FC)
-
-#define SYS_CTRL_USBHSMPH_CTRL         IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x40)
-#define SYS_CTRL_USBHSMPH_STAT         IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x44)
-#define SYS_CTRL_REF300_DIV            IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xF8)
-#define SYS_CTRL_USBHSPHY_CTRL         IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x84)
-#define SYS_CTRL_USB_CTRL              IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x90)
-
-/* pcie */
-#define SYS_CTRL_HCSL_CTRL             IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x114)
-
-/* System control multi-function pin function selection */
-#define SYS_CTRL_SECONDARY_SEL         IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x14)
-#define SYS_CTRL_TERTIARY_SEL          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x8c)
-#define SYS_CTRL_QUATERNARY_SEL                IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x94)
-#define SYS_CTRL_DEBUG_SEL             IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x9c)
-#define SYS_CTRL_ALTERNATIVE_SEL       IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xa4)
-#define SYS_CTRL_PULLUP_SEL            IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xac)
-
-/* Secure control multi-function pin function selection */
-#define SEC_CTRL_SECONDARY_SEL         IOMEM(OXNAS_SECCRTL_BASE_VA + 0x14)
-#define SEC_CTRL_TERTIARY_SEL          IOMEM(OXNAS_SECCRTL_BASE_VA + 0x8c)
-#define SEC_CTRL_QUATERNARY_SEL                IOMEM(OXNAS_SECCRTL_BASE_VA + 0x94)
-#define SEC_CTRL_DEBUG_SEL             IOMEM(OXNAS_SECCRTL_BASE_VA + 0x9c)
-#define SEC_CTRL_ALTERNATIVE_SEL       IOMEM(OXNAS_SECCRTL_BASE_VA + 0xa4)
-#define SEC_CTRL_PULLUP_SEL            IOMEM(OXNAS_SECCRTL_BASE_VA + 0xac)
-
-#define SEC_CTRL_COPRO_CTRL            IOMEM(OXNAS_SECCRTL_BASE_VA + 0x68)
-#define SEC_CTRL_SECURE_CTRL           IOMEM(OXNAS_SECCRTL_BASE_VA + 0x98)
-#define SEC_CTRL_LEON_DEBUG            IOMEM(OXNAS_SECCRTL_BASE_VA + 0xF0)
-#define SEC_CTRL_PLLB_DIV_CTRL         IOMEM(OXNAS_SECCRTL_BASE_VA + 0xF8)
-#define SEC_CTRL_PLLB_CTRL0            IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F0)
-#define SEC_CTRL_PLLB_CTRL1            IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F4)
-#define SEC_CTRL_PLLB_CTRL8            IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F4)
-
-#define RPSA_IRQ_SOFT                  IOMEM(OXNAS_RPSA_BASE_VA + 0x10)
-#define RPSA_FIQ_ENABLE                        IOMEM(OXNAS_RPSA_BASE_VA + 0x108)
-#define RPSA_FIQ_DISABLE               IOMEM(OXNAS_RPSA_BASE_VA + 0x10C)
-#define RPSA_FIQ_IRQ_TO_FIQ            IOMEM(OXNAS_RPSA_BASE_VA + 0x1FC)
-
-#define RPSC_IRQ_SOFT                  IOMEM(OXNAS_RPSC_BASE_VA + 0x10)
-#define RPSC_FIQ_ENABLE                        IOMEM(OXNAS_RPSC_BASE_VA + 0x108)
-#define RPSC_FIQ_DISABLE               IOMEM(OXNAS_RPSC_BASE_VA + 0x10C)
-#define RPSC_FIQ_IRQ_TO_FIQ            IOMEM(OXNAS_RPSC_BASE_VA + 0x1FC)
-
-#define RPSA_TIMER2_VAL                        IOMEM(OXNAS_RPSA_BASE_VA + 0x224)
-
-#define REF300_DIV_INT_SHIFT           8
-#define REF300_DIV_FRAC_SHIFT          0
-#define REF300_DIV_INT(val)            ((val) << REF300_DIV_INT_SHIFT)
-#define REF300_DIV_FRAC(val)           ((val) << REF300_DIV_FRAC_SHIFT)
-
-#define USBHSPHY_SUSPENDM_MANUAL_ENABLE                16
-#define USBHSPHY_SUSPENDM_MANUAL_STATE         15
-#define USBHSPHY_ATE_ESET                      14
-#define USBHSPHY_TEST_DIN                      6
-#define USBHSPHY_TEST_ADD                      2
-#define USBHSPHY_TEST_DOUT_SEL                 1
-#define USBHSPHY_TEST_CLK                      0
-
-#define USB_CTRL_USBAPHY_CKSEL_SHIFT   5
-#define USB_CLK_XTAL0_XTAL1            (0 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
-#define USB_CLK_XTAL0                  (1 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
-#define USB_CLK_INTERNAL               (2 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
-
-#define USBAMUX_DEVICE                 BIT(4)
-
-#define USBPHY_REFCLKDIV_SHIFT         2
-#define USB_PHY_REF_12MHZ              (0 << USBPHY_REFCLKDIV_SHIFT)
-#define USB_PHY_REF_24MHZ              (1 << USBPHY_REFCLKDIV_SHIFT)
-#define USB_PHY_REF_48MHZ              (2 << USBPHY_REFCLKDIV_SHIFT)
-
-#define USB_CTRL_USB_CKO_SEL_BIT       0
-
-#define USB_INT_CLK_XTAL               0
-#define USB_INT_CLK_REF300             2
-#define USB_INT_CLK_PLLB               3
-
-#define SYS_CTRL_GMAC_CKEN_RX_IN       14
-#define SYS_CTRL_GMAC_CKEN_RXN_OUT     13
-#define SYS_CTRL_GMAC_CKEN_RX_OUT      12
-#define SYS_CTRL_GMAC_CKEN_TX_IN       10
-#define SYS_CTRL_GMAC_CKEN_TXN_OUT     9
-#define SYS_CTRL_GMAC_CKEN_TX_OUT      8
-#define SYS_CTRL_GMAC_RX_SOURCE                7
-#define SYS_CTRL_GMAC_TX_SOURCE                6
-#define SYS_CTRL_GMAC_LOW_TX_SOURCE    4
-#define SYS_CTRL_GMAC_AUTO_TX_SOURCE   3
-#define SYS_CTRL_GMAC_RGMII            2
-#define SYS_CTRL_GMAC_SIMPLE_MUX       1
-#define SYS_CTRL_GMAC_CKEN_GTX         0
-#define SYS_CTRL_GMAC_TX_VARDELAY_SHIFT                0
-#define SYS_CTRL_GMAC_TXN_VARDELAY_SHIFT       8
-#define SYS_CTRL_GMAC_RX_VARDELAY_SHIFT                16
-#define SYS_CTRL_GMAC_RXN_VARDELAY_SHIFT       24
-#define SYS_CTRL_GMAC_TX_VARDELAY(d)   ((d)<<SYS_CTRL_GMAC_TX_VARDELAY_SHIFT)
-#define SYS_CTRL_GMAC_TXN_VARDELAY(d)  ((d)<<SYS_CTRL_GMAC_TXN_VARDELAY_SHIFT)
-#define SYS_CTRL_GMAC_RX_VARDELAY(d)   ((d)<<SYS_CTRL_GMAC_RX_VARDELAY_SHIFT)
-#define SYS_CTRL_GMAC_RXN_VARDELAY(d)  ((d)<<SYS_CTRL_GMAC_RXN_VARDELAY_SHIFT)
-
-#define PLLB_BYPASS                    1
-#define PLLB_ENSAT                     3
-#define PLLB_OUTDIV                    4
-#define PLLB_REFDIV                    8
-#define PLLB_DIV_INT_SHIFT             8
-#define PLLB_DIV_FRAC_SHIFT            0
-#define PLLB_DIV_INT(val)              ((val) << PLLB_DIV_INT_SHIFT)
-#define PLLB_DIV_FRAC(val)             ((val) << PLLB_DIV_FRAC_SHIFT)
-
-#define SYS_CTRL_CKCTRL_PCI_DIV_BIT    0
-#define SYS_CTRL_CKCTRL_SLOW_BIT       8
-
-#define SYS_CTRL_UART2_DEQ_EN          0
-#define SYS_CTRL_UART3_DEQ_EN          1
-#define SYS_CTRL_UART3_IQ_EN           2
-#define SYS_CTRL_UART4_IQ_EN           3
-#define SYS_CTRL_UART4_NOT_PCI_MODE    4
-
-#define SYS_CTRL_PCI_CTRL1_PCI_STATIC_RQ_BIT   11
-
-#define PLLA_REFDIV_MASK               0x3F
-#define PLLA_REFDIV_SHIFT              8
-#define PLLA_OUTDIV_MASK               0x7
-#define PLLA_OUTDIV_SHIFT              4
-
-/* bit numbers of clock control register */
-#define SYS_CTRL_CLK_COPRO             0
-#define SYS_CTRL_CLK_DMA               1
-#define SYS_CTRL_CLK_CIPHER            2
-#define SYS_CTRL_CLK_SD                        3
-#define SYS_CTRL_CLK_SATA              4
-#define SYS_CTRL_CLK_I2S               5
-#define SYS_CTRL_CLK_USBHS             6
-#define SYS_CTRL_CLK_MACA              7
-#define SYS_CTRL_CLK_MAC               SYS_CTRL_CLK_MACA
-#define SYS_CTRL_CLK_PCIEA             8
-#define SYS_CTRL_CLK_STATIC            9
-#define SYS_CTRL_CLK_MACB              10
-#define SYS_CTRL_CLK_PCIEB             11
-#define SYS_CTRL_CLK_REF600            12
-#define SYS_CTRL_CLK_USBDEV            13
-#define SYS_CTRL_CLK_DDR               14
-#define SYS_CTRL_CLK_DDRPHY            15
-#define SYS_CTRL_CLK_DDRCK             16
-
-
-/* bit numbers of reset control register */
-#define SYS_CTRL_RST_SCU               0
-#define SYS_CTRL_RST_COPRO             1
-#define SYS_CTRL_RST_ARM0              2
-#define SYS_CTRL_RST_ARM1              3
-#define SYS_CTRL_RST_USBHS             4
-#define SYS_CTRL_RST_USBHSPHYA         5
-#define SYS_CTRL_RST_MACA              6
-#define SYS_CTRL_RST_MAC               SYS_CTRL_RST_MACA
-#define SYS_CTRL_RST_PCIEA             7
-#define SYS_CTRL_RST_SGDMA             8
-#define SYS_CTRL_RST_CIPHER            9
-#define SYS_CTRL_RST_DDR               10
-#define SYS_CTRL_RST_SATA              11
-#define SYS_CTRL_RST_SATA_LINK         12
-#define SYS_CTRL_RST_SATA_PHY          13
-#define SYS_CTRL_RST_PCIEPHY           14
-#define SYS_CTRL_RST_STATIC            15
-#define SYS_CTRL_RST_GPIO              16
-#define SYS_CTRL_RST_UART1             17
-#define SYS_CTRL_RST_UART2             18
-#define SYS_CTRL_RST_MISC              19
-#define SYS_CTRL_RST_I2S               20
-#define SYS_CTRL_RST_SD                        21
-#define SYS_CTRL_RST_MACB              22
-#define SYS_CTRL_RST_PCIEB             23
-#define SYS_CTRL_RST_VIDEO             24
-#define SYS_CTRL_RST_DDR_PHY           25
-#define SYS_CTRL_RST_USBHSPHYB         26
-#define SYS_CTRL_RST_USBDEV            27
-#define SYS_CTRL_RST_ARMDBG            29
-#define SYS_CTRL_RST_PLLA              30
-#define SYS_CTRL_RST_PLLB              31
-
-#endif
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/iomap.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/iomap.h
deleted file mode 100644 (file)
index 01de7b7..0000000
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef __MACH_OXNAS_IOMAP_H
-#define __MACH_OXNAS_IOMAP_H
-
-#include <linux/sizes.h>
-
-#define OXNAS_UART1_BASE       0x44200000
-#define OXNAS_UART1_SIZE       SZ_32
-#define OXNAS_UART1_BASE_VA    0xF0000000
-
-#define OXNAS_UART2_BASE       0x44300000
-#define OXNAS_UART2_SIZE       SZ_32
-
-#define OXNAS_PERCPU_BASE      0x47000000
-#define OXNAS_PERCPU_SIZE      SZ_8K
-#define OXNAS_PERCPU_BASE_VA   0xF0002000
-
-#define OXNAS_SYSCRTL_BASE     0x44E00000
-#define OXNAS_SYSCRTL_SIZE     SZ_4K
-#define OXNAS_SYSCRTL_BASE_VA  0xF0004000
-
-#define OXNAS_SECCRTL_BASE     0x44F00000
-#define OXNAS_SECCRTL_SIZE     SZ_4K
-#define OXNAS_SECCRTL_BASE_VA  0xF0005000
-
-#define OXNAS_RPSA_BASE                0x44400000
-#define OXNAS_RPSA_SIZE                SZ_4K
-#define OXNAS_RPSA_BASE_VA     0xF0006000
-
-#define OXNAS_RPSC_BASE                0x44500000
-#define OXNAS_RPSC_SIZE                SZ_4K
-#define OXNAS_RPSC_BASE_VA     0xF0007000
-
-#endif
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/irqs.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/irqs.h
deleted file mode 100644 (file)
index bcafd10..0000000
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-#define IRQ_SOFT       1
-#define NR_IRQS                160
-
-#endif
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/smp.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/smp.h
deleted file mode 100644 (file)
index 1128635..0000000
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * smp.h
- *
- *  Created on: Sep 24, 2013
- *      Author: mahaijun
- */
-
-#ifndef _NAS782X_SMP_H_
-#define _NAS782X_SMP_H_
-
-#include <mach/hardware.h>
-
-extern void ox820_secondary_startup(void);
-extern void ox820_cpu_die(unsigned int cpu);
-
-static inline void write_pen_release(int val)
-{
-       writel(val, HOLDINGPEN_CPU);
-}
-
-static inline int read_pen_release(void)
-{
-       return readl(HOLDINGPEN_CPU);
-}
-
-extern struct smp_operations ox820_smp_ops;
-
-extern unsigned char ox820_fiq_start, ox820_fiq_end;
-extern void v6_dma_map_area(const void *, size_t, int);
-extern void v6_dma_unmap_area(const void *, size_t, int);
-extern void v6_dma_flush_range(const void *, const void *);
-extern void v6_flush_kern_dcache_area(void *, size_t);
-
-#endif /* _NAS782X_SMP_H_ */
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/timex.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/timex.h
deleted file mode 100644 (file)
index 4133594..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-
-#define CLOCK_TICK_RATE                6250000
-
-#endif
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/uncompress.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/uncompress.h
deleted file mode 100644 (file)
index fbc3727..0000000
+++ /dev/null
@@ -1,32 +0,0 @@
-/* linux/include/asm-arm/arch-oxnas/uncompress.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-
-#define OXNAS_UART1_BASE 0x44200000
-
-static inline void putc(int c)
-{
-       static volatile unsigned char *uart =
-               (volatile unsigned char *)OXNAS_UART1_BASE;
-
-       while (!(uart[5] & 0x20)) {     /* LSR reg THR empty bit */
-               barrier();
-       }
-       uart[0] = c;                    /* THR register */
-}
-
-static inline void flush(void)
-{
-}
-
-#define arch_decomp_setup()
-
-#define arch_decomp_wdog()
-
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/utils.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/utils.h
deleted file mode 100644 (file)
index 910d701..0000000
+++ /dev/null
@@ -1,34 +0,0 @@
-#ifndef _NAS782X_UTILS_H
-#define _NAS782X_UTILS_H
-
-#include <linux/io.h>
-#include <mach/hardware.h>
-
-static inline void oxnas_register_clear_mask(void __iomem *p, unsigned mask)
-{
-       u32 val = readl_relaxed(p);
-
-       val &= ~mask;
-       writel_relaxed(val, p);
-}
-
-static inline void oxnas_register_set_mask(void __iomem *p, unsigned mask)
-{
-       u32 val = readl_relaxed(p);
-
-       val |= mask;
-       writel_relaxed(val, p);
-}
-
-static inline void oxnas_register_value_mask(void __iomem *p,
-                                            unsigned mask, unsigned new_value)
-{
-       /* TODO sanity check mask & new_value = new_value */
-       u32 val = readl_relaxed(p);
-
-       val &= ~mask;
-       val |= new_value;
-       writel_relaxed(val, p);
-}
-
-#endif /* _NAS782X_UTILS_H */
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/mach-ox820.c b/target/linux/oxnas/files/arch/arm/mach-oxnas/mach-ox820.c
deleted file mode 100644 (file)
index 31b7c90..0000000
+++ /dev/null
@@ -1,183 +0,0 @@
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/bug.h>
-#include <linux/of_platform.h>
-#include <linux/clocksource.h>
-#include <linux/clk-provider.h>
-#include <linux/clk.h>
-#include <linux/slab.h>
-#include <linux/gfp.h>
-#include <linux/reset.h>
-#include <asm/mach-types.h>
-#include <asm/mach/map.h>
-#include <asm/mach/arch.h>
-#include <asm/page.h>
-#include <mach/iomap.h>
-#include <mach/hardware.h>
-#include <mach/utils.h>
-#include <mach/smp.h>
-
-static struct map_desc ox820_io_desc[] __initdata = {
-       {
-               .virtual = (unsigned long)OXNAS_PERCPU_BASE_VA,
-               .pfn = __phys_to_pfn(OXNAS_PERCPU_BASE),
-               .length = OXNAS_PERCPU_SIZE,
-               .type = MT_DEVICE,
-       },
-       {
-               .virtual = (unsigned long)OXNAS_SYSCRTL_BASE_VA,
-               .pfn = __phys_to_pfn(OXNAS_SYSCRTL_BASE),
-               .length = OXNAS_SYSCRTL_SIZE,
-               .type = MT_DEVICE,
-       },
-       {
-               .virtual = (unsigned long)OXNAS_SECCRTL_BASE_VA,
-               .pfn = __phys_to_pfn(OXNAS_SECCRTL_BASE),
-               .length = OXNAS_SECCRTL_SIZE,
-               .type = MT_DEVICE,
-       },
-       {
-               .virtual = (unsigned long)OXNAS_RPSA_BASE_VA,
-               .pfn = __phys_to_pfn(OXNAS_RPSA_BASE),
-               .length = OXNAS_RPSA_SIZE,
-               .type = MT_DEVICE,
-       },
-       {
-               .virtual = (unsigned long)OXNAS_RPSC_BASE_VA,
-               .pfn = __phys_to_pfn(OXNAS_RPSC_BASE),
-               .length = OXNAS_RPSC_SIZE,
-               .type = MT_DEVICE,
-       },
-};
-
-void __init ox820_map_common_io(void)
-{
-       debug_ll_io_init();
-       iotable_init(ox820_io_desc, ARRAY_SIZE(ox820_io_desc));
-}
-
-static void __init ox820_dt_init(void)
-{
-       int ret;
-
-       ret = of_platform_populate(NULL, of_default_bus_match_table, NULL,
-                                       NULL);
-
-       if (ret) {
-               pr_err("of_platform_populate failed: %d\n", ret);
-               BUG();
-       }
-
-}
-
-static void __init ox820_timer_init(void)
-{
-       of_clk_init(NULL);
-       clocksource_probe();
-}
-
-void ox820_init_early(void)
-{
-
-}
-
-void ox820_assert_system_reset(enum reboot_mode mode, const char *cmd)
-{
-       u32 value;
-
-/* Assert reset to cores as per power on defaults
- * Don't touch the DDR interface as things will come to an impromptu stop
- * NB Possibly should be asserting reset for PLLB, but there are timing
- *    concerns here according to the docs */
-       value = BIT(SYS_CTRL_RST_COPRO)         |
-               BIT(SYS_CTRL_RST_USBHS)         |
-               BIT(SYS_CTRL_RST_USBHSPHYA)     |
-               BIT(SYS_CTRL_RST_MACA)          |
-               BIT(SYS_CTRL_RST_PCIEA)         |
-               BIT(SYS_CTRL_RST_SGDMA)         |
-               BIT(SYS_CTRL_RST_CIPHER)        |
-               BIT(SYS_CTRL_RST_SATA)          |
-               BIT(SYS_CTRL_RST_SATA_LINK)     |
-               BIT(SYS_CTRL_RST_SATA_PHY)      |
-               BIT(SYS_CTRL_RST_PCIEPHY)       |
-               BIT(SYS_CTRL_RST_STATIC)        |
-               BIT(SYS_CTRL_RST_UART1)         |
-               BIT(SYS_CTRL_RST_UART2)         |
-               BIT(SYS_CTRL_RST_MISC)          |
-               BIT(SYS_CTRL_RST_I2S)           |
-               BIT(SYS_CTRL_RST_SD)            |
-               BIT(SYS_CTRL_RST_MACB)          |
-               BIT(SYS_CTRL_RST_PCIEB)         |
-               BIT(SYS_CTRL_RST_VIDEO)         |
-               BIT(SYS_CTRL_RST_USBHSPHYB)     |
-               BIT(SYS_CTRL_RST_USBDEV);
-
-       writel(value, SYS_CTRL_RST_SET_CTRL);
-
-       /* Release reset to cores as per power on defaults */
-       writel(BIT(SYS_CTRL_RST_GPIO), SYS_CTRL_RST_CLR_CTRL);
-
-       /* Disable clocks to cores as per power-on defaults - must leave DDR
-        * related clocks enabled otherwise we'll stop rather abruptly. */
-       value =
-               BIT(SYS_CTRL_CLK_COPRO)         |
-               BIT(SYS_CTRL_CLK_DMA)           |
-               BIT(SYS_CTRL_CLK_CIPHER)        |
-               BIT(SYS_CTRL_CLK_SD)            |
-               BIT(SYS_CTRL_CLK_SATA)          |
-               BIT(SYS_CTRL_CLK_I2S)           |
-               BIT(SYS_CTRL_CLK_USBHS)         |
-               BIT(SYS_CTRL_CLK_MAC)           |
-               BIT(SYS_CTRL_CLK_PCIEA)         |
-               BIT(SYS_CTRL_CLK_STATIC)        |
-               BIT(SYS_CTRL_CLK_MACB)          |
-               BIT(SYS_CTRL_CLK_PCIEB)         |
-               BIT(SYS_CTRL_CLK_REF600)        |
-               BIT(SYS_CTRL_CLK_USBDEV);
-
-       writel(value, SYS_CTRL_CLK_CLR_CTRL);
-
-       /* Enable clocks to cores as per power-on defaults */
-
-       /* Set sys-control pin mux'ing as per power-on defaults */
-       writel(0, SYS_CTRL_SECONDARY_SEL);
-       writel(0, SYS_CTRL_TERTIARY_SEL);
-       writel(0, SYS_CTRL_QUATERNARY_SEL);
-       writel(0, SYS_CTRL_DEBUG_SEL);
-       writel(0, SYS_CTRL_ALTERNATIVE_SEL);
-       writel(0, SYS_CTRL_PULLUP_SEL);
-
-       writel(0, SEC_CTRL_SECONDARY_SEL);
-       writel(0, SEC_CTRL_TERTIARY_SEL);
-       writel(0, SEC_CTRL_QUATERNARY_SEL);
-       writel(0, SEC_CTRL_DEBUG_SEL);
-       writel(0, SEC_CTRL_ALTERNATIVE_SEL);
-       writel(0, SEC_CTRL_PULLUP_SEL);
-
-       /* No need to save any state, as the ROM loader can determine whether
-        * reset is due to power cycling or programatic action, just hit the
-        * (self-clearing) CPU reset bit of the block reset register */
-       value =
-               BIT(SYS_CTRL_RST_SCU) |
-               BIT(SYS_CTRL_RST_ARM0) |
-               BIT(SYS_CTRL_RST_ARM1);
-
-       writel(value, SYS_CTRL_RST_SET_CTRL);
-}
-
-static const char * const ox820_dt_board_compat[] = {
-       "plxtech,nas7820",
-       "plxtech,nas7821",
-       "plxtech,nas7825",
-       NULL
-};
-
-DT_MACHINE_START(OX820_DT, "PLXTECH NAS782X SoC (Flattened Device Tree)")
-       .map_io         = ox820_map_common_io,
-       .smp            = smp_ops(ox820_smp_ops),
-       .init_early     = ox820_init_early,
-       .init_time      = ox820_timer_init,
-       .init_machine   = ox820_dt_init,
-       .restart        = ox820_assert_system_reset,
-       .dt_compat      = ox820_dt_board_compat,
-MACHINE_END
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/platsmp.c b/target/linux/oxnas/files/arch/arm/mach-oxnas/platsmp.c
deleted file mode 100644 (file)
index 8e4e2d8..0000000
+++ /dev/null
@@ -1,315 +0,0 @@
-/*
- *  arch/arm/mach-ox820/platsmp.c
- *
- *  Copyright (C) 2002 ARM Ltd.
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/jiffies.h>
-#include <linux/smp.h>
-#include <linux/io.h>
-#include <linux/dma-mapping.h>
-#include <linux/cache.h>
-#include <asm/cacheflush.h>
-#include <asm/smp_scu.h>
-#include <asm/tlbflush.h>
-#include <asm/cputype.h>
-#include <linux/delay.h>
-#include <asm/fiq.h>
-
-#include <linux/irqchip/arm-gic.h>
-#include <mach/iomap.h>
-#include <mach/smp.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-
-#ifdef CONFIG_DMA_CACHE_FIQ_BROADCAST
-
-#define FIQ_GENERATE           0x00000002
-#define OXNAS_MAP_AREA         0x01000000
-#define OXNAS_UNMAP_AREA       0x02000000
-#define OXNAS_FLUSH_RANGE      0x03000000
-
-struct fiq_req {
-       union {
-               struct {
-                       const void *addr;
-                       size_t size;
-               } map;
-               struct {
-                       const void *addr;
-                       size_t size;
-               } unmap;
-               struct {
-                       const void *start;
-                       const void *end;
-               } flush;
-       };
-       volatile uint flags;
-       void __iomem *reg;
-} ____cacheline_aligned;
-
-static struct fiq_handler fh = {
-       .name = "oxnas-fiq"
-};
-
-DEFINE_PER_CPU(struct fiq_req, fiq_data);
-
-static inline void ox820_set_fiq_regs(unsigned int cpu)
-{
-       struct pt_regs FIQ_regs;
-       struct fiq_req *fiq_req = &per_cpu(fiq_data, !cpu);
-
-       FIQ_regs.ARM_r8 = 0;
-       FIQ_regs.ARM_ip = (unsigned int)fiq_req;
-       FIQ_regs.ARM_sp = (int)(cpu ? RPSC_IRQ_SOFT : RPSA_IRQ_SOFT);
-       fiq_req->reg = cpu ? RPSC_IRQ_SOFT : RPSA_IRQ_SOFT;
-
-       set_fiq_regs(&FIQ_regs);
-}
-
-static void __init ox820_init_fiq(void)
-{
-       void *fiqhandler_start;
-       unsigned int fiqhandler_length;
-       int ret;
-
-       fiqhandler_start = &ox820_fiq_start;
-       fiqhandler_length = &ox820_fiq_end - &ox820_fiq_start;
-
-       ret = claim_fiq(&fh);
-
-       if (ret)
-               return;
-
-       set_fiq_handler(fiqhandler_start, fiqhandler_length);
-
-       writel(IRQ_SOFT, RPSA_FIQ_IRQ_TO_FIQ);
-       writel(1, RPSA_FIQ_ENABLE);
-       writel(IRQ_SOFT, RPSC_FIQ_IRQ_TO_FIQ);
-       writel(1, RPSC_FIQ_ENABLE);
-}
-
-void fiq_dma_map_area(const void *addr, size_t size, int dir)
-{
-       unsigned long flags;
-       struct fiq_req *req;
-
-       raw_local_irq_save(flags);
-       /* currently, not possible to take cpu0 down, so only check cpu1 */
-       if (!cpu_online(1)) {
-               raw_local_irq_restore(flags);
-               v6_dma_map_area(addr, size, dir);
-               return;
-       }
-
-       req = this_cpu_ptr(&fiq_data);
-       req->map.addr = addr;
-       req->map.size = size;
-       req->flags = dir | OXNAS_MAP_AREA;
-       smp_mb();
-
-       writel_relaxed(FIQ_GENERATE, req->reg);
-
-       v6_dma_map_area(addr, size, dir);
-       while (req->flags)
-               barrier();
-
-       raw_local_irq_restore(flags);
-}
-
-void fiq_dma_unmap_area(const void *addr, size_t size, int dir)
-{
-       unsigned long flags;
-       struct fiq_req *req;
-
-       raw_local_irq_save(flags);
-       /* currently, not possible to take cpu0 down, so only check cpu1 */
-       if (!cpu_online(1)) {
-               raw_local_irq_restore(flags);
-               v6_dma_unmap_area(addr, size, dir);
-               return;
-       }
-
-       req = this_cpu_ptr(&fiq_data);
-       req->unmap.addr = addr;
-       req->unmap.size = size;
-       req->flags = dir | OXNAS_UNMAP_AREA;
-       smp_mb();
-
-       writel_relaxed(FIQ_GENERATE, req->reg);
-
-       v6_dma_unmap_area(addr, size, dir);
-       while (req->flags)
-               barrier();
-
-       raw_local_irq_restore(flags);
-}
-
-void fiq_dma_flush_range(const void *start, const void *end)
-{
-       unsigned long flags;
-       struct fiq_req *req;
-
-       raw_local_irq_save(flags);
-       /* currently, not possible to take cpu0 down, so only check cpu1 */
-       if (!cpu_online(1)) {
-               raw_local_irq_restore(flags);
-               v6_dma_flush_range(start, end);
-               return;
-       }
-
-       req = this_cpu_ptr(&fiq_data);
-
-       req->flush.start = start;
-       req->flush.end = end;
-       req->flags = OXNAS_FLUSH_RANGE;
-       smp_mb();
-
-       writel_relaxed(FIQ_GENERATE, req->reg);
-
-       v6_dma_flush_range(start, end);
-
-       while (req->flags)
-               barrier();
-
-       raw_local_irq_restore(flags);
-}
-
-void fiq_flush_kern_dcache_area(void *addr, size_t size)
-{
-       fiq_dma_flush_range(addr, addr + size);
-}
-#else
-
-#define ox820_set_fiq_regs(cpu)        do {} while (0) /* nothing */
-#define ox820_init_fiq()       do {} while (0) /* nothing */
-
-#endif /* DMA_CACHE_FIQ_BROADCAST */
-
-static DEFINE_SPINLOCK(boot_lock);
-
-void ox820_secondary_init(unsigned int cpu)
-{
-       /*
-        * Setup Secondary Core FIQ regs
-        */
-       ox820_set_fiq_regs(1);
-
-       /*
-        * let the primary processor know we're out of the
-        * pen, then head off into the C entry point
-        */
-       write_pen_release(-1);
-
-       /*
-        * Synchronise with the boot thread.
-        */
-       spin_lock(&boot_lock);
-       spin_unlock(&boot_lock);
-}
-
-int ox820_boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
-       unsigned long timeout;
-
-       /*
-        * Set synchronisation state between this boot processor
-        * and the secondary one
-        */
-       spin_lock(&boot_lock);
-
-       /*
-        * This is really belt and braces; we hold unintended secondary
-        * CPUs in the holding pen until we're ready for them.  However,
-        * since we haven't sent them a soft interrupt, they shouldn't
-        * be there.
-        */
-       write_pen_release(cpu);
-
-       writel(1, IOMEM(OXNAS_GICN_BASE_VA(cpu) + GIC_CPU_CTRL));
-
-       /*
-        * Send the secondary CPU a soft interrupt, thereby causing
-        * the boot monitor to read the system wide flags register,
-        * and branch to the address found there.
-        */
-
-       arch_send_wakeup_ipi_mask(cpumask_of(cpu));
-       timeout = jiffies + (1 * HZ);
-       while (time_before(jiffies, timeout)) {
-               smp_rmb();
-               if (read_pen_release() == -1)
-                       break;
-
-               udelay(10);
-       }
-
-       /*
-        * now the secondary core is starting up let it run its
-        * calibrations, then wait for it to finish
-        */
-       spin_unlock(&boot_lock);
-
-       return read_pen_release() != -1 ? -ENOSYS : 0;
-}
-
-void *scu_base_addr(void)
-{
-       return IOMEM(OXNAS_SCU_BASE_VA);
-}
-
-/*
- * Initialise the CPU possible map early - this describes the CPUs
- * which may be present or become present in the system.
- */
-static void __init ox820_smp_init_cpus(void)
-{
-       void __iomem *scu_base = scu_base_addr();
-       unsigned int i, ncores;
-
-       ncores = scu_base ? scu_get_core_count(scu_base) : 1;
-
-       /* sanity check */
-       if (ncores > nr_cpu_ids) {
-               pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
-                       ncores, nr_cpu_ids);
-               ncores = nr_cpu_ids;
-       }
-
-       for (i = 0; i < ncores; i++)
-               set_cpu_possible(i, true);
-}
-
-static void __init ox820_smp_prepare_cpus(unsigned int max_cpus)
-{
-
-       scu_enable(scu_base_addr());
-
-       /*
-        * Write the address of secondary startup into the
-        * system-wide flags register. The BootMonitor waits
-        * until it receives a soft interrupt, and then the
-        * secondary CPU branches to this address.
-        */
-       writel(virt_to_phys(ox820_secondary_startup),
-                                       HOLDINGPEN_LOCATION);
-       ox820_init_fiq();
-
-       ox820_set_fiq_regs(0);
-}
-
-struct smp_operations ox820_smp_ops __initdata = {
-       .smp_init_cpus          = ox820_smp_init_cpus,
-       .smp_prepare_cpus       = ox820_smp_prepare_cpus,
-       .smp_secondary_init     = ox820_secondary_init,
-       .smp_boot_secondary     = ox820_boot_secondary,
-#ifdef CONFIG_HOTPLUG_CPU
-       .cpu_die                = ox820_cpu_die,
-#endif
-};
index 291a06f..64afa72 100644 (file)
 #include <linux/clk.h>
 #include <linux/reset.h>
 
-#include <mach/utils.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+static inline void oxnas_register_clear_mask(void __iomem *p, unsigned mask)
+{
+       u32 val = readl_relaxed(p);
+
+       val &= ~mask;
+       writel_relaxed(val, p);
+}
+
+static inline void oxnas_register_set_mask(void __iomem *p, unsigned mask)
+{
+       u32 val = readl_relaxed(p);
+
+       val |= mask;
+       writel_relaxed(val, p);
+}
+
+static inline void oxnas_register_value_mask(void __iomem *p,
+                                            unsigned mask, unsigned new_value)
+{
+       /* TODO sanity check mask & new_value = new_value */
+       u32 val = readl_relaxed(p);
+
+       val &= ~mask;
+       val |= new_value;
+       writel_relaxed(val, p);
+}
 
 /* sgdma request structure */
 struct sgdma_request {
@@ -848,7 +876,7 @@ wait_for_lock:
                 * list so want to give reentrant accessors a chance to get
                 * access ASAP
                 */
-               if (!list_empty(&hd->scsi_wait_queue.task_list))
+               if (!list_empty(&hd->scsi_wait_queue.head))
                        wake_up(&hd->scsi_wait_queue);
        }
 
@@ -867,7 +895,7 @@ int sata_core_has_fast_waiters(struct ata_host *ah)
        struct sata_oxnas_host_priv *hd = ah->private_data;
 
        spin_lock_irqsave(&hd->core_lock, flags);
-       has_waiters = !list_empty(&hd->fast_wait_queue.task_list);
+       has_waiters = !list_empty(&hd->fast_wait_queue.head);
        spin_unlock_irqrestore(&hd->core_lock, flags);
 
        return has_waiters;
@@ -882,7 +910,7 @@ int sata_core_has_scsi_waiters(struct ata_host *ah)
 
        spin_lock_irqsave(&hd->core_lock, flags);
        has_waiters = hd->scsi_nonblocking_attempts ||
-                     !list_empty(&hd->scsi_wait_queue.task_list);
+                     !list_empty(&hd->scsi_wait_queue.head);
        spin_unlock_irqrestore(&hd->core_lock, flags);
 
        return has_waiters;
@@ -954,7 +982,7 @@ static void sata_oxnas_release_hw(struct ata_port *ap)
                        hd->locker_uid = 0;
                        hd->core_locked = 0;
                        released = 1;
-                       wake_up(!list_empty(&hd->scsi_wait_queue.task_list) ?
+                       wake_up(!list_empty(&hd->scsi_wait_queue.head) ?
                                                &hd->scsi_wait_queue :
                                                &hd->fast_wait_queue);
                }
diff --git a/target/linux/oxnas/files/drivers/clk/clk-oxnas.c b/target/linux/oxnas/files/drivers/clk/clk-oxnas.c
deleted file mode 100644 (file)
index 4dc6c44..0000000
+++ /dev/null
@@ -1,297 +0,0 @@
-/*
- * Copyright (C) 2010 Broadcom
- * Copyright (C) 2012 Stephen Warren
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/delay.h>
-#include <linux/stringify.h>
-#include <linux/reset.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/utils.h>
-
-#define MHZ (1000 * 1000)
-
-struct clk_oxnas_pllb {
-       struct clk_hw hw;
-       struct device_node *devnode;
-       struct reset_control *rstc;
-};
-
-#define to_clk_oxnas_pllb(_hw) container_of(_hw, struct clk_oxnas_pllb, hw)
-
-static unsigned long plla_clk_recalc_rate(struct clk_hw *hw,
-       unsigned long parent_rate)
-{
-       unsigned long fin = parent_rate;
-       unsigned long pll0;
-       unsigned long fbdiv, refdiv, outdiv;
-
-       pll0 = readl_relaxed(SYS_CTRL_PLLA_CTRL0);
-       refdiv = (pll0 >> PLLA_REFDIV_SHIFT) & PLLA_REFDIV_MASK;
-       refdiv += 1;
-       outdiv = (pll0 >> PLLA_OUTDIV_SHIFT) & PLLA_OUTDIV_MASK;
-       outdiv += 1;
-       fbdiv = readl_relaxed(SYS_CTRL_PLLA_CTRL1);
-
-       /* seems we will not be here when pll is bypassed, so ignore this
-        * case */
-
-       return fin / MHZ * fbdiv / (refdiv * outdiv) / 32768 * MHZ;
-}
-
-static const char *pll_clk_parents[] = {
-       "oscillator",
-};
-
-static struct clk_ops plla_ops = {
-       .recalc_rate = plla_clk_recalc_rate,
-};
-
-static struct clk_init_data clk_plla_init = {
-       .name = "plla",
-       .ops = &plla_ops,
-       .parent_names = pll_clk_parents,
-       .num_parents = ARRAY_SIZE(pll_clk_parents),
-};
-
-static struct clk_hw plla_hw = {
-       .init = &clk_plla_init,
-};
-
-static int pllb_clk_is_prepared(struct clk_hw *hw)
-{
-       struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw);
-
-       return !!pllb->rstc;
-}
-
-static int pllb_clk_prepare(struct clk_hw *hw)
-{
-       struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw);
-
-       pllb->rstc = of_reset_control_get(pllb->devnode, NULL);
-
-       return IS_ERR(pllb->rstc) ? PTR_ERR(pllb->rstc) : 0;
-}
-
-static void pllb_clk_unprepare(struct clk_hw *hw)
-{
-       struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw);
-
-       BUG_ON(IS_ERR(pllb->rstc));
-
-       reset_control_put(pllb->rstc);
-       pllb->rstc = NULL;
-}
-
-static int pllb_clk_enable(struct clk_hw *hw)
-{
-       struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw);
-
-       BUG_ON(IS_ERR(pllb->rstc));
-
-       /* put PLL into bypass */
-       oxnas_register_set_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS));
-       wmb();
-       udelay(10);
-       reset_control_assert(pllb->rstc);
-       udelay(10);
-       /* set PLL B control information */
-       writel((1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV),
-                               SEC_CTRL_PLLB_CTRL0);
-       reset_control_deassert(pllb->rstc);
-       udelay(100);
-       oxnas_register_clear_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS));
-
-       return 0;
-}
-
-static void pllb_clk_disable(struct clk_hw *hw)
-{
-       struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw);
-
-       BUG_ON(IS_ERR(pllb->rstc));
-
-       /* put PLL into bypass */
-       oxnas_register_set_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS));
-       wmb();
-       udelay(10);
-
-       reset_control_assert(pllb->rstc);
-}
-
-static struct clk_ops pllb_ops = {
-       .prepare = pllb_clk_prepare,
-       .unprepare = pllb_clk_unprepare,
-       .is_prepared = pllb_clk_is_prepared,
-       .enable = pllb_clk_enable,
-       .disable = pllb_clk_disable,
-};
-
-static struct clk_init_data clk_pllb_init = {
-       .name = "pllb",
-       .ops = &pllb_ops,
-       .parent_names = pll_clk_parents,
-       .num_parents = ARRAY_SIZE(pll_clk_parents),
-};
-
-
-/* standard gate clock */
-struct clk_std {
-       struct clk_hw hw;
-       signed char bit;
-};
-
-#define NUM_STD_CLKS 17
-#define to_stdclk(_hw) container_of(_hw, struct clk_std, hw)
-
-static int std_clk_is_enabled(struct clk_hw *hw)
-{
-       struct clk_std *std = to_stdclk(hw);
-
-       return readl_relaxed(SYSCTRL_CLK_STAT) & BIT(std->bit);
-}
-
-static int std_clk_enable(struct clk_hw *hw)
-{
-       struct clk_std *std = to_stdclk(hw);
-
-       writel(BIT(std->bit), SYS_CTRL_CLK_SET_CTRL);
-       return 0;
-}
-
-static void std_clk_disable(struct clk_hw *hw)
-{
-       struct clk_std *std = to_stdclk(hw);
-
-       writel(BIT(std->bit), SYS_CTRL_CLK_CLR_CTRL);
-}
-
-static struct clk_ops std_clk_ops = {
-       .enable = std_clk_enable,
-       .disable = std_clk_disable,
-       .is_enabled = std_clk_is_enabled,
-};
-
-static const char *std_clk_parents[] = {
-       "oscillator",
-};
-
-static const char *eth_parents[] = {
-       "gmacclk",
-};
-
-#define DECLARE_STD_CLKP(__clk, __bit, __parent)       \
-static struct clk_init_data clk_##__clk##_init = {     \
-       .name = __stringify(__clk),                     \
-       .ops = &std_clk_ops,                            \
-       .parent_names = __parent,               \
-       .num_parents = ARRAY_SIZE(__parent),    \
-};                                                     \
-                                                       \
-static struct clk_std clk_##__clk = {                  \
-       .bit = __bit,                                   \
-       .hw = {                                         \
-               .init = &clk_##__clk##_init,            \
-       },                                              \
-}
-
-#define DECLARE_STD_CLK(__clk, __bit) DECLARE_STD_CLKP(__clk, __bit, \
-                                                       std_clk_parents)
-
-DECLARE_STD_CLK(leon, 0);
-DECLARE_STD_CLK(dma_sgdma, 1);
-DECLARE_STD_CLK(cipher, 2);
-DECLARE_STD_CLK(sd, 3);
-DECLARE_STD_CLK(sata, 4);
-DECLARE_STD_CLK(audio, 5);
-DECLARE_STD_CLK(usbmph, 6);
-DECLARE_STD_CLKP(etha, 7, eth_parents);
-DECLARE_STD_CLK(pciea, 8);
-DECLARE_STD_CLK(static, 9);
-DECLARE_STD_CLK(ethb, 10);
-DECLARE_STD_CLK(pcieb, 11);
-DECLARE_STD_CLK(ref600, 12);
-DECLARE_STD_CLK(usbdev, 13);
-
-struct clk_hw *std_clk_hw_tbl[] = {
-       &clk_leon.hw,
-       &clk_dma_sgdma.hw,
-       &clk_cipher.hw,
-       &clk_sd.hw,
-       &clk_sata.hw,
-       &clk_audio.hw,
-       &clk_usbmph.hw,
-       &clk_etha.hw,
-       &clk_pciea.hw,
-       &clk_static.hw,
-       &clk_ethb.hw,
-       &clk_pcieb.hw,
-       &clk_ref600.hw,
-       &clk_usbdev.hw,
-};
-
-struct clk *std_clk_tbl[ARRAY_SIZE(std_clk_hw_tbl)];
-
-static struct clk_onecell_data std_clk_data;
-
-void __init oxnas_init_stdclk(struct device_node *np)
-{
-       int i;
-
-       for (i = 0; i < ARRAY_SIZE(std_clk_hw_tbl); i++) {
-               std_clk_tbl[i] = clk_register(NULL, std_clk_hw_tbl[i]);
-               BUG_ON(IS_ERR(std_clk_tbl[i]));
-       }
-       std_clk_data.clks = std_clk_tbl;
-       std_clk_data.clk_num = ARRAY_SIZE(std_clk_tbl);
-       of_clk_add_provider(np, of_clk_src_onecell_get, &std_clk_data);
-}
-CLK_OF_DECLARE(oxnas_pllstd, "plxtech,nas782x-stdclk", oxnas_init_stdclk);
-
-void __init oxnas_init_plla(struct device_node *np)
-{
-       struct clk *clk;
-
-       clk = clk_register(NULL, &plla_hw);
-       BUG_ON(IS_ERR(clk));
-       /* mark it as enabled */
-       clk_prepare_enable(clk);
-       of_clk_add_provider(np, of_clk_src_simple_get, clk);
-}
-CLK_OF_DECLARE(oxnas_plla, "plxtech,nas782x-plla", oxnas_init_plla);
-
-void __init oxnas_init_pllb(struct device_node *np)
-{
-       struct clk *clk;
-       struct clk_oxnas_pllb *pllb;
-
-       pllb = kmalloc(sizeof(*pllb), GFP_KERNEL);
-       BUG_ON(!pllb);
-
-       pllb->hw.init = &clk_pllb_init;
-       pllb->devnode = np;
-       pllb->rstc = NULL;
-
-       clk = clk_register(NULL, &pllb->hw);
-       BUG_ON(IS_ERR(clk));
-       of_clk_add_provider(np, of_clk_src_simple_get, clk);
-}
-CLK_OF_DECLARE(oxnas_pllb, "plxtech,nas782x-pllb", oxnas_init_pllb);
diff --git a/target/linux/oxnas/files/drivers/clocksource/oxnas_rps_timer.c b/target/linux/oxnas/files/drivers/clocksource/oxnas_rps_timer.c
deleted file mode 100644 (file)
index 7c8c4cf..0000000
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * arch/arm/mach-ox820/rps-time.c
- *
- * Copyright (C) 2009 Oxford Semiconductor Ltd
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/clockchips.h>
-#include <linux/clk.h>
-#include <linux/of_irq.h>
-#include <linux/of_address.h>
-#include <linux/sched_clock.h>
-#include <mach/hardware.h>
-
-enum {
-       TIMER_LOAD = 0,
-       TIMER_CURR = 4,
-       TIMER_CTRL = 8,
-       TIMER_CLRINT = 0xC,
-
-       TIMER_BITS = 24,
-
-       TIMER_MAX_VAL = (1 << TIMER_BITS) - 1,
-
-       TIMER_PERIODIC = (1 << 6),
-       TIMER_ENABLE = (1 << 7),
-
-       TIMER_DIV1  = (0 << 2),
-       TIMER_DIV16  = (1 << 2),
-       TIMER_DIV256  = (2 << 2),
-
-       TIMER1_OFFSET = 0,
-       TIMER2_OFFSET = 0x20,
-
-};
-
-static u64 notrace rps_read_sched_clock(void)
-{
-       return ~readl_relaxed(RPSA_TIMER2_VAL);
-}
-
-static void __init rps_clocksource_init(void __iomem *base, ulong ref_rate)
-{
-       int ret;
-       ulong clock_rate;
-       /* use prescale 16 */
-       clock_rate = ref_rate / 16;
-
-       iowrite32(TIMER_MAX_VAL, base + TIMER_LOAD);
-       iowrite32(TIMER_PERIODIC | TIMER_ENABLE | TIMER_DIV16,
-                       base + TIMER_CTRL);
-
-       ret = clocksource_mmio_init(base + TIMER_CURR, "rps_clocksource_timer",
-                                       clock_rate, 250, TIMER_BITS,
-                                       clocksource_mmio_readl_down);
-       if (ret)
-               panic("can't register clocksource\n");
-
-       sched_clock_register(rps_read_sched_clock, TIMER_BITS, clock_rate);
-}
-
-static void __init rps_timer_init(struct device_node *np)
-{
-       struct clk *refclk;
-       unsigned long ref_rate;
-       void __iomem *base;
-
-       refclk = of_clk_get(np, 0);
-
-       if (IS_ERR(refclk) || clk_prepare_enable(refclk))
-               panic("rps_timer_init: failed to get refclk\n");
-       ref_rate = clk_get_rate(refclk);
-
-       base = of_iomap(np, 0);
-       if (!base)
-               panic("rps_timer_init: failed to map io\n");
-
-       rps_clocksource_init(base + TIMER2_OFFSET, ref_rate);
-}
-
-CLOCKSOURCE_OF_DECLARE(nas782x, "plxtech,nas782x-rps-timer", rps_timer_init);
diff --git a/target/linux/oxnas/files/drivers/irqchip/irq-rps.c b/target/linux/oxnas/files/drivers/irqchip/irq-rps.c
deleted file mode 100644 (file)
index f2b0829..0000000
+++ /dev/null
@@ -1,145 +0,0 @@
-#include <linux/irqdomain.h>
-#include <linux/irq.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/irqchip/chained_irq.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/irqchip.h>
-
-struct rps_chip_data {
-       void __iomem *base;
-       struct irq_chip chip;
-       struct irq_domain *domain;
-} rps_data;
-
-enum {
-       RPS_IRQ_BASE = 64,
-       RPS_IRQ_COUNT = 32,
-       PRS_HWIRQ_BASE = 0,
-
-       RPS_STATUS = 0,
-       RPS_RAW_STATUS = 4,
-       RPS_UNMASK = 8,
-       RPS_MASK = 0xc,
-};
-
-/*
- * Routines to acknowledge, disable and enable interrupts
- */
-static void rps_mask_irq(struct irq_data *d)
-{
-       struct rps_chip_data *chip_data = irq_data_get_irq_chip_data(d);
-       u32 mask = BIT(d->hwirq);
-
-       iowrite32(mask, chip_data->base + RPS_MASK);
-}
-
-static void rps_unmask_irq(struct irq_data *d)
-{
-       struct rps_chip_data *chip_data = irq_data_get_irq_chip_data(d);
-       u32 mask = BIT(d->hwirq);
-
-       iowrite32(mask, chip_data->base + RPS_UNMASK);
-}
-
-static struct irq_chip rps_chip = {
-       .name                   = "RPS",
-       .irq_mask               = rps_mask_irq,
-       .irq_unmask             = rps_unmask_irq,
-};
-
-static int rps_irq_domain_xlate(struct irq_domain *d,
-                               struct device_node *controller,
-                               const u32 *intspec, unsigned int intsize,
-                               unsigned long *out_hwirq,
-                               unsigned int *out_type)
-{
-       if (irq_domain_get_of_node(d) != controller)
-               return -EINVAL;
-       if (intsize < 1)
-               return -EINVAL;
-
-       *out_hwirq = intspec[0];
-       /* Honestly I do not know the type */
-       *out_type = IRQ_TYPE_LEVEL_HIGH;
-
-       return 0;
-}
-
-static int rps_irq_domain_map(struct irq_domain *d, unsigned int irq,
-                               irq_hw_number_t hw)
-{
-       irq_set_chip_and_handler(irq, &rps_chip, handle_level_irq);
-       irq_set_probe(irq);
-       irq_set_chip_data(irq, d->host_data);
-       return 0;
-}
-
-const struct irq_domain_ops rps_irq_domain_ops = {
-       .map = rps_irq_domain_map,
-       .xlate = rps_irq_domain_xlate,
-};
-
-static void rps_handle_cascade_irq(struct irq_desc *desc)
-{
-       struct rps_chip_data *chip_data = irq_desc_get_handler_data(desc);
-       struct irq_chip *chip = irq_desc_get_chip(desc);
-       unsigned int cascade_irq, rps_irq;
-       u32 status;
-
-       chained_irq_enter(chip, desc);
-
-       status = ioread32(chip_data->base + RPS_STATUS);
-       rps_irq = __ffs(status);
-       cascade_irq = irq_find_mapping(chip_data->domain, rps_irq);
-
-       if (unlikely(rps_irq >= RPS_IRQ_COUNT))
-               handle_bad_irq(desc);
-       else
-               generic_handle_irq(cascade_irq);
-
-       chained_irq_exit(chip, desc);
-}
-
-#ifdef CONFIG_OF
-int __init rps_of_init(struct device_node *node, struct device_node *parent)
-{
-       void __iomem *rps_base;
-       int irq_start = RPS_IRQ_BASE;
-       int irq_base;
-       int irq;
-
-       if (WARN_ON(!node))
-               return -ENODEV;
-
-       rps_base = of_iomap(node, 0);
-       WARN(!rps_base, "unable to map rps registers\n");
-       rps_data.base = rps_base;
-
-       irq_base = irq_alloc_descs(irq_start, 0, RPS_IRQ_COUNT, numa_node_id());
-       if (IS_ERR_VALUE(irq_base)) {
-               WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
-                    irq_start);
-               irq_base = irq_start;
-       }
-
-       rps_data.domain = irq_domain_add_legacy(node, RPS_IRQ_COUNT, irq_base,
-                       PRS_HWIRQ_BASE, &rps_irq_domain_ops, &rps_data);
-
-       if (WARN_ON(!rps_data.domain))
-               return -ENOMEM;
-
-       if (parent) {
-               irq = irq_of_parse_and_map(node, 0);
-               if (irq_set_handler_data(irq, &rps_data) != 0)
-                       BUG();
-               irq_set_chained_handler(irq, rps_handle_cascade_irq);
-       }
-       return 0;
-
-}
-
-IRQCHIP_DECLARE(nas782x, "plxtech,nas782x-rps", rps_of_init);
-#endif
diff --git a/target/linux/oxnas/files/drivers/mtd/nand/oxnas_nand.c b/target/linux/oxnas/files/drivers/mtd/nand/oxnas_nand.c
deleted file mode 100644 (file)
index 36807b7..0000000
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * Oxford Semiconductor OXNAS NAND driver
-
- * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
- * Heavily based on plat_nand.c :
- * Author: Vitaly Wool <vitalywool@gmail.com>
- * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
- * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/clk.h>
-#include <linux/reset.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/of.h>
-
-/* Nand commands */
-#define OXNAS_NAND_CMD_ALE             BIT(18)
-#define OXNAS_NAND_CMD_CLE             BIT(19)
-
-#define OXNAS_NAND_MAX_CHIPS   1
-
-struct oxnas_nand {
-       struct nand_hw_control base;
-       void __iomem *io_base;
-       struct clk *clk;
-       struct nand_chip *chips[OXNAS_NAND_MAX_CHIPS];
-       unsigned long ctrl;
-       struct mtd_partition *partitions;
-       int nr_partitions;
-};
-
-static uint8_t oxnas_nand_read_byte(struct mtd_info *mtd)
-{
-       struct nand_chip *chip = mtd_to_nand(mtd);
-       struct oxnas_nand *oxnas = nand_get_controller_data(chip);
-
-       return readb(oxnas->io_base);
-}
-
-static void oxnas_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
-{
-       struct nand_chip *chip = mtd_to_nand(mtd);
-       struct oxnas_nand *oxnas = nand_get_controller_data(chip);
-
-       ioread8_rep(oxnas->io_base, buf, len);
-}
-
-static void oxnas_nand_write_buf(struct mtd_info *mtd,
-                                const uint8_t *buf, int len)
-{
-       struct nand_chip *chip = mtd_to_nand(mtd);
-       struct oxnas_nand *oxnas = nand_get_controller_data(chip);
-
-       iowrite8_rep(oxnas->io_base + oxnas->ctrl, buf, len);
-}
-
-/* Single CS command control */
-static void oxnas_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
-                               unsigned int ctrl)
-{
-       struct nand_chip *chip = mtd_to_nand(mtd);
-       struct oxnas_nand *oxnas = nand_get_controller_data(chip);
-
-       if (ctrl & NAND_CTRL_CHANGE) {
-               if (ctrl & NAND_CLE)
-                       oxnas->ctrl = OXNAS_NAND_CMD_CLE;
-               else if (ctrl & NAND_ALE)
-                       oxnas->ctrl = OXNAS_NAND_CMD_ALE;
-               else
-                       oxnas->ctrl = 0;
-       }
-
-       if (cmd != NAND_CMD_NONE)
-               writeb(cmd, oxnas->io_base + oxnas->ctrl);
-}
-
-/*
- * Probe for the NAND device.
- */
-static int oxnas_nand_probe(struct platform_device *pdev)
-{
-       struct device_node *np = pdev->dev.of_node;
-       struct device_node *nand_np;
-       struct oxnas_nand *oxnas;
-       struct nand_chip *chip;
-       struct mtd_info *mtd;
-       struct resource *res;
-       int nchips = 0;
-       int count = 0;
-       int err = 0;
-
-       /* Allocate memory for the device structure (and zero it) */
-       oxnas = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip),
-                           GFP_KERNEL);
-       if (!oxnas)
-               return -ENOMEM;
-
-       nand_hw_control_init(&oxnas->base);
-
-       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-       oxnas->io_base = devm_ioremap_resource(&pdev->dev, res);
-       if (IS_ERR(oxnas->io_base))
-               return PTR_ERR(oxnas->io_base);
-
-       oxnas->clk = devm_clk_get(&pdev->dev, NULL);
-       if (IS_ERR(oxnas->clk))
-               oxnas->clk = NULL;
-
-       /* Only a single chip node is supported */
-       count = of_get_child_count(np);
-       if (count > 1)
-               return -EINVAL;
-
-       clk_prepare_enable(oxnas->clk);
-       device_reset_optional(&pdev->dev);
-
-       for_each_child_of_node(np, nand_np) {
-               chip = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip),
-                                   GFP_KERNEL);
-               if (!chip)
-                       return -ENOMEM;
-
-               chip->controller = &oxnas->base;
-
-               nand_set_flash_node(chip, nand_np);
-               nand_set_controller_data(chip, oxnas);
-
-               mtd = nand_to_mtd(chip);
-               mtd->dev.parent = &pdev->dev;
-               mtd->priv = chip;
-
-               chip->cmd_ctrl = oxnas_nand_cmd_ctrl;
-               chip->read_buf = oxnas_nand_read_buf;
-               chip->read_byte = oxnas_nand_read_byte;
-               chip->write_buf = oxnas_nand_write_buf;
-               chip->chip_delay = 30;
-
-               /* Scan to find existence of the device */
-               err = nand_scan(mtd, 1);
-               if (err)
-                       return err;
-
-               err = mtd_device_register(mtd, NULL, 0);
-               if (err) {
-                       nand_release(mtd);
-                       return err;
-               }
-
-               oxnas->chips[nchips] = chip;
-               ++nchips;
-       }
-
-       /* Exit if no chips found */
-       if (!nchips)
-               return -ENODEV;
-
-       platform_set_drvdata(pdev, oxnas);
-
-       return 0;
-}
-
-static int oxnas_nand_remove(struct platform_device *pdev)
-{
-       struct oxnas_nand *oxnas = platform_get_drvdata(pdev);
-
-       if (oxnas->chips[0])
-               nand_release(nand_to_mtd(oxnas->chips[0]));
-
-       clk_disable_unprepare(oxnas->clk);
-
-       return 0;
-}
-
-static const struct of_device_id oxnas_nand_match[] = {
-       { .compatible = "oxsemi,ox820-nand" },
-       {},
-};
-MODULE_DEVICE_TABLE(of, oxnas_nand_match);
-
-static struct platform_driver oxnas_nand_driver = {
-       .probe  = oxnas_nand_probe,
-       .remove = oxnas_nand_remove,
-       .driver = {
-               .name           = "oxnas_nand",
-               .of_match_table = oxnas_nand_match,
-       },
-};
-
-module_platform_driver(oxnas_nand_driver);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
-MODULE_DESCRIPTION("Oxnas NAND driver");
-MODULE_ALIAS("platform:oxnas_nand");
diff --git a/target/linux/oxnas/files/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c b/target/linux/oxnas/files/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c
deleted file mode 100644 (file)
index aafb118..0000000
+++ /dev/null
@@ -1,145 +0,0 @@
-/* Copyright OpenWrt.org (C) 2015.
- * Copyright Altera Corporation (C) 2014. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, version 2,
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- *
- * Adopted from dwmac-socfpga.c
- * Based on code found in mach-oxnas.c
- */
-
-#include <linux/mfd/syscon.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_net.h>
-#include <linux/phy.h>
-#include <linux/regmap.h>
-#include <linux/reset.h>
-#include <linux/stmmac.h>
-
-#include <mach/hardware.h>
-
-#include "stmmac.h"
-#include "stmmac_platform.h"
-
-struct oxnas_gmac {
-       struct clk *clk;
-};
-
-static int oxnas_gmac_init(struct platform_device *pdev, void *priv)
-{
-       struct oxnas_gmac *bsp_priv = priv;
-       int ret = 0;
-       unsigned value;
-
-       ret = device_reset(&pdev->dev);
-       if (ret)
-               return ret;
-
-       if (IS_ERR(bsp_priv->clk))
-               return PTR_ERR(bsp_priv->clk);
-       clk_prepare_enable(bsp_priv->clk);
-
-       value = readl(SYS_CTRL_GMAC_CTRL);
-
-       /* Enable GMII_GTXCLK to follow GMII_REFCLK, required for gigabit PHY */
-       value |= BIT(SYS_CTRL_GMAC_CKEN_GTX);
-       /* Use simple mux for 25/125 Mhz clock switching */
-       value |= BIT(SYS_CTRL_GMAC_SIMPLE_MUX);
-       /* set auto switch tx clock source */
-       value |= BIT(SYS_CTRL_GMAC_AUTO_TX_SOURCE);
-       /* enable tx & rx vardelay */
-       value |= BIT(SYS_CTRL_GMAC_CKEN_TX_OUT);
-       value |= BIT(SYS_CTRL_GMAC_CKEN_TXN_OUT);
-       value |= BIT(SYS_CTRL_GMAC_CKEN_TX_IN);
-       value |= BIT(SYS_CTRL_GMAC_CKEN_RX_OUT);
-       value |= BIT(SYS_CTRL_GMAC_CKEN_RXN_OUT);
-       value |= BIT(SYS_CTRL_GMAC_CKEN_RX_IN);
-       writel(value, SYS_CTRL_GMAC_CTRL);
-
-       /* set tx & rx vardelay */
-       value = 0;
-       value |= SYS_CTRL_GMAC_TX_VARDELAY(4);
-       value |= SYS_CTRL_GMAC_TXN_VARDELAY(2);
-       value |= SYS_CTRL_GMAC_RX_VARDELAY(10);
-       value |= SYS_CTRL_GMAC_RXN_VARDELAY(8);
-       writel(value, SYS_CTRL_GMAC_DELAY_CTRL);
-
-       return 0;
-}
-
-static void oxnas_gmac_exit(struct platform_device *pdev, void *priv)
-{
-       struct reset_control *rstc;
-
-       clk_disable_unprepare(priv);
-       devm_clk_put(&pdev->dev, priv);
-
-       rstc = reset_control_get(&pdev->dev, NULL);
-       if (!IS_ERR(rstc)) {
-               reset_control_assert(rstc);
-               reset_control_put(rstc);
-       }
-}
-
-static int oxnas_gmac_probe(struct platform_device *pdev)
-{
-       struct plat_stmmacenet_data *plat_dat;
-       struct stmmac_resources stmmac_res;
-       int                     ret;
-       struct device           *dev = &pdev->dev;
-       struct oxnas_gmac       *bsp_priv;
-
-       bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
-       if (!bsp_priv)
-               return -ENOMEM;
-       bsp_priv->clk = devm_clk_get(dev, "gmac");
-       if (IS_ERR(bsp_priv->clk))
-               return PTR_ERR(bsp_priv->clk);
-
-       ret = stmmac_get_platform_resources(pdev, &stmmac_res);
-       if (ret)
-               return ret;
-
-       plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
-       if (IS_ERR(plat_dat))
-               return PTR_ERR(plat_dat);
-
-       plat_dat->bsp_priv = bsp_priv;
-       plat_dat->init = oxnas_gmac_init;
-       plat_dat->exit = oxnas_gmac_exit;
-
-       ret = oxnas_gmac_init(pdev, bsp_priv);
-       if (ret)
-               return ret;
-
-       return stmmac_dvr_probe(dev, plat_dat, &stmmac_res);
-}
-
-static const struct of_device_id oxnas_gmac_match[] = {
-       { .compatible = "plxtech,nas782x-gmac" },
-       { }
-};
-MODULE_DEVICE_TABLE(of, oxnas_gmac_match);
-
-static struct platform_driver oxnas_gmac_driver = {
-       .probe  = oxnas_gmac_probe,
-       .remove = stmmac_pltfr_remove,
-       .driver = {
-               .name           = "oxnas-gmac",
-               .pm             = &stmmac_pltfr_pm_ops,
-               .of_match_table = oxnas_gmac_match,
-       },
-};
-module_platform_driver(oxnas_gmac_driver);
-
-MODULE_LICENSE("GPL v2");
index 9e8d6d9..7cf3ad1 100644 (file)
 #include <linux/delay.h>
 #include <linux/clk.h>
 #include <linux/reset.h>
-#include <mach/iomap.h>
-#include <mach/hardware.h>
-#include <mach/utils.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#define OXNAS_UART1_BASE       0x44200000
+#define OXNAS_UART1_SIZE       SZ_32
+#define OXNAS_UART1_BASE_VA    0xF0000000
+
+#define OXNAS_UART2_BASE       0x44300000
+#define OXNAS_UART2_SIZE       SZ_32
+
+#define OXNAS_PERCPU_BASE      0x47000000
+#define OXNAS_PERCPU_SIZE      SZ_8K
+#define OXNAS_PERCPU_BASE_VA   0xF0002000
+
+#define OXNAS_SYSCRTL_BASE     0x44E00000
+#define OXNAS_SYSCRTL_SIZE     SZ_4K
+#define OXNAS_SYSCRTL_BASE_VA  0xF0004000
+
+#define OXNAS_SECCRTL_BASE     0x44F00000
+#define OXNAS_SECCRTL_SIZE     SZ_4K
+#define OXNAS_SECCRTL_BASE_VA  0xF0005000
+
+#define OXNAS_RPSA_BASE                0x44400000
+#define OXNAS_RPSA_SIZE                SZ_4K
+#define OXNAS_RPSA_BASE_VA     0xF0006000
+
+#define OXNAS_RPSC_BASE                0x44500000
+#define OXNAS_RPSC_SIZE                SZ_4K
+#define OXNAS_RPSC_BASE_VA     0xF0007000
+
+
+/*
+ * Location of flags and vectors in SRAM for controlling the booting of the
+ * secondary ARM11 processors.
+ */
+
+#define OXNAS_SCU_BASE_VA              OXNAS_PERCPU_BASE_VA
+#define OXNAS_GICN_BASE_VA(n)          (OXNAS_PERCPU_BASE_VA + 0x200 + n*0x100)
+
+#define HOLDINGPEN_CPU                 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc8)
+#define HOLDINGPEN_LOCATION            IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc4)
+
+/**
+ * System block reset and clock control
+ */
+#define SYS_CTRL_PCI_STAT              IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x20)
+#define SYSCTRL_CLK_STAT               IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x24)
+#define SYS_CTRL_CLK_SET_CTRL          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x2C)
+#define SYS_CTRL_CLK_CLR_CTRL          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x30)
+#define SYS_CTRL_RST_SET_CTRL          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x34)
+#define SYS_CTRL_RST_CLR_CTRL          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x38)
+
+#define SYS_CTRL_PLLSYS_CTRL           IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x48)
+#define SYS_CTRL_CLK_CTRL              IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x64)
+#define SYS_CTRL_PLLSYS_KEY_CTRL       IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x6C)
+#define SYS_CTRL_GMAC_CTRL             IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x78)
+#define SYS_CTRL_GMAC_DELAY_CTRL       IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x100)
+
+/* Scratch registers */
+#define SYS_CTRL_SCRATCHWORD0          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc4)
+#define SYS_CTRL_SCRATCHWORD1          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc8)
+#define SYS_CTRL_SCRATCHWORD2          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xcc)
+#define SYS_CTRL_SCRATCHWORD3          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xd0)
+
+#define SYS_CTRL_PLLA_CTRL0            IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F0)
+#define SYS_CTRL_PLLA_CTRL1            IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F4)
+#define SYS_CTRL_PLLA_CTRL2            IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F8)
+#define SYS_CTRL_PLLA_CTRL3            IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1FC)
+
+#define SYS_CTRL_USBHSMPH_CTRL         IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x40)
+#define SYS_CTRL_USBHSMPH_STAT         IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x44)
+#define SYS_CTRL_REF300_DIV            IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xF8)
+#define SYS_CTRL_USBHSPHY_CTRL         IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x84)
+#define SYS_CTRL_USB_CTRL              IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x90)
+
+/* pcie */
+#define SYS_CTRL_HCSL_CTRL             IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x114)
+
+/* System control multi-function pin function selection */
+#define SYS_CTRL_SECONDARY_SEL         IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x14)
+#define SYS_CTRL_TERTIARY_SEL          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x8c)
+#define SYS_CTRL_QUATERNARY_SEL                IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x94)
+#define SYS_CTRL_DEBUG_SEL             IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x9c)
+#define SYS_CTRL_ALTERNATIVE_SEL       IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xa4)
+#define SYS_CTRL_PULLUP_SEL            IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xac)
+
+/* Secure control multi-function pin function selection */
+#define SEC_CTRL_SECONDARY_SEL         IOMEM(OXNAS_SECCRTL_BASE_VA + 0x14)
+#define SEC_CTRL_TERTIARY_SEL          IOMEM(OXNAS_SECCRTL_BASE_VA + 0x8c)
+#define SEC_CTRL_QUATERNARY_SEL                IOMEM(OXNAS_SECCRTL_BASE_VA + 0x94)
+#define SEC_CTRL_DEBUG_SEL             IOMEM(OXNAS_SECCRTL_BASE_VA + 0x9c)
+#define SEC_CTRL_ALTERNATIVE_SEL       IOMEM(OXNAS_SECCRTL_BASE_VA + 0xa4)
+#define SEC_CTRL_PULLUP_SEL            IOMEM(OXNAS_SECCRTL_BASE_VA + 0xac)
+
+#define SEC_CTRL_COPRO_CTRL            IOMEM(OXNAS_SECCRTL_BASE_VA + 0x68)
+#define SEC_CTRL_SECURE_CTRL           IOMEM(OXNAS_SECCRTL_BASE_VA + 0x98)
+#define SEC_CTRL_LEON_DEBUG            IOMEM(OXNAS_SECCRTL_BASE_VA + 0xF0)
+#define SEC_CTRL_PLLB_DIV_CTRL         IOMEM(OXNAS_SECCRTL_BASE_VA + 0xF8)
+#define SEC_CTRL_PLLB_CTRL0            IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F0)
+#define SEC_CTRL_PLLB_CTRL1            IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F4)
+#define SEC_CTRL_PLLB_CTRL8            IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F4)
+
+#define RPSA_IRQ_SOFT                  IOMEM(OXNAS_RPSA_BASE_VA + 0x10)
+#define RPSA_FIQ_ENABLE                        IOMEM(OXNAS_RPSA_BASE_VA + 0x108)
+#define RPSA_FIQ_DISABLE               IOMEM(OXNAS_RPSA_BASE_VA + 0x10C)
+#define RPSA_FIQ_IRQ_TO_FIQ            IOMEM(OXNAS_RPSA_BASE_VA + 0x1FC)
+
+#define RPSC_IRQ_SOFT                  IOMEM(OXNAS_RPSC_BASE_VA + 0x10)
+#define RPSC_FIQ_ENABLE                        IOMEM(OXNAS_RPSC_BASE_VA + 0x108)
+#define RPSC_FIQ_DISABLE               IOMEM(OXNAS_RPSC_BASE_VA + 0x10C)
+#define RPSC_FIQ_IRQ_TO_FIQ            IOMEM(OXNAS_RPSC_BASE_VA + 0x1FC)
+
+#define RPSA_TIMER2_VAL                        IOMEM(OXNAS_RPSA_BASE_VA + 0x224)
+
+#define REF300_DIV_INT_SHIFT           8
+#define REF300_DIV_FRAC_SHIFT          0
+#define REF300_DIV_INT(val)            ((val) << REF300_DIV_INT_SHIFT)
+#define REF300_DIV_FRAC(val)           ((val) << REF300_DIV_FRAC_SHIFT)
+
+#define USBHSPHY_SUSPENDM_MANUAL_ENABLE                16
+#define USBHSPHY_SUSPENDM_MANUAL_STATE         15
+#define USBHSPHY_ATE_ESET                      14
+#define USBHSPHY_TEST_DIN                      6
+#define USBHSPHY_TEST_ADD                      2
+#define USBHSPHY_TEST_DOUT_SEL                 1
+#define USBHSPHY_TEST_CLK                      0
+
+#define USB_CTRL_USBAPHY_CKSEL_SHIFT   5
+#define USB_CLK_XTAL0_XTAL1            (0 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
+#define USB_CLK_XTAL0                  (1 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
+#define USB_CLK_INTERNAL               (2 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
+
+#define USBAMUX_DEVICE                 BIT(4)
+
+#define USBPHY_REFCLKDIV_SHIFT         2
+#define USB_PHY_REF_12MHZ              (0 << USBPHY_REFCLKDIV_SHIFT)
+#define USB_PHY_REF_24MHZ              (1 << USBPHY_REFCLKDIV_SHIFT)
+#define USB_PHY_REF_48MHZ              (2 << USBPHY_REFCLKDIV_SHIFT)
+
+#define USB_CTRL_USB_CKO_SEL_BIT       0
+
+#define USB_INT_CLK_XTAL               0
+#define USB_INT_CLK_REF300             2
+#define USB_INT_CLK_PLLB               3
+
+#define SYS_CTRL_GMAC_CKEN_RX_IN       14
+#define SYS_CTRL_GMAC_CKEN_RXN_OUT     13
+#define SYS_CTRL_GMAC_CKEN_RX_OUT      12
+#define SYS_CTRL_GMAC_CKEN_TX_IN       10
+#define SYS_CTRL_GMAC_CKEN_TXN_OUT     9
+#define SYS_CTRL_GMAC_CKEN_TX_OUT      8
+#define SYS_CTRL_GMAC_RX_SOURCE                7
+#define SYS_CTRL_GMAC_TX_SOURCE                6
+#define SYS_CTRL_GMAC_LOW_TX_SOURCE    4
+#define SYS_CTRL_GMAC_AUTO_TX_SOURCE   3
+#define SYS_CTRL_GMAC_RGMII            2
+#define SYS_CTRL_GMAC_SIMPLE_MUX       1
+#define SYS_CTRL_GMAC_CKEN_GTX         0
+#define SYS_CTRL_GMAC_TX_VARDELAY_SHIFT                0
+#define SYS_CTRL_GMAC_TXN_VARDELAY_SHIFT       8
+#define SYS_CTRL_GMAC_RX_VARDELAY_SHIFT                16
+#define SYS_CTRL_GMAC_RXN_VARDELAY_SHIFT       24
+#define SYS_CTRL_GMAC_TX_VARDELAY(d)   ((d)<<SYS_CTRL_GMAC_TX_VARDELAY_SHIFT)
+#define SYS_CTRL_GMAC_TXN_VARDELAY(d)  ((d)<<SYS_CTRL_GMAC_TXN_VARDELAY_SHIFT)
+#define SYS_CTRL_GMAC_RX_VARDELAY(d)   ((d)<<SYS_CTRL_GMAC_RX_VARDELAY_SHIFT)
+#define SYS_CTRL_GMAC_RXN_VARDELAY(d)  ((d)<<SYS_CTRL_GMAC_RXN_VARDELAY_SHIFT)
+
+#define PLLB_BYPASS                    1
+#define PLLB_ENSAT                     3
+#define PLLB_OUTDIV                    4
+#define PLLB_REFDIV                    8
+#define PLLB_DIV_INT_SHIFT             8
+#define PLLB_DIV_FRAC_SHIFT            0
+#define PLLB_DIV_INT(val)              ((val) << PLLB_DIV_INT_SHIFT)
+#define PLLB_DIV_FRAC(val)             ((val) << PLLB_DIV_FRAC_SHIFT)
+
+#define SYS_CTRL_CKCTRL_PCI_DIV_BIT    0
+#define SYS_CTRL_CKCTRL_SLOW_BIT       8
+
+#define SYS_CTRL_UART2_DEQ_EN          0
+#define SYS_CTRL_UART3_DEQ_EN          1
+#define SYS_CTRL_UART3_IQ_EN           2
+#define SYS_CTRL_UART4_IQ_EN           3
+#define SYS_CTRL_UART4_NOT_PCI_MODE    4
+
+#define SYS_CTRL_PCI_CTRL1_PCI_STATIC_RQ_BIT   11
+
+#define PLLA_REFDIV_MASK               0x3F
+#define PLLA_REFDIV_SHIFT              8
+#define PLLA_OUTDIV_MASK               0x7
+#define PLLA_OUTDIV_SHIFT              4
+
+/* bit numbers of clock control register */
+#define SYS_CTRL_CLK_COPRO             0
+#define SYS_CTRL_CLK_DMA               1
+#define SYS_CTRL_CLK_CIPHER            2
+#define SYS_CTRL_CLK_SD                        3
+#define SYS_CTRL_CLK_SATA              4
+#define SYS_CTRL_CLK_I2S               5
+#define SYS_CTRL_CLK_USBHS             6
+#define SYS_CTRL_CLK_MACA              7
+#define SYS_CTRL_CLK_MAC               SYS_CTRL_CLK_MACA
+#define SYS_CTRL_CLK_PCIEA             8
+#define SYS_CTRL_CLK_STATIC            9
+#define SYS_CTRL_CLK_MACB              10
+#define SYS_CTRL_CLK_PCIEB             11
+#define SYS_CTRL_CLK_REF600            12
+#define SYS_CTRL_CLK_USBDEV            13
+#define SYS_CTRL_CLK_DDR               14
+#define SYS_CTRL_CLK_DDRPHY            15
+#define SYS_CTRL_CLK_DDRCK             16
+
+
+/* bit numbers of reset control register */
+#define SYS_CTRL_RST_SCU               0
+#define SYS_CTRL_RST_COPRO             1
+#define SYS_CTRL_RST_ARM0              2
+#define SYS_CTRL_RST_ARM1              3
+#define SYS_CTRL_RST_USBHS             4
+#define SYS_CTRL_RST_USBHSPHYA         5
+#define SYS_CTRL_RST_MACA              6
+#define SYS_CTRL_RST_MAC               SYS_CTRL_RST_MACA
+#define SYS_CTRL_RST_PCIEA             7
+#define SYS_CTRL_RST_SGDMA             8
+#define SYS_CTRL_RST_CIPHER            9
+#define SYS_CTRL_RST_DDR               10
+#define SYS_CTRL_RST_SATA              11
+#define SYS_CTRL_RST_SATA_LINK         12
+#define SYS_CTRL_RST_SATA_PHY          13
+#define SYS_CTRL_RST_PCIEPHY           14
+#define SYS_CTRL_RST_STATIC            15
+#define SYS_CTRL_RST_GPIO              16
+#define SYS_CTRL_RST_UART1             17
+#define SYS_CTRL_RST_UART2             18
+#define SYS_CTRL_RST_MISC              19
+#define SYS_CTRL_RST_I2S               20
+#define SYS_CTRL_RST_SD                        21
+#define SYS_CTRL_RST_MACB              22
+#define SYS_CTRL_RST_PCIEB             23
+#define SYS_CTRL_RST_VIDEO             24
+#define SYS_CTRL_RST_DDR_PHY           25
+#define SYS_CTRL_RST_USBHSPHYB         26
+#define SYS_CTRL_RST_USBDEV            27
+#define SYS_CTRL_RST_ARMDBG            29
+#define SYS_CTRL_RST_PLLA              30
+#define SYS_CTRL_RST_PLLB              31
+
+static inline void oxnas_register_clear_mask(void __iomem *p, unsigned mask)
+{
+       u32 val = readl_relaxed(p);
+
+       val &= ~mask;
+       writel_relaxed(val, p);
+}
+
+static inline void oxnas_register_set_mask(void __iomem *p, unsigned mask)
+{
+       u32 val = readl_relaxed(p);
+
+       val |= mask;
+       writel_relaxed(val, p);
+}
+
+static inline void oxnas_register_value_mask(void __iomem *p,
+                                            unsigned mask, unsigned new_value)
+{
+       /* TODO sanity check mask & new_value = new_value */
+       u32 val = readl_relaxed(p);
+
+       val &= ~mask;
+       val |= new_value;
+       writel_relaxed(val, p);
+}
 
 #define VERSION_ID_MAGIC               0x082510b5
 #define LINK_UP_TIMEOUT_SECONDS                1
diff --git a/target/linux/oxnas/files/drivers/pinctrl/pinctrl-oxnas.c b/target/linux/oxnas/files/drivers/pinctrl/pinctrl-oxnas.c
deleted file mode 100644 (file)
index 38a8cbb..0000000
+++ /dev/null
@@ -1,1461 +0,0 @@
-/*
- * oxnas pinctrl driver based on at91 pinctrl driver
- *
- * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * Under GPLv2 only
- */
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/irqchip/chained_irq.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-/* Since we request GPIOs from ourself */
-#include <linux/pinctrl/consumer.h>
-#include <linux/spinlock.h>
-
-#include "core.h"
-
-#include <mach/utils.h>
-
-#define MAX_NB_GPIO_PER_BANK   32
-#define MAX_GPIO_BANKS         2
-
-struct oxnas_gpio_chip {
-       struct gpio_chip        chip;
-       struct pinctrl_gpio_range range;
-       void __iomem            *regbase;  /* GPIOA/B virtual address */
-       void __iomem            *ctrlbase; /* SYS/SEC_CTRL virtual address */
-       struct irq_domain       *domain;   /* associated irq domain */
-       spinlock_t              lock;
-};
-
-#define to_oxnas_gpio_chip(c) container_of(c, struct oxnas_gpio_chip, chip)
-
-static struct oxnas_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
-
-static int gpio_banks;
-
-#define PULL_UP                (1 << 0)
-#define PULL_DOWN      (1 << 1)
-#define DEBOUNCE       (1 << 2)
-
-/**
- * struct oxnas_pmx_func - describes pinmux functions
- * @name: the name of this specific function
- * @groups: corresponding pin groups
- * @ngroups: the number of groups
- */
-struct oxnas_pmx_func {
-       const char      *name;
-       const char      **groups;
-       unsigned        ngroups;
-};
-
-enum oxnas_mux {
-       OXNAS_PINMUX_GPIO,
-       OXNAS_PINMUX_FUNC2,
-       OXNAS_PINMUX_FUNC3,
-       OXNAS_PINMUX_FUNC4,
-       OXNAS_PINMUX_DEBUG,
-       OXNAS_PINMUX_ALT,
-};
-
-enum {
-       INPUT_VALUE = 0,
-       OUTPUT_ENABLE = 4,
-       IRQ_PENDING = 0xC,
-       OUTPUT_VALUE = 0x10,
-       OUTPUT_SET = 0x14,
-       OUTPUT_CLEAR = 0x18,
-       OUTPUT_EN_SET = 0x1C,
-       OUTPUT_EN_CLEAR = 0x20,
-       DEBOUNCE_ENABLE = 0x24,
-       RE_IRQ_ENABLE = 0x28, /* rising edge */
-       FE_IRQ_ENABLE = 0x2C, /* falling edge */
-       RE_IRQ_PENDING = 0x30, /* rising edge */
-       FE_IRQ_PENDING = 0x34, /* falling edge */
-       CLOCK_DIV = 0x48,
-       PULL_ENABLE = 0x50,
-       PULL_SENSE = 0x54, /* 1 up, 0 down */
-
-
-       DEBOUNCE_MASK = 0x3FFF0000,
-       /* put hw debounce and soft config at same bit position*/
-       DEBOUNCE_SHIFT = 16
-};
-
-enum {
-       PINMUX_SECONDARY_SEL = 0x14,
-       PINMUX_TERTIARY_SEL = 0x8c,
-       PINMUX_QUATERNARY_SEL = 0x94,
-       PINMUX_DEBUG_SEL = 0x9c,
-       PINMUX_ALTERNATIVE_SEL = 0xa4,
-       PINMUX_PULLUP_SEL = 0xac,
-};
-
-/**
- * struct oxnas_pmx_pin - describes an pin mux
- * @bank: the bank of the pin
- * @pin: the pin number in the @bank
- * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
- * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
- */
-struct oxnas_pmx_pin {
-       uint32_t        bank;
-       uint32_t        pin;
-       enum oxnas_mux  mux;
-       unsigned long   conf;
-};
-
-/**
- * struct oxnas_pin_group - describes an pin group
- * @name: the name of this specific pin group
- * @pins_conf: the mux mode for each pin in this group. The size of this
- *     array is the same as pins.
- * @pins: an array of discrete physical pins used in this group, taken
- *     from the driver-local pin enumeration space
- * @npins: the number of pins in this group array, i.e. the number of
- *     elements in .pins so we can iterate over that array
- */
-struct oxnas_pin_group {
-       const char              *name;
-       struct oxnas_pmx_pin    *pins_conf;
-       unsigned int            *pins;
-       unsigned                npins;
-};
-
-struct oxnas_pinctrl {
-       struct device           *dev;
-       struct pinctrl_dev      *pctl;
-
-       int                     nbanks;
-
-       uint32_t                *mux_mask;
-       int                     nmux;
-
-       struct oxnas_pmx_func   *functions;
-       int                     nfunctions;
-
-       struct oxnas_pin_group  *groups;
-       int                     ngroups;
-};
-
-static const inline struct oxnas_pin_group *oxnas_pinctrl_find_group_by_name(
-                               const struct oxnas_pinctrl *info,
-                               const char *name)
-{
-       const struct oxnas_pin_group *grp = NULL;
-       int i;
-
-       for (i = 0; i < info->ngroups; i++) {
-               if (strcmp(info->groups[i].name, name))
-                       continue;
-
-               grp = &info->groups[i];
-               dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins,
-                       grp->pins[0]);
-               break;
-       }
-
-       return grp;
-}
-
-static int oxnas_get_groups_count(struct pinctrl_dev *pctldev)
-{
-       struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
-
-       return info->ngroups;
-}
-
-static const char *oxnas_get_group_name(struct pinctrl_dev *pctldev,
-                                      unsigned selector)
-{
-       struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
-
-       return info->groups[selector].name;
-}
-
-static int oxnas_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
-                              const unsigned **pins,
-                              unsigned *npins)
-{
-       struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
-
-       if (selector >= info->ngroups)
-               return -EINVAL;
-
-       *pins = info->groups[selector].pins;
-       *npins = info->groups[selector].npins;
-
-       return 0;
-}
-
-static void oxnas_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
-                  unsigned offset)
-{
-       seq_printf(s, "%s", dev_name(pctldev->dev));
-}
-
-static int oxnas_dt_node_to_map(struct pinctrl_dev *pctldev,
-                       struct device_node *np,
-                       struct pinctrl_map **map, unsigned *num_maps)
-{
-       struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
-       const struct oxnas_pin_group *grp;
-       struct pinctrl_map *new_map;
-       struct device_node *parent;
-       int map_num = 1;
-       int i;
-
-       /*
-        * first find the group of this node and check if we need create
-        * config maps for pins
-        */
-       grp = oxnas_pinctrl_find_group_by_name(info, np->name);
-       if (!grp) {
-               dev_err(info->dev, "unable to find group for node %s\n",
-                       np->name);
-               return -EINVAL;
-       }
-
-       map_num += grp->npins;
-       new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
-                              GFP_KERNEL);
-       if (!new_map)
-               return -ENOMEM;
-
-       *map = new_map;
-       *num_maps = map_num;
-
-       /* create mux map */
-       parent = of_get_parent(np);
-       if (!parent) {
-               devm_kfree(pctldev->dev, new_map);
-               return -EINVAL;
-       }
-       new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
-       new_map[0].data.mux.function = parent->name;
-       new_map[0].data.mux.group = np->name;
-       of_node_put(parent);
-
-       /* create config map */
-       new_map++;
-       for (i = 0; i < grp->npins; i++) {
-               new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
-               new_map[i].data.configs.group_or_pin =
-                               pin_get_name(pctldev, grp->pins[i]);
-               new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
-               new_map[i].data.configs.num_configs = 1;
-       }
-
-       dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
-               (*map)->data.mux.function, (*map)->data.mux.group, map_num);
-
-       return 0;
-}
-
-static void oxnas_dt_free_map(struct pinctrl_dev *pctldev,
-                               struct pinctrl_map *map, unsigned num_maps)
-{
-}
-
-static const struct pinctrl_ops oxnas_pctrl_ops = {
-       .get_groups_count       = oxnas_get_groups_count,
-       .get_group_name         = oxnas_get_group_name,
-       .get_group_pins         = oxnas_get_group_pins,
-       .pin_dbg_show           = oxnas_pin_dbg_show,
-       .dt_node_to_map         = oxnas_dt_node_to_map,
-       .dt_free_map            = oxnas_dt_free_map,
-};
-
-static void __iomem *pin_to_gpioctrl(struct oxnas_pinctrl *info,
-                                unsigned int bank)
-{
-       return gpio_chips[bank]->regbase;
-}
-
-static void __iomem *pin_to_muxctrl(struct oxnas_pinctrl *info,
-                                unsigned int bank)
-{
-       return gpio_chips[bank]->ctrlbase;
-}
-
-
-static inline int pin_to_bank(unsigned pin)
-{
-       return pin / MAX_NB_GPIO_PER_BANK;
-}
-
-static unsigned pin_to_mask(unsigned int pin)
-{
-       return 1 << pin;
-}
-
-static void oxnas_mux_disable_interrupt(void __iomem *pio, unsigned mask)
-{
-       oxnas_register_clear_mask(pio + RE_IRQ_ENABLE, mask);
-       oxnas_register_clear_mask(pio + FE_IRQ_ENABLE, mask);
-}
-
-static unsigned oxnas_mux_get_pullup(void __iomem *pio, unsigned pin)
-{
-       return (readl_relaxed(pio + PULL_ENABLE) & BIT(pin)) &&
-               (readl_relaxed(pio + PULL_SENSE) & BIT(pin));
-}
-
-static void oxnas_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
-{
-       if (on) {
-               oxnas_register_set_mask(pio + PULL_SENSE, mask);
-               oxnas_register_set_mask(pio + PULL_ENABLE, mask);
-       } else {
-               oxnas_register_clear_mask(pio + PULL_ENABLE, mask);
-       }
-}
-
-static bool oxnas_mux_get_pulldown(void __iomem *pio, unsigned pin)
-{
-       return (readl_relaxed(pio + PULL_ENABLE) & BIT(pin)) &&
-                       (!(readl_relaxed(pio + PULL_SENSE) & BIT(pin)));
-}
-
-static void oxnas_mux_set_pulldown(void __iomem *pio, unsigned mask, bool on)
-{
-       if (on) {
-               oxnas_register_clear_mask(pio + PULL_SENSE, mask);
-               oxnas_register_set_mask(pio + PULL_ENABLE, mask);
-       } else {
-               oxnas_register_clear_mask(pio + PULL_ENABLE, mask);
-       };
-}
-
-/* unfortunately debounce control are shared */
-static bool oxnas_mux_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
-{
-       *div = __raw_readl(pio + CLOCK_DIV) & DEBOUNCE_MASK;
-       return __raw_readl(pio + DEBOUNCE_ENABLE) & BIT(pin);
-}
-
-static void oxnas_mux_set_debounce(void __iomem *pio, unsigned mask,
-                               bool is_on, u32 div)
-{
-       if (is_on) {
-               oxnas_register_value_mask(pio + CLOCK_DIV, DEBOUNCE_MASK, div);
-               oxnas_register_set_mask(pio + DEBOUNCE_ENABLE, mask);
-       } else {
-               oxnas_register_clear_mask(pio + DEBOUNCE_ENABLE, mask);
-       }
-}
-
-
-static void oxnas_mux_set_func2(void __iomem *cio, unsigned mask)
-{
-/* in fact, SECONDARY takes precedence, so clear others is not necessary */
-       oxnas_register_set_mask(cio + PINMUX_SECONDARY_SEL, mask);
-       oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask);
-       oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask);
-       oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask);
-       oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask);
-}
-
-static void oxnas_mux_set_func3(void __iomem *cio, unsigned mask)
-{
-       oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask);
-       oxnas_register_set_mask(cio + PINMUX_TERTIARY_SEL, mask);
-       oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask);
-       oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask);
-       oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask);
-}
-
-static void oxnas_mux_set_func4(void __iomem *cio, unsigned mask)
-{
-       oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask);
-       oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask);
-       oxnas_register_set_mask(cio + PINMUX_QUATERNARY_SEL, mask);
-       oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask);
-       oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask);
-}
-
-static void oxnas_mux_set_func_dbg(void __iomem *cio, unsigned mask)
-{
-       oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask);
-       oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask);
-       oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask);
-       oxnas_register_set_mask(cio + PINMUX_DEBUG_SEL, mask);
-       oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask);
-}
-
-static void oxnas_mux_set_func_alt(void __iomem *cio, unsigned mask)
-{
-       oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask);
-       oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask);
-       oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask);
-       oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask);
-       oxnas_register_set_mask(cio + PINMUX_ALTERNATIVE_SEL, mask);
-}
-
-static void oxnas_mux_set_gpio(void __iomem *cio, unsigned mask)
-{
-       oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask);
-       oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask);
-       oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask);
-       oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask);
-       oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask);
-}
-
-static enum oxnas_mux oxnas_mux_get_func(void __iomem *cio, unsigned mask)
-{
-       if (readl_relaxed(cio + PINMUX_SECONDARY_SEL) & mask)
-               return OXNAS_PINMUX_FUNC2;
-       if (readl_relaxed(cio + PINMUX_TERTIARY_SEL) & mask)
-               return OXNAS_PINMUX_FUNC3;
-       if (readl_relaxed(cio + PINMUX_QUATERNARY_SEL) & mask)
-               return OXNAS_PINMUX_FUNC4;
-       if (readl_relaxed(cio + PINMUX_DEBUG_SEL) & mask)
-               return OXNAS_PINMUX_DEBUG;
-       if (readl_relaxed(cio + PINMUX_ALTERNATIVE_SEL) & mask)
-               return OXNAS_PINMUX_ALT;
-       return OXNAS_PINMUX_GPIO;
-}
-
-
-static void oxnas_pin_dbg(const struct device *dev,
-                         const struct oxnas_pmx_pin *pin)
-{
-       if (pin->mux) {
-               dev_dbg(dev,
-                       "MF_%c%d configured as periph%c with conf = 0x%lu\n",
-                       pin->bank + 'A', pin->pin, pin->mux - 1 + 'A',
-                       pin->conf);
-       } else {
-               dev_dbg(dev, "MF_%c%d configured as gpio with conf = 0x%lu\n",
-                       pin->bank + 'A', pin->pin, pin->conf);
-       }
-}
-
-static int pin_check_config(struct oxnas_pinctrl *info, const char *name,
-                           int index, const struct oxnas_pmx_pin *pin)
-{
-       int mux;
-
-       /* check if it's a valid config */
-       if (pin->bank >= info->nbanks) {
-               dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
-                       name, index, pin->bank, info->nbanks);
-               return -EINVAL;
-       }
-
-       if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
-               dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
-                       name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
-               return -EINVAL;
-       }
-       /* gpio always allowed */
-       if (!pin->mux)
-               return 0;
-
-       mux = pin->mux - 1;
-
-       if (mux >= info->nmux) {
-               dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
-                       name, index, mux, info->nmux);
-               return -EINVAL;
-       }
-
-       if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
-               dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for MF_%c%d\n",
-                       name, index, mux, pin->bank + 'A', pin->pin);
-               return -EINVAL;
-       }
-
-       return 0;
-}
-
-static void oxnas_mux_gpio_enable(void __iomem *cio, void __iomem *pio,
-                                 unsigned mask, bool input)
-{
-       oxnas_mux_set_gpio(cio, mask);
-       if (input)
-               writel_relaxed(mask, pio + OUTPUT_EN_CLEAR);
-       else
-               writel_relaxed(mask, pio + OUTPUT_EN_SET);
-}
-
-static void oxnas_mux_gpio_disable(void __iomem *cio, void __iomem *pio,
-                                  unsigned mask)
-{
-       /* when switch to other function,  gpio is disabled automatically */
-       return;
-}
-
-static int oxnas_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
-                           unsigned group)
-{
-       struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
-       const struct oxnas_pmx_pin *pins_conf = info->groups[group].pins_conf;
-       const struct oxnas_pmx_pin *pin;
-       uint32_t npins = info->groups[group].npins;
-       int i, ret;
-       unsigned mask;
-       void __iomem *pio;
-       void __iomem *cio;
-
-       dev_dbg(info->dev, "enable function %s group %s\n",
-               info->functions[selector].name, info->groups[group].name);
-
-       /* first check that all the pins of the group are valid with a valid
-        * paramter */
-       for (i = 0; i < npins; i++) {
-               pin = &pins_conf[i];
-               ret = pin_check_config(info, info->groups[group].name, i, pin);
-               if (ret)
-                       return ret;
-       }
-
-       for (i = 0; i < npins; i++) {
-               pin = &pins_conf[i];
-               oxnas_pin_dbg(info->dev, pin);
-
-               pio = pin_to_gpioctrl(info, pin->bank);
-               cio = pin_to_muxctrl(info, pin->bank);
-
-               mask = pin_to_mask(pin->pin);
-               oxnas_mux_disable_interrupt(pio, mask);
-
-               switch (pin->mux) {
-               case OXNAS_PINMUX_GPIO:
-                       oxnas_mux_gpio_enable(cio, pio, mask, 1);
-                       break;
-               case OXNAS_PINMUX_FUNC2:
-                       oxnas_mux_set_func2(cio, mask);
-                       break;
-               case OXNAS_PINMUX_FUNC3:
-                       oxnas_mux_set_func3(cio, mask);
-                       break;
-               case OXNAS_PINMUX_FUNC4:
-                       oxnas_mux_set_func4(cio, mask);
-                       break;
-               case OXNAS_PINMUX_DEBUG:
-                       oxnas_mux_set_func_dbg(cio, mask);
-                       break;
-               case OXNAS_PINMUX_ALT:
-                       oxnas_mux_set_func_alt(cio, mask);
-                       break;
-               }
-               if (pin->mux)
-                       oxnas_mux_gpio_disable(cio, pio, mask);
-       }
-
-       return 0;
-}
-
-static int oxnas_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
-{
-       struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
-
-       return info->nfunctions;
-}
-
-static const char *oxnas_pmx_get_func_name(struct pinctrl_dev *pctldev,
-                                          unsigned selector)
-{
-       struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
-
-       return info->functions[selector].name;
-}
-
-static int oxnas_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
-                               const char * const **groups,
-                               unsigned * const num_groups)
-{
-       struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
-
-       *groups = info->functions[selector].groups;
-       *num_groups = info->functions[selector].ngroups;
-
-       return 0;
-}
-
-static int oxnas_gpio_request_enable(struct pinctrl_dev *pctldev,
-                                    struct pinctrl_gpio_range *range,
-                                    unsigned offset)
-{
-       struct oxnas_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
-       struct oxnas_gpio_chip *oxnas_chip;
-       struct gpio_chip *chip;
-       unsigned mask;
-
-       if (!range) {
-               dev_err(npct->dev, "invalid range\n");
-               return -EINVAL;
-       }
-       if (!range->gc) {
-               dev_err(npct->dev, "missing GPIO chip in range\n");
-               return -EINVAL;
-       }
-       chip = range->gc;
-       oxnas_chip = container_of(chip, struct oxnas_gpio_chip, chip);
-
-       dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
-
-       mask = 1 << (offset - chip->base);
-
-       dev_dbg(npct->dev, "enable pin %u as MF_%c%d 0x%x\n",
-               offset, 'A' + range->id, offset - chip->base, mask);
-
-       oxnas_mux_set_gpio(oxnas_chip->ctrlbase, mask);
-
-       return 0;
-}
-
-static void oxnas_gpio_disable_free(struct pinctrl_dev *pctldev,
-                                   struct pinctrl_gpio_range *range,
-                                   unsigned offset)
-{
-       struct oxnas_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
-
-       dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
-       /* Set the pin to some default state, GPIO is usually default */
-}
-
-static const struct pinmux_ops oxnas_pmx_ops = {
-       .get_functions_count    = oxnas_pmx_get_funcs_count,
-       .get_function_name      = oxnas_pmx_get_func_name,
-       .get_function_groups    = oxnas_pmx_get_groups,
-       .set_mux                = oxnas_pmx_set_mux,
-       .gpio_request_enable    = oxnas_gpio_request_enable,
-       .gpio_disable_free      = oxnas_gpio_disable_free,
-};
-
-static int oxnas_pinconf_get(struct pinctrl_dev *pctldev,
-                            unsigned pin_id, unsigned long *config)
-{
-       struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
-       void __iomem *pio;
-       unsigned pin;
-       int div;
-
-       dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__,
-               __LINE__, pin_id, *config);
-       pio = pin_to_gpioctrl(info, pin_to_bank(pin_id));
-       pin = pin_id % MAX_NB_GPIO_PER_BANK;
-
-       if (oxnas_mux_get_pullup(pio, pin))
-               *config |= PULL_UP;
-
-       if (oxnas_mux_get_pulldown(pio, pin))
-               *config |= PULL_DOWN;
-
-       if (oxnas_mux_get_debounce(pio, pin, &div))
-               *config |= DEBOUNCE | div;
-       return 0;
-}
-
-static int oxnas_pinconf_set(struct pinctrl_dev *pctldev,
-                            unsigned pin_id, unsigned long *configs,
-                            unsigned num_configs)
-{
-       struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
-       unsigned mask;
-       void __iomem *pio;
-       int i;
-       unsigned long config;
-
-       pio = pin_to_gpioctrl(info, pin_to_bank(pin_id));
-       mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK);
-
-       for (i = 0; i < num_configs; i++) {
-               config = configs[i];
-
-               dev_dbg(info->dev,
-                       "%s:%d, pin_id=%d, config=0x%lx",
-                       __func__, __LINE__, pin_id, config);
-
-               if ((config & PULL_UP) && (config & PULL_DOWN))
-                       return -EINVAL;
-
-               oxnas_mux_set_pullup(pio, mask, config & PULL_UP);
-               oxnas_mux_set_pulldown(pio, mask, config & PULL_DOWN);
-               oxnas_mux_set_debounce(pio, mask, config & DEBOUNCE,
-                                      config & DEBOUNCE_MASK);
-
-       } /* for each config */
-
-       return 0;
-}
-
-static void oxnas_pinconf_dbg_show(struct pinctrl_dev *pctldev,
-                                  struct seq_file *s, unsigned pin_id)
-{
-
-}
-
-static void oxnas_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
-                                        struct seq_file *s, unsigned group)
-{
-}
-
-static const struct pinconf_ops oxnas_pinconf_ops = {
-       .pin_config_get                 = oxnas_pinconf_get,
-       .pin_config_set                 = oxnas_pinconf_set,
-       .pin_config_dbg_show            = oxnas_pinconf_dbg_show,
-       .pin_config_group_dbg_show      = oxnas_pinconf_group_dbg_show,
-};
-
-static struct pinctrl_desc oxnas_pinctrl_desc = {
-       .pctlops        = &oxnas_pctrl_ops,
-       .pmxops         = &oxnas_pmx_ops,
-       .confops        = &oxnas_pinconf_ops,
-       .owner          = THIS_MODULE,
-};
-
-static const char *gpio_compat = "plxtech,nas782x-gpio";
-
-static void oxnas_pinctrl_child_count(struct oxnas_pinctrl *info,
-                                     struct device_node *np)
-{
-       struct device_node *child;
-
-       for_each_child_of_node(np, child) {
-               if (of_device_is_compatible(child, gpio_compat)) {
-                       info->nbanks++;
-               } else {
-                       info->nfunctions++;
-                       info->ngroups += of_get_child_count(child);
-               }
-       }
-}
-
-static int oxnas_pinctrl_mux_mask(struct oxnas_pinctrl *info,
-                                 struct device_node *np)
-{
-       int ret = 0;
-       int size;
-       const __be32 *list;
-
-       list = of_get_property(np, "plxtech,mux-mask", &size);
-       if (!list) {
-               dev_err(info->dev, "can not read the mux-mask of %d\n", size);
-               return -EINVAL;
-       }
-
-       size /= sizeof(*list);
-       if (!size || size % info->nbanks) {
-               dev_err(info->dev, "wrong mux mask array should be by %d\n",
-                       info->nbanks);
-               return -EINVAL;
-       }
-       info->nmux = size / info->nbanks;
-
-       info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
-       if (!info->mux_mask) {
-               dev_err(info->dev, "could not alloc mux_mask\n");
-               return -ENOMEM;
-       }
-
-       ret = of_property_read_u32_array(np, "plxtech,mux-mask",
-                                         info->mux_mask, size);
-       if (ret)
-               dev_err(info->dev, "can not read the mux-mask of %d\n", size);
-       return ret;
-}
-
-static int oxnas_pinctrl_parse_groups(struct device_node *np,
-                                     struct oxnas_pin_group *grp,
-                                     struct oxnas_pinctrl *info, u32 index)
-{
-       struct oxnas_pmx_pin *pin;
-       int size;
-       const __be32 *list;
-       int i, j;
-
-       dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
-
-       /* Initialise group */
-       grp->name = np->name;
-
-       /*
-        * the binding format is plxtech,pins = <bank pin mux CONFIG ...>,
-        * do sanity check and calculate pins number
-        */
-       list = of_get_property(np, "plxtech,pins", &size);
-       /* we do not check return since it's safe node passed down */
-       size /= sizeof(*list);
-       if (!size || size % 4) {
-               dev_err(info->dev, "wrong pins number or pins and configs"
-                       " should be divisible by 4\n");
-               return -EINVAL;
-       }
-
-       grp->npins = size / 4;
-       pin = grp->pins_conf = devm_kzalloc(info->dev,
-                               grp->npins * sizeof(struct oxnas_pmx_pin),
-                               GFP_KERNEL);
-       grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
-                               GFP_KERNEL);
-       if (!grp->pins_conf || !grp->pins)
-               return -ENOMEM;
-
-       for (i = 0, j = 0; i < size; i += 4, j++) {
-               pin->bank = be32_to_cpu(*list++);
-               pin->pin = be32_to_cpu(*list++);
-               grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
-               pin->mux = be32_to_cpu(*list++);
-               pin->conf = be32_to_cpu(*list++);
-
-               oxnas_pin_dbg(info->dev, pin);
-               pin++;
-       }
-
-       return 0;
-}
-
-static int oxnas_pinctrl_parse_functions(struct device_node *np,
-                                       struct oxnas_pinctrl *info, u32 index)
-{
-       struct device_node *child;
-       struct oxnas_pmx_func *func;
-       struct oxnas_pin_group *grp;
-       int ret;
-       static u32 grp_index;
-       u32 i = 0;
-
-       dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
-
-       func = &info->functions[index];
-
-       /* Initialise function */
-       func->name = np->name;
-       func->ngroups = of_get_child_count(np);
-       if (func->ngroups <= 0) {
-               dev_err(info->dev, "no groups defined\n");
-               return -EINVAL;
-       }
-       func->groups = devm_kzalloc(info->dev,
-                       func->ngroups * sizeof(char *), GFP_KERNEL);
-       if (!func->groups)
-               return -ENOMEM;
-
-       for_each_child_of_node(np, child) {
-               func->groups[i] = child->name;
-               grp = &info->groups[grp_index++];
-               ret = oxnas_pinctrl_parse_groups(child, grp, info, i++);
-               if (ret)
-                       return ret;
-       }
-
-       return 0;
-}
-
-static struct of_device_id oxnas_pinctrl_of_match[] = {
-       { .compatible = "plxtech,nas782x-pinctrl"},
-       { /* sentinel */ }
-};
-
-static int oxnas_pinctrl_probe_dt(struct platform_device *pdev,
-                                struct oxnas_pinctrl *info)
-{
-       int ret = 0;
-       int i, j;
-       uint32_t *tmp;
-       struct device_node *np = pdev->dev.of_node;
-       struct device_node *child;
-
-       if (!np)
-               return -ENODEV;
-
-       info->dev = &pdev->dev;
-
-       oxnas_pinctrl_child_count(info, np);
-
-       if (info->nbanks < 1) {
-               dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n");
-               return -EINVAL;
-       }
-
-       ret = oxnas_pinctrl_mux_mask(info, np);
-       if (ret)
-               return ret;
-
-       dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
-
-       dev_dbg(&pdev->dev, "mux-mask\n");
-       tmp = info->mux_mask;
-       for (i = 0; i < info->nbanks; i++)
-               for (j = 0; j < info->nmux; j++, tmp++)
-                       dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
-
-       dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
-       dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
-       info->functions = devm_kzalloc(&pdev->dev, info->nfunctions *
-                                               sizeof(struct oxnas_pmx_func),
-                                       GFP_KERNEL);
-       if (!info->functions)
-               return -ENOMEM;
-
-       info->groups = devm_kzalloc(&pdev->dev, info->ngroups *
-                                       sizeof(struct oxnas_pin_group),
-                                   GFP_KERNEL);
-       if (!info->groups)
-               return -ENOMEM;
-
-       dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks);
-       dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
-       dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
-
-       i = 0;
-
-       for_each_child_of_node(np, child) {
-               if (of_device_is_compatible(child, gpio_compat))
-                       continue;
-               ret = oxnas_pinctrl_parse_functions(child, info, i++);
-               if (ret) {
-                       dev_err(&pdev->dev, "failed to parse function\n");
-                       return ret;
-               }
-       }
-
-       return 0;
-}
-
-static int oxnas_pinctrl_probe(struct platform_device *pdev)
-{
-       struct oxnas_pinctrl *info;
-       struct pinctrl_pin_desc *pdesc;
-       int ret, i, j, k;
-
-       info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
-       if (!info)
-               return -ENOMEM;
-
-       ret = oxnas_pinctrl_probe_dt(pdev, info);
-       if (ret)
-               return ret;
-
-       /*
-        * We need all the GPIO drivers to probe FIRST, or we will not be able
-        * to obtain references to the struct gpio_chip * for them, and we
-        * need this to proceed.
-        */
-       for (i = 0; i < info->nbanks; i++) {
-               if (!gpio_chips[i]) {
-                       dev_warn(&pdev->dev,
-                                "GPIO chip %d not registered yet\n", i);
-                       devm_kfree(&pdev->dev, info);
-                       return -EPROBE_DEFER;
-               }
-       }
-
-       oxnas_pinctrl_desc.name = dev_name(&pdev->dev);
-       oxnas_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK;
-       oxnas_pinctrl_desc.pins = pdesc =
-               devm_kzalloc(&pdev->dev, sizeof(*pdesc) *
-                               oxnas_pinctrl_desc.npins, GFP_KERNEL);
-
-       if (!oxnas_pinctrl_desc.pins)
-               return -ENOMEM;
-
-       for (i = 0 , k = 0; i < info->nbanks; i++) {
-               for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
-                       pdesc->number = k;
-                       pdesc->name = kasprintf(GFP_KERNEL, "MF_%c%d", i + 'A',
-                                               j);
-                       pdesc++;
-               }
-       }
-
-       platform_set_drvdata(pdev, info);
-       info->pctl = pinctrl_register(&oxnas_pinctrl_desc, &pdev->dev, info);
-
-       if (!info->pctl) {
-               dev_err(&pdev->dev, "could not register OX820 pinctrl driver\n");
-               ret = -EINVAL;
-               goto err;
-       }
-
-       /* We will handle a range of GPIO pins */
-       for (i = 0; i < info->nbanks; i++)
-               pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
-
-       dev_info(&pdev->dev, "initialized OX820 pinctrl driver\n");
-
-       return 0;
-
-err:
-       return ret;
-}
-
-static int oxnas_pinctrl_remove(struct platform_device *pdev)
-{
-       struct oxnas_pinctrl *info = platform_get_drvdata(pdev);
-
-       pinctrl_unregister(info->pctl);
-
-       return 0;
-}
-
-static int oxnas_gpio_request(struct gpio_chip *chip, unsigned offset)
-{
-       /*
-        * Map back to global GPIO space and request muxing, the direction
-        * parameter does not matter for this controller.
-        */
-       int gpio = chip->base + offset;
-       int bank = chip->base / chip->ngpio;
-
-       dev_dbg(chip->dev, "%s:%d MF_%c%d(%d)\n", __func__, __LINE__,
-               'A' + bank, offset, gpio);
-
-       return pinctrl_request_gpio(gpio);
-}
-
-static void oxnas_gpio_free(struct gpio_chip *chip, unsigned offset)
-{
-       int gpio = chip->base + offset;
-
-       pinctrl_free_gpio(gpio);
-}
-
-static int oxnas_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
-       struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip);
-       void __iomem *pio = oxnas_gpio->regbase;
-
-       writel_relaxed(BIT(offset), pio + OUTPUT_EN_CLEAR);
-       return 0;
-}
-
-static int oxnas_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
-       struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip);
-       void __iomem *pio = oxnas_gpio->regbase;
-       unsigned mask = 1 << offset;
-       u32 pdsr;
-
-       pdsr = readl_relaxed(pio + INPUT_VALUE);
-       return (pdsr & mask) != 0;
-}
-
-static void oxnas_gpio_set(struct gpio_chip *chip, unsigned offset,
-                               int val)
-{
-       struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip);
-       void __iomem *pio = oxnas_gpio->regbase;
-
-       if (val)
-               writel_relaxed(BIT(offset), pio + OUTPUT_SET);
-       else
-               writel_relaxed(BIT(offset), pio + OUTPUT_CLEAR);
-
-}
-
-static int oxnas_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
-                               int val)
-{
-       struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip);
-       void __iomem *pio = oxnas_gpio->regbase;
-
-       if (val)
-               writel_relaxed(BIT(offset), pio + OUTPUT_SET);
-       else
-               writel_relaxed(BIT(offset), pio + OUTPUT_CLEAR);
-
-       writel_relaxed(BIT(offset), pio + OUTPUT_EN_SET);
-
-       return 0;
-}
-
-static int oxnas_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-       struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip);
-       int virq;
-
-       if (offset < chip->ngpio)
-               virq = irq_create_mapping(oxnas_gpio->domain, offset);
-       else
-               virq = -ENXIO;
-
-       dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
-                               chip->label, offset + chip->base, virq);
-       return virq;
-}
-
-#ifdef CONFIG_DEBUG_FS
-static void oxnas_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
-{
-       enum oxnas_mux mode;
-       int i;
-       struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip);
-       void __iomem *pio = oxnas_gpio->regbase;
-       void __iomem *cio = oxnas_gpio->ctrlbase;
-
-       for (i = 0; i < chip->ngpio; i++) {
-               unsigned pin = chip->base + i;
-               unsigned mask = pin_to_mask(pin);
-               const char *gpio_label;
-               u32 pdsr;
-
-               gpio_label = gpiochip_is_requested(chip, i);
-               if (!gpio_label)
-                       continue;
-               /* FIXME */
-               mode = oxnas_mux_get_func(cio, mask);
-               seq_printf(s, "[%s] GPIO%s%d: ",
-                          gpio_label, chip->label, i);
-               if (mode == OXNAS_PINMUX_GPIO) {
-                       pdsr = readl_relaxed(pio + INPUT_VALUE);
-
-                       seq_printf(s, "[gpio] %s\n",
-                                  pdsr & mask ?
-                                  "set" : "clear");
-               } else {
-                       seq_printf(s, "[periph %c]\n",
-                                  mode + 'A' - 1);
-               }
-       }
-}
-#else
-#define oxnas_gpio_dbg_show    NULL
-#endif
-
-/* Several AIC controller irqs are dispatched through this GPIO handler.
- * To use any AT91_PIN_* as an externally triggered IRQ, first call
- * oxnas_set_gpio_input() then maybe enable its glitch filter.
- * Then just request_irq() with the pin ID; it works like any ARM IRQ
- * handler.
- */
-
-static void gpio_irq_mask(struct irq_data *d)
-{
-       struct oxnas_gpio_chip *oxnas_gpio = irq_data_get_irq_chip_data(d);
-       void __iomem    *pio = oxnas_gpio->regbase;
-       unsigned        mask = 1 << d->hwirq;
-       unsigned        type = irqd_get_trigger_type(d);
-       unsigned long   flags;
-
-       if (!(type & IRQ_TYPE_EDGE_BOTH))
-               return;
-
-       spin_lock_irqsave(&oxnas_gpio->lock, flags);
-       if (type & IRQ_TYPE_EDGE_RISING)
-               oxnas_register_clear_mask(pio + RE_IRQ_ENABLE, mask);
-       if (type & IRQ_TYPE_EDGE_FALLING)
-               oxnas_register_clear_mask(pio + FE_IRQ_ENABLE, mask);
-       spin_unlock_irqrestore(&oxnas_gpio->lock, flags);
-}
-
-static void gpio_irq_unmask(struct irq_data *d)
-{
-       struct oxnas_gpio_chip *oxnas_gpio = irq_data_get_irq_chip_data(d);
-       void __iomem    *pio = oxnas_gpio->regbase;
-       unsigned        mask = 1 << d->hwirq;
-       unsigned        type = irqd_get_trigger_type(d);
-       unsigned long   flags;
-
-       if (!(type & IRQ_TYPE_EDGE_BOTH))
-               return;
-
-       spin_lock_irqsave(&oxnas_gpio->lock, flags);
-       if (type & IRQ_TYPE_EDGE_RISING)
-               oxnas_register_set_mask(pio + RE_IRQ_ENABLE, mask);
-       if (type & IRQ_TYPE_EDGE_FALLING)
-               oxnas_register_set_mask(pio + FE_IRQ_ENABLE, mask);
-       spin_unlock_irqrestore(&oxnas_gpio->lock, flags);
-}
-
-
-static int gpio_irq_type(struct irq_data *d, unsigned type)
-{
-       if ((type & IRQ_TYPE_EDGE_BOTH) == 0) {
-               pr_warn("OX820: Unsupported type for irq %d\n",
-                       gpio_to_irq(d->irq));
-               return -EINVAL;
-       }
-       /* seems no way to set trigger type without enable irq, so leave it to unmask time */
-
-       return 0;
-}
-
-static struct irq_chip gpio_irqchip = {
-       .name           = "GPIO",
-       .irq_disable    = gpio_irq_mask,
-       .irq_mask       = gpio_irq_mask,
-       .irq_unmask     = gpio_irq_unmask,
-       .irq_set_type   = gpio_irq_type,
-};
-
-static void gpio_irq_handler(struct irq_desc *desc)
-{
-       struct irq_chip *chip = irq_desc_get_chip(desc);
-       struct irq_data *idata = irq_desc_get_irq_data(desc);
-       struct oxnas_gpio_chip *oxnas_gpio = irq_data_get_irq_chip_data(idata);
-       void __iomem *pio = oxnas_gpio->regbase;
-       unsigned long isr;
-       int n;
-
-       chained_irq_enter(chip, desc);
-       for (;;) {
-               /* TODO: see if it works */
-               isr = readl_relaxed(pio + IRQ_PENDING);
-               if (!isr)
-                       break;
-               /* acks pending interrupts */
-               writel_relaxed(isr, pio + IRQ_PENDING);
-
-               for_each_set_bit(n, &isr, BITS_PER_LONG) {
-                       generic_handle_irq(irq_find_mapping(oxnas_gpio->domain,
-                                                           n));
-               }
-       }
-       chained_irq_exit(chip, desc);
-       /* now it may re-trigger */
-}
-
-/*
- * This lock class tells lockdep that GPIO irqs are in a different
- * category than their parents, so it won't report false recursion.
- */
-static struct lock_class_key gpio_lock_class;
-
-static int oxnas_gpio_irq_map(struct irq_domain *h, unsigned int virq,
-                             irq_hw_number_t hw)
-{
-       struct oxnas_gpio_chip *oxnas_gpio = h->host_data;
-
-       irq_set_lockdep_class(virq, &gpio_lock_class);
-
-       irq_set_chip_and_handler(virq, &gpio_irqchip, handle_edge_irq);
-       irq_set_chip_data(virq, oxnas_gpio);
-
-       return 0;
-}
-
-static int oxnas_gpio_irq_domain_xlate(struct irq_domain *d,
-                                      struct device_node *ctrlr,
-                                      const u32 *intspec,
-                                      unsigned int intsize,
-                                      irq_hw_number_t *out_hwirq,
-                                      unsigned int *out_type)
-{
-       struct oxnas_gpio_chip *oxnas_gpio = d->host_data;
-       int ret;
-       int pin = oxnas_gpio->chip.base + intspec[0];
-
-       if (WARN_ON(intsize < 2))
-               return -EINVAL;
-       *out_hwirq = intspec[0];
-       *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
-
-       ret = gpio_request(pin, ctrlr->full_name);
-       if (ret)
-               return ret;
-
-       ret = gpio_direction_input(pin);
-       if (ret)
-               return ret;
-
-       return 0;
-}
-
-static struct irq_domain_ops oxnas_gpio_ops = {
-       .map    = oxnas_gpio_irq_map,
-       .xlate  = oxnas_gpio_irq_domain_xlate,
-};
-
-static int oxnas_gpio_of_irq_setup(struct device_node *node,
-                                  struct oxnas_gpio_chip *oxnas_gpio,
-                                  unsigned int irq)
-{
-       /* Disable irqs of this controller */
-       writel_relaxed(0, oxnas_gpio->regbase + RE_IRQ_ENABLE);
-       writel_relaxed(0, oxnas_gpio->regbase + FE_IRQ_ENABLE);
-
-       /* Setup irq domain */
-       oxnas_gpio->domain = irq_domain_add_linear(node, oxnas_gpio->chip.ngpio,
-                                                  &oxnas_gpio_ops, oxnas_gpio);
-       if (!oxnas_gpio->domain)
-               panic("oxnas_gpio: couldn't allocate irq domain (DT).\n");
-
-       irq_set_chip_data(irq, oxnas_gpio);
-       irq_set_chained_handler(irq, gpio_irq_handler);
-
-       return 0;
-}
-
-/* This structure is replicated for each GPIO block allocated at probe time */
-static struct gpio_chip oxnas_gpio_template = {
-       .request                = oxnas_gpio_request,
-       .free                   = oxnas_gpio_free,
-       .direction_input        = oxnas_gpio_direction_input,
-       .get                    = oxnas_gpio_get,
-       .direction_output       = oxnas_gpio_direction_output,
-       .set                    = oxnas_gpio_set,
-       .to_irq                 = oxnas_gpio_to_irq,
-       .dbg_show               = oxnas_gpio_dbg_show,
-       .can_sleep              = 0,
-       .ngpio                  = MAX_NB_GPIO_PER_BANK,
-};
-
-static struct of_device_id oxnas_gpio_of_match[] = {
-       { .compatible = "plxtech,nas782x-gpio"},
-       { /* sentinel */ }
-};
-
-static int oxnas_gpio_probe(struct platform_device *pdev)
-{
-       struct device_node *np = pdev->dev.of_node;
-       struct resource *res;
-       struct oxnas_gpio_chip *oxnas_chip = NULL;
-       struct gpio_chip *chip;
-       struct pinctrl_gpio_range *range;
-       int ret = 0;
-       int irq, i;
-       int alias_idx = of_alias_get_id(np, "gpio");
-       uint32_t ngpio;
-       char **names;
-
-       BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
-       if (gpio_chips[alias_idx]) {
-               ret = -EBUSY;
-               goto err;
-       }
-
-       irq = platform_get_irq(pdev, 0);
-       if (irq < 0) {
-               ret = irq;
-               goto err;
-       }
-
-       oxnas_chip = devm_kzalloc(&pdev->dev, sizeof(*oxnas_chip), GFP_KERNEL);
-       if (!oxnas_chip) {
-               ret = -ENOMEM;
-               goto err;
-       }
-
-       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-       oxnas_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
-       if (IS_ERR(oxnas_chip->regbase)) {
-               ret = PTR_ERR(oxnas_chip->regbase);
-               goto err;
-       }
-
-       res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-       oxnas_chip->ctrlbase = devm_ioremap_resource(&pdev->dev, res);
-       if (IS_ERR(oxnas_chip->ctrlbase)) {
-               ret = PTR_ERR(oxnas_chip->ctrlbase);
-               goto err;
-       }
-
-       oxnas_chip->chip = oxnas_gpio_template;
-
-       spin_lock_init(&oxnas_chip->lock);
-
-       chip = &oxnas_chip->chip;
-       chip->of_node = np;
-       chip->label = dev_name(&pdev->dev);
-       chip->dev = &pdev->dev;
-       chip->owner = THIS_MODULE;
-       chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
-
-       if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
-               if (ngpio > MAX_NB_GPIO_PER_BANK)
-                       pr_err("oxnas_gpio.%d, gpio-nb >= %d failback to %d\n",
-                              alias_idx, MAX_NB_GPIO_PER_BANK,
-                              MAX_NB_GPIO_PER_BANK);
-               else
-                       chip->ngpio = ngpio;
-       }
-
-       names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio,
-                            GFP_KERNEL);
-
-       if (!names) {
-               ret = -ENOMEM;
-               goto err;
-       }
-
-       for (i = 0; i < chip->ngpio; i++)
-               names[i] = kasprintf(GFP_KERNEL, "MF_%c%d", alias_idx + 'A', i);
-
-       chip->names = (const char *const *)names;
-
-       range = &oxnas_chip->range;
-       range->name = chip->label;
-       range->id = alias_idx;
-       range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
-
-       range->npins = chip->ngpio;
-       range->gc = chip;
-
-       ret = gpiochip_add(chip);
-       if (ret)
-               goto err;
-
-       gpio_chips[alias_idx] = oxnas_chip;
-       gpio_banks = max(gpio_banks, alias_idx + 1);
-
-       oxnas_gpio_of_irq_setup(np, oxnas_chip, irq);
-
-       dev_info(&pdev->dev, "at address %p\n", oxnas_chip->regbase);
-
-       return 0;
-err:
-       dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
-
-       return ret;
-}
-
-static struct platform_driver oxnas_gpio_driver = {
-       .driver = {
-               .name = "gpio-oxnas",
-               .owner = THIS_MODULE,
-               .of_match_table = of_match_ptr(oxnas_gpio_of_match),
-       },
-       .probe = oxnas_gpio_probe,
-};
-
-static struct platform_driver oxnas_pinctrl_driver = {
-       .driver = {
-               .name = "pinctrl-oxnas",
-               .owner = THIS_MODULE,
-               .of_match_table = of_match_ptr(oxnas_pinctrl_of_match),
-       },
-       .probe = oxnas_pinctrl_probe,
-       .remove = oxnas_pinctrl_remove,
-};
-
-static int __init oxnas_pinctrl_init(void)
-{
-       int ret;
-
-       ret = platform_driver_register(&oxnas_gpio_driver);
-       if (ret)
-               return ret;
-       return platform_driver_register(&oxnas_pinctrl_driver);
-}
-arch_initcall(oxnas_pinctrl_init);
-
-static void __exit oxnas_pinctrl_exit(void)
-{
-       platform_driver_unregister(&oxnas_pinctrl_driver);
-}
-
-module_exit(oxnas_pinctrl_exit);
-MODULE_AUTHOR("Ma Hajun <mahaijuns@gmail.com>");
-MODULE_DESCRIPTION("Plxtech Nas782x pinctrl driver");
-MODULE_LICENSE("GPL v2");
diff --git a/target/linux/oxnas/files/drivers/reset/reset-ox820.c b/target/linux/oxnas/files/drivers/reset/reset-ox820.c
deleted file mode 100644 (file)
index 0a28de5..0000000
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/reset-controller.h>
-#include <linux/slab.h>
-#include <linux/types.h>
-#include <mach/hardware.h>
-
-static int ox820_reset_reset(struct reset_controller_dev *rcdev,
-                             unsigned long id)
-{
-       writel(BIT(id), SYS_CTRL_RST_SET_CTRL);
-       writel(BIT(id), SYS_CTRL_RST_CLR_CTRL);
-       return 0;
-}
-
-static int ox820_reset_assert(struct reset_controller_dev *rcdev,
-                             unsigned long id)
-{
-       writel(BIT(id), SYS_CTRL_RST_SET_CTRL);
-
-       return 0;
-}
-
-static int ox820_reset_deassert(struct reset_controller_dev *rcdev,
-                               unsigned long id)
-{
-       writel(BIT(id), SYS_CTRL_RST_CLR_CTRL);
-
-       return 0;
-}
-
-static struct reset_control_ops ox820_reset_ops = {
-       .reset          = ox820_reset_reset,
-       .assert         = ox820_reset_assert,
-       .deassert       = ox820_reset_deassert,
-};
-
-static const struct of_device_id ox820_reset_dt_ids[] = {
-        { .compatible = "plxtech,nas782x-reset", },
-        { /* sentinel */ },
-};
-MODULE_DEVICE_TABLE(of, ox820_reset_dt_ids);
-
-struct reset_controller_dev rcdev;
-
-static int ox820_reset_probe(struct platform_device *pdev)
-{
-       struct reset_controller_dev *rcdev;
-
-       rcdev = devm_kzalloc(&pdev->dev, sizeof(*rcdev), GFP_KERNEL);
-       if (!rcdev)
-               return -ENOMEM;
-
-       /* note: reset controller is statically mapped */
-
-       rcdev->owner = THIS_MODULE;
-       rcdev->nr_resets = 32;
-       rcdev->ops = &ox820_reset_ops;
-       rcdev->of_node = pdev->dev.of_node;
-       reset_controller_register(rcdev);
-       platform_set_drvdata(pdev, rcdev);
-
-       return 0;
-}
-
-static int ox820_reset_remove(struct platform_device *pdev)
-{
-       struct reset_controller_dev *rcdev = platform_get_drvdata(pdev);
-
-       reset_controller_unregister(rcdev);
-
-       return 0;
-}
-
-static struct platform_driver ox820_reset_driver = {
-       .probe  = ox820_reset_probe,
-       .remove = ox820_reset_remove,
-       .driver = {
-               .name           = "ox820-reset",
-               .owner          = THIS_MODULE,
-               .of_match_table = ox820_reset_dt_ids,
-       },
-};
-
-static int __init ox820_reset_init(void)
-{
-       return platform_driver_probe(&ox820_reset_driver,
-                                    ox820_reset_probe);
-}
-/*
- * reset controller does not support probe deferral, so it has to be
- * initialized before any user, in particular, PCIE uses subsys_initcall.
- */
-arch_initcall(ox820_reset_init);
-
-MODULE_AUTHOR("Ma Haijun");
-MODULE_LICENSE("GPL");
index 15578a3..79c4fa3 100644 (file)
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <linux/mfd/syscon.h>
 #include <linux/usb.h>
 #include <linux/usb/hcd.h>
 #include <linux/dma-mapping.h>
 #include <linux/clk.h>
+#include <linux/regmap.h>
 #include <linux/reset.h>
-#include <mach/hardware.h>
-#include <mach/utils.h>
+
+#define USBHSMPH_CTRL_REGOFFSET                0x40
+#define USBHSMPH_STAT_REGOFFSET                0x44
+#define REF300_DIV_REGOFFSET           0xF8
+#define USBHSPHY_CTRL_REGOFFSET                0x84
+#define USB_CTRL_REGOFFSET             0x90
+#define PLLB_DIV_CTRL_REGOFFSET                0x1000F8
+#define USBHSPHY_SUSPENDM_MANUAL_ENABLE                16
+#define USBHSPHY_SUSPENDM_MANUAL_STATE         15
+#define USBHSPHY_ATE_ESET                      14
+#define USBHSPHY_TEST_DIN                      6
+#define USBHSPHY_TEST_ADD                      2
+#define USBHSPHY_TEST_DOUT_SEL                 1
+#define USBHSPHY_TEST_CLK                      0
+
+#define USB_CTRL_USBAPHY_CKSEL_SHIFT   5
+#define USB_CLK_XTAL0_XTAL1            (0 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
+#define USB_CLK_XTAL0                  (1 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
+#define USB_CLK_INTERNAL               (2 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
+
+#define USBAMUX_DEVICE                 BIT(4)
+
+#define USBPHY_REFCLKDIV_SHIFT         2
+#define USB_PHY_REF_12MHZ              (0 << USBPHY_REFCLKDIV_SHIFT)
+#define USB_PHY_REF_24MHZ              (1 << USBPHY_REFCLKDIV_SHIFT)
+#define USB_PHY_REF_48MHZ              (2 << USBPHY_REFCLKDIV_SHIFT)
+
+#define USB_CTRL_USB_CKO_SEL_BIT       0
+
+#define USB_INT_CLK_XTAL               0
+#define USB_INT_CLK_REF300             2
+#define USB_INT_CLK_PLLB               3
+
+#define REF300_DIV_INT_SHIFT            8
+#define REF300_DIV_FRAC_SHIFT           0
+#define REF300_DIV_INT(val)             ((val) << REF300_DIV_INT_SHIFT)
+#define REF300_DIV_FRAC(val)            ((val) << REF300_DIV_FRAC_SHIFT)
+
+#define PLLB_BYPASS                     1
+#define PLLB_ENSAT                      3
+#define PLLB_OUTDIV                     4
+#define PLLB_REFDIV                     8
+#define PLLB_DIV_INT_SHIFT              8
+#define PLLB_DIV_FRAC_SHIFT             0
+#define PLLB_DIV_INT(val)               ((val) << PLLB_DIV_INT_SHIFT)
+#define PLLB_DIV_FRAC(val)              ((val) << PLLB_DIV_FRAC_SHIFT)
 
 #include "ehci.h"
 
@@ -33,6 +79,7 @@ struct oxnas_hcd {
        struct reset_control *rst_host;
        struct reset_control *rst_phya;
        struct reset_control *rst_phyb;
+       struct regmap *syscon;
 };
 
 #define DRIVER_DESC "Oxnas On-Chip EHCI Host Controller"
@@ -41,21 +88,16 @@ static struct hc_driver __read_mostly oxnas_hc_driver;
 
 static void start_oxnas_usb_ehci(struct oxnas_hcd *oxnas)
 {
-       u32 reg;
-
        if (oxnas->use_pllb) {
                /* enable pllb */
                clk_prepare_enable(oxnas->refsrc);
                /* enable ref600 */
                clk_prepare_enable(oxnas->phyref);
                /* 600MHz pllb divider for 12MHz */
-               writel(PLLB_DIV_INT(50) | PLLB_DIV_FRAC(0),
-                       SEC_CTRL_PLLB_DIV_CTRL);
-
+               regmap_write_bits(oxnas->syscon, PLLB_DIV_CTRL_REGOFFSET, 0xffff, PLLB_DIV_INT(50) | PLLB_DIV_FRAC(0));
        } else {
                /* ref 300 divider for 12MHz */
-               writel(REF300_DIV_INT(25) | REF300_DIV_FRAC(0),
-                       SYS_CTRL_REF300_DIV);
+               regmap_write_bits(oxnas->syscon, REF300_DIV_REGOFFSET, 0xffff, REF300_DIV_INT(25) | REF300_DIV_FRAC(0));
        }
 
        /* Ensure the USB block is properly reset */
@@ -65,31 +107,34 @@ static void start_oxnas_usb_ehci(struct oxnas_hcd *oxnas)
 
        /* Force the high speed clock to be generated all the time, via serial
         programming of the USB HS PHY */
-       writel((2UL << USBHSPHY_TEST_ADD) |
-                  (0xe0UL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
+       regmap_write_bits(oxnas->syscon, USBHSPHY_CTRL_REGOFFSET, 0xffff,
+                         (2UL << USBHSPHY_TEST_ADD) |
+                         (0xe0UL << USBHSPHY_TEST_DIN));
 
-       writel((1UL << USBHSPHY_TEST_CLK) |
-                  (2UL << USBHSPHY_TEST_ADD) |
-                  (0xe0UL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
+       regmap_write_bits(oxnas->syscon, USBHSPHY_CTRL_REGOFFSET, 0xffff,
+                         (1UL << USBHSPHY_TEST_CLK) |
+                         (2UL << USBHSPHY_TEST_ADD) |
+                         (0xe0UL << USBHSPHY_TEST_DIN));
 
-       writel((0xfUL << USBHSPHY_TEST_ADD) |
-                  (0xaaUL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
+       regmap_write_bits(oxnas->syscon, USBHSPHY_CTRL_REGOFFSET, 0xffff,
+                         (0xfUL << USBHSPHY_TEST_ADD) |
+                         (0xaaUL << USBHSPHY_TEST_DIN));
 
-       writel((1UL << USBHSPHY_TEST_CLK) |
-                  (0xfUL << USBHSPHY_TEST_ADD) |
-                  (0xaaUL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
+       regmap_write_bits(oxnas->syscon, USBHSPHY_CTRL_REGOFFSET, 0xffff,
+                         (1UL << USBHSPHY_TEST_CLK) |
+                         (0xfUL << USBHSPHY_TEST_ADD) |
+                         (0xaaUL << USBHSPHY_TEST_DIN));
 
        if (oxnas->use_pllb) /* use pllb clock */
-               writel(USB_CLK_INTERNAL | USB_INT_CLK_PLLB, SYS_CTRL_USB_CTRL);
+               regmap_write_bits(oxnas->syscon, USB_CTRL_REGOFFSET, 0xffff,
+                                 USB_CLK_INTERNAL | USB_INT_CLK_PLLB);
        else /* use ref300 derived clock */
-               writel(USB_CLK_INTERNAL | USB_INT_CLK_REF300,
-                       SYS_CTRL_USB_CTRL);
+               regmap_write_bits(oxnas->syscon, USB_CTRL_REGOFFSET, 0xffff,
+                                 USB_CLK_INTERNAL | USB_INT_CLK_REF300);
 
        if (oxnas->use_phya) {
                /* Configure USB PHYA as a host */
-               reg = readl(SYS_CTRL_USB_CTRL);
-               reg &= ~USBAMUX_DEVICE;
-               writel(reg, SYS_CTRL_USB_CTRL);
+               regmap_update_bits(oxnas->syscon, USB_CTRL_REGOFFSET, USBAMUX_DEVICE, 0);
        }
 
        /* Enable the clock to the USB block */
@@ -172,8 +217,14 @@ static int ehci_oxnas_drv_probe(struct platform_device *ofdev)
 
        oxnas = (struct oxnas_hcd *)hcd_to_ehci(hcd)->priv;
 
-       oxnas->use_pllb = of_property_read_bool(np, "plxtech,ehci_use_pllb");
-       oxnas->use_phya = of_property_read_bool(np, "plxtech,ehci_use_phya");
+       oxnas->use_pllb = of_property_read_bool(np, "oxsemi,ehci_use_pllb");
+       oxnas->use_phya = of_property_read_bool(np, "oxsemi,ehci_use_phya");
+
+       oxnas->syscon = syscon_regmap_lookup_by_phandle(np, "oxsemi,sys-ctrl");
+       if (IS_ERR(oxnas->syscon)) {
+               err = PTR_ERR(oxnas->syscon);
+               goto err_syscon;
+       }
 
        oxnas->clk = of_clk_get_by_name(np, "usb");
        if (IS_ERR(oxnas->clk)) {
@@ -249,6 +300,7 @@ err_phyref:
                clk_put(oxnas->refsrc);
 err_refsrc:
        clk_put(oxnas->clk);
+err_syscon:
 err_clk:
 err_ioremap:
 err_res:
index bfa0f0c..644c2b8 100644 (file)
-#
-# Copyright (C) 2013-2016 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
 include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/image.mk
 
-UBIFS_OPTS = -m 2048 -e 126KiB -c 4096
-
-DEVICE_VARS += DTS UBIFS_OPTS
-
-KERNEL_LOADADDR := 0x60008000
-
-define Build/ubootable
-       (dd if="$(STAGING_DIR_IMAGE)/u-boot.bin" bs=128k conv=sync; \
-        dd if="$@" bs=128k conv=sync ) >> $@.new
-       @mv "$@.new" "$@"
-endef
-
-define Device/Default
-  KERNEL_DEPENDS = $$(wildcard $$(DTS_DIR)/ox820-$$(DTS).dts)
-  KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/ox820-$$(DTS).dtb
-  KERNEL_NAME := zImage
-  KERNEL_SUFFIX := -uImage
-  KERNEL_INSTALL := 1
-  KERNEL_INITRAMFS = kernel-bin | lzma | fit lzma $$(DTS_DIR)/ox820-$$(DTS).dtb | ubootable
-  KERNEL_INITRAMFS_PREFIX = $$(IMAGE_PREFIX)-u-boot-initramfs
-  KERNEL_INITRAMFS_SUFFIX := .bin
-  BLOCKSIZE := 128k
-  PAGESIZE := 2048
-  SUBPAGESIZE := 512
-  FILESYSTEMS := squashfs ubifs
-  PROFILES = Default $$(DTS)
-  IMAGES := ubinized.bin sysupgrade.tar
-  IMAGE/ubinized.bin := append-ubi
-  IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata
-  KERNEL_IN_UBI := 1
-  UBOOTENV_IN_UBI := 1
-endef
-
-define Device/akitio
-  DTS := akitio
-  DEVICE_TITLE := Akitio MyCloud mini / Silverstone DC01
-  DEVICE_PACKAGES := kmod-i2c-gpio kmod-rtc-ds1307
-endef
-TARGET_DEVICES += akitio
-
-define Build/omninas-factory
-       rm -rf $@.tmp $@.dummy $@.dummy.gz
-       mkdir -p $@.tmp
-       $(CP) $@ $@.tmp/uImage
-       dd if=/dev/zero bs=64k count=4 of=$@.dummy
-       gzip $@.dummy
-       mkimage -A arm -T ramdisk -C gzip -n "dummy" \
-               -d $@.dummy.gz \
-               $@.tmp/rdimg.gz
-       echo 2.35.20140102 > $@.tmp/version ; echo >> $@.tmp/version
-       chmod 0744 $@.tmp/*
-       $(TAR) -C $@.tmp -czvf $@ \
-               $(if $(SOURCE_DATE_EPOCH),--mtime="@$(SOURCE_DATE_EPOCH)") .
-endef
-
-define Build/encrypt-3des
-       openssl enc -des3 -a -k $(1) -in $@ -out $@.new && mv $@.new $@
-endef
-
-define Device/kd20
-  DEVICE_DTS := ox820-kd20
-  DEVICE_TITLE := Shuttle KD20
-  KERNEL := kernel-bin | append-dtb | uImage none
-  KERNEL_INITRAMFS_PREFIX = $$(IMAGE_PREFIX)-factory
-  KERNEL_INITRAMFS_SUFFIX := .tar.gz
-  KERNEL_INITRAMFS = kernel-bin | append-dtb | uImage none | omninas-factory | encrypt-3des sohmuntitnlaes
-  KERNEL_IMAGE := zImage
-  DEVICE_PACKAGES := kmod-usb3 kmod-i2c-gpio kmod-rtc-pcf8563 kmod-gpio-beeper \
-                     kmod-hwmon-core kmod-hwmon-gpiofan \
-                     kmod-md-mod kmod-md-raid0 kmod-md-raid1 kmod-fs-ext4 kmod-fs-xfs
-  KERNEL_IN_UBI := 
-  UBOOTENV_IN_UBI := 
-endef
-TARGET_DEVICES += kd20
-
-define Device/pogoplug-pro
-  DTS := pogoplug-pro
-  DEVICE_TITLE := Cloud Engines Pogoplug Pro (with mPCIe)
-endef
-TARGET_DEVICES += pogoplug-pro
-
-define Device/pogoplug-v3
-  DTS := pogoplug-v3
-  DEVICE_TITLE := Cloud Engines Pogoplug V3 (no mPCIe)
-endef
-TARGET_DEVICES += pogoplug-v3
-
-define Device/stg212
-  DTS := stg212
-  DEVICE_TITLE := MitraStar STG-212
-endef
-TARGET_DEVICES += stg212
-
 VMLINUX:=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux
 UIMAGE:=$(BIN_DIR)/$(IMG_PREFIX)-uImage
 
+ifeq ($(SUBTARGET),ox810se)
+include ox810se.mk
+endif
+
+ifeq ($(SUBTARGET),ox820)
+include ox820.mk
+endif
+
 $(eval $(call BuildImage))
diff --git a/target/linux/oxnas/image/ox810se.mk b/target/linux/oxnas/image/ox810se.mk
new file mode 100644 (file)
index 0000000..52170a2
--- /dev/null
@@ -0,0 +1,18 @@
+KERNEL_LOADADDR := 0x48008000
+
+define Device/Default
+  KERNEL_NAME := zImage
+  KERNEL_SUFFIX := -uImage
+  KERNEL_INSTALL := 1
+  FILESYSTEMS := squashfs ext4
+  PROFILES = Default $$(DTS)
+  IMAGES := sysupgrade.tar
+  IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata
+endef
+
+define Device/wd-mbwe
+  DEVICE_DTS := ox810se-wd-mbwe
+  DEVICE_TITLE := Western Digital My Book World Edition
+  KERNEL := kernel-bin | append-dtb | uImage none
+endef
+TARGET_DEVICES += wd-mbwe
diff --git a/target/linux/oxnas/image/ox820.mk b/target/linux/oxnas/image/ox820.mk
new file mode 100644 (file)
index 0000000..9d41270
--- /dev/null
@@ -0,0 +1,81 @@
+UBIFS_OPTS = -m 2048 -e 126KiB -c 4096
+DEVICE_VARS += DTS UBIFS_OPTS
+KERNEL_LOADADDR := 0x60008000
+
+define Device/Default
+  KERNEL_NAME := zImage
+  KERNEL_SUFFIX := -uImage
+  KERNEL_INSTALL := 1
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  SUBPAGESIZE := 512
+  FILESYSTEMS := squashfs ubifs
+  PROFILES = Default $$(DTS)
+  KERNEL := kernel-bin | append-dtb | uImage none
+  IMAGES := ubinized.bin sysupgrade.tar
+  IMAGE/ubinized.bin := append-ubi
+  IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata
+endef
+
+define Build/omninas-factory
+       rm -rf $@.tmp $@.dummy $@.dummy.gz
+       mkdir -p $@.tmp
+       $(CP) $@ $@.tmp/uImage
+       dd if=/dev/zero bs=64k count=4 of=$@.dummy
+       gzip $@.dummy
+       mkimage -A arm -T ramdisk -C gzip -n "dummy" \
+               -d $@.dummy.gz \
+               $@.tmp/rdimg.gz
+       echo 2.35.20140102 > $@.tmp/version ; echo >> $@.tmp/version
+       chmod 0744 $@.tmp/*
+       $(TAR) -C $@.tmp -czvf $@ \
+               $(if $(SOURCE_DATE_EPOCH),--mtime="@$(SOURCE_DATE_EPOCH)") .
+endef
+
+define Build/encrypt-3des
+       openssl enc -des3 -a -k $(1) -in $@ -out $@.new && mv $@.new $@
+endef
+
+define Device/akitio-mycloud
+  DEVICE_DTS := ox820-akitio-mycloud
+  DEVICE_TITLE := Akition myCloud (mini) / SilverStone DC01
+  DEVICE_PACKAGES := kmod-usb2-oxnas kmod-ata-oxnas-sata kmod-ledtrig-usbdev \
+                     kmod-i2c-gpio kmod-rtc-ds1307
+endef
+TARGET_DEVICES += akitio-mycloud
+
+define Device/cloudengines-pogoplug-pro
+  DEVICE_DTS := ox820-cloudengines-pogoplug-pro
+  DEVICE_TITLE := Cloud Engines PogoPlug Pro (with mPCIe)
+  DEVICE_PACKAGES := kmod-usb2-oxnas kmod-ledtrig-usbdev
+endef
+TARGET_DEVICES += cloudengines-pogoplug-pro
+
+define Device/cloudengines-pogoplug-series-3
+  DEVICE_DTS := ox820-cloudengines-pogoplug-series-3
+  DEVICE_TITLE := Cloud Engines PogoPlug Series V3 (without mPCIe)
+  DEVICE_PACKAGES := kmod-usb2-oxnas kmod-ledtrig-usbdev
+endef
+TARGET_DEVICES += cloudengines-pogoplug-series-3
+
+define Device/shuttle-kd20
+  DEVICE_DTS := ox820-shuttle-kd20
+  DEVICE_TITLE := Shuttle KD20
+  KERNEL := kernel-bin | append-dtb | uImage none
+  KERNEL_INITRAMFS_PREFIX = $$(IMAGE_PREFIX)-factory
+  KERNEL_INITRAMFS_SUFFIX := .tar.gz
+  KERNEL_INITRAMFS = kernel-bin | append-dtb | uImage none | omninas-factory | encrypt-3des sohmuntitnlaes
+  DEVICE_PACKAGES := kmod-usb2-oxnas kmod-ata-oxnas-sata kmod-ledtrig-usbdev \
+                     kmod-usb3 kmod-i2c-gpio kmod-rtc-pcf8563 kmod-gpio-beeper \
+                     kmod-hwmon-core kmod-hwmon-gpiofan \
+                     kmod-md-mod kmod-md-raid0 kmod-md-raid1 kmod-fs-ext4 kmod-fs-xfs
+endef
+TARGET_DEVICES += shuttle-kd20
+
+define Device/mitrastar-stg212
+  DEVICE_DTS := ox820-mitrastar-stg212
+  DEVICE_TITLE := MitraStar STG-212
+  KERNEL := kernel-bin | append-dtb | uImage none
+  DEVICE_PACKAGES := kmod-usb2-oxnas kmod-ata-oxnas-sata kmod-ledtrig-usbdev
+endef
+TARGET_DEVICES += mitrastar-stg212
index 7016398..e7c9595 100644 (file)
@@ -1,11 +1,3 @@
-#
-# Copyright (C) 2006-2014 OpenWrt.org
-# Copyright (C) 2016 LEDE project
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
 define KernelPackage/ata-oxnas-sata
   SUBMENU:=$(BLOCK_MENU)
   TITLE:=oxnas Serial ATA support
@@ -17,7 +9,7 @@ define KernelPackage/ata-oxnas-sata
 endef
 
 define KernelPackage/ata-oxnas-sata/description
- SATA support for OX934 core found in the OX82x/PLX782x SoCs
+ SATA support for OX934 core found in the OX8xx/PLX782x SoCs
 endef
 
 $(eval $(call KernelPackage,ata-oxnas-sata))
@@ -25,8 +17,8 @@ $(eval $(call KernelPackage,ata-oxnas-sata))
 
 define KernelPackage/usb2-oxnas
   SUBMENU:=$(BLOCK_MENU)
-  TITLE:=OXNAS USB controller driver
-  DEPENDS:=@TARGET_oxnas +kmod-usb2
+  TITLE:=OX820 EHCI driver
+  DEPENDS:=@TARGET_oxnas_ox820 +kmod-usb2
   KCONFIG:=CONFIG_USB_EHCI_OXNAS
   FILES:=$(LINUX_DIR)/drivers/usb/host/ehci-oxnas.ko
   AUTOLOAD:=$(call AutoLoad,55,ehci-oxnas,1)
@@ -35,7 +27,7 @@ endef
 
 define KernelPackage/usb2-oxnas/description
  This driver provides USB Device Controller support for the
- EHCI USB host built-in to the PLXTECH NAS782x SoC
+ EHCI USB host built-in to the OX820 SoC.
 endef
 
 $(eval $(call KernelPackage,usb2-oxnas))
diff --git a/target/linux/oxnas/ox810se/config-default b/target/linux/oxnas/ox810se/config-default
new file mode 100644 (file)
index 0000000..e8257ce
--- /dev/null
@@ -0,0 +1,39 @@
+CONFIG_ARCH_MULTI_CPU_AUTO=y
+# CONFIG_ARCH_MULTI_V4 is not set
+# CONFIG_ARCH_MULTI_V4T is not set
+CONFIG_ARCH_MULTI_V4_V5=y
+CONFIG_ARCH_MULTI_V5=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_ARM926T=y
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_IDLE=y
+# CONFIG_CPU_IDLE_GOV_LADDER is not set
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_USE_DOMAINS=y
+# CONFIG_DEBUG_LL is not set
+# CONFIG_DEBUG_UNCOMPRESS is not set
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_MACH_OX810SE=y
+CONFIG_NEED_KUSER_HELPERS=y
+CONFIG_NEED_PER_CPU_KM=y
+# CONFIG_RCU_EXPERT is not set
+# CONFIG_RCU_NEED_SEGCBLIST is not set
+# CONFIG_RCU_STALL_COMMON is not set
+CONFIG_SPLIT_PTLOCK_CPUS=999999
+CONFIG_TINY_SRCU=y
+CONFIG_EXT4_FS=y
+CONFIG_FAT_FS=y
+CONFIG_FS_MBCACHE=y
diff --git a/target/linux/oxnas/ox810se/profiles/00-default.mk b/target/linux/oxnas/ox810se/profiles/00-default.mk
new file mode 100644 (file)
index 0000000..275a9e1
--- /dev/null
@@ -0,0 +1,10 @@
+define Profile/Default
+       NAME:=Default Profile
+       PRIORITY:=1
+endef
+
+define Profile/Default/Description
+       Default package set compatible with most boards.
+endef
+
+$(eval $(call Profile,Default))
diff --git a/target/linux/oxnas/ox810se/target.mk b/target/linux/oxnas/ox810se/target.mk
new file mode 100644 (file)
index 0000000..4031fc5
--- /dev/null
@@ -0,0 +1,9 @@
+FEATURES+=source-only
+
+SUBTARGET:=ox810se
+BOARDNAME:=OX810SE
+CPU_TYPE:=arm926ej-s
+
+define Target/Description
+    Oxford OX810SE
+endef
diff --git a/target/linux/oxnas/ox820/config-default b/target/linux/oxnas/ox820/config-default
new file mode 100644 (file)
index 0000000..47cd89d
--- /dev/null
@@ -0,0 +1,106 @@
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+# CONFIG_ARCH_MULTI_CPU_AUTO is not set
+CONFIG_ARCH_MULTI_V6=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HEAVY_MB=y
+CONFIG_CACHE_L2X0=y
+# CONFIG_CACHE_L2X0_PMU is not set
+CONFIG_CPU_32v6=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_ABRT_EV6=y
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_HAS_ASID=y
+# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_IDLE=y
+# CONFIG_CPU_IDLE_GOV_LADDER is not set
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_PABRT_V6=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_V6K=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
+CONFIG_DEBUG_LL_UART_8250=y
+# CONFIG_DEBUG_UART_8250 is not set
+# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set
+CONFIG_DEBUG_UART_8250_SHIFT=0
+CONFIG_DEBUG_UART_PHYS=0x44200000
+CONFIG_DEBUG_UART_VIRT=0xf4200000
+CONFIG_DEBUG_UNCOMPRESS=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress-ox820.h"
+CONFIG_DMA_CACHE_RWFO=y
+CONFIG_FIXED_PHY=y
+CONFIG_FORCE_MAX_ZONEORDER=12
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_HAVE_ARM_SCU=y
+CONFIG_HAVE_ARM_TWD=y
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+CONFIG_HAVE_SMP=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_MACH_OX820=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGHT_HAVE_PCI=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NR_CPUS=16
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+# CONFIG_PL310_ERRATA_588369 is not set
+# CONFIG_PL310_ERRATA_727915 is not set
+# CONFIG_PL310_ERRATA_753970 is not set
+# CONFIG_PL310_ERRATA_769419 is not set
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+# CONFIG_RCU_EXPERT is not set
+CONFIG_RCU_NEED_SEGCBLIST=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_XPS=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_OXNAS=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+# CONFIG_MTD_CFI is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_OXNAS=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+# CONFIG_MTD_UBI_FASTMAP is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_SECURITY=y
+CONFIG_UBIFS_FS_ZLIB=y
+CONFIG_ARCH_WANT_LIBATA_LEDS=y
+CONFIG_ATA_LEDS=y
diff --git a/target/linux/oxnas/ox820/profiles/00-default.mk b/target/linux/oxnas/ox820/profiles/00-default.mk
new file mode 100644 (file)
index 0000000..fedf730
--- /dev/null
@@ -0,0 +1,21 @@
+#
+# Copyright (C) 2016 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+define Profile/Default
+       NAME:=Default Profile
+       PRIORITY:=1
+       PACKAGES:=\
+               kmod-i2c-gpio kmod-gpio-beeper kmod-hwmon-core \
+               kmod-hwmon-gpiofan kmod-rtc-pcf8563 kmod-rtc-ds1307 \
+               kmod-usb3
+endef
+
+define Profile/Default/Description
+       Default package set compatible with most boards.
+endef
+
+$(eval $(call Profile,Default))
diff --git a/target/linux/oxnas/ox820/target.mk b/target/linux/oxnas/ox820/target.mk
new file mode 100644 (file)
index 0000000..7c57458
--- /dev/null
@@ -0,0 +1,12 @@
+SUBTARGET:=ox820
+BOARDNAME:=OX820/NAS782x
+CPU_TYPE:=mpcore
+FEATURES+=nand pci pcie ubifs usb
+
+DEFAULT_PACKAGES += \
+       uboot-oxnas-ox820
+
+
+define Target/Description
+    Oxford/PLXTECH OX820/NAS782x
+endef
\ No newline at end of file
diff --git a/target/linux/oxnas/patches-4.14/0001-ARM-dts-rename-oxnas-dts-files.patch b/target/linux/oxnas/patches-4.14/0001-ARM-dts-rename-oxnas-dts-files.patch
new file mode 100644 (file)
index 0000000..20289b3
--- /dev/null
@@ -0,0 +1,48 @@
+From a9d2b105ccd23e07e3dd99d010a34bd5d1c95b42 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sat, 13 Jan 2018 18:35:59 +0100
+Subject: [PATCH 1/3] ARM: dts: rename oxnas dts files
+
+Other platforms' device-tree files start with a platform prefix, such as
+sun7i-a20-*.dts or at91-*.dts.
+This naming scheme turns out to be handy when using multi-platform build
+systems such as OpenWrt.
+Prepend oxnas files with their platform prefix to comply with the naming
+scheme already used for most other platforms.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+---
+ arch/arm/boot/dts/Makefile                                    | 4 ++--
+ arch/arm/boot/dts/{wd-mbwe.dts => ox810se-wd-mbwe.dts}        | 0
+ ...-series-3.dts => ox820-cloudengines-pogoplug-series-3.dts} | 0
+ 3 files changed, 2 insertions(+), 2 deletions(-)
+ rename arch/arm/boot/dts/{wd-mbwe.dts => ox810se-wd-mbwe.dts} (100%)
+ rename arch/arm/boot/dts/{cloudengines-pogoplug-series-3.dts => ox820-cloudengines-pogoplug-series-3.dts} (100%)
+
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index eff87a344566..1ae23ffa6ff4 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -685,8 +685,8 @@ dtb-$(CONFIG_ARCH_ACTIONS) += \
+ dtb-$(CONFIG_ARCH_PRIMA2) += \
+       prima2-evb.dtb
+ dtb-$(CONFIG_ARCH_OXNAS) += \
+-      wd-mbwe.dtb \
+-      cloudengines-pogoplug-series-3.dtb
++      ox810se-wd-mbwe.dtb \
++      ox820-cloudengines-pogoplug-series-3.dtb
+ dtb-$(CONFIG_ARCH_QCOM) += \
+       qcom-apq8060-dragonboard.dtb \
+       qcom-apq8064-arrow-sd-600eval.dtb \
+diff --git a/arch/arm/boot/dts/wd-mbwe.dts b/arch/arm/boot/dts/ox810se-wd-mbwe.dts
+similarity index 100%
+rename from arch/arm/boot/dts/wd-mbwe.dts
+rename to arch/arm/boot/dts/ox810se-wd-mbwe.dts
+diff --git a/arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
+similarity index 100%
+rename from arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts
+rename to arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
+-- 
+2.17.1
+
diff --git a/target/linux/oxnas/patches-4.14/0002-MAINTAINERS-update-ARM-OXNAS-platform-support-patter.patch b/target/linux/oxnas/patches-4.14/0002-MAINTAINERS-update-ARM-OXNAS-platform-support-patter.patch
new file mode 100644 (file)
index 0000000..66dacab
--- /dev/null
@@ -0,0 +1,39 @@
+From a018141970d80677d2822fef9d391b85bf9cf99f Mon Sep 17 00:00:00 2001
+From: Joe Perches <joe@perches.com>
+Date: Tue, 6 Feb 2018 15:42:33 -0800
+Subject: [PATCH 2/3] MAINTAINERS: update "ARM/OXNAS platform support" patterns
+
+Commit 9e6c62b05c1b ("ARM: dts: rename oxnas dts files") renamed the
+files, update the patterns.
+
+[akpm@linux-foundation.org: crunch into a single globbed term, per Arnd]
+Link: http://lkml.kernel.org/r/b39d779e143b3c0a4e7dff827346e509447e3e8e.1517147485.git.joe@perches.com
+Signed-off-by: Joe Perches <joe@perches.com>
+Reviewed-by: Andrew Morton <akpm@linux-foundation.org>
+Cc: Daniel Golle <daniel@makrotopia.org>
+Cc: Arnd Bergmann <arnd@arndb.de>
+Cc: Neil Armstrong <narmstrong@baylibre.com>
+Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
+Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
+---
+ MAINTAINERS | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 546beb6b0176..6ecdaed0a3ef 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -1677,9 +1677,7 @@ L:       linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+ L:    linux-oxnas@lists.tuxfamily.org (moderated for non-subscribers)
+ S:    Maintained
+ F:    arch/arm/mach-oxnas/
+-F:    arch/arm/boot/dts/ox8*.dtsi
+-F:    arch/arm/boot/dts/wd-mbwe.dts
+-F:    arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts
++F:    arch/arm/boot/dts/ox8*.dts*
+ N:    oxnas
+ ARM/PALM TREO SUPPORT
+-- 
+2.17.1
+
diff --git a/target/linux/oxnas/patches-4.14/0003-ARM-configs-add-OXNAS-v6-defconfig.patch b/target/linux/oxnas/patches-4.14/0003-ARM-configs-add-OXNAS-v6-defconfig.patch
new file mode 100644 (file)
index 0000000..bc4bc36
--- /dev/null
@@ -0,0 +1,117 @@
+From 22c1774af921a1cdb33bd37b44977b5b34ea58d0 Mon Sep 17 00:00:00 2001
+From: Neil Armstrong <narmstrong@baylibre.com>
+Date: Wed, 14 Mar 2018 09:35:44 +0100
+Subject: [PATCH 3/3] ARM: configs: add OXNAS v6 defconfig
+
+This patchs adds the minimal defconfig for the OXNAS ARMv6 SoCs
+including the OX820 SoC and needed minimal configurations.
+
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+---
+ arch/arm/configs/oxnas_v6_defconfig | 93 +++++++++++++++++++++++++++++
+ 1 file changed, 93 insertions(+)
+ create mode 100644 arch/arm/configs/oxnas_v6_defconfig
+
+diff --git a/arch/arm/configs/oxnas_v6_defconfig b/arch/arm/configs/oxnas_v6_defconfig
+new file mode 100644
+index 000000000000..f6ba32c9d173
+--- /dev/null
++++ b/arch/arm/configs/oxnas_v6_defconfig
+@@ -0,0 +1,93 @@
++CONFIG_SYSVIPC=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_CGROUPS=y
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_EMBEDDED=y
++CONFIG_PERF_EVENTS=y
++CONFIG_STRICT_KERNEL_RWX=y
++CONFIG_STRICT_MODULE_RWX=y
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_PARTITION_ADVANCED=y
++CONFIG_CMDLINE_PARTITION=y
++CONFIG_ARCH_MULTI_V6=y
++CONFIG_ARCH_OXNAS=y
++CONFIG_MACH_OX820=y
++CONFIG_SMP=y
++CONFIG_NR_CPUS=16
++CONFIG_CMA=y
++CONFIG_FORCE_MAX_ZONEORDER=12
++CONFIG_SECCOMP=y
++CONFIG_ARM_APPENDED_DTB=y
++CONFIG_ARM_ATAG_DTB_COMPAT=y
++CONFIG_KEXEC=y
++CONFIG_EFI=y
++CONFIG_CPU_IDLE=y
++CONFIG_ARM_CPUIDLE=y
++CONFIG_VFP=y
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_UNIX=y
++CONFIG_INET=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_BOOTP=y
++CONFIG_IP_PNP_RARP=y
++CONFIG_IPV6_ROUTER_PREF=y
++CONFIG_IPV6_OPTIMISTIC_DAD=y
++CONFIG_INET6_AH=m
++CONFIG_INET6_ESP=m
++CONFIG_INET6_IPCOMP=m
++CONFIG_IPV6_MIP6=m
++CONFIG_IPV6_TUNNEL=m
++CONFIG_IPV6_MULTIPLE_TABLES=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_DMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=64
++CONFIG_SIMPLE_PM_BUS=y
++CONFIG_MTD=y
++CONFIG_MTD_CMDLINE_PARTS=y
++CONFIG_MTD_BLOCK=y
++CONFIG_MTD_NAND=y
++CONFIG_MTD_NAND_OXNAS=y
++CONFIG_MTD_UBI=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_SIZE=65536
++CONFIG_NETDEVICES=y
++CONFIG_STMMAC_ETH=y
++CONFIG_REALTEK_PHY=y
++CONFIG_INPUT_EVDEV=y
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_GPIO_GENERIC_PLATFORM=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_CLASS_FLASH=m
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_GPIO=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_ARM_TIMER_SP804=y
++CONFIG_EXT4_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_UBIFS_FS=y
++CONFIG_PSTORE=y
++CONFIG_PSTORE_CONSOLE=y
++CONFIG_PSTORE_PMSG=y
++CONFIG_PSTORE_RAM=y
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_UTF8=y
++CONFIG_PRINTK_TIME=y
++CONFIG_MAGIC_SYSRQ=y
+-- 
+2.17.1
+
diff --git a/target/linux/oxnas/patches-4.14/050-ox820-remove-left-overs.patch b/target/linux/oxnas/patches-4.14/050-ox820-remove-left-overs.patch
new file mode 100644 (file)
index 0000000..6dd3b05
--- /dev/null
@@ -0,0 +1,70 @@
+From 552ed4955c1fee1109bf5ba137dc35a411a1448c Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Fri, 1 Jun 2018 02:41:15 +0200
+Subject: [PATCH] arm: ox820: remove left-overs
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/clk/clk-oxnas.c                  |  2 --
+ include/dt-bindings/clock/oxsemi,ox820.h | 32 +++++++++++-------------
+ 2 files changed, 14 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/clk/clk-oxnas.c b/drivers/clk/clk-oxnas.c
+index e51e0023fc6e..da6af71649de 100644
+--- a/drivers/clk/clk-oxnas.c
++++ b/drivers/clk/clk-oxnas.c
+@@ -40,8 +40,6 @@ struct oxnas_stdclk_data {
+       struct clk_hw_onecell_data *onecell_data;
+       struct clk_oxnas_gate **gates;
+       unsigned int ngates;
+-      struct clk_oxnas_pll **plls;
+-      unsigned int nplls;
+ };
+ /* Regmap offsets */
+diff --git a/include/dt-bindings/clock/oxsemi,ox820.h b/include/dt-bindings/clock/oxsemi,ox820.h
+index f661ecc8d760..35b44ca1b104 100644
+--- a/include/dt-bindings/clock/oxsemi,ox820.h
++++ b/include/dt-bindings/clock/oxsemi,ox820.h
+@@ -17,24 +17,20 @@
+ #ifndef DT_CLOCK_OXSEMI_OX820_H
+ #define DT_CLOCK_OXSEMI_OX820_H
+-/* PLLs */
+-#define CLK_820_PLLA          0
+-#define CLK_820_PLLB          1
+-
+ /* Gate Clocks */
+-#define CLK_820_LEON          2
+-#define CLK_820_DMA_SGDMA     3
+-#define CLK_820_CIPHER                4
+-#define CLK_820_SD            5
+-#define CLK_820_SATA          6
+-#define CLK_820_AUDIO         7
+-#define CLK_820_USBMPH                8
+-#define CLK_820_ETHA          9
+-#define CLK_820_PCIEA         10
+-#define CLK_820_NAND          11
+-#define CLK_820_PCIEB         12
+-#define CLK_820_ETHB          13
+-#define CLK_820_REF600                14
+-#define CLK_820_USBDEV                15
++#define CLK_820_LEON          0
++#define CLK_820_DMA_SGDMA     1
++#define CLK_820_CIPHER                2
++#define CLK_820_SD            3
++#define CLK_820_SATA          4
++#define CLK_820_AUDIO         5
++#define CLK_820_USBMPH                6
++#define CLK_820_ETHA          7
++#define CLK_820_PCIEA         8
++#define CLK_820_NAND          9
++#define CLK_820_PCIEB         10
++#define CLK_820_ETHB          11
++#define CLK_820_REF600                12
++#define CLK_820_USBDEV                13
+ #endif /* DT_CLOCK_OXSEMI_OX820_H */
+-- 
+2.17.1
+
diff --git a/target/linux/oxnas/patches-4.14/100-oxnas-clk-plla-pllb.patch b/target/linux/oxnas/patches-4.14/100-oxnas-clk-plla-pllb.patch
new file mode 100644 (file)
index 0000000..f78ecb2
--- /dev/null
@@ -0,0 +1,273 @@
+--- a/drivers/clk/clk-oxnas.c
++++ b/drivers/clk/clk-oxnas.c
+@@ -16,19 +16,42 @@
+  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
++#include <linux/clk.h>
++#include <linux/clkdev.h>
+ #include <linux/clk-provider.h>
+ #include <linux/kernel.h>
+ #include <linux/init.h>
++#include <linux/delay.h>
+ #include <linux/of.h>
+ #include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ #include <linux/stringify.h>
+ #include <linux/regmap.h>
+ #include <linux/mfd/syscon.h>
++#include <linux/reset.h>
+ #include <dt-bindings/clock/oxsemi,ox810se.h>
+ #include <dt-bindings/clock/oxsemi,ox820.h>
++#define REF300_DIV_INT_SHIFT          8
++#define REF300_DIV_FRAC_SHIFT         0
++#define REF300_DIV_INT(val)           ((val) << REF300_DIV_INT_SHIFT)
++#define REF300_DIV_FRAC(val)          ((val) << REF300_DIV_FRAC_SHIFT)
++
++#define PLLB_BYPASS                   1
++#define PLLB_ENSAT                    3
++#define PLLB_OUTDIV                   4
++#define PLLB_REFDIV                   8
++#define PLLB_DIV_INT_SHIFT            8
++#define PLLB_DIV_FRAC_SHIFT           0
++#define PLLB_DIV_INT(val)             ((val) << PLLB_DIV_INT_SHIFT)
++#define PLLB_DIV_FRAC(val)            ((val) << PLLB_DIV_FRAC_SHIFT)
++
++#define PLLA_REFDIV_MASK              0x3F
++#define PLLA_REFDIV_SHIFT             8
++#define PLLA_OUTDIV_MASK              0x7
++#define PLLA_OUTDIV_SHIFT             4
++
+ /* Standard regmap gate clocks */
+ struct clk_oxnas_gate {
+       struct clk_hw hw;
+@@ -49,6 +70,135 @@ struct oxnas_stdclk_data {
+ #define CLK_SET_REGOFFSET     0x2c
+ #define CLK_CLR_REGOFFSET     0x30
++#define PLLA_CTRL0_REGOFFSET  0x1f0
++#define PLLA_CTRL1_REGOFFSET  0x1f4
++#define PLLB_CTRL0_REGOFFSET  0x1001f0
++#define MHZ (1000 * 1000)
++
++struct clk_oxnas_pll {
++      struct clk_hw hw;
++      struct device_node *devnode;
++      struct reset_control *rstc;
++      struct regmap *syscon;
++};
++
++#define to_clk_oxnas_pll(_hw) container_of(_hw, struct clk_oxnas_pll, hw)
++
++static unsigned long plla_clk_recalc_rate(struct clk_hw *hw,
++      unsigned long parent_rate)
++{
++      struct clk_oxnas_pll *plla = to_clk_oxnas_pll(hw);
++      unsigned long fin = parent_rate;
++      unsigned long refdiv, outdiv;
++      unsigned int pll0, fbdiv;
++
++      BUG_ON(regmap_read(plla->syscon, PLLA_CTRL0_REGOFFSET, &pll0));
++
++      refdiv = (pll0 >> PLLA_REFDIV_SHIFT) & PLLA_REFDIV_MASK;
++      refdiv += 1;
++      outdiv = (pll0 >> PLLA_OUTDIV_SHIFT) & PLLA_OUTDIV_MASK;
++      outdiv += 1;
++
++      BUG_ON(regmap_read(plla->syscon, PLLA_CTRL1_REGOFFSET, &fbdiv));
++      /* seems we will not be here when pll is bypassed, so ignore this
++       * case */
++
++      return fin / MHZ * fbdiv / (refdiv * outdiv) / 32768 * MHZ;
++}
++
++static const char *pll_clk_parents[] = {
++      "oscillator",
++};
++
++static struct clk_ops plla_ops = {
++      .recalc_rate = plla_clk_recalc_rate,
++};
++
++static struct clk_init_data clk_plla_init = {
++      .name = "plla",
++      .ops = &plla_ops,
++      .parent_names = pll_clk_parents,
++      .num_parents = ARRAY_SIZE(pll_clk_parents),
++};
++
++static int pllb_clk_is_prepared(struct clk_hw *hw)
++{
++      struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
++
++      return !!pllb->rstc;
++}
++
++static int pllb_clk_prepare(struct clk_hw *hw)
++{
++      struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
++
++      pllb->rstc = of_reset_control_get(pllb->devnode, NULL);
++
++      return IS_ERR(pllb->rstc) ? PTR_ERR(pllb->rstc) : 0;
++}
++
++static void pllb_clk_unprepare(struct clk_hw *hw)
++{
++      struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
++
++      BUG_ON(IS_ERR(pllb->rstc));
++
++      reset_control_put(pllb->rstc);
++      pllb->rstc = NULL;
++}
++
++static int pllb_clk_enable(struct clk_hw *hw)
++{
++      struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
++
++      BUG_ON(IS_ERR(pllb->rstc));
++
++      /* put PLL into bypass */
++      regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), BIT(PLLB_BYPASS));
++      wmb();
++      udelay(10);
++      reset_control_assert(pllb->rstc);
++      udelay(10);
++      /* set PLL B control information */
++      regmap_write_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, 0xffff,
++                        (1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV));
++      reset_control_deassert(pllb->rstc);
++      udelay(100);
++      regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), 0);
++
++      return 0;
++}
++
++static void pllb_clk_disable(struct clk_hw *hw)
++{
++      struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
++
++      BUG_ON(IS_ERR(pllb->rstc));
++
++      /* put PLL into bypass */
++      regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), BIT(PLLB_BYPASS));
++
++      wmb();
++      udelay(10);
++
++      reset_control_assert(pllb->rstc);
++}
++
++static struct clk_ops pllb_ops = {
++      .prepare = pllb_clk_prepare,
++      .unprepare = pllb_clk_unprepare,
++      .is_prepared = pllb_clk_is_prepared,
++      .enable = pllb_clk_enable,
++      .disable = pllb_clk_disable,
++};
++
++static struct clk_init_data clk_pllb_init = {
++      .name = "pllb",
++      .ops = &pllb_ops,
++      .parent_names = pll_clk_parents,
++      .num_parents = ARRAY_SIZE(pll_clk_parents),
++};
++
+ static inline struct clk_oxnas_gate *to_clk_oxnas_gate(struct clk_hw *hw)
+ {
+       return container_of(hw, struct clk_oxnas_gate, hw);
+@@ -262,3 +412,42 @@ static struct platform_driver oxnas_stdc
+       },
+ };
+ builtin_platform_driver(oxnas_stdclk_driver);
++
++void __init oxnas_init_plla(struct device_node *np)
++{
++      struct clk *clk;
++      struct clk_oxnas_pll *plla;
++
++      plla = kmalloc(sizeof(*plla), GFP_KERNEL);
++      BUG_ON(!plla);
++
++      plla->syscon = syscon_node_to_regmap(of_get_parent(np));
++      plla->hw.init = &clk_plla_init;
++      plla->devnode = np;
++      plla->rstc = NULL;
++      clk = clk_register(NULL, &plla->hw);
++      BUG_ON(IS_ERR(clk));
++      /* mark it as enabled */
++      clk_prepare_enable(clk);
++      of_clk_add_provider(np, of_clk_src_simple_get, clk);
++}
++CLK_OF_DECLARE(oxnas_plla, "plxtech,nas782x-plla", oxnas_init_plla);
++
++void __init oxnas_init_pllb(struct device_node *np)
++{
++      struct clk *clk;
++      struct clk_oxnas_pll *pllb;
++
++      pllb = kmalloc(sizeof(*pllb), GFP_KERNEL);
++      BUG_ON(!pllb);
++
++      pllb->syscon = syscon_node_to_regmap(of_get_parent(np));
++      pllb->hw.init = &clk_pllb_init;
++      pllb->devnode = np;
++      pllb->rstc = NULL;
++
++      clk = clk_register(NULL, &pllb->hw);
++      BUG_ON(IS_ERR(clk));
++      of_clk_add_provider(np, of_clk_src_simple_get, clk);
++}
++CLK_OF_DECLARE(oxnas_pllb, "plxtech,nas782x-pllb", oxnas_init_pllb);
+--- a/arch/arm/boot/dts/ox820.dtsi
++++ b/arch/arm/boot/dts/ox820.dtsi
+@@ -60,12 +60,6 @@
+                       clocks = <&osc>;
+               };
+-              plla: plla {
+-                      compatible = "fixed-clock";
+-                      #clock-cells = <0>;
+-                      clock-frequency = <850000000>;
+-              };
+-
+               armclk: armclk {
+                       compatible = "fixed-factor-clock";
+                       #clock-cells = <0>;
+@@ -265,6 +259,19 @@
+                                       compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk";
+                                       #clock-cells = <1>;
+                               };
++
++                              plla: plla {
++                                      compatible = "plxtech,nas782x-plla";
++                                      #clock-cells = <0>;
++                                      clocks = <&osc>;
++                              };
++
++                              pllb: pllb {
++                                      compatible = "plxtech,nas782x-pllb";
++                                      #clock-cells = <0>;
++                                      clocks = <&osc>;
++                                      resets = <&reset RESET_PLLB>;
++                              };
+                       };
+               };
+@@ -286,6 +293,13 @@
+                               clocks = <&armclk>;
+                       };
++                      watchdog@620 {
++                              compatible = "mpcore_wdt";
++                              reg = <0x620 0x20>;
++                              interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3)|IRQ_TYPE_LEVEL_HIGH)>;
++                              clocks = <&armclk>;
++                      };
++
+                       gic: gic@1000 {
+                               compatible = "arm,arm11mp-gic";
+                               interrupt-controller;
diff --git a/target/linux/oxnas/patches-4.14/340-oxnas-pcie.patch b/target/linux/oxnas/patches-4.14/340-oxnas-pcie.patch
new file mode 100644 (file)
index 0000000..b1ae62b
--- /dev/null
@@ -0,0 +1,108 @@
+--- a/drivers/pci/host/Kconfig
++++ b/drivers/pci/host/Kconfig
+@@ -220,4 +220,9 @@ config VMD
+         To compile this driver as a module, choose M here: the
+         module will be called vmd.
++config PCIE_OXNAS
++      bool "PLX Oxnas PCIe controller"
++      depends on ARCH_OXNAS
++      select PCIEPORTBUS
++
+ endmenu
+--- a/drivers/pci/host/Makefile
++++ b/drivers/pci/host/Makefile
+@@ -20,6 +20,7 @@ obj-$(CONFIG_PCIE_ALTERA) += pcie-altera
+ obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
+ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
+ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
++obj-$(CONFIG_PCIE_OXNAS) += pcie-oxnas.o
+ obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
+ obj-$(CONFIG_VMD) += vmd.o
+--- a/arch/arm/boot/dts/ox820.dtsi
++++ b/arch/arm/boot/dts/ox820.dtsi
+@@ -302,6 +302,83 @@
+                               reg = <0x1000 0x1000>,
+                                     <0x100 0x500>;
+                       };
++
++                      pcie0: pcie-controller@c00000 {
++                              compatible = "plxtech,nas782x-pcie";
++                              device_type = "pci";
++                              #address-cells = <3>;
++                              #size-cells = <2>;
++
++                              /*              flag & space    bus address     host address    size */
++                              ranges = <      0x82000000      0 0x48000000    0x48000000      0 0x2000000
++                                              0xC2000000      0 0x4A000000    0x4A000000      0 0x1E00000
++                                              0x81000000      0 0x4BE00000    0x4BE00000      0 0x0100000
++                                              0x80000000      0 0x4BF00000    0x4BF00000      0 0x0100000>;
++
++                              bus-range = <0x00 0x7f>;
++
++                              /*      cfg                     inbound translator      phy*/
++                              reg =   <0x47C00000 0x1000>,    <0x47D00000 0x100>,      <0x44A00000 0x10>;
++
++                              #interrupt-cells = <1>;
++                              /* wild card mask, match all bus address & interrupt specifier */
++                              /* format: bus address mask, interrupt specifier mask */
++                              /* each bit 1 means need match, 0 means ignored when match */
++                              interrupt-map-mask = <0 0 0 0>;
++                              /* format: a list of: bus address, interrupt specifier,
++                               * parent interrupt controller & specifier */
++                              interrupt-map = <0 0 0 0 &gic 0 19 0x304>;
++
++                              gpios = <&gpio1 12 0>;
++                              clocks = <&stdclk CLK_820_PCIEA>, <&pllb>;
++                              clock-names = "pcie", "busclk";
++                              resets = <&reset RESET_PCIEA>, <&reset RESET_PCIEPHY>;
++                              reset-names = "pcie", "phy";
++
++                              plxtech,pcie-hcsl-bit = <2>;
++                              plxtech,pcie-ctrl-offset = <0x120>;
++                              plxtech,pcie-outbound-offset = <0x138>;
++                              status = "disabled";
++                      };
++
++                      pcie1: pcie-controller@e00000 {
++                              compatible = "plxtech,nas782x-pcie";
++                              device_type = "pci";
++                              #address-cells = <3>;
++                              #size-cells = <2>;
++
++                              /*              flag & space    bus address     host address    size */
++                              ranges = <      0x82000000      0 0x4C000000    0x4C000000      0 0x2000000
++                                              0xC2000000      0 0x4E000000    0x4E000000      0 0x1E00000
++                                              0x81000000      0 0x4FE00000    0x4FE00000      0 0x0100000
++                                              0x80000000      0 0x4FF00000    0x4FF00000      0 0x0100000>;
++
++                              bus-range = <0x80 0xff>;
++
++                              /*      cfg                     inbound translator      phy*/
++                              reg =   <0x47E00000 0x1000>,    <0x47F00000 0x100>,     <0x44A00000 0x10>;
++
++                              #interrupt-cells = <1>;
++                              /* wild card mask, match all bus address & interrupt specifier */
++                              /* format: bus address mask, interrupt specifier mask */
++                              /* each bit 1 means need match, 0 means ignored when match */
++                              interrupt-map-mask = <0 0 0 0>;
++                              /* format: a list of: bus address, interrupt specifier,
++                               * parent interrupt controller & specifier */
++                              interrupt-map = <0 0 0 0 &gic 0 20 0x304>;
++
++                              /* gpios = <&gpio1 12 0>; */
++                              clocks = <&stdclk CLK_820_PCIEB>, <&pllb>;
++                              clock-names = "pcie", "busclk";
++                              resets = <&reset RESET_PCIEB>, <&reset RESET_PCIEPHY>;
++                              reset-names = "pcie", "phy";
++
++                              plxtech,pcie-hcsl-bit = <3>;
++                              plxtech,pcie-ctrl-offset = <0x124>;
++                              plxtech,pcie-outbound-offset = <0x174>;
++                              status = "disabled";
++                      };
++
+               };
+       };
+ };
diff --git a/target/linux/oxnas/patches-4.14/500-oxnas-sata.patch b/target/linux/oxnas/patches-4.14/500-oxnas-sata.patch
new file mode 100644 (file)
index 0000000..3825ef0
--- /dev/null
@@ -0,0 +1,49 @@
+--- a/drivers/ata/Kconfig
++++ b/drivers/ata/Kconfig
+@@ -492,6 +492,13 @@ config SATA_VITESSE
+         If unsure, say N.
++config SATA_OXNAS
++      tristate "PLXTECH NAS782X SATA support"
++      help
++        This option enables support for Nas782x Serial ATA controller.
++
++        If unsure, say N.
++
+ comment "PATA SFF controllers with BMDMA"
+ config PATA_ALI
+--- a/drivers/ata/Makefile
++++ b/drivers/ata/Makefile
+@@ -46,6 +46,7 @@ obj-$(CONFIG_SATA_SVW)               += sata_svw.o
+ obj-$(CONFIG_SATA_ULI)                += sata_uli.o
+ obj-$(CONFIG_SATA_VIA)                += sata_via.o
+ obj-$(CONFIG_SATA_VITESSE)    += sata_vsc.o
++obj-$(CONFIG_SATA_OXNAS)      += sata_oxnas.o
+ # SFF PATA w/ BMDMA
+ obj-$(CONFIG_PATA_ALI)                += pata_ali.o
+--- a/arch/arm/boot/dts/ox820.dtsi
++++ b/arch/arm/boot/dts/ox820.dtsi
+@@ -380,5 +380,20 @@
+                       };
+               };
++
++              sata: sata@45900000 {
++                      compatible = "plxtech,nas782x-sata";
++                              /*      ports           dmactl          sgdma   */
++                      reg = <0x45900000 0x20000>, <0x459A0000 0x40>, <0x459B0000 0x20>,
++                              /*      core            phy             descriptors (optional)  */
++                              <0x459E0000 0x2000>, <0x44900000 0x0C>, <0x50000000 0x1000>;
++                      interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&stdclk CLK_820_SATA>;
++                      resets = <&reset RESET_SATA>, <&reset RESET_SATA_LINK>, <&reset RESET_SATA_PHY>;
++                      reset-names = "sata", "link", "phy";
++                      nr-ports = <1>;
++                      status = "disabled";
++              };
++
+       };
+ };
diff --git a/target/linux/oxnas/patches-4.14/510-ox820-libata-leds.patch b/target/linux/oxnas/patches-4.14/510-ox820-libata-leds.patch
new file mode 100644 (file)
index 0000000..7788802
--- /dev/null
@@ -0,0 +1,10 @@
+--- linux-4.14.44.orig/arch/arm/mach-oxnas/Kconfig
++++ linux-4.14.44/arch/arm/mach-oxnas/Kconfig
+@@ -1,6 +1,7 @@
+ menuconfig ARCH_OXNAS
+       bool "Oxford Semiconductor OXNAS Family SoCs"
+       select ARCH_HAS_RESET_CONTROLLER
++      select ARCH_WANT_LIBATA_LEDS
+       select COMMON_CLK_OXNAS
+       select GPIOLIB
+       select MFD_SYSCON
diff --git a/target/linux/oxnas/patches-4.14/800-oxnas-ehci.patch b/target/linux/oxnas/patches-4.14/800-oxnas-ehci.patch
new file mode 100644 (file)
index 0000000..8fd6f69
--- /dev/null
@@ -0,0 +1,51 @@
+--- a/drivers/usb/host/Kconfig
++++ b/drivers/usb/host/Kconfig
+@@ -334,6 +334,13 @@ config USB_OCTEON_EHCI
+         USB 2.0 device support.  All CN6XXX based chips with USB are
+         supported.
++config USB_EHCI_OXNAS
++      tristate "OXNAS EHCI Module"
++      depends on USB_EHCI_HCD && ARCH_OXNAS
++      select USB_EHCI_ROOT_HUB_TT
++      ---help---
++        Enable support for the OX820 SOC's on-chip EHCI controller.
++
+ endif # USB_EHCI_HCD
+ config USB_OXU210HP_HCD
+--- a/drivers/usb/host/Makefile
++++ b/drivers/usb/host/Makefile
+@@ -43,6 +43,7 @@ obj-$(CONFIG_USB_EHCI_HCD_AT91) += ehci-
+ obj-$(CONFIG_USB_EHCI_MSM)    += ehci-msm.o
+ obj-$(CONFIG_USB_EHCI_TEGRA)  += ehci-tegra.o
+ obj-$(CONFIG_USB_W90X900_EHCI)        += ehci-w90x900.o
++obj-$(CONFIG_USB_EHCI_OXNAS)  += ehci-oxnas.o
+ obj-$(CONFIG_USB_OXU210HP_HCD)        += oxu210hp-hcd.o
+ obj-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o
+--- a/arch/arm/boot/dts/ox820.dtsi
++++ b/arch/arm/boot/dts/ox820.dtsi
+@@ -120,6 +120,22 @@
+                       status = "disabled";
+               };
++              ehci: ehci@40200100 {
++                      compatible = "plxtech,nas782x-ehci";
++                      reg = <0x40200100 0xf00>;
++                      interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&stdclk CLK_820_USBMPH>, <&pllb>, <&stdclk CLK_820_REF600>;
++                      clock-names = "usb", "refsrc", "phyref";
++                      resets = <&reset RESET_USBHS>, <&reset RESET_USBPHYA>, <&reset RESET_USBPHYB>;
++                      reset-names = "host", "phya", "phyb";
++                      oxsemi,sys-ctrl = <&sys>;
++                      /* Otherwise ref300 is used, which is derived from sata phy
++                       * in that case, usb depends on sata initialization */
++                      /* FIXME: how to make this dependency explicit ? */
++                      oxsemi,ehci_use_pllb;
++                      status = "disabled";
++              };
++
+               apb-bridge@44000000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
diff --git a/target/linux/oxnas/patches-4.14/996-generic-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/oxnas/patches-4.14/996-generic-Mangle-bootloader-s-kernel-arguments.patch
new file mode 100644 (file)
index 0000000..7a4dce7
--- /dev/null
@@ -0,0 +1,189 @@
+From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001
+From: Adrian Panella <ianchi74@outlook.com>
+Date: Thu, 9 Mar 2017 09:37:17 +0100
+Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments
+
+The command-line arguments provided by the boot loader will be
+appended to a new device tree property: bootloader-args.
+If there is a property "append-rootblock" in DT under /chosen
+and a root= option in bootloaders command line it will be parsed
+and added to DT bootargs with the form: <append-rootblock>XX.
+Only command line ATAG will be processed, the rest of the ATAGs
+sent by bootloader will be ignored.
+This is usefull in dual boot systems, to get the current root partition
+without afecting the rest of the system.
+
+Signed-off-by: Adrian Panella <ianchi74@outlook.com>
+---
+ arch/arm/Kconfig                        | 11 +++++
+ arch/arm/boot/compressed/atags_to_fdt.c | 72 ++++++++++++++++++++++++++++++++-
+ init/main.c                             | 16 ++++++++
+ 3 files changed, 98 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1938,6 +1938,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
+         The command-line arguments provided by the boot loader will be
+         appended to the the device tree bootargs property.
++config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
++      bool "Append rootblock parsing bootloader's kernel arguments"
++      help
++        The command-line arguments provided by the boot loader will be
++        appended to a new device tree property: bootloader-args.
++        If there is a property "append-rootblock" in DT under /chosen 
++        and a root= option in bootloaders command line it will be parsed 
++        and added to DT bootargs with the form: <append-rootblock>XX.
++        Only command line ATAG will be processed, the rest of the ATAGs
++        sent by bootloader will be ignored.
++
+ endchoice
+ config CMDLINE
+--- a/arch/arm/boot/compressed/atags_to_fdt.c
++++ b/arch/arm/boot/compressed/atags_to_fdt.c
+@@ -4,6 +4,8 @@
+ #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
+ #define do_extend_cmdline 1
++#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
++#define do_extend_cmdline 1
+ #else
+ #define do_extend_cmdline 0
+ #endif
+@@ -67,6 +69,59 @@ static uint32_t get_cell_size(const void
+       return cell_size;
+ }
++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
++
++static char *append_rootblock(char *dest, const char *str, int len, void *fdt)
++{
++      char *ptr, *end;
++      char *root="root=";
++      int i, l;
++      const char *rootblock;
++
++      //ARM doesn't have __HAVE_ARCH_STRSTR, so search manually
++      ptr = str - 1;
++
++      do {
++              //first find an 'r' at the begining or after a space
++              do {
++                      ptr++;
++                      ptr = strchr(ptr, 'r');
++                      if(!ptr) return dest;
++
++              } while (ptr != str && *(ptr-1) != ' ');
++
++              //then check for the rest
++              for(i = 1; i <= 4; i++)
++                      if(*(ptr+i) != *(root+i)) break;
++
++      } while (i != 5);
++
++      end = strchr(ptr, ' ');
++      end = end ? (end - 1) : (strchr(ptr, 0) - 1);
++
++      //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX )
++      for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);
++      ptr = end + 1;
++
++      /* if append-rootblock property is set use it to append to command line */
++      rootblock = getprop(fdt, "/chosen", "append-rootblock", &l);
++      if(rootblock != NULL) {
++              if(*dest != ' ') {
++                      *dest = ' ';
++                      dest++;
++                      len++;
++              }
++              if (len + l + i <= COMMAND_LINE_SIZE) {
++                      memcpy(dest, rootblock, l);
++                      dest += l - 1;
++                      memcpy(dest, ptr, i);
++                      dest += i;
++              }
++      }
++      return dest;
++}
++#endif
++
+ static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
+ {
+       char cmdline[COMMAND_LINE_SIZE];
+@@ -86,12 +141,21 @@ static void merge_fdt_bootargs(void *fdt
+       /* and append the ATAG_CMDLINE */
+       if (fdt_cmdline) {
++
++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
++              //save original bootloader args
++              //and append ubi.mtd with root partition number to current cmdline
++              setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline);
++              ptr = append_rootblock(ptr, fdt_cmdline, len, fdt);
++
++#else
+               len = strlen(fdt_cmdline);
+               if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
+                       *ptr++ = ' ';
+                       memcpy(ptr, fdt_cmdline, len);
+                       ptr += len;
+               }
++#endif
+       }
+       *ptr = '\0';
+@@ -148,7 +212,9 @@ int atags_to_fdt(void *atag_list, void *
+                       else
+                               setprop_string(fdt, "/chosen", "bootargs",
+                                              atag->u.cmdline.cmdline);
+-              } else if (atag->hdr.tag == ATAG_MEM) {
++              }
++#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
++              else if (atag->hdr.tag == ATAG_MEM) {
+                       if (memcount >= sizeof(mem_reg_property)/4)
+                               continue;
+                       if (!atag->u.mem.size)
+@@ -187,6 +253,10 @@ int atags_to_fdt(void *atag_list, void *
+               setprop(fdt, "/memory", "reg", mem_reg_property,
+                       4 * memcount * memsize);
+       }
++#else
++
++      }
++#endif
+       return fdt_pack(fdt);
+ }
+--- a/init/main.c
++++ b/init/main.c
+@@ -96,6 +96,10 @@
+ #include <asm/sections.h>
+ #include <asm/cacheflush.h>
++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
++#include <linux/of.h>
++#endif
++
+ static int kernel_init(void *);
+ extern void init_IRQ(void);
+@@ -575,6 +579,18 @@ asmlinkage __visible void __init start_k
+       page_alloc_init();
+       pr_notice("Kernel command line: %s\n", boot_command_line);
++
++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
++      //Show bootloader's original command line for reference
++      if(of_chosen) {
++              const char *prop = of_get_property(of_chosen, "bootloader-args", NULL);
++              if(prop)
++                      pr_notice("Bootloader command line (ignored): %s\n", prop);
++              else
++                      pr_notice("Bootloader command line not present\n");
++      }
++#endif
++
+       parse_early_param();
+       after_dashes = parse_args("Booting kernel",
+                                 static_command_line, __start___param,
diff --git a/target/linux/oxnas/patches-4.14/999-libata-hacks.patch b/target/linux/oxnas/patches-4.14/999-libata-hacks.patch
new file mode 100644 (file)
index 0000000..2a3ba72
--- /dev/null
@@ -0,0 +1,57 @@
+--- a/drivers/ata/libata-core.c
++++ b/drivers/ata/libata-core.c
+@@ -1599,6 +1599,14 @@ unsigned ata_exec_internal_sg(struct ata
+               return AC_ERR_SYSTEM;
+       }
++      if (ap->ops->acquire_hw && !ap->ops->acquire_hw(ap, 0, 0)) {
++              spin_unlock_irqrestore(ap->lock, flags);
++              if (!ap->ops->acquire_hw(ap, 1, (2*HZ))) {
++                      return AC_ERR_TIMEOUT;
++              }
++              spin_lock_irqsave(ap->lock, flags);
++      }
++
+       /* initialize internal qc */
+       /* XXX: Tag 0 is used for drivers with legacy EH as some
+@@ -5096,6 +5104,9 @@ struct ata_queued_cmd *ata_qc_new_init(s
+       if (unlikely(ap->pflags & ATA_PFLAG_FROZEN))
+               return NULL;
++      if (ap->ops->qc_new && ap->ops->qc_new(ap))
++              return NULL;
++
+       /* libsas case */
+       if (ap->flags & ATA_FLAG_SAS_HOST) {
+               tag = ata_sas_allocate_tag(ap);
+@@ -5141,6 +5152,8 @@ void ata_qc_free(struct ata_queued_cmd *
+               qc->tag = ATA_TAG_POISON;
+               if (ap->flags & ATA_FLAG_SAS_HOST)
+                       ata_sas_free_tag(tag, ap);
++              if (ap->ops->qc_free)
++                      ap->ops->qc_free(qc);
+       }
+ }
+--- a/include/linux/libata.h
++++ b/include/linux/libata.h
+@@ -918,6 +918,8 @@ struct ata_port_operations {
+       void (*qc_prep)(struct ata_queued_cmd *qc);
+       unsigned int (*qc_issue)(struct ata_queued_cmd *qc);
+       bool (*qc_fill_rtf)(struct ata_queued_cmd *qc);
++      int (*qc_new)(struct ata_port *ap);
++      void (*qc_free)(struct ata_queued_cmd *qc);
+       /*
+        * Configuration and exception handling
+@@ -1008,6 +1010,9 @@ struct ata_port_operations {
+       void (*phy_reset)(struct ata_port *ap);
+       void (*eng_timeout)(struct ata_port *ap);
++      int (*acquire_hw)(struct ata_port *ap, int may_sleep,
++                        int timeout_jiffies);
++
+       /*
+        * ->inherits must be the last field and all the preceding
+        * fields must be pointers.
diff --git a/target/linux/oxnas/patches-4.4/0072-mtd-backport-v4.7-0day-patches-from-Boris.patch b/target/linux/oxnas/patches-4.4/0072-mtd-backport-v4.7-0day-patches-from-Boris.patch
deleted file mode 100644 (file)
index 204d6e0..0000000
+++ /dev/null
@@ -1,5281 +0,0 @@
-From a369af5149e6eb442b22ce89b564dd7a76e03638 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Tue, 26 Apr 2016 19:05:01 +0200
-Subject: [PATCH 072/102] mtd: backport v4.7-0day patches from Boris
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/mtd/Kconfig                 |    4 +-
- drivers/mtd/cmdlinepart.c           |    3 +-
- drivers/mtd/devices/m25p80.c        |   44 +--
- drivers/mtd/maps/physmap_of.c       |    6 +-
- drivers/mtd/mtdchar.c               |  123 ++++++--
- drivers/mtd/mtdconcat.c             |    2 +-
- drivers/mtd/mtdcore.c               |  428 ++++++++++++++++++++++++--
- drivers/mtd/mtdcore.h               |    7 +-
- drivers/mtd/mtdpart.c               |  161 ++++++----
- drivers/mtd/mtdswap.c               |   24 +-
- drivers/mtd/nand/Kconfig            |   21 +-
- drivers/mtd/nand/Makefile           |    2 +
- drivers/mtd/nand/nand_base.c        |  571 +++++++++++++++++++----------------
- drivers/mtd/nand/nand_bbt.c         |   34 +--
- drivers/mtd/nand/nand_bch.c         |   52 ++--
- drivers/mtd/nand/nand_ecc.c         |    6 +-
- drivers/mtd/nand/nand_ids.c         |    4 +-
- drivers/mtd/nand/nandsim.c          |   43 +--
- drivers/mtd/ofpart.c                |   53 ++--
- drivers/mtd/spi-nor/Kconfig         |   10 +-
- drivers/mtd/spi-nor/Makefile        |    1 +
- drivers/mtd/spi-nor/mtk-quadspi.c   |  485 +++++++++++++++++++++++++++++
- drivers/mtd/spi-nor/spi-nor.c       |  321 +++++++++++++-------
- drivers/mtd/tests/mtd_nandecctest.c |    2 +-
- drivers/mtd/tests/oobtest.c         |   49 ++-
- drivers/mtd/tests/pagetest.c        |    3 +-
- include/linux/mtd/bbm.h             |    1 -
- include/linux/mtd/fsmc.h            |   18 --
- include/linux/mtd/inftl.h           |    1 -
- include/linux/mtd/map.h             |    9 +-
- include/linux/mtd/mtd.h             |   80 ++++-
- include/linux/mtd/nand.h            |   94 ++++--
- include/linux/mtd/nand_bch.h        |   10 +-
- include/linux/mtd/nftl.h            |    1 -
- include/linux/mtd/onenand.h         |    2 -
- include/linux/mtd/partitions.h      |   27 +-
- include/linux/mtd/sh_flctl.h        |    4 +-
- include/linux/mtd/sharpsl.h         |    2 +-
- include/linux/mtd/spi-nor.h         |   23 +-
- include/uapi/mtd/mtd-abi.h          |    2 +-
- 45 files changed, 2077 insertions(+), 748 deletions(-)
- create mode 100644 drivers/mtd/spi-nor/mtk-quadspi.c
-
---- a/drivers/mtd/Kconfig
-+++ b/drivers/mtd/Kconfig
-@@ -131,7 +131,7 @@ config MTD_CMDLINE_PARTS
- config MTD_AFS_PARTS
-       tristate "ARM Firmware Suite partition parsing"
--      depends on ARM
-+      depends on (ARM || ARM64)
-       ---help---
-         The ARM Firmware Suite allows the user to divide flash devices into
-         multiple 'images'. Each such image has a header containing its name
-@@ -161,7 +161,7 @@ config MTD_AR7_PARTS
- config MTD_BCM63XX_PARTS
-       tristate "BCM63XX CFE partitioning support"
--      depends on BCM63XX
-+      depends on BCM63XX || BMIPS_GENERIC || COMPILE_TEST
-       select CRC32
-       help
-         This provides partions parsing for BCM63xx devices with CFE
---- a/drivers/mtd/cmdlinepart.c
-+++ b/drivers/mtd/cmdlinepart.c
-@@ -304,7 +304,7 @@ static int mtdpart_setup_real(char *s)
-  * the first one in the chain if a NULL mtd_id is passed in.
-  */
- static int parse_cmdline_partitions(struct mtd_info *master,
--                                  struct mtd_partition **pparts,
-+                                  const struct mtd_partition **pparts,
-                                   struct mtd_part_parser_data *data)
- {
-       unsigned long long offset;
-@@ -382,7 +382,6 @@ static int __init mtdpart_setup(char *s)
- __setup("mtdparts=", mtdpart_setup);
- static struct mtd_part_parser cmdline_parser = {
--      .owner = THIS_MODULE,
-       .parse_fn = parse_cmdline_partitions,
-       .name = "cmdlinepart",
- };
---- a/drivers/mtd/devices/m25p80.c
-+++ b/drivers/mtd/devices/m25p80.c
-@@ -174,22 +174,6 @@ static int m25p80_read(struct spi_nor *n
-       return 0;
- }
--static int m25p80_erase(struct spi_nor *nor, loff_t offset)
--{
--      struct m25p *flash = nor->priv;
--
--      dev_dbg(nor->dev, "%dKiB at 0x%08x\n",
--              flash->spi_nor.mtd.erasesize / 1024, (u32)offset);
--
--      /* Set up command buffer. */
--      flash->command[0] = nor->erase_opcode;
--      m25p_addr2cmd(nor, offset, flash->command);
--
--      spi_write(flash->spi, flash->command, m25p_cmdsz(nor));
--
--      return 0;
--}
--
- /*
-  * board specific setup should have ensured the SPI clock used here
-  * matches what the READ command supports, at least until this driver
-@@ -197,12 +181,11 @@ static int m25p80_erase(struct spi_nor *
-  */
- static int m25p_probe(struct spi_device *spi)
- {
--      struct mtd_part_parser_data     ppdata;
-       struct flash_platform_data      *data;
-       struct m25p *flash;
-       struct spi_nor *nor;
-       enum read_mode mode = SPI_NOR_NORMAL;
--      char *flash_name = NULL;
-+      char *flash_name;
-       int ret;
-       data = dev_get_platdata(&spi->dev);
-@@ -216,12 +199,11 @@ static int m25p_probe(struct spi_device
-       /* install the hooks */
-       nor->read = m25p80_read;
-       nor->write = m25p80_write;
--      nor->erase = m25p80_erase;
-       nor->write_reg = m25p80_write_reg;
-       nor->read_reg = m25p80_read_reg;
-       nor->dev = &spi->dev;
--      nor->flash_node = spi->dev.of_node;
-+      spi_nor_set_flash_node(nor, spi->dev.of_node);
-       nor->priv = flash;
-       spi_set_drvdata(spi, flash);
-@@ -242,6 +224,8 @@ static int m25p_probe(struct spi_device
-        */
-       if (data && data->type)
-               flash_name = data->type;
-+      else if (!strcmp(spi->modalias, "spi-nor"))
-+              flash_name = NULL; /* auto-detect */
-       else
-               flash_name = spi->modalias;
-@@ -249,11 +233,8 @@ static int m25p_probe(struct spi_device
-       if (ret)
-               return ret;
--      ppdata.of_node = spi->dev.of_node;
--
--      return mtd_device_parse_register(&nor->mtd, NULL, &ppdata,
--                      data ? data->parts : NULL,
--                      data ? data->nr_parts : 0);
-+      return mtd_device_register(&nor->mtd, data ? data->parts : NULL,
-+                                 data ? data->nr_parts : 0);
- }
-@@ -279,14 +260,21 @@ static int m25p_remove(struct spi_device
-  */
- static const struct spi_device_id m25p_ids[] = {
-       /*
-+       * Allow non-DT platform devices to bind to the "spi-nor" modalias, and
-+       * hack around the fact that the SPI core does not provide uevent
-+       * matching for .of_match_table
-+       */
-+      {"spi-nor"},
-+
-+      /*
-        * Entries not used in DTs that should be safe to drop after replacing
--       * them with "nor-jedec" in platform data.
-+       * them with "spi-nor" in platform data.
-        */
-       {"s25sl064a"},  {"w25x16"},     {"m25p10"},     {"m25px64"},
-       /*
--       * Entries that were used in DTs without "nor-jedec" fallback and should
--       * be kept for backward compatibility.
-+       * Entries that were used in DTs without "jedec,spi-nor" fallback and
-+       * should be kept for backward compatibility.
-        */
-       {"at25df321a"}, {"at25df641"},  {"at26df081a"},
-       {"mr25h256"},
---- a/drivers/mtd/maps/physmap_of.c
-+++ b/drivers/mtd/maps/physmap_of.c
-@@ -128,7 +128,6 @@ static int of_flash_probe(struct platfor
-       int reg_tuple_size;
-       struct mtd_info **mtd_list = NULL;
-       resource_size_t res_size;
--      struct mtd_part_parser_data ppdata;
-       bool map_indirect;
-       const char *mtd_name = NULL;
-@@ -272,8 +271,9 @@ static int of_flash_probe(struct platfor
-       if (err)
-               goto err_out;
--      ppdata.of_node = dp;
--      mtd_device_parse_register(info->cmtd, part_probe_types_def, &ppdata,
-+      info->cmtd->dev.parent = &dev->dev;
-+      mtd_set_of_node(info->cmtd, dp);
-+      mtd_device_parse_register(info->cmtd, part_probe_types_def, NULL,
-                       NULL, 0);
-       kfree(mtd_list);
---- a/drivers/mtd/mtdchar.c
-+++ b/drivers/mtd/mtdchar.c
-@@ -465,38 +465,111 @@ static int mtdchar_readoob(struct file *
- }
- /*
-- * Copies (and truncates, if necessary) data from the larger struct,
-- * nand_ecclayout, to the smaller, deprecated layout struct,
-- * nand_ecclayout_user. This is necessary only to support the deprecated
-- * API ioctl ECCGETLAYOUT while allowing all new functionality to use
-- * nand_ecclayout flexibly (i.e. the struct may change size in new
-- * releases without requiring major rewrites).
-+ * Copies (and truncates, if necessary) OOB layout information to the
-+ * deprecated layout struct, nand_ecclayout_user. This is necessary only to
-+ * support the deprecated API ioctl ECCGETLAYOUT while allowing all new
-+ * functionality to use mtd_ooblayout_ops flexibly (i.e. mtd_ooblayout_ops
-+ * can describe any kind of OOB layout with almost zero overhead from a
-+ * memory usage point of view).
-  */
--static int shrink_ecclayout(const struct nand_ecclayout *from,
--              struct nand_ecclayout_user *to)
-+static int shrink_ecclayout(struct mtd_info *mtd,
-+                          struct nand_ecclayout_user *to)
- {
--      int i;
-+      struct mtd_oob_region oobregion;
-+      int i, section = 0, ret;
--      if (!from || !to)
-+      if (!mtd || !to)
-               return -EINVAL;
-       memset(to, 0, sizeof(*to));
--      to->eccbytes = min((int)from->eccbytes, MTD_MAX_ECCPOS_ENTRIES);
--      for (i = 0; i < to->eccbytes; i++)
--              to->eccpos[i] = from->eccpos[i];
-+      to->eccbytes = 0;
-+      for (i = 0; i < MTD_MAX_ECCPOS_ENTRIES;) {
-+              u32 eccpos;
-+
-+              ret = mtd_ooblayout_ecc(mtd, section, &oobregion);
-+              if (ret < 0) {
-+                      if (ret != -ERANGE)
-+                              return ret;
-+
-+                      break;
-+              }
-+
-+              eccpos = oobregion.offset;
-+              for (; i < MTD_MAX_ECCPOS_ENTRIES &&
-+                     eccpos < oobregion.offset + oobregion.length; i++) {
-+                      to->eccpos[i] = eccpos++;
-+                      to->eccbytes++;
-+              }
-+      }
-       for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES; i++) {
--              if (from->oobfree[i].length == 0 &&
--                              from->oobfree[i].offset == 0)
-+              ret = mtd_ooblayout_free(mtd, i, &oobregion);
-+              if (ret < 0) {
-+                      if (ret != -ERANGE)
-+                              return ret;
-+
-                       break;
--              to->oobavail += from->oobfree[i].length;
--              to->oobfree[i] = from->oobfree[i];
-+              }
-+
-+              to->oobfree[i].offset = oobregion.offset;
-+              to->oobfree[i].length = oobregion.length;
-+              to->oobavail += to->oobfree[i].length;
-       }
-       return 0;
- }
-+static int get_oobinfo(struct mtd_info *mtd, struct nand_oobinfo *to)
-+{
-+      struct mtd_oob_region oobregion;
-+      int i, section = 0, ret;
-+
-+      if (!mtd || !to)
-+              return -EINVAL;
-+
-+      memset(to, 0, sizeof(*to));
-+
-+      to->eccbytes = 0;
-+      for (i = 0; i < ARRAY_SIZE(to->eccpos);) {
-+              u32 eccpos;
-+
-+              ret = mtd_ooblayout_ecc(mtd, section, &oobregion);
-+              if (ret < 0) {
-+                      if (ret != -ERANGE)
-+                              return ret;
-+
-+                      break;
-+              }
-+
-+              if (oobregion.length + i > ARRAY_SIZE(to->eccpos))
-+                      return -EINVAL;
-+
-+              eccpos = oobregion.offset;
-+              for (; eccpos < oobregion.offset + oobregion.length; i++) {
-+                      to->eccpos[i] = eccpos++;
-+                      to->eccbytes++;
-+              }
-+      }
-+
-+      for (i = 0; i < 8; i++) {
-+              ret = mtd_ooblayout_free(mtd, i, &oobregion);
-+              if (ret < 0) {
-+                      if (ret != -ERANGE)
-+                              return ret;
-+
-+                      break;
-+              }
-+
-+              to->oobfree[i][0] = oobregion.offset;
-+              to->oobfree[i][1] = oobregion.length;
-+      }
-+
-+      to->useecc = MTD_NANDECC_AUTOPLACE;
-+
-+      return 0;
-+}
-+
- static int mtdchar_blkpg_ioctl(struct mtd_info *mtd,
-                              struct blkpg_ioctl_arg *arg)
- {
-@@ -815,16 +888,12 @@ static int mtdchar_ioctl(struct file *fi
-       {
-               struct nand_oobinfo oi;
--              if (!mtd->ecclayout)
-+              if (!mtd->ooblayout)
-                       return -EOPNOTSUPP;
--              if (mtd->ecclayout->eccbytes > ARRAY_SIZE(oi.eccpos))
--                      return -EINVAL;
--              oi.useecc = MTD_NANDECC_AUTOPLACE;
--              memcpy(&oi.eccpos, mtd->ecclayout->eccpos, sizeof(oi.eccpos));
--              memcpy(&oi.oobfree, mtd->ecclayout->oobfree,
--                     sizeof(oi.oobfree));
--              oi.eccbytes = mtd->ecclayout->eccbytes;
-+              ret = get_oobinfo(mtd, &oi);
-+              if (ret)
-+                      return ret;
-               if (copy_to_user(argp, &oi, sizeof(struct nand_oobinfo)))
-                       return -EFAULT;
-@@ -913,14 +982,14 @@ static int mtdchar_ioctl(struct file *fi
-       {
-               struct nand_ecclayout_user *usrlay;
--              if (!mtd->ecclayout)
-+              if (!mtd->ooblayout)
-                       return -EOPNOTSUPP;
-               usrlay = kmalloc(sizeof(*usrlay), GFP_KERNEL);
-               if (!usrlay)
-                       return -ENOMEM;
--              shrink_ecclayout(mtd->ecclayout, usrlay);
-+              shrink_ecclayout(mtd, usrlay);
-               if (copy_to_user(argp, usrlay, sizeof(*usrlay)))
-                       ret = -EFAULT;
---- a/drivers/mtd/mtdconcat.c
-+++ b/drivers/mtd/mtdconcat.c
-@@ -777,7 +777,7 @@ struct mtd_info *mtd_concat_create(struc
-       }
--      concat->mtd.ecclayout = subdev[0]->ecclayout;
-+      mtd_set_ooblayout(&concat->mtd, subdev[0]->ooblayout);
-       concat->num_subdev = num_devs;
-       concat->mtd.name = name;
---- a/drivers/mtd/mtdcore.c
-+++ b/drivers/mtd/mtdcore.c
-@@ -32,6 +32,7 @@
- #include <linux/err.h>
- #include <linux/ioctl.h>
- #include <linux/init.h>
-+#include <linux/of.h>
- #include <linux/proc_fs.h>
- #include <linux/idr.h>